A sic-based semiconductor device package structure

Abstract

The application discloses a SIC-based semiconductor device packaging structure and relates to the technical field of semiconductors.The SIC-based semiconductor device packaging structure comprises a first frame, a second frame, a chip and a copper clamp piece; the copper clamp piece comprises an extension part, a lower concave part, a convex part and a connecting part which are sequentially connected; a copper connecting table which is matched with the chip is arranged below the lower concave part; the extension part of the copper clamp piece extends to the outside of the edge of the chip, thereby forming a physical barrier, effectively reducing the stress of plastic sealing material flow on the surface of the chip, preventing the generation of micro cracks and improving the yield rate. The planar contact area of the copper connecting table and the chip is 7 times that of a traditional solder wire, the parasitic inductance is reduced by about 3nH, the thermal resistance is reduced and the uniform heat diffusion is realized.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a SiC-based semiconductor device packaging structure. Background Technology

[0002] Silicon carbide (SiC) Schottky barrier diodes (SBDs), as representatives of third-generation semiconductor power devices, are characterized by their wide bandgap, high critical breakdown electric field, high thermal conductivity (4.9 W / cm·K), and high electron saturation drift velocity (2 × 10⁻⁶). 7 With its superior physical properties such as high speed (cm / s), SiC SBDs demonstrate revolutionary advantages in high-temperature, high-frequency, and high-voltage applications. Compared to traditional silicon-based diodes, SiC SBDs possess near-zero reverse recovery charge (Qrr), low switching losses, high switching frequency capability, and excellent high-temperature stability (operating temperature can reach over 200℃), making them core components in high-efficiency energy conversion systems such as electric vehicle on-board chargers (OBC), DC / DC converters, photovoltaic inverters, industrial motor drives, and data center power supplies. Major global automakers have adopted SiC power modules as standard technology for next-generation electric vehicles. For example, Tesla's Model 3 main drive inverter, using SiC MOSFETs, has increased its driving range by 5-10%, fully demonstrating the system-level advantages of SiC devices.

[0003] However, the superior properties of SiC materials themselves have not been fully translated into device performance advantages. The core contradiction currently facing the industry lies in the fact that improvements in chip-level performance are limited by lagging packaging technology. Traditional silicon-based device packaging architectures (such as TO-247 and D²PAK) cannot fully utilize the high-frequency and high-temperature potential of SiC chips, instead introducing bottlenecks such as parasitic inductance and thermal mismatch, resulting in system efficiency losses as high as 15-20%. Therefore, how to reduce parasitic inductance and thermal resistance, and improve heat dissipation, are the urgent technical problems that need to be solved in this case. Utility Model Content

[0004] To address the above problems, this invention provides a SiC-based semiconductor device packaging structure that reduces parasitic inductance and thermal resistance, and improves heat dissipation.

[0005] The technical solution of this utility model is: A SiC-based semiconductor device packaging structure, characterized in that it comprises: The first frame has a chip mounting position at one end within the molding compound and extends out of the molding compound at the other end. The chip is disposed at the chip mounting position; The second frame has one end located inside the encapsulation body and spaced apart from the first frame, and the other end extends out from the encapsulation body (500); A copper clip includes an extension portion, a recessed portion, a protrusion portion, and a connecting portion connected in sequence; the extension portion is located above the chip and extends to the outer side of the chip edge; a copper connecting platform adapted to the chip is provided below the recessed portion; the top surface of the protrusion portion is located above the top surface of the recessed portion; the connecting portion is electrically connected to a second frame.

[0006] Specifically, the chip is a SiC chip.

[0007] Specifically, the cathode of the chip is connected to the first frame, and the anode is connected to the copper clip.

[0008] Specifically, the molding compound has a coefficient of thermal expansion of 9 × 10⁻⁻⁻⁻⁶. 6 / K molding compound.

[0009] Specifically, the width of the recess is not less than the width of the chip.

[0010] Specifically, the top of the recessed portion is provided with a groove.

[0011] This invention includes a first frame, a second frame, a chip, and a copper clip. The copper clip includes an extension portion, a recessed portion, a protruding portion, and a connecting portion connected in sequence. A copper connecting platform adapted to the chip is provided below the recessed portion. The extension portion of the copper clip extends to the outer edge of the chip, forming a physical barrier that effectively reduces the stress on the chip surface caused by the flow of molding compound, prevents microcracks, and improves the yield. The planar contact area between the copper connecting platform and the chip is increased by 7 times compared to traditional wire bonding, reducing parasitic inductance by approximately 3nH and reducing thermal resistance, thus achieving uniform heat dissipation. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of this utility model; Figure 2 This is a schematic diagram of the finished structure of the first and second frames; Figure 3 yes Figure 1 Top view of the structure; Figure 4 This is a simulation diagram of thermal stress on the front of the chip; Figure 5 This is a simulation diagram of thermal stress on the back of the chip; In the diagram, 100 represents the first frame, 200 the second frame, and 300 the chip. 400 is a copper clip, 410 is an extension section, 420 is a recessed section, 421 is a copper connecting platform, 430 is a protrusion, and 440 is a connecting section. 500 is a plastic encapsulated form. Detailed Implementation

[0013] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0014] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0015] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0016] The following is for reference. Figure 1-5 Describe this utility model; A SiC-based semiconductor device packaging structure, comprising: The first frame 100 has a chip mounting position at one end located inside the molding compound 500, and the other end extends out from the molding compound 500; Chip 300 is disposed on the chip mounting position; in this case, chip 300 is a SiC chip. The second frame 200 has one end located inside the encapsulation body 500 and spaced apart from the first frame 100, and the other end extends out from the encapsulation body 500. The copper clip 400 includes an extension portion 410, a recessed portion 420, a protrusion portion 430, and a connecting portion 440 connected in sequence. The extension portion 410 is located above the chip 300 and extends to the outer side of the edge of the chip 300 to reduce the impact of the molding compound on the surface of the chip 300 during the molding process. A copper connecting platform 421 adapted to the chip 300 is provided below the recessed portion 420. The top surface of the protrusion portion 430 is located above the top surface of the recessed portion 420. The connecting portion 440 is electrically connected to the second frame 200.

[0017] The extension 410 of the copper clip 400 extends to the outer edge of the chip 300, forming a physical barrier that effectively reduces the stress on the chip surface caused by the molding compound flow, prevents microcracks, and improves yield. The copper connector 421 has a 7-fold larger planar contact area with the chip compared to traditional bonding wires, reducing parasitic inductance by approximately 3nH and lowering thermal resistance, achieving uniform heat dissipation. Through ANSYS 3D modeling and finite element analysis, under temperature conditions of 25℃~265℃, the thermal stress on the front of the chip is 370.48MPa. Figure 4 As shown, the thermal stress on the back of the chip is 436.02 MPa. Figure 5 As shown.

[0018] The 420 recessed structure provides a natural flow path for the molding compound, increasing the filling speed by 25% while avoiding air bubble residue.

[0019] A high-lead bonding solder paste layer is provided between the copper connector 421 and the chip. The thermal expansion coefficients of the copper clip 400 (CTE≈17 ppm / ℃) and the SiC chip (CTE≈4 ppm / ℃) differ by more than 4 times. Shear stress is generated during temperature cycling, which can easily lead to interface delamination (solder or silver sintering layer). Therefore, the chip surface is electroplated with a silver coating to prevent oxidation, improve the solder wetting effect, reduce the void ratio, and avoid interface delamination.

[0020] The cathode of the chip is connected to the first frame 100, and the anode is connected to the copper clip 400.

[0021] The molding compound has a coefficient of thermal expansion of 9×10⁻ 6 / K molding compound achieves near-matching with SiC chips; improves the mechanical strength of the product after aging at 150℃.

[0022] The width of the recessed portion 420 is not less than the width of the chip 300. In this case, the width is based on... Figure 1 For example, Figure 1 The horizontal direction is the width direction.

[0023] The top of the recessed portion 420 is provided with a groove. The elastic deformation zone formed by the groove can absorb the shrinkage stress during the curing of the molding compound, while reducing the mechanical stress transmission between the copper clip and the chip.

[0024] The manufacturing method of the SiC-based chip packaging structure in this case includes the following steps: Place the first frame 100 and the second frame 200 in the automatic line track and clamp them with pressure fingers; then apply an appropriate amount of solder paste to the substrate of the first frame 100 with the corresponding dispensing head; mount the SiC chip on the substrate stage of the first frame 100 with the cathode side facing down. Apply an appropriate amount of solder paste to the anode surface of the SiC chip and the 200V trench of the second frame using the corresponding dispensing head; A copper clip 400 is placed on the anode of the SiC chip; the copper clip 400 is interconnected with the anode of the SiC chip, and the pins of the copper clip 400 are interconnected with the second frame 200. High-lead solder paste is used for the interconnection. The assembled products are placed in a vacuum reflow welding furnace or tunnel furnace for sintering; after sintering, the products are encapsulated, post-cured, pre-cut, tin-plated, cut into shape, tested, printed, taped, inspected, and put into storage.

[0025] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A SiC-based semiconductor device packaging structure, characterized in that, include: The first frame (100) has a chip mounting position at one end inside the molding compound (500), and the other end extends out from the molding compound (500); Chip (300) is disposed on the chip mounting position; The second frame (200) has one end located inside the encapsulation body (500) and spaced apart from the first frame (100), and the other end extends out from the encapsulation body (500); The copper clip (400) includes an extension (410), a recess (420), a protrusion (430), and a connecting portion (440) connected in sequence; the extension (410) is located above the chip (300) and extends to the outer side of the edge of the chip (300); a copper connecting platform (421) adapted to the chip (300) is provided below the recess (420); the top surface of the protrusion (430) is located above the top surface of the recess (420); the connecting portion (440) is electrically connected to the second frame (200).

2. The SiC-based semiconductor device packaging structure according to claim 1, characterized in that, The chip is an SiC chip.

3. A SiC-based semiconductor device packaging structure according to claim 1 or 2, characterized in that, The cathode of the chip is connected to the first frame (100), and the anode is connected to the copper clip (400).

4. The SiC-based semiconductor device packaging structure according to claim 1, characterized in that, The molding compound has a coefficient of thermal expansion of 9×10⁻ 6 / K molding compound.

5. A SiC-based semiconductor device packaging structure according to claim 1 or 2, characterized in that, The width of the recess (420) is not less than the width of the chip (300).

6. The SiC-based semiconductor device packaging structure according to claim 1, characterized in that, The top of the recessed portion (420) is provided with a groove.

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