Pin multiplexing circuit for LCD display and GPIO output and MCU

Abstract

The utility model relates to the technical field of tube foot multiplexing, disclose a kind of tube foot multiplexing circuit and MCU for LCD display and GPIO output, when using, the tube foot multiplexing circuit of the utility model selects higher voltage in LCD drive voltage VLCD and GPIO level VDD and carries out output by being arranged voltage selection unit on one hand, and the voltage selected is accessed to the substrate of upper switch tube M1, upper switch tube M3 and output switch tube M5, can avoid voltage backflow;On the other hand by setting switch S3-switch S8, when carrying out GPIO output and LCD display output switching, by the on-off of control switch S3-switch S8, the tube foot multiplexing circuit of the utility model can be disconnected with corresponding control logic, avoid the situation that GPIO output and LCD display output overlap output, guarantee circuit normal operation.

Description

Technical Field

[0001] This utility model relates to the field of pin multiplexing technology, specifically to a pin multiplexing circuit and MCU for LCD display and GPIO output. Background Technology

[0002] In MCUs, to improve pin utilization, multiple functional modules often share pins; for example, the LCD display interface and GPIO pins are multiplexed. While this multiplexing improves pin utilization in practice, it also introduces new problems, specifically... Figure 1 The existing pin multiplexing circuit shown is used for illustration: exist Figure 1 In the middle, the GPIO control logic and LCD control logic control the on / off state of the corresponding MOSFET based on the mode signal MODE, thereby controlling whether the pin is used for GPIO output or LCD display output; However, due to Figure 1 The substrate of MOSFET M1 is connected to the GPIO level VDD, and the substrate of MOSFET M3 is connected to the LCD driving voltage VLCD. When the LCD driving voltage VLCD and the GPIO level VDD are incompatible, i.e., the two voltages are different, it is easy to cause voltage backflow. In addition, there is a race condition when switching between GPIO output and LCD display output on the pins. The overlapping output of the two can cause functional errors. Utility Model Content

[0003] In view of the shortcomings of the background technology, the present invention provides a pin multiplexing circuit and MCU for LCD display and GPIO output. The technical problems to be solved are that the existing pin multiplexing circuit for LCD and GPIO has the problem of voltage backflow, and the problem of functional error caused by the overlapping enable of GPIO output and LCD display output.

[0004] To solve the above technical problems, in the first aspect, this utility model provides the following technical solution: a pin multiplexing circuit for LCD display and GPIO output, including a first output branch formed by an upper switch M1 and a lower switch M2 connected in series, a second output branch formed by an upper switch M3 and a lower switch M4 connected in series, and an output switch M5; The input terminal of the upper switch M1 is used to connect to the GPIO level VDD, and the output terminal of the lower switch M2 is grounded; the input terminal of the upper switch M3 is used to connect to the LCD driving voltage VLCD, and the output terminal of the lower switch M3 is grounded; the intermediate node of the first output branch is electrically connected to the intermediate node of the second output branch. The input terminal of the output switch M5 is used to connect half of the LCD driving voltage VLCD, and the output terminal of the output switch M5 is electrically connected to the intermediate node of the second output branch; it also includes: a voltage selection unit, switch S3, switch S4, switch S5, switch S6, switch S7 and switch S8; The voltage selection unit is used to select the higher voltage from the LCD driving voltage VLCD and the GPIO level VDD for output. The voltage output terminal of the voltage selection unit is electrically connected to the substrate of the upper switch M1, the input terminal of switch S4, the substrate of the upper switch M3, the input terminal of switch S6, the input terminal of switch S8 and the substrate of the output switch M5, respectively. The output terminal of switch S4 is electrically connected to the control terminal of upper switch tube M1 and the output terminal of switch S3, respectively; the output terminal of switch S6 is electrically connected to the control terminal of upper switch tube M3 and the output terminal of switch S5, respectively; the output terminal of switch S8 is electrically connected to the control terminal of output switch tube M5 and the output terminal of switch S7, respectively.

[0005] In one embodiment of the first aspect, the voltage selection unit includes a comparator CMP1, a switch S1, and a switch S2; The positive input terminal of comparator CMP1 and the input terminal of switch S1 are respectively used to connect to the GPIO level VDD, and the negative input terminal of comparator CMP1 and the input terminal of switch S2 are respectively used to connect to the LCD driving voltage VLCD; the output terminal of comparator CMP1 is electrically connected to the control terminal of switch S1, and the non-output terminal of comparator CMP1 is electrically connected to the control terminal of switch S2; the output terminals of switch S1 and switch S2 are electrically connected and serve as the voltage output terminals of the voltage selection unit.

[0006] In one embodiment of the first aspect, the voltage selection unit includes a comparator CMP1, a switch S1, and a switch S2; The negative input terminal of comparator CMP1 and the input terminal of switch S2 are respectively used to connect to the GPIO level VDD, and the positive input terminal of comparator CMP1 and the input terminal of switch S1 are respectively used to connect to the LCD driving voltage VLCD. The output terminal of comparator CMP1 is electrically connected to the control terminal of switch S1, and the non-output terminal of comparator CMP1 is electrically connected to the control terminal of switch S2. The output terminals of switch S1 and switch S2 are electrically connected and serve as the voltage output terminals of the voltage selection unit.

[0007] In one embodiment of the first aspect, the control terminal of switch S1 is turned on when a high-level signal is input and turned off when a low-level signal is input; the control terminal of switch S2 is turned on when a high-level signal is input and turned off when a low-level signal is input.

[0008] In one embodiment of the first aspect, the switches S1 and S2 are NMOS transistors or transmission gates.

[0009] In one embodiment of the first aspect, the control terminals of switches S3-S8 are turned on when a high-level signal is input and turned off when a low-level signal is input.

[0010] In one embodiment of the first aspect, the control terminals of switch S3, switch S6 and switch S8 are used to input a first control signal A, and the control terminals of switch S4, switch S5 and switch S7 are used to input a second control signal B, wherein the first control signal A and the second control signal B are two opposite signals.

[0011] In one embodiment of the first aspect, the present invention further includes a control signal generation circuit, which includes an inverter INV1 and an inverter INV2. The input terminal of the inverter INV1 is used to input a mode signal MODE, the output terminal of the inverter INV1 is used to output a first control signal A and is electrically connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is used to output a second control signal B.

[0012] In one embodiment of the first aspect, the switches S3-S8 are all NMOS transistors or transmission gates.

[0013] Secondly, this utility model also provides an MCU, including GPIO control logic and LCD control logic, and also includes the aforementioned pin multiplexing circuit for LCD display and GPIO output. The GPIO control logic is electrically connected to the input terminal of switch S3 and the control terminal of the lower switch M2, and the LCD control logic is electrically connected to the input terminals of switch S5, switch S7 and the control terminal of the lower switch M4.

[0014] Compared with the prior art, the advantages of this utility model are as follows: On the one hand, by setting a voltage selection unit, this utility model selects the higher voltage from the LCD driving voltage VLCD and the GPIO level VDD for output, and connects the selected voltage to the substrate of the upper switch M1, upper switch M3 and output switch M5, which can avoid voltage backflow; on the other hand, by setting switches S3-S8, when switching between GPIO output and LCD display output, the pin multiplexing circuit of this utility model can be disconnected from the corresponding control logic by controlling the on / off state of switches S3-S8, avoiding overlapping output between GPIO output and LCD display output, and ensuring normal circuit operation. Attached Figure Description

[0015] Figure 1The circuit diagram for the pin multiplexing circuit of the existing LCD and GPIO; Figure 2 This is a circuit diagram of the pin multiplexing circuit in Example 1; Figure 3 This is a circuit diagram of the voltage selection unit in Embodiment 1; Figure 4 This is a circuit diagram of the control signal generation circuit in Embodiment 1; Figure 5 The GPIO control logic and LCD control logic in Example 2 are... Figure 2 Circuit connection diagram. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the present invention, and therefore only show the components relevant to the present invention.

[0017] Example 1 like Figure 2 As shown, the pin multiplexing circuit for LCD display and GPIO output provided in this embodiment includes a first output branch 1 formed by connecting an upper switch M1 and a lower switch M2 in series, a second output branch 2 formed by connecting an upper switch M3 and a lower switch M4 in series, and an output switch M5; wherein the upper switch M1, the lower switch M2, the upper switch M3, the lower switch M4, and the output switch M5 are all MOSFETs; The input terminal of the upper switch M1 is used to connect to the GPIO level VDD, and the output terminal of the lower switch M2 is grounded; the input terminal of the upper switch M3 is used to connect to the LCD driving voltage VLCD, and the output terminal of the lower switch M3 is grounded; the middle node of the first output branch is electrically connected to the middle node of the second output branch, and is used to electrically connect to the PAD pin. The input terminal of the output switch M5 is used to connect half of the LCD driving voltage VLCD, and the output terminal of the output switch M5 is electrically connected to the intermediate node of the second output branch 2. It also includes: voltage selection unit 3, switch S3, switch S4, switch S5, switch S6, switch S7 and switch S8; The voltage selection unit 3 is used to select the higher voltage from the LCD driving voltage VLCD and the GPIO level VDD for output. The voltage output terminal of the voltage selection unit 3 is electrically connected to the substrate of the upper switch M1, the input terminal of switch S4, the substrate of the upper switch M3, the input terminal of switch S6, the input terminal of switch S8 and the substrate of the output switch M5, respectively. The output terminal of switch S4 is electrically connected to the control terminal of the upper switch tube M1 and the output terminal of switch S3, respectively; the output terminal of switch S6 is electrically connected to the control terminal of the upper switch tube M3 and the output terminal of switch S5, respectively; the output terminal of switch S8 is electrically connected to the control terminal of the output switch tube M5 and the output terminal of switch S7, respectively.

[0018] In practical use, this invention, on the one hand, selects the higher voltage from the LCD driving voltage VLCD and the GPIO level VDD for output by setting the voltage selection unit 3, and connects the selected voltage to the substrate of the upper switch M1, upper switch M3 and output switch M5, which can avoid voltage backflow; on the other hand, by setting switches S3, S5 and S7, when switching between GPIO output and LCD display output, the pin multiplexing circuit of this invention can be disconnected from the corresponding control logic by controlling the on and off of switches S3, S5 and S7, avoiding overlapping output between GPIO output and LCD display output, and ensuring normal circuit operation.

[0019] Specifically, in this embodiment, the circuit of voltage selection unit 3 is as follows: Figure 3 As shown, it includes comparator CMP1, switch S1 and switch S2; The positive input terminal of comparator CMP1 and the input terminal of switch S1 are respectively used to connect to the GPIO level VDD, and the negative input terminal of comparator CMP1 and the input terminal of switch S2 are respectively used to connect to the LCD driving voltage VLCD. The output terminal of comparator CMP1 is electrically connected to the control terminal of switch S1, and the non-output terminal of comparator CMP1 is electrically connected to the control terminal of switch S2. The output terminals of switch S1 and switch S2 are electrically connected to form the voltage output terminal of voltage selection unit 3.

[0020] In practical use, Figure 3 The circuit shown compares the GPIO level VDD and the LCD driving voltage VLCD using comparator CMP1, and controls the on / off state of switches S1 and S2 based on the comparison result, thereby selecting the higher voltage for output.

[0021] In one implementation, the GPIO level VDD and the LCD driving voltage VLCD can also be connected to the comparator CMP1 in the following manner: The negative input of comparator CMP1 and the input of switch S2 are respectively used to connect to the GPIO level VDD, and the positive input of comparator CMP1 and the input of switch S1 are respectively used to connect to the LCD driving voltage VLCD. In addition, the output terminal of comparator CMP1 is electrically connected to the control terminal of switch S1, and the non-output terminal of comparator CMP1 is electrically connected to the control terminal of switch S2; the output terminals of switch S1 and switch S2 are electrically connected to form the voltage output terminal of voltage selection unit 3.

[0022] In this embodiment, the control methods for switches S1 and S2 are as follows: The control terminal of switch S1 is turned on when a high-level signal is input and turned off when a low-level signal is input; the control terminal of switch S2 is turned on when a high-level signal is input and turned off when a low-level signal is input; for example, switches S1 and S2 can be NMOS transistors or transmission gates.

[0023] In this embodiment, the control method for switches S3-S8 is as follows: The control terminals of switches S3-S8 are turned on when a high-level signal is input and turned off when a low-level signal is input; switches S3-S8 can be NMOS transistors or transmission gates.

[0024] More specifically, in this embodiment, the control terminals of switches S3, S6, and S8 are used to input the first control signal A, and the control terminals of switches S4, S5, and S7 are used to input the second control signal B. The first control signal A and the second control signal B are two opposite signals; that is, at the same time, when switches S3, S6, and S8 are turned on, switches S4, S5, and S7 are turned off; when switches S3, S6, and S8 are turned off, switches S4, S5, and S7 are turned on.

[0025] In practical use, switches S4, S6, and S8 control the gates of the upper switching transistor M1, upper switching transistor M3, and output switching transistor M5, respectively. This ensures that when the GPIO function is selected, the gates of upper switching transistor M3 and output switching transistor M5 are at their highest potentials, guaranteeing that the MOSFETs are in the off state and preventing false turn-on from affecting the actual circuit output. It also ensures that when the LCD function is selected, the gate of upper switching transistor M1 is at its highest potential, guaranteeing that the MOSFETs are in the off state and preventing false turn-on from affecting the actual circuit output.

[0026] In this embodiment, the present invention also includes, for example, Figure 4 The control signal generation circuit shown is in Figure 4In this circuit, the control signal generation circuit includes inverters INV1 and INV2. The input terminal of inverter INV1 is used to input the mode signal MODE, and the output terminal of inverter INV1 is used to output the first control signal A and is electrically connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is used to output the second control signal B. The mode signal MODE is an existing configuration signal that can be generated by configuring the registers in the MCU.

[0027] for Figure 2 , Figure 3 and Figure 4 The circuit in the example is described in Example 2, and will not be described here again.

[0028] Example 2 like Figure 5 As shown, this embodiment provides an MCU, including GPIO control logic and LCD control logic, and also includes a pin multiplexing circuit for LCD display and GPIO output as described in Embodiment 1. The GPIO control logic is electrically connected to the input terminal of switch S3 and the control terminal of the lower switch M2, and the LCD control logic is electrically connected to the input terminals of switch S5, switch S7 and the control terminal of the lower switch M4.

[0029] In actual use, when the mode signal MODE is configured to be high, the PAD pin is configured to LCD output mode; at the same time, the GPIO control logic is controlled by the mode signal MODE. When the mode signal MODE is high, the GPIO control logic outputs a low-level signal to the control terminal of the lower switch M2, so that its state is cut off. The design with the highest priority MODE signal effectively avoids contention between multiplexed pins during function switching. Controlled by the MODE signal, the control signal generation circuit drives switch S3 to open and switch S4 to open. The control terminal and substrate of the upper switch M1 are both at VDDPORT potential, the highest potential, ensuring no risk of voltage backflow and preventing leakage. Under the control of the control signal generation circuit, switches S5 and S7 are open, while switches S6 and S8 are closed. The substrates of the upper switch M3 and the output switch M5 are at the highest potential, ensuring no risk of voltage backflow and preventing leakage. The control terminal potentials of the upper switch M3, lower switch M4, and output switch M5 are all controlled by the LCD control logic to achieve the LCD display function. When the mode signal MODE is configured to low, pin PAD is in GPIO mode. Controlled by MODE, switch S3 is on, switch S4 is off, and the substrate of the upper switch M1 is at its highest potential, ensuring no backflow risk and preventing leakage. The gate potentials of both the upper and lower switches M1 and M2 are controlled by the GPIO control logic, enabling GPIO output functionality. The LCD control logic is controlled by the mode signal MODE. When MODE is low, it outputs a low level to the gate of the lower switch M4, turning it off. The highest priority design of the mode signal MODE effectively avoids contention between multiplexed pins during function switching. Switches S5 and S7 are off, while switches S6 and S8 are on. The gates and substrates of the upper switch M3 and the output switch M5 are both at VDDPORT potential, the highest potential, ensuring no backflow risk and preventing leakage.

[0030] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A pin multiplexing circuit for LCD display and GPIO output, comprising a first output branch formed by an upper switch M1 and a lower switch M2 connected in series, a second output branch formed by an upper switch M3 and a lower switch M4 connected in series, and an output switch M5; The input terminal of the upper switch M1 is used to connect to the GPIO level VDD, and the output terminal of the lower switch M2 is grounded; the input terminal of the upper switch M3 is used to connect to the LCD driving voltage VLCD, and the output terminal of the lower switch M3 is grounded; the intermediate node of the first output branch is electrically connected to the intermediate node of the second output branch. The input terminal of the output switch M5 is used to connect half of the LCD driving voltage VLCD, and the output terminal of the output switch M5 is electrically connected to the intermediate node of the second output branch; characterized in that, Also includes: Voltage selection unit, switch S3, switch S4, switch S5, switch S6, switch S7 and switch S8; The voltage selection unit is used to select the higher voltage from the LCD driving voltage VLCD and the GPIO level VDD for output. The voltage output terminal of the voltage selection unit is electrically connected to the substrate of the upper switch M1, the input terminal of switch S4, the substrate of the upper switch M3, the input terminal of switch S6, the input terminal of switch S8 and the substrate of the output switch M5, respectively. The output terminal of switch S4 is electrically connected to the control terminal of upper switch tube M1 and the output terminal of switch S3, respectively; the output terminal of switch S6 is electrically connected to the control terminal of upper switch tube M3 and the output terminal of switch S5, respectively; the output terminal of switch S8 is electrically connected to the control terminal of output switch tube M5 and the output terminal of switch S7, respectively.

2. The pin multiplexing circuit for LCD display and GPIO output according to claim 1, characterized in that, The voltage selection unit includes a comparator CMP1, a switch S1, and a switch S2; The positive input terminal of comparator CMP1 and the input terminal of switch S1 are respectively used to connect to the GPIO level VDD, and the negative input terminal of comparator CMP1 and the input terminal of switch S2 are respectively used to connect to the LCD driving voltage VLCD; the output terminal of comparator CMP1 is electrically connected to the control terminal of switch S1, and the non-output terminal of comparator CMP1 is electrically connected to the control terminal of switch S2; the output terminals of switch S1 and switch S2 are electrically connected and serve as the voltage output terminals of the voltage selection unit.

3. A pin multiplexing circuit for LCD display and GPIO output according to claim 1, characterized in that, The voltage selection unit includes a comparator CMP1, a switch S1, and a switch S2; The negative input terminal of comparator CMP1 and the input terminal of switch S2 are respectively used to connect to the GPIO level VDD, and the positive input terminal of comparator CMP1 and the input terminal of switch S1 are respectively used to connect to the LCD driving voltage VLCD. The output terminal of comparator CMP1 is electrically connected to the control terminal of switch S1, and the non-output terminal of comparator CMP1 is electrically connected to the control terminal of switch S2. The output terminals of switch S1 and switch S2 are electrically connected and serve as the voltage output terminals of the voltage selection unit.

4. A pin multiplexing circuit for LCD display and GPIO output according to claim 2 or 3, characterized in that, The control terminal of switch S1 is turned on when a high-level signal is input and turned off when a low-level signal is input; the control terminal of switch S2 is turned on when a high-level signal is input and turned off when a low-level signal is input.

5. A pin multiplexing circuit for LCD display and GPIO output according to claim 4, characterized in that, The switches S1 and S2 are NMOS transistors or transmission gates.

6. A pin multiplexing circuit for LCD display and GPIO output according to claim 1, characterized in that, The control terminals of switches S3-S8 are turned on when a high-level signal is input and turned off when a low-level signal is input.

7. A pin multiplexing circuit for LCD display and GPIO output according to claim 6, characterized in that, The control terminals of switches S3, S6, and S8 are used to input a first control signal A, and the control terminals of switches S4, S5, and S7 are used to input a second control signal B. The first control signal A and the second control signal B are two opposite signals.

8. A pin multiplexing circuit for LCD display and GPIO output according to claim 7, characterized in that, It also includes a control signal generation circuit, which includes inverters INV1 and INV2. The input terminal of inverter INV1 is used to input the mode signal MODE, the output terminal of inverter INV1 is used to output the first control signal A and is electrically connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is used to output the second control signal B.

9. A pin multiplexing circuit for LCD display and GPIO output according to claim 6, characterized in that, All switches S3-S8 are NMOS transistors or transmission gates.

10. An MCU, comprising GPIO control logic and LCD control logic, characterized in that, It also includes a pin multiplexing circuit for LCD display and GPIO output as described in any one of claims 1-9, wherein the GPIO control logic is electrically connected to the input terminal of switch S3 and the control terminal of the lower switch M2, and the LCD control logic is electrically connected to the input terminal of switch S5, the input terminal of switch S7 and the control terminal of the lower switch M4.

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