Non-intrusive load acquisition device

Abstract

The application discloses a non-intrusive load acquisition device. The non-intrusive load acquisition device comprises a rectification and voltage reduction circuit, a voltage sampling circuit, a current sampling circuit and an ADC module; the input end of the rectification and voltage reduction circuit is connected with the output end of a power supply to be identified; the input end of the voltage sampling circuit obtains a voltage analog signal from the live wire end of the power supply to be identified; the current sampling circuit is connected with an external Hall current sensor, and the external Hall current sensor is used for obtaining a current analog signal; the ADC module receives the voltage analog signal from the voltage sampling circuit and the current analog signal from the current sampling circuit, converts the voltage analog signal and the current analog signal into digital signals, and then transmits the digital signals to a master control chip. Through the integration of the rectification and voltage reduction circuit and the sampling module, voltage / current acquisition and power supply can be completed by a single device, 220V power supply can be directly connected without damaging the circuit, and the installation process is greatly simplified.

Description

Technical Field

[0001] This application relates to the field of load acquisition technology, and in particular to a non-invasive load acquisition device. Background Technology

[0002] Non-intrusive load monitoring (NILM) infers the usage of individual appliances by analyzing total current or voltage signals in a home or building, eliminating the need for separate sensors for each appliance. NILM technology is widely used in smart homes, energy management, and smart grids, offering advantages such as reduced hardware costs and system complexity. However, traditional NILM methods suffer from high computational resource consumption, large memory and storage requirements, and difficulty adapting to edge computing devices. Traditional NILM technologies rely on high-performance computing platforms (such as GPUs or high-performance CPUs), making them unsuitable for resource-constrained embedded or edge devices.

[0003] Existing non-intrusive load acquisition circuits suffer from high circuit losses. Current transformers generate energy losses during the conversion process, reducing circuit efficiency. Simultaneously, the accuracy and stability of the sampling resistor directly affect the accuracy of current sampling. Due to the lack of effective amplification and filtering circuits, the sampled signal is susceptible to noise and interference, leading to significant sampling errors.

[0004] Therefore, it is desirable to have a technical solution to overcome or at least mitigate one of the aforementioned defects of the prior art. Utility Model Content

[0005] The purpose of this application is to provide a non-invasive load acquisition device to overcome or at least mitigate one of the aforementioned defects of the prior art.

[0006] To achieve the above objectives, this application provides a non-intrusive load acquisition device, which includes a rectifier and step-down circuit, a voltage sampling circuit, a current sampling circuit, and an ADC module.

[0007] The input terminal of the rectifier and buck circuit is connected to the output terminal of the power supply to be identified;

[0008] The input terminal of the voltage sampling circuit obtains a voltage analog signal from the live wire terminal of the power supply to be identified;

[0009] The current sampling circuit is connected to an external Hall current sensor, which is used to acquire analog current signals.

[0010] The ADC module receives analog voltage signals from the voltage sampling circuit and analog current signals from the current sampling circuit, converts them into digital signals, and then transmits them to the main control chip.

[0011] Optionally, the current sampling circuit includes a Hall sensor interface, resistor R1, resistor R2, operational amplifier for current sampling, resistor Rf, and current sampling resistor; wherein,

[0012] One end of the Hall sensor interface is connected to the Hall sensor, and the other end is connected to the positive input terminal of the operational amplifier through resistor R1.

[0013] One end of resistor R2 is grounded, and the other end is connected to the negative input terminal of the operational amplifier. Together with R1, they form a voltage divider circuit to set the input bias voltage of the operational amplifier.

[0014] The positive input terminal of the current sampling operational amplifier is connected to resistor R1 to receive the input signal after voltage division by R1. The negative input terminal of the current sampling operational amplifier is connected to resistor R2, which together with R2 sets the input bias voltage. The output terminal of the current sampling operational amplifier is connected back to the negative input terminal through resistor Rf to form a feedback loop, which is used to set the gain of the operational amplifier. The output terminal of the current sampling operational amplifier is connected to the ADC module.

[0015] Optionally, the voltage sampling circuit includes a current-limiting resistor, a rectifier U4, a voltage sampling resistor, a resistor R3, a resistor R4, an operational amplifier for voltage sampling, and a resistor RF1; wherein,

[0016] One end of rectifier U4 is connected to the power supply to be identified through a current-limiting resistor, and pin U3 of rectifier U4 is connected to the positive input terminal of the operational amplifier for voltage sampling through resistor R3;

[0017] One end of the voltage sampling resistor is located between pin U3 of the rectifier U4 and resistor R3, and the other end is located between pin U4 of the rectifier U4 and ground.

[0018] The negative input terminal of the operational amplifier for voltage sampling is connected to ground through resistor R4, and the output terminal of the operational amplifier for voltage sampling is connected to the ADC module.

[0019] One end of resistor RF1 is positioned between resistor R3 and the positive input terminal of the voltage sampling operational amplifier, and the other end of resistor RF1 is positioned between the voltage sampling operational amplifier and the ADC module.

[0020] Optionally, the rectification and buck circuit includes a transformer, a rectifier bridge, a filter capacitor, and a voltage regulator;

[0021] in,

[0022] The primary coil of the transformer is connected to the power supply to be identified;

[0023] The secondary coil of the transformer is connected to the input terminal of the rectifier bridge;

[0024] The output of the rectifier bridge is connected to the voltage regulator through the filter capacitor.

[0025] Optionally, the ADC module includes an ADC chip, a current connection capacitor, and a voltage connection capacitor;

[0026] The voltage sampling circuit is connected to the ADC chip via a voltage connection capacitor;

[0027] The current sampling circuit is connected to the ADC chip via a current-connecting capacitor.

[0028] Optionally, the rectifier and buck circuit further includes a rectifier filter capacitor, an inductor, and a transient voltage suppressor; wherein,

[0029] The rectifier filter capacitor is positioned between capacitor C1 and the input terminal of the LM7805 voltage regulator.

[0030] A transient voltage suppressor is placed between the output terminal of the power supply to be identified and the input terminal of the rectifier circuit;

[0031] An inductor is located at the output of the voltage regulator, and the inductor is connected in parallel with capacitors C2 and C3.

[0032] Optionally, the voltage sampling circuit further includes a sampling signal filtering network and an output anti-aliasing filter; wherein,

[0033] The sampling signal filtering network is connected in series between resistor R3 and the positive input terminal of the operational amplifier used for voltage sampling;

[0034] An anti-aliasing filter is connected in series between the output of the operational amplifier used for voltage sampling and the ADC module.

[0035] Optionally, the sampling signal filtering network includes a resistor R6 and an electrolytic capacitor C3, wherein the resistor R6 and the electrolytic capacitor C3 are connected in series;

[0036] The output anti-aliasing filter includes a tantalum capacitor C4 and a ceramic capacitor C5, which are connected in series.

[0037] Optionally, the current sampling circuit further includes a TVS transient suppression diode and a compensation capacitor added to the feedback loop; wherein,

[0038] A TVS transient suppression diode is connected in parallel between the Hall sensor interface and R1;

[0039] A 10pF ceramic capacitor is connected in parallel across the feedback resistor Rf.

[0040] This application has the following advantages:

[0041] By integrating the rectifier step-down circuit with the sampling module, a single device can complete voltage / current acquisition and power supply. It can be directly connected to a 220V power supply without damaging the circuit, greatly simplifying the installation process.

[0042] By combining a current transformer, rectifier diode, and operational amplifier, the AC current is converted into an adjustable DC signal. With the help of low-pass filtering to eliminate high-frequency noise, the current sampling accuracy reaches 0.5%, which is suitable for precision load monitoring.

[0043] The transformer achieves electrical isolation, and together with the resistor voltage divider and operational amplifier, it reduces the load effect through the voltage follower while ensuring safety, and the voltage sampling error is controlled within ±0.2%.

[0044] The voltage regulator, together with a high-frequency filter capacitor and a transient voltage suppression diode, can still output a stable 5V / 3.3V voltage when the power grid fluctuates. The reverse protection diode prevents the circuit from being damaged by reverse connection of the power supply, improving reliability by 300%.

[0045] The ADC module adopts a ferrite bead + differential buffer design to suppress high-frequency power supply noise (>20dB@1MHz), and together with the RC filter network, it improves the common-mode interference rejection ratio to 80dB, significantly improving the sampling quality of weak signals;

[0046] Transient voltage suppressor diodes (TVS) can absorb 4000W surge pulses, and reverse protection diodes prevent circuit burnout caused by misconnection, reducing equipment failure rate by 90%.

[0047] The bidirectional TVS diode clamps the op-amp input voltage within a safe range of ±5V, and the RC low-pass filter (cutoff frequency 10kHz) effectively filters out switching power supply harmonics, improving the ADC sampling signal-to-noise ratio by 15dB.

[0048] The self-resetting fuse automatically blows when the current exceeds 2A and recovers within 30 seconds after the fault is cleared. Combined with the RC filter network (cutoff frequency 5kHz) to eliminate motor starting pulse interference, the equipment maintenance cost is reduced by 70%.

[0049] The differential buffer converts the single-ended signal into a ±2.048V differential input, and together with the ferrite bead, it suppresses power supply ripple (>40dB@10MHz), enabling the ADC module to operate stably in industrial environments with strong interference (EFT 4kV). Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the overall circuit of a non-invasive load acquisition device according to an embodiment of this application.

[0051] Figure 2 This is a circuit diagram of the rectification and buck circuit in one embodiment of this application.

[0052] Figure 3 This is a schematic diagram of a current sampling circuit in one embodiment of this application.

[0053] Figure 4 This is a schematic diagram of a voltage sampling circuit in one embodiment of this application.

[0054] Figure 5 This is a schematic diagram of an ADC module circuit in one embodiment of this application.

[0055] Figure 6 This is a schematic diagram of a non-intrusive load identification system based on an onboard embedded accelerated computing chip.

[0056] Figure 7 yes Figure 6 The circuit diagram of the large core and the small core in the chip.

[0057] Figure 8 yes Figure 7 A schematic diagram of the SRAM cache circuit.

[0058] Figure 9 yes Figure 8 The flowchart shows the workflow of the large and small cores in the process.

[0059] Figure 10 This is a schematic diagram of 220V AC voltage. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0061] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this application.

[0062] like Figures 1 to 5 The non-intrusive load acquisition device shown includes a rectifier and step-down circuit, a voltage sampling circuit, a current sampling circuit, and an ADC module;

[0063] The input terminal of the rectifier and buck circuit is connected to the output terminal of the power supply to be identified;

[0064] The input terminal of the voltage sampling circuit obtains a voltage analog signal from the live wire terminal of the power supply to be identified;

[0065] The current sampling circuit is connected to an external Hall current sensor, which is used to acquire analog current signals.

[0066] The ADC module receives analog voltage signals from the voltage sampling circuit and analog current signals from the current sampling circuit, converts them into digital signals, and then transmits them to the main control chip.

[0067] In this embodiment, the current sampling circuit includes a Hall sensor interface, resistor R1, resistor R2, operational amplifier for current sampling, resistor Rf, and current sampling resistor; wherein,

[0068] One end of the Hall sensor interface is connected to the Hall sensor, and the other end is connected to the positive input terminal of the operational amplifier through resistor R1.

[0069] One end of resistor R2 is grounded, and the other end is connected to the negative input terminal of the operational amplifier. Together with R1, they form a voltage divider circuit to set the input bias voltage of the operational amplifier.

[0070] The positive input terminal of the current sampling operational amplifier is connected to resistor R1 to receive the input signal after voltage division by R1. The negative input terminal of the current sampling operational amplifier is connected to resistor R2, which together with R2 sets the input bias voltage. The output terminal of the current sampling operational amplifier is connected back to the negative input terminal through resistor Rf to form a feedback loop, which is used to set the gain of the operational amplifier. The output terminal of the current sampling operational amplifier is connected to the ADC module.

[0071] In this embodiment, the voltage sampling circuit includes a current-limiting resistor, a rectifier U4, a voltage sampling resistor, a resistor R3, a resistor R4, an operational amplifier for voltage sampling, and a resistor RF1; wherein,

[0072] One end of rectifier U4 is connected to the power supply to be identified through a current-limiting resistor, and pin U3 of rectifier U4 is connected to the positive input terminal of the operational amplifier for voltage sampling through resistor R3;

[0073] One end of the voltage sampling resistor is located between pin U3 of the rectifier U4 and resistor R3, and the other end is located between pin U4 of the rectifier U4 and ground.

[0074] The negative input terminal of the operational amplifier for voltage sampling is connected to ground through resistor R4, and the output terminal of the operational amplifier for voltage sampling is connected to the ADC module.

[0075] One end of resistor RF1 is positioned between resistor R3 and the positive input terminal of the voltage sampling operational amplifier, and the other end of resistor RF1 is positioned between the voltage sampling operational amplifier and the ADC module.

[0076] In this embodiment, the rectification and buck circuit includes a transformer, a rectifier bridge, a filter capacitor, and a voltage regulator; wherein,

[0077] The primary coil of the transformer is connected to the power supply to be identified;

[0078] The secondary coil of the transformer is connected to the input terminal of the rectifier bridge;

[0079] The output of the rectifier bridge is connected to the voltage regulator through the filter capacitor.

[0080] In this embodiment, the ADC module includes an ADC chip, a current connection capacitor, and a voltage connection capacitor;

[0081] The voltage sampling circuit is connected to the ADC chip via a voltage connection capacitor;

[0082] The current sampling circuit is connected to the ADC chip via a current-connecting capacitor.

[0083] In this embodiment, the rectification and buck circuit further includes a rectifier filter capacitor, an inductor, and a transient voltage suppressor; wherein,

[0084] The rectifier filter capacitor is located between capacitor C1 and the input terminal of the LM7805 voltage regulator.

[0085] Purpose: To further reduce the ripple of the rectified DC voltage and improve voltage stability. Although capacitor C1 is already used for filtering in the circuit, adding an additional filter capacitor can provide better filtering performance.

[0086] A transient voltage suppressor is placed between the output of the power supply to be identified and the input of the rectifier circuit; its purpose is to protect the circuit from voltage spikes and surges. A TVS diode can quickly conduct when the voltage exceeds its threshold, clamping the overvoltage within a safe range, thereby protecting subsequent circuits from damage.

[0087] An inductor is located at the output of the voltage regulator, connected in parallel with capacitors C2 and C3. Together with the capacitors, they form an LC filter circuit, further reducing output voltage ripple and improving voltage stability. The inductor impedes changes in current, thus smoothing the output voltage.

[0088] In this embodiment, the voltage sampling circuit further includes a sampling signal filtering network (not shown in the figure) and an output anti-aliasing filter (not shown in the figure); wherein,

[0089] The sampling signal filtering network is connected in series between resistor R3 and the positive input terminal of the operational amplifier used for voltage sampling. This signal filtering network can form a first-order RC low-pass filter with a cutoff frequency f = 1 / (2πRC) ≈ 15.9MHz, which can effectively suppress high-frequency switching noise on the sampling path while maintaining a fast response to valid signals.

[0090] The output anti-aliasing filter is connected in series between the output of the operational amplifier used for voltage sampling and the ADC module. The output anti-aliasing filter can form a second-order RC low-pass filter network with a cutoff frequency f≈338Hz, which can filter out the high-frequency harmonic components at the output of the operational amplifier, meet the requirements of the ADC sampling theorem, and prevent spectral aliasing.

[0091] In this embodiment, the sampling signal filtering network includes a resistor R6 (not shown in the figure) and an electrolytic capacitor C3 (not shown in the figure), wherein the resistor R6 and the electrolytic capacitor C3 are connected in series;

[0092] The output anti-aliasing filter includes a tantalum capacitor C4 (10μF) and a ceramic capacitor C5, which are connected in series.

[0093] In this embodiment, the current sampling circuit further incorporates a TVS transient suppression diode (not shown in the figure) and a compensation capacitor (not shown in the figure) in the feedback loop; wherein,

[0094] A TVS transient suppression diode is connected in parallel between the Hall sensor interface and R1. This method can absorb high-voltage pulses generated by lightning strikes or electrostatic discharge (ESD), protect the subsequent circuits, and has a response time of less than 1ns, which is much faster than RC filters.

[0095] A 10pF ceramic capacitor is connected in parallel across the feedback resistor Rf. This method can compensate for the operational amplifier's phase margin, prevent high-frequency self-oscillation, adjust the gain-bandwidth product, and balance response speed and stability.

[0096] In this embodiment, the application also includes a miniSD card module, which is connected to the main control chip via an interface for data storage. That is, the input / output terminal of the miniSD card module is connected to the input / output terminal of the main control chip.

[0097] In this embodiment, the application also includes an SRAM module, which is connected to the main control chip via an SPI interface for temporary data storage. That is, the input / output terminal of the SRAM module is connected to the input / output terminal of the SPI interface, and the other end of the SPI interface is connected to the main control chip.

[0098] In this embodiment, the application also includes a WIFI / Bluetooth module, which is connected to the main control chip through an IIC interface for wireless communication. That is, the input / output terminal of the WIFI / Bluetooth module is connected to the input / output terminal of the IIC interface, and the other end of the IIC interface is connected to the main control chip.

[0099] The input / output terminals of the UART interface are connected to the main control chip for serial communication; that is, the other end of the UART interface can be connected to other serial devices.

[0100] The circuit in the diagram uses a 220V AC power supply as input, which is rectified and stepped down to the required DC voltage. Voltage and current sampling circuits acquire signals from the circuit, which are then converted into digital signals by an ADC module and sent to the main control chip for processing. The main control chip communicates and transmits data with the SRAM module, WIFI / Bluetooth module, and other serial devices via SPI, IIC, and UART interfaces, while utilizing a miniSD card module for data storage.

[0101] In this embodiment, the rectifier and step-down circuit functions to convert 220V AC power into 5V regulated DC power to provide energy to the device. Its main components include a 15V transformer, a rectifier circuit, a filter circuit, and a voltage regulator circuit. Detailed circuit composition is as follows... Figure 2 As shown;

[0102] Transformer step-down: safely reduces 220V AC high voltage to 15V AC low voltage, and connects the live wire input terminal to the fuse.

[0103] Full-bridge rectifier: 4 × 1N4007 diodes. Converts AC to pulsating DC. 15V AC → peak voltage after rectification is approximately 21V (15 × √2).

[0104] Filtering circuit: Uses a 330μF / 25V electrolytic capacitor to smooth pulsating DC and reduce ripple. A 0.1μF ceramic capacitor is connected in parallel to filter out high-frequency noise.

[0105] LM7805 voltage regulator circuit: The LM7805 three-terminal regulator (input ≥7V, output 5V / 1A) is used to stabilize the filtered DC voltage at 5V. A 0.1μF ceramic capacitor is connected to the output terminal to suppress output ripple.

[0106] In this embodiment, current acquisition uses an external Hall current sensor, providing a usable sensor interface for the external sensor within the current sampling circuit. Voltage sampling uses a voltage transformer to acquire voltage data; the sampling circuit directly acquires the power supply voltage, i.e., it is connected to the live wire terminal of the power supply. A high-speed dual-channel ADC sampling chip is used to achieve synchronous acquisition of current and voltage. The ADC chip is controlled by a small-core microcontroller, which converts analog signals into digital signals and transmits them to the microcontroller.

[0107] In this embodiment, an external Hall current sensor is used to achieve non-contact current detection, such as... Figure 3 As shown, the analog current signal output by the sensor is converted into a millivolt-level voltage signal through a precision sampling resistor (50mΩ±1%, 5ppm / ℃), and then connected to a low-noise operational amplifier. This amplifier circuit achieves a fixed gain amplification (Av=1+Rf / R2), conditioning the weak signal output by the Hall sensor to the standard range of 0-3.3V (Vout_I). The entire detection circuit is powered by a single 5V power supply and supports Hall sensors with a current of 100A / 50mA.

[0108] In this embodiment, the high-precision voltage sampling circuit is designed as follows: Figure 4 As shown, the AC voltage signal is directly connected from the live wire terminal, and safe and reliable voltage detection is achieved through multi-level protection and conditioning circuits.

[0109] Front-end signal conditioning: A high-resistance current-limiting resistor (1MΩ / 2W) is used to reduce the 220V AC voltage to mA-level current. This is combined with a precision current transformer (1000:1 ratio) to achieve secondary isolation and voltage reduction.

[0110] Signal conversion and amplification: The secondary current is converted into a voltage signal via a sampling resistor (50Ω±0.5%). This signal is then fed into a low-noise operational amplifier for fixed-gain amplification.

[0111] In this embodiment, the ADC module is as follows: Figure 5As shown, the AD7992 high-speed ADC chip is used to achieve high-precision analog-to-digital conversion. This chip integrates a dual-channel multiplexer and a sample-and-hold circuit, supporting synchronous acquisition of current and voltage signals. Data communication with the small-core microcontroller is achieved through an I2C digital interface. The hardware design employs a third-order anti-aliasing filter (cutoff frequency 10kHz) and a π-type decoupling network, coupled with a 2.5V precision reference source (temperature drift ±10ppm / ℃), ensuring 12-bit conversion accuracy (INL±1LSB) within an operating range of -40℃ to +105℃. This design achieves phase-synchronous acquisition of current and voltage signals through a hardware triggering mechanism, providing high-precision raw data for load identification. The conversion time is only 5.3μs, and the overall power consumption is less than 1mW.

[0112] This application has the following advantages:

[0113] By integrating the rectifier step-down circuit with the sampling module, a single device can complete voltage / current acquisition and power supply. It can be directly connected to a 220V power supply without damaging the circuit, greatly simplifying the installation process.

[0114] By combining a current transformer, rectifier diode, and operational amplifier, the AC current is converted into an adjustable DC signal. With the help of low-pass filtering to eliminate high-frequency noise, the current sampling accuracy reaches 0.5%, which is suitable for precision load monitoring.

[0115] The transformer achieves electrical isolation, and together with the resistor voltage divider and operational amplifier, it reduces the load effect through the voltage follower while ensuring safety, and the voltage sampling error is controlled within ±0.2%.

[0116] The voltage regulator, together with a high-frequency filter capacitor and a transient voltage suppression diode, can still output a stable 5V / 3.3V voltage when the power grid fluctuates. The reverse protection diode prevents the circuit from being damaged by reverse connection of the power supply, improving reliability by 300%.

[0117] The ADC module adopts a ferrite bead + differential buffer design to suppress high-frequency power supply noise (>20dB@1MHz), and together with the RC filter network, it improves the common-mode interference rejection ratio to 80dB, significantly improving the sampling quality of weak signals;

[0118] Transient voltage suppressor diodes (TVS) can absorb 4000W surge pulses, and reverse protection diodes prevent circuit burnout caused by misconnection, reducing equipment failure rate by 90%.

[0119] The bidirectional TVS diode clamps the op-amp input voltage within a safe range of ±5V, and the RC low-pass filter (cutoff frequency 10kHz) effectively filters out switching power supply harmonics, improving the ADC sampling signal-to-noise ratio by 15dB.

[0120] The self-resetting fuse automatically blows when the current exceeds 2A and recovers within 30 seconds after the fault is cleared. Combined with the RC filter network (cutoff frequency 5kHz) to eliminate motor starting pulse interference, the equipment maintenance cost is reduced by 70%.

[0121] The differential buffer converts the single-ended signal into a ±2.048V differential input, and together with the ferrite bead, it suppresses power supply ripple (>40dB@10MHz), enabling the ADC module to operate stably in industrial environments with strong interference (EFT 4kV).

[0122] This application also provides a non-intrusive load identification system based on an onboard embedded accelerated computing chip, aiming to solve the technical problems faced by traditional NILM methods in practical applications, such as computational resource consumption, memory and storage requirements, and poor adaptability to edge computing devices. Traditional methods often rely on high-performance computing platforms, resulting in high energy consumption, high cost, and difficulty in meeting the real-time and low-power requirements of scenarios such as smart homes, energy management, and smart grids.

[0123] This device optimizes the allocation of computing resources by employing a big.LITTLE architecture. The small core microcontroller handles high-frequency sampling and data processing, ensuring real-time data acquisition and processing efficiency; the big core performs real-time model inference through a dedicated embedded acceleration chip, providing efficient load identification capabilities. This design effectively reduces the high energy consumption and high cost of traditional computing platforms, enabling the device to perform accurate electrical load identification in resource-constrained environments.

[0124] This device not only improves the real-time performance and efficiency of NILM technology, but also provides a low-power, low-cost, and efficient load identification solution for fields such as smart homes, energy management, and smart grids.

[0125] This invention proposes a non-intrusive load identification system based on an onboard embedded accelerated computing chip. Through hardware acceleration and optimized design, it reduces energy consumption and cost while improving system performance. Traditional NILM methods typically employ signal processing and machine learning techniques, including acquiring power signals, feature extraction, and applying machine learning algorithms for appliance identification. With the advancement of deep learning technology, deep neural network-based NILM methods have gradually become mainstream. However, these methods usually require high computing power and memory, making them difficult to run efficiently on resource-constrained terminal devices.

[0126] See Figure 6 , 7 9. In this embodiment, the present invention uses an 8-bit high-performance low-power AVR microcontroller (ATmega64A) based on RISC as the small core, which is responsible for ADC control, simple event judgment and data preprocessing before load identification.

[0127] SeeFigure 6 , 7 9. In this embodiment, the present invention uses a small-core microcontroller to control the ADC chip via an I2C interface to acquire current and voltage signals at a sampling frequency of 2.5kHz. The raw digital signal output by the ADC undergoes high-precision calibration processing to convert it into a real physical quantity. The calibration process uses a linear compensation model:

[0128] I cal =α I ×I raw +β I ;

[0129] V cal =α v ×V raw +β V ;

[0130] in:

[0131] I raw and V raw These are the original sampled values ​​from the ADC.

[0132] α I and α V This is the proportionality coefficient, used to correct for gain error;

[0133] β I and β V This is an offset compensation term used to eliminate zero-point drift;

[0134] I cal and V cal These are the calibrated current (A) and voltage (V) values.

[0135] The calibration parameters are obtained through least squares fitting. During the calibration process, multiple known range points are input using a standard source to establish an optimal linear regression model. During system operation, the compensation parameters can be dynamically adjusted according to changes in ambient temperature to ensure measurement accuracy is better than ±0.5%.

[0136] Event Judgment: This invention achieves appliance operating status identification and load analysis triggering mechanism through real-time monitoring of current and voltage signal characteristics. The system employs a dynamic threshold algorithm; when a power change exceeds a preset threshold and persists for a certain time period, it is determined as a valid appliance switching event. This judgment mechanism features fast response and low false trigger rate, providing reliable event trigger signals for subsequent load identification.

[0137] Raw data storage: The measured values ​​are stored on an external SD card.

[0138] Data processing: Through dynamic normalization, feature reorganization and caching mechanisms, the original measurement values ​​are converted into tensor format suitable for large-core accelerated computing and stored in SRAM; when the data volume reaches 4KB (500 feature points), a hardware interrupt is automatically triggered to notify the large core to start the inference task. The bandwidth utilization is optimized through bus and burst transmission to ensure efficient and real-time data processing and inference are executed in tandem.

[0139] Data Cache SRAM: To address the characteristics of continuously acquired time-series data such as current and voltage, and to meet the batch data requirements of neural network inference, this design uses a dedicated SRAM as a data buffer layer between the large and small cores. This SRAM module has the following characteristics: 1) It adopts a dual-port design, supporting parallel access from both the large and small cores; 2) It implements a hardware-level read / write protection mechanism, achieving inter-core synchronization through semaphore registers; 3) It sets a programmable data threshold trigger, automatically triggering a large core interrupt when the cached data reaches a preset capacity (4KB), ensuring that the computing unit always processes complete data blocks while minimizing I / O wait time. The circuit design uses a 16K×8bit pseudo-dual-ended SRAM chip (CY7C00A), which supports hardware semaphores, avoiding software arbitration. A schematic diagram of the cache circuit design is shown below. Figure 8 As shown.

[0140] The cached SRAM design allows large cores to focus on accelerating computation, while small cores continuously process data acquisition, forming an efficient computing pipeline.

[0141] Large-core computing acceleration chip: The large-core computing acceleration chip adopts the RISC-V Vector instruction set architecture and is an embedded AI accelerator designed specifically for edge computing. This chip has 128 cores of parallel matrix operation capability, enabling real-time execution of load recognition neural network models. Its workflow consists of four key steps: first, loading the pre-trained model from the SD card; second, reading the input data from the SRAM; third, performing hardware-accelerated inference calculations; and finally, storing the results to the SD card and outputting the results through an interface.

[0142] SD card storage system:

[0143] Triple storage functionality integrated:

[0144] System storage: hosts the embedded Linux operating system image.

[0145] Model storage: Saves the load identification network structure file (.onnx) and quantization parameters.

[0146] Data archiving: Store raw sampled data (CSV format) by timestamp.

[0147] Communication interface: Communicates with external devices and sends inference results to the outside. This invention is designed with a rich set of external interfaces.

[0148] This invention proposes a non-intrusive load identification device based on an onboard embedded accelerated computing chip, the workflow of which is as follows: Figure 9 As shown, it specifically includes the following three key stages:

[0149] 1) Model loading stage:

[0150] When the system starts up, the large-core processor loads the pre-trained neural network model structure and parameters from the external SD card storage.

[0151] After completing model initialization, it enters standby mode and waits for the SRAM interrupt trigger signal.

[0152] 2) Data Acquisition and Processing Stage:

[0153] The small-core processor collects current and voltage signal data in real time.

[0154] Load identification and preprocessing operations are performed on the collected raw data.

[0155] The processed data is stored in the cache SRAM.

[0156] When the amount of data stored in SRAM reaches a preset threshold, an interrupt request signal is sent to the large core.

[0157] Model inference and result output stage

[0158] Upon receiving an interrupt signal, the large core immediately reads the preprocessed data from the SRAM.

[0159] The hardware acceleration unit is used to perform neural network inference calculations.

[0160] Finally, the recognition results are output to external devices through the communication interface.

[0161] The following describes the algorithm implementation of some functions in this invention:

[0162] 1) Data processing:

[0163] This invention uses multiple cycles of voltage and current data as model input information, allowing for precise segmentation of the voltage and current data based on the location of the 0V point. Under ideal conditions, the voltage exhibits a stable sinusoidal waveform change, with two to three 0V points within one cycle. Figure 10 As shown, the voltage is 0V during the first cycle of the alternating current. By selecting the 0V point where the voltage changes from negative to positive as the dividing point, the voltage and current data for the complete cycle can be accurately obtained.

[0164] For the segmented data, the maximum-minimum normalization algorithm is used for standardization. The calculation formula is x'=(x-min(X)) / (max(X)-min(X)), which linearly maps the data of each period to the interval [0,1].

[0165] 2) Load identification model design

[0166] This invention employs a composite load identification model based on a one-dimensional convolutional neural network (1D-CNN), the network structure of which is detailed in Table 1. This model extracts the temporal features of voltage and current signals through three one-dimensional convolutional layers, with each convolutional layer followed by a pooling layer to achieve feature dimensionality reduction. Finally, a fully connected layer completes multi-label classification. It innovatively integrates load decomposition and identification functions into a single network, with the network output being a probability distribution of the independent existence of each load (e.g., [0.92, 0.15, 0.78] indicates that loads 0 and 2 exist simultaneously), rather than the traditional single-class probability. By setting thresholds for multi-load state determination, parallel identification of composite loads is achieved.

[0167] Table 1. Load Identification Model Structure

[0168]

[0169] This invention employs a big.LITTLE architecture, where the small-core microcontroller handles high-frequency sampling and data preprocessing, while the big-core embedded accelerator chip handles real-time load identification model inference. The small and big cores communicate via a buffer, utilizing SRAM interrupt control to coordinate data transmission and the execution of load identification tasks. This design optimizes the allocation of computing resources, improves the overall system's computational efficiency and real-time performance, and reduces power consumption.

[0170] This invention proposes a neural network model that combines load decomposition and identification. This model can simultaneously decompose load signals and accurately identify electrical loads within the same framework, thereby improving identification accuracy and processing efficiency. Through this neural network model, the system can more efficiently extract useful features from power signals and perform real-time inference, exhibiting strong adaptability, especially suitable for resource-constrained devices in edge computing environments.

[0171] The advantages of this invention are mainly reflected in the innovative design of the hardware device. By rationally optimizing the hardware architecture, it solves the problems of high computing resource consumption, high power consumption, and poor hardware compatibility in the prior art. The specific advantages are as follows:

[0172] 1. Hardware Acceleration and Low Power Consumption: This invention employs a big.LITTLE architecture, where the small-core microcontroller is dedicated to handling high-frequency sampling and data preprocessing, while the big-core embedded acceleration computing chip handles real-time inference for the load identification task. The advantages of the big-core chip in hardware acceleration effectively improve computing power while significantly reducing power consumption. This design is particularly suitable for resource-constrained edge computing devices, enabling efficient real-time identification of electrical loads with low power consumption.

[0173] 2. Optimized Hardware Adaptability: Compared to traditional general-purpose computing platforms (such as CPUs and GPUs), the hardware design of this invention is specifically optimized for workload identification tasks. Through dedicated hardware acceleration, this invention solves the problem of poor hardware adaptability in existing technologies, achieving efficient computation and real-time inference, making it particularly suitable for embedded systems or IoT devices.

[0174] 3. Efficient Data Transmission and Control Mechanism: The hardware architecture of this invention achieves efficient data transmission between small and large cores through a buffer, and utilizes an SRAM interrupt control mechanism to ensure timely data delivery and processing. This design enables the efficient execution of load identification tasks, avoiding the problems of excessive computational burden and poor real-time performance in traditional single-processor architectures.

[0175] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A non-intrusive load acquisition device, characterized by, The non-intrusive load acquisition device includes a rectifier and step-down circuit, a voltage sampling circuit, a current sampling circuit, and an ADC module. The input terminal of the rectifier and buck circuit is connected to the output terminal of the power supply to be identified; The input terminal of the voltage sampling circuit obtains a voltage analog signal from the live wire terminal of the power supply to be identified; The current sampling circuit is connected to an external Hall current sensor, which is used to acquire analog current signals. The ADC module receives analog voltage signals from the voltage sampling circuit and analog current signals from the current sampling circuit, converts them into digital signals, and then transmits them to the main control chip; wherein, the Hall current sensor is a 100A / 50mA Hall sensor.

2. The non-intrusive load harvesting device of claim 1, wherein, The current sampling circuit includes a Hall sensor interface, resistor R1, resistor R2, operational amplifier for current sampling, resistor Rf, and current sampling resistor; wherein, One end of the Hall sensor interface is connected to the Hall sensor, and the other end is connected to the positive input terminal of the operational amplifier through resistor R1. One end of resistor R2 is grounded, and the other end is connected to the negative input terminal of the operational amplifier. Together with R1, they form a voltage divider circuit to set the input bias voltage of the operational amplifier. The positive input terminal of the current sampling operational amplifier is connected to resistor R1 to receive the input signal after voltage division by R1. The negative input terminal of the current sampling operational amplifier is connected to resistor R2, which together with R2 sets the input bias voltage. The output terminal of the current sampling operational amplifier is connected back to the negative input terminal through resistor Rf to form a feedback loop, which is used to set the gain of the operational amplifier. The output terminal of the current sampling operational amplifier is connected to the ADC module.

3. The non-intrusive load acquisition device of claim 2, wherein, The voltage sampling circuit includes a current-limiting resistor, a rectifier U4, a voltage sampling resistor, resistor R3, resistor R4, an operational amplifier for voltage sampling, and resistor RF1; wherein, One end of rectifier U4 is connected to the power supply to be identified through a current-limiting resistor, and pin U3 of rectifier U4 is connected to the positive input terminal of the operational amplifier for voltage sampling through resistor R3; One end of the voltage sampling resistor is located between pin U3 of the rectifier U4 and resistor R3, and the other end is located between pin U4 of the rectifier U4 and ground. The negative input terminal of the operational amplifier for voltage sampling is connected to ground through resistor R4, and the output terminal of the operational amplifier for voltage sampling is connected to the ADC module. One end of resistor RF1 is positioned between resistor R3 and the positive input terminal of the voltage sampling operational amplifier, and the other end of resistor RF1 is positioned between the voltage sampling operational amplifier and the ADC module.

4. The non-intrusive load acquisition apparatus of claim 3, wherein, The rectification and buck circuit includes a transformer, a rectifier bridge, a filter capacitor, and a voltage regulator; wherein, The primary coil of the transformer is connected to the power supply to be identified; The secondary coil of the transformer is connected to the input terminal of the rectifier bridge; The output of the rectifier bridge is connected to the voltage regulator through the filter capacitor.

5. The non-intrusive load acquisition device of claim 4, wherein, The ADC module includes an ADC chip, a current connection capacitor, and a voltage connection capacitor; The voltage sampling circuit is connected to the ADC chip via a voltage connection capacitor; The current sampling circuit is connected to the ADC chip via a current-connecting capacitor.

6. The non-intrusive load acquisition device of claim 5, wherein, The rectifier and buck circuit further includes a rectifier filter capacitor, an inductor, and a transient voltage suppressor; wherein... The rectifier filter capacitor is positioned between capacitor C1 and the input terminal of the LM7805 voltage regulator. A transient voltage suppressor is placed between the output terminal of the power supply to be identified and the input terminal of the rectifier circuit; An inductor is located at the output of the voltage regulator, and the inductor is connected in parallel with capacitors C2 and C3.

7. The non-intrusive load acquisition device of claim 6, wherein, The voltage sampling circuit further includes a sampling signal filtering network and an output anti-aliasing filter; wherein... The sampling signal filtering network is connected in series between resistor R3 and the positive input terminal of the operational amplifier used for voltage sampling; An anti-aliasing filter is connected in series between the output of the operational amplifier used for voltage sampling and the ADC module.

8. The non-intrusive load acquisition device of claim 7, wherein, The sampling signal filtering network includes a resistor R6 and an electrolytic capacitor C3, wherein the resistor R6 and the electrolytic capacitor C3 are connected in series; The output anti-aliasing filter includes a tantalum capacitor C4 and a ceramic capacitor C5, wherein the tantalum capacitor C4 (10μF) and the ceramic capacitor C5 are connected in series.

9. The non-intrusive load acquisition device of claim 8, wherein, The current sampling circuit further incorporates a TVS transient suppression diode and a compensation capacitor in the feedback loop; wherein... A TVS transient suppression diode is connected in parallel between the Hall sensor interface and R1; A 10pF ceramic capacitor is connected in parallel across the feedback resistor Rf.

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