Voltage acquisition system

Abstract

The application provides a voltage acquisition system, comprising: a voltage acquisition module (containing multiple sets of isolated differential amplification circuits connected to the positive and negative electrodes of a single battery cell), an ADC module (a multi-channel synchronous sampling ADC chip), a control processing module (an FPGA or a dual-core MCU outputting a synchronous pulse to the ADC), a data analysis module (a multi-core processor), and an output module (an isolated communication interface and an Ethernet interface). The modules form a one-way real-time processing link in the order of voltage acquisition, ADC, control processing, data analysis, and output. The control processing module can generate a synchronization pulse with a precision of ≤1 μs to trigger the ADC module, enabling multi-channel voltage synchronous acquisition and solving the problem of multi-channel sampling timing deviation. The voltage synchronization precision can reach ±0.01%, ensuring the accuracy of battery consistency analysis.

Description

Technical Field

[0001] This application relates to the field of battery testing technology, specifically to a high-precision multi-channel voltage acquisition hardware system for monitoring the voltage of individual cells in a battery pack, which is particularly suitable for scenarios such as electric vehicle BMS and energy storage battery safety monitoring. Background Technology

[0002] In the field of battery testing for electric vehicles and energy storage systems, real-time synchronous monitoring of the voltage of each cell in the battery pack is a core requirement for assessing battery consistency and safety status (such as overvoltage / undervoltage). However, traditional voltage acquisition systems suffer from the following hardware-level defects:

[0003] 1. Insufficient synchronization.

[0004] The mainstream approach uses CPU time-sharing control of multiple ADCs, relying on software polling to trigger sampling, resulting in timing deviations between channels exceeding 10 ms. Real-world testing shows that this deviation causes consistency analysis errors in series-connected battery packs to reach as high as ±0.5%, making it impossible to accurately locate degraded cells.

[0005] 2. Weak ability to resist common-mode interference.

[0006] In high-voltage battery packs (≥800 V), traditional differential amplifier circuits lack front-end filtering and transient suppression design, resulting in common-mode noise that expands the voltage acquisition error to ±0.1%, which can even trigger overvoltage protection in severe cases.

[0007] 3. System scalability is limited.

[0008] Commercial acquisition chips typically support a maximum of 16 channels, requiring mechanical relays to switch between channels, which introduces contact resistance temperature drift (>100 ppm / ℃), and the switching delay can easily lead to synchronization failure. Utility Model Content

[0009] This application aims to solve at least one technical problem existing in the prior art mentioned above, and proposes a voltage acquisition system that aims to solve the problem of multi-channel sampling timing deviation, so that the voltage synchronization accuracy can reach ±0.01%, thereby ensuring the accuracy of battery consistency analysis.

[0010] This application provides a voltage acquisition system, including:

[0011] The voltage acquisition module includes multiple isolated differential amplifier circuits, each circuit being connected to the positive and negative terminals of a single cell in the battery pack, for acquiring the cell terminal voltage.

[0012] The ADC module is connected to the output of the voltage acquisition module. It uses a multi-channel synchronous sampling ADC chip to synchronously convert the voltage signals of all channels under the control of an external trigger signal.

[0013] The control processing module consists of an FPGA or a dual-core MCU with a built-in hardware timer. Its output is connected to the trigger pin of the ADC module to generate synchronous sampling pulses, and its input receives the conversion data from the ADC module.

[0014] The data analysis module, integrated into the multi-core processor, is connected to the control processing module, and receives raw voltage data in real time and executes anomaly detection algorithms.

[0015] The output module, which includes an isolated communication interface and an Ethernet interface, connects to the output end of the data analysis module and is used to transmit the processing results to the host computer or BMS platform.

[0016] The voltage acquisition module → ADC module → control processing module → data analysis module → output module constitute a unidirectional real-time processing link.

[0017] Furthermore, the differential amplifier circuit of the voltage acquisition module is connected in series with an EMI filter at the front end and in parallel with a TVS diode in the operational amplifier feedback loop.

[0018] Furthermore, the ADC module adopts a daisy-chain cascade architecture, with the main ADC chip triggering the SYNC_IN pin of the slave ADC chip through the SYNC_OUT pin.

[0019] Furthermore, the FPGA of the control processing module has a built-in dual-port RAM, and ADC data is directly written to a designated storage area of ​​the RAM via a parallel bus.

[0020] Furthermore, the data analysis module includes a dedicated hardware comparator that can compare voltage data with a preset overvoltage threshold or a preset undervoltage threshold in real time, and trigger an interrupt when an anomaly is detected.

[0021] Furthermore, the output module's isolated communication interface uses a magnetically coupled isolation chip, and the Ethernet interface integrates a transformer.

[0022] Furthermore, the voltage acquisition module includes a precision resistor voltage divider network, using metal foil resistors with a temperature coefficient of less than 5 ppm / ℃.

[0023] Furthermore, the reference voltage source of the ADC module adopts a low-temperature drift reference chip, and is connected in parallel with a 100 μF tantalum capacitor and a 0.1 μF ceramic capacitor.

[0024] Furthermore, the control processing module includes a DMA controller, through which ADC data is directly transferred to the shared memory of the multi-core processor.

[0025] Furthermore, the input terminal of the voltage acquisition module is equipped with an overcurrent protection circuit consisting of a self-resetting fuse connected in series with a gas discharge tube.

[0026] This application provides a voltage acquisition system, comprising: a voltage acquisition module (including multiple sets of isolated differential amplifier circuits connected to the positive and negative terminals of a single battery cell) and an ADC module (a multi-channel synchronous sampling ADC chip).

[0027] The system comprises a control processing module (FPGA or dual-core MCU, outputting synchronous pulses to the ADC), a data analysis module (multi-core processor), and an output module (isolated communication interface and Ethernet interface). Each module forms a unidirectional real-time processing link in the order of voltage acquisition → ADC → control processing → data analysis → output. The control processing module can generate synchronous pulses with an accuracy of ≤1 μs to trigger the ADC module, enabling multi-channel synchronous voltage acquisition. This solves the problem of multi-channel sampling timing deviation, achieving a voltage synchronization accuracy of ±0.01%, thus ensuring the accuracy of battery consistency analysis. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic block diagram of a voltage acquisition system provided in an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0031] The terms "comprising" or "having," and any variations thereof, in the specification, claims, or drawings of this application are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0032] Traditional voltage acquisition systems lack dedicated synchronous triggering circuits and rely on CPU software scheduling, resulting in asynchronous sampling between channels and distorted battery consistency analysis. The input stage typically lacks transient suppression devices (TVS / LC filters), leading to high-voltage common-mode interference, which degrades measurement accuracy and increases safety risks. Mechanical relay switching introduces additional impedance and delay, causing channel expansion delays and making large-scale battery stack monitoring infeasible. To address these hardware deficiencies, embodiments of this invention provide a high-precision multi-channel voltage acquisition system, focusing on solving the following technical problems.

[0033] 1. How to achieve a multi-channel sampling timing deviation of ≤1 μs through a hardware-level synchronous triggering circuit (FPGA + cascaded ADC).

[0034] 2. How to integrate a common-mode interference suppression circuit (π-type LC+TVS) at the input front end to ensure ±0.01% accuracy.

[0035] 3. How to construct a one-way processing link without relays (acquisition → ADC → FPGA → output) to avoid extended latency.

[0036] refer to Figure 1 One embodiment of this application provides a high-precision multi-channel voltage acquisition system, which may specifically include a voltage acquisition module, a high-precision ADC module, a control processing module, a data analysis module, and an output module.

[0037] 1. Voltage Acquisition Module. It contains multiple sets of isolated differential amplifier circuits, each set of circuits is connected to the positive and negative terminals of a single cell in the battery pack, and is used to acquire the cell terminal voltage and suppress common-mode interference.

[0038] Preferably, the differential amplifier circuit of the voltage acquisition module has an EMI filter (including a π-type LC circuit) connected in series at the front end, and a TVS diode connected in parallel in the operational amplifier feedback loop. Specifically, in a 200 V high-voltage battery pack, the TVS diode clamps the transient overvoltage at the input to ±15 V, and the LC filter attenuates high-frequency noise above 100 MHz. This configuration improves the electromagnetic interference immunity and reduces the voltage acquisition error from ±0.1% to ±0.01%.

[0039] Preferably, the voltage acquisition module includes a precision resistor divider network, employing metal foil resistors (such as Vishay Z201) with a temperature coefficient <5 ppm / ℃. Specifically, the voltage divider circuit uses Z201 resistors, with a voltage division ratio drift of <0.001% in the range of -40 ℃ to 85 ℃. This setting eliminates the influence of temperature drift and ensures measurement accuracy across the entire temperature range.

[0040] Preferably, the input terminal of the voltage acquisition module is equipped with an overcurrent protection circuit consisting of a self-resetting fuse (PPTC) and a gas discharge tube (GDT) connected in series. Specifically, in the event of a misconnection of high voltage to the sampling line, the PPTC can cut off the circuit within 1 ms, and the GDT can absorb a 10kV surge. This configuration can prevent cascading damage to equipment and reduce the system failure rate by 90%.

[0041] 2. High-precision ADC module. It is connected to the output of the voltage acquisition module and uses a multi-channel synchronous sampling ADC chip to synchronously convert the voltage signals of all channels under the control of an external trigger signal.

[0042] Preferably, the high-precision ADC module adopts a daisy-chain cascade architecture, with the main ADC chip triggering the SYNC_IN pin of the slave ADC chips via the SYNC_OUT pin. Specifically, four 24-bit Σ-Δ ADCs (e.g., ADS131M08) are cascaded to achieve 96 channels of synchronous sampling with a synchronization deviation of <50 ns. This configuration overcomes the single-chip channel limitation and supports synchronous monitoring of ultra-large-scale battery stack voltages.

[0043] Preferably, the reference voltage source of the high-precision ADC module uses a low-temperature drift reference chip (e.g., REF5040), connected in parallel with a 100 μF tantalum capacitor and a 0.1 μF ceramic capacitor. Specifically, the REF5040 provides a 2.5 V reference with ±0.05% initial accuracy and 2 ppm / ℃ temperature drift, and the capacitor combination suppresses power supply ripple. This configuration increases the effective number of bits of the ADC to 22.5 bits and reduces quantization noise.

[0044] 3. Control and processing module. It consists of an FPGA or a dual-core MCU with built-in hardware timers. Its output is connected to the trigger pin of the ADC module to generate synchronous sampling pulses, and its input receives the converted data from the ADC module.

[0045] Preferably, the FPGA of the control processing module has a built-in dual-port RAM, and ADC data is directly written to a designated storage area of ​​the RAM via a parallel bus. Specifically, the ADC is connected to the FPGA via a 16-bit parallel interface, and the converted data is stored in real time in the 0x2000-0x2FFF address range of the dual-port RAM. This configuration eliminates the need for a data buffer relay, reducing the transmission latency to less than 10 μs.

[0046] Preferably, the control processing module includes a DMA controller, through which ADC data is directly transferred to the shared memory of the multi-core processor. Specifically, the STM32H7 series MCU's DMA2 writes the ADC data stream to the AXI SRAM in real time, and the CPU only performs flag bit checks. This configuration frees up CPU resources, allowing the system to simultaneously handle 256 channels of data plus SOC computation tasks.

[0047] 4. Data Analysis Module. Integrated into the multi-core processor, it connects to the control processing module via a high-speed bus, receiving raw voltage data in real time and executing anomaly detection algorithms.

[0048] Preferably, the data analysis module includes a dedicated hardware comparator capable of comparing voltage data with preset thresholds (overvoltage / undervoltage values) in real time and triggering an interrupt upon detecting an anomaly. Specifically, when the voltage of a single cell is >4.25 V or <2.8 V, the dedicated hardware comparator outputs a high level to trigger an emergency interrupt on the MCU. This configuration reduces the overvoltage / undervoltage response time to 5 μs, thereby improving the safety of the battery system.

[0049] 5. Output Module. It includes an isolated communication interface (CAN / RS 485) and an Ethernet interface, which are connected to the output of the data analysis module and used to transmit processing results to the host computer or BMS platform.

[0050] Preferably, the output module's isolated communication interface uses a magnetically coupled isolation chip (e.g., ADuM5401), and the Ethernet interface integrates a transformer (e.g., HX1188NL). Specifically, the CAN bus achieves 5000 Vrms electrical isolation through the ADuM5401, and the Ethernet port incorporates an HX1188NL magnetically isolated transformer. This configuration effectively blocks ground loop interference, reducing the communication bit error rate to 10%. ﹣9 the following.

[0051] The voltage acquisition module → ADC module → control processing module → data analysis module → output module constitute a unidirectional real-time processing link, with a synchronous sampling pulse accuracy of ≤1 μs. The control processing module can generate a synchronous pulse with an accuracy of ≤1 μs to trigger the ADC module, enabling multi-channel voltage synchronous acquisition. This solves the problem of multi-channel sampling timing deviation, achieving a voltage synchronization accuracy of ±0.01%, thus ensuring the accuracy of battery consistency analysis.

[0052] Those skilled in the art will understand that the technical features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, without departing from the spirit and teachings of this application, the technical features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, and all such combinations and / or combinations fall within the scope of this application.

[0053] Although this application has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this application without departing from the spirit and scope of the application as defined by the appended claims and their equivalents. Therefore, the scope of this application should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A voltage acquisition system, characterized in that, include: The voltage acquisition module includes multiple isolated differential amplifier circuits, each circuit being connected to the positive and negative terminals of a single cell in the battery pack, for acquiring the cell terminal voltage. The ADC module is connected to the output of the voltage acquisition module. It uses a multi-channel synchronous sampling ADC chip to synchronously convert the voltage signals of all channels under the control of an external trigger signal. The control processing module consists of an FPGA or a dual-core MCU with a built-in hardware timer. Its output is connected to the trigger pin of the ADC module to generate synchronous sampling pulses, and its input receives the conversion data from the ADC module. The data analysis module, integrated into the multi-core processor, is connected to the control processing module, and receives raw voltage data in real time and executes anomaly detection algorithms. The output module, which includes an isolated communication interface and an Ethernet interface, connects to the output end of the data analysis module and is used to transmit the processing results to the host computer or BMS platform. The voltage acquisition module → ADC module → control processing module → data analysis module → output module constitute a unidirectional real-time processing link.

2. The voltage acquisition system according to claim 1, characterized in that, The voltage acquisition module has an EMI filter connected in series at the front end of the differential amplifier circuit, and a TVS diode connected in parallel in the operational amplifier feedback loop.

3. The voltage acquisition system according to claim 1, characterized in that, The ADC module adopts a daisy-chain cascade architecture, and the main ADC chip triggers the SYNC_IN pin of the slave ADC chip through the SYNC_OUT pin.

4. The voltage acquisition system according to claim 1, characterized in that, The FPGA of the control processing module has a built-in dual-port RAM, and ADC data is directly written to a designated storage area of ​​the RAM via a parallel bus.

5. The voltage acquisition system according to claim 1, characterized in that, The data analysis module includes a dedicated hardware comparator that can compare voltage data with a preset overvoltage threshold or a preset undervoltage threshold in real time, and trigger an interrupt when an anomaly is detected.

6. The voltage acquisition system according to claim 1, characterized in that, The output module's isolated communication interface uses a magnetically coupled isolation chip, and the Ethernet interface integrates a transformer.

7. The voltage acquisition system according to claim 1, characterized in that, The voltage acquisition module includes a precision resistor voltage divider network and uses metal foil resistors with a temperature coefficient of less than 5 ppm / ℃.

8. The voltage acquisition system according to claim 1, characterized in that, The reference voltage source of the ADC module adopts a low-temperature drift reference chip, and is connected in parallel with a 100 μF tantalum capacitor and a 0.1 μF ceramic capacitor.

9. The voltage acquisition system according to claim 1, characterized in that, The control processing module includes a DMA controller, through which ADC data is directly transferred to the shared memory of the multi-core processor.

10. The voltage acquisition system according to any one of claims 1-9, characterized in that, The input terminal of the voltage acquisition module is equipped with an overcurrent protection circuit consisting of a self-resetting fuse and a gas discharge tube connected in series.

Images