Package substrate and semiconductor package
By adopting a composite dielectric material packaging method and encapsulating adhesive structure design, the RDL delamination problem caused by moisture absorption of PSPI material in FOPLP was solved, simplifying the packaging process and reducing costs, thus achieving high reliability and high performance semiconductor packaging.
Patent Information
- Application Number
- CN202521481816.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-15
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2035-07-15
AI Technical Summary
In existing FOPLP technology, the PSPI material is prone to moisture absorption, which can lead to RDL delamination. Traditional six-sided packaging methods are complex and costly.
A composite dielectric material encapsulation method is adopted, using silicon dioxide and/or silicon nitride as the multilayer insulating structure, and the encapsulating adhesive structure seals five sides, simplifying the encapsulation process and avoiding moisture absorption of PSPI material. The encapsulating adhesive structure is designed with a width greater than 25μm to provide protection.
This solution addresses the RDL delamination issue caused by moisture absorption in PSPI materials, simplifies the packaging process, reduces costs, and ensures product reliability and performance.
Smart Images
Figure CN224684696U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and semiconductor packaging. Background Technology
[0002] As electronic products become thinner, smaller, and higher-performance, semiconductor packaging technology is constantly innovating. Fan-out surface-level packaging (FOPLP), as a novel packaging technology, has attracted widespread attention due to its ability to provide higher integration and better electrical performance. In FOPLP technology, the packaging substrate is a key component, and its structural design and material selection directly affect the reliability and performance of the package.
[0003] Currently, various packaging structures exist in the semiconductor packaging field. However, some technical problems exist in existing technologies. In particular, in FOPLP technology, the commonly used PSPI (photosensitive polyimide) material is highly hygroscopic. If exposed to the atmosphere, it can cause delamination of the redistribution layer (RDL), severely affecting product reliability. Furthermore, traditional six-sided packaging methods require multiple processes such as board transfer, molding, grinding, and board removal, which not only complicates the process but also significantly increases packaging costs.
[0004] While existing packaging structures have addressed issues of packaging integration and electrical performance to some extent, they lack effective solutions for RDL delamination caused by PSPI material moisture absorption and high costs resulting from complex processes. Therefore, a novel packaging substrate structure is urgently needed that can solve the PSPI material moisture absorption problem, simplify the packaging process, reduce packaging costs, and simultaneously ensure product reliability and performance. Utility Model Content
[0005] The technical problem to be solved by this application is that, in the prior art, PSPI (photosensitive polyimide) material is extremely prone to moisture absorption in FOPLP (fan-out panel-level packaging), and exposure to the atmosphere will cause RDL (redistribution layer) delamination, which seriously affects product reliability. In addition, the traditional six-sided packaging method requires multiple processes (transfer, mold, grinding, and depaneling), which leads to a significant increase in packaging cost. The application provides a packaging substrate and semiconductor packaging.
[0006] This application provides a packaging substrate, including:
[0007] The core insulation structure boasts the highest height.
[0008] A multilayer insulation structure is disposed on the lower surface of the core insulation structure, wherein the multilayer insulation structure is made of silicon dioxide and / or silicon nitride;
[0009] An encapsulating adhesive structure is applied to the sidewalls of the multilayer insulation structure and the core insulation structure. The encapsulating adhesive structure has a first width, which is greater than the first height.
[0010] Multiple wiring structures extend through the core insulation structure and the multilayer insulation structure, and a first connection pad is provided on the lower surface of the wiring structure.
[0011] Optionally, the core insulation structure includes at least one first insulation layer.
[0012] Optionally, the first insulating layer is made of photosensitive polyimide.
[0013] Optionally, the thickness of the first insulating layer is between 3 μm and 20 μm.
[0014] Optionally, the thickness of the multilayer insulation structure is between 2 μm and 10 μm.
[0015] Optionally, the wiring structure is connected to an external connection terminal via a first connection pad.
[0016] Optionally, the first width is the vertical distance between the sidewall of the core insulation structure and the outer edge of the encapsulating adhesive structure, and the first width is greater than 25 μm.
[0017] This application provides a semiconductor package, including: a chip, an interposer, multiple connectors and a molding compound, and also includes the above-mentioned package substrate;
[0018] The upper surface of the wiring structure is provided with a second connection pad;
[0019] The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector.
[0020] The connector extends through the interposer layer and connects the second connection pad to the chip.
[0021] The encapsulation structure encapsulates the chip and partially covers the upper surface of the packaging substrate.
[0022] Optionally, the connector may employ a bump, the diameter of which is between 250μm and 300μm.
[0023] Optionally, the connector is made of solder balls with a diameter of 250μm-300μm.
[0024] This application employs a composite dielectric material encapsulation method, encapsulating the core insulating structure within other insulating materials to prevent contact with the atmosphere and avoid moisture absorption issues. Using silicon dioxide and / or silicon nitride, which possess insulating, oxygen- and moisture-proof properties, as the multilayer insulating structure effectively improves product reliability. By using SiO2 and Si3N4 as the bottom seal and encapsulating adhesive on five sides, the traditional six-sided encapsulation process of disassembly and flipping is avoided, simplifying the process and reducing encapsulation costs. Simultaneously, the flatness and photosensitive properties of the core insulating structure are maintained, allowing for vias smaller than 10µm to meet the requirements of fine-line routing layers. Furthermore, by designing the first width of the encapsulating adhesive structure to be greater than 25µm, cracking due to excessive thinness is prevented, ensuring sufficient sidewall protection to achieve moisture insulation. Compared to existing technologies, this application solves the problem of wiring structure delamination caused by moisture absorption of the core insulating material, simplifies the encapsulation process, reduces costs, and simultaneously ensures product reliability and performance. Attached Figure Description
[0025] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0026] Figure 1 This is a cross-sectional view of one embodiment of the semiconductor package described in this application. Detailed Implementation
[0027] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.
[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0029] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0030] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0031] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.
[0032] The following terms are used in this document.
[0033] FOPLP (Fanout panel level package): Fanout panel level package;
[0034] PSPI (Photosensitive Polyimide): Photosensitive polyimide;
[0035] ABF (Ajinomoto Build-up Film): Ajinomoto's build-up material.
[0036] RDL (redistribution layer): redistribution layer;
[0037] PLP (panel level package): Panel-level packaging;
[0038] Molding compound: molding compound / molding material.
[0039] Example 1
[0040] See Figure 1 As shown, a packaging substrate includes a core insulating structure 2, a multilayer insulating structure 4, an encapsulating adhesive structure 1, and multiple wiring structures 3.
[0041] The core insulation structure 2 has a first height 'a' and includes at least one first insulating layer. The first insulating layer is made of photosensitive polyimide material and has a thickness between 3 μm and 20 μm. In a preferred embodiment, the thickness of the first insulating layer is 5 μm, which ensures sufficient insulation performance without making the overall structure too thick.
[0042] A multilayer insulation structure 4 is disposed on the lower surface of the core insulation structure 2, and is made of silicon dioxide and / or silicon nitride. The thickness c of the multilayer insulation structure 4 is between 2 μm and 10 μm. In a preferred embodiment, the thickness of the multilayer insulation structure 4 is 4 μm, and it is made of a composite material of silicon dioxide and silicon nitride, which provides excellent insulation performance and thermal stability. The multilayer insulation structure 4 is tightly bonded to the core insulation structure 2, forming a complete insulation base.
[0043] The encapsulating structure 1 covers the sidewalls of the multilayer insulation structure 4 and the core insulation structure 2, providing protection and support. The encapsulating structure 1 has a first width b, which refers to the vertical distance between the sidewall of the core insulation structure 2 and the outer edge of the encapsulating structure 1, and the first width b is greater than 25 μm. In a preferred embodiment, the first width b is 30 μm, a design that ensures sufficient mechanical strength and protective effect. Notably, the first width b is greater than the first height a of the core insulation structure 2, a design that allows the encapsulating structure 1 to provide better lateral protection and support.
[0044] Multiple wiring structures 3 penetrate the core insulation structure 2 and the multilayer insulation structure 4, forming an electrical connection channel. The lower surface of each wiring structure 3 is provided with first connection pads 31 for connection to external terminals. The wiring structures 3 are typically made of conductive metal materials, such as copper, aluminum, or gold, to ensure good conductivity. The surface of the first connection pads 31 can be gold-plated or tin-plated to improve soldering performance and oxidation resistance.
[0045] In practical applications, the wiring structure 3 is connected to the external connection terminals via the first connection pad 31 to form a complete circuit system. The external connection terminals can be solder balls, pins, or other forms of connection structures, with the appropriate connection method selected based on the specific application scenario. This connection method enables the package substrate to achieve reliable electrical connections with other electronic components or circuit boards.
[0046] This packaging substrate features a rationally designed structure with all components working collaboratively to provide excellent insulation performance, mechanical strength, and reliable electrical connections. The core insulation structure 2 and the multilayer insulation structure 4 together form a robust insulating base, while the encapsulation structure 1 provides comprehensive protection, and the wiring structure 3 ensures effective transmission of electrical signals. This packaging substrate is suitable for various high-performance electronic devices, especially applications with high requirements for insulation performance and reliability.
[0047] In this embodiment, a composite dielectric material encapsulation method is used to encapsulate the PSPI within other insulating materials, preventing it from contacting the atmosphere and avoiding the moisture absorption problem of the PSPI material. Silicon dioxide and / or silicon nitride, with their insulating, oxygen- and moisture-proof properties, are used as the multilayer insulating structure, effectively improving product reliability. By using SiO2 and Si3N4 for the bottom and molding compound for the five sides, the traditional six-sided encapsulation process of disassembly and flipping is avoided, simplifying the process and reducing packaging costs. Simultaneously, the flatness and photosensitive properties of the PSPI are maintained, allowing for vias smaller than 10µm to meet the requirements of fine-line trace layers. Furthermore, by designing the first width of the encapsulating adhesive structure to be greater than 25µm, the encapsulating adhesive structure is prevented from cracking due to being too thin, ensuring sufficient sidewall protection to achieve moisture insulation. Compared with existing technologies, this application solves the RDL delamination problem caused by PSPI material moisture absorption, simplifies the packaging process, reduces costs, and simultaneously ensures product reliability and performance.
[0048] Example 2
[0049] See Figure 1 As shown, a semiconductor package includes a chip 5, an interposer 6, multiple connectors 7, a molding compound 8, and a packaging substrate.
[0050] The structure of the packaging substrate is the same as described in Embodiment 1, including a core insulating structure 2, a multilayer insulating structure 4, an encapsulating adhesive structure 1, and multiple wiring structures 3. The core insulating structure 2 has a first height 'a' and includes at least one first insulating layer made of photosensitive polyimide material with a thickness between 3 μm and 20 μm. The multilayer insulating structure 4 is disposed on the lower surface of the core insulating structure 2 and is made of silicon dioxide and / or silicon nitride material with a thickness between 2 μm and 10 μm. The encapsulating adhesive structure 1 covers the sidewalls of the multilayer insulating structure 4 and the core insulating structure 2, and has a first width 'b' greater than 25 μm and greater than the first height 'a' of the core insulating structure 2. Multiple wiring structures 3 penetrate the core insulating structure 2 and the multilayer insulating structure 4. A first connecting pad 31 is provided on the lower surface of each wiring structure 3 for connection to external terminals.
[0051] The upper surface of the wiring structure 3 is provided with a second connecting pad for electrical connection with the connector 7. The wiring structure 3 may be made of electroplated copper, a material with excellent conductivity and reliability.
[0052] Intermediate layer 6 is located between the packaging substrate and chip 5, serving as a buffer and connection. Vertical interconnect structures are provided within intermediate layer 6 for electrical connection of connectors 7. These vertical interconnect structures are less than 100 μm wide, enabling high-density electrical interconnection. In a preferred embodiment, the width of the vertical interconnect structures is 80 μm, a size that meets both electrical performance requirements and the needs of miniaturized packaging. Intermediate layer 6 uses a filler material with good insulation properties and thermal stability.
[0053] The connector 7 extends through the interposer layer 6, connecting the second bonding pad and the chip 5 to form a complete electrical path. In a preferred embodiment, the connector 7 is a bump with a diameter between 250 μm and 300 μm. In another preferred embodiment, the connector 7 is a solder ball with a diameter also between 250 μm and 300 μm. This size of connector 7 ensures both sufficient mechanical strength and meets electrical performance requirements.
[0054] The molding compound 8 encapsulates the chip 5 and partially covers the upper surface of the packaging substrate, providing protection and support. The molding compound 8 is typically made of epoxy resin, which has good insulation properties, mechanical strength, and heat resistance.
[0055] The semiconductor package may also include at least one surface-mount passive component disposed on the upper surface of the core insulating structure 2 and electrically connected to the wiring structure 3. These passive components may be resistors, capacitors, or inductors, etc., used to implement specific circuit functions and improve the integration and performance of the package.
[0056] This semiconductor package structure is rationally designed, with all components working together to provide excellent electrical performance, mechanical strength, and reliability. The package substrate provides a robust foundation, the interposer 6 and connector 7 ensure a reliable connection between the chip 5 and the substrate, and the molding compound 8 provides comprehensive protection. This semiconductor package is suitable for various high-performance electronic devices, especially applications with high requirements for integration and reliability.
[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A packaging substrate, characterized in that, include: The core insulation structure has the highest height. A multilayer insulation structure is disposed on the lower surface of the core insulation structure, and the multilayer insulation structure is made of silicon dioxide or silicon nitride. An encapsulating adhesive structure is applied to the sidewalls of the multilayer insulation structure and the core insulation structure. The encapsulating adhesive structure has a first width, which is greater than the first height. Multiple wiring structures extend through the core insulation structure and the multilayer insulation structure, and a first connection pad is provided on the lower surface of the wiring structure.
2. The packaging substrate according to claim 1, characterized in that, The core insulation structure includes at least one first insulation layer.
3. The packaging substrate according to claim 2, characterized in that, The first insulating layer is made of photosensitive polyimide.
4. The packaging substrate according to claim 2 or 3, characterized in that, The thickness of the first insulating layer is between 3 μm and 20 μm.
5. The packaging substrate according to claim 1, characterized in that, The thickness of the multilayer insulation structure is between 2 μm and 10 μm.
6. The packaging substrate according to claim 1, characterized in that, The wiring structure is connected to external connection terminals via a first connection pad.
7. The packaging substrate according to claim 1, characterized in that, The first width is the vertical distance between the sidewall of the core insulation structure and the outer edge of the encapsulating adhesive structure, and the first width is greater than 25 μm.
8. A semiconductor package, comprising: A chip, an interposer, multiple connectors, and a molding compound, characterized in that it further comprises the packaging substrate according to any one of claims 1-7; The upper surface of the wiring structure is provided with a second connection pad; The interposer layer is located between the packaging substrate and the chip, and the interposer layer has a vertical interconnect structure inside, which is electrically connected to the connector. The connector extends through the interposer layer and connects the second connection pad to the chip. The molding compound encapsulates the chip and partially covers the upper surface of the packaging substrate.
9. The semiconductor package according to claim 8, characterized in that, The connector uses a bump, the diameter of which is between 250μm and 300μm.
10. The semiconductor package according to claim 8, characterized in that, The connector uses solder balls with a diameter of 250μm-300μm.