Packaging structure

Abstract

A packaging structure includes a first chip, a first bonding surface including an inorganic layer and a plurality of first metal structures, the first bonding surface including a first bonding region and a second bonding region; a second chip located on the first bonding region; and a third chip located on the second bonding region, the second chip and the third chip each including a second bonding surface including a polymer layer and a plurality of second metal structures, the first metal structures and the second metal structures forming a metal bonding structure, and the inorganic layer and the polymer layer forming a dielectric bonding structure. The dielectric bonding structure of the inorganic-polymer in the packaging structure has good robustness and interface quality, and the stability of the structure is also indirectly improved, which improves the quality of the metal bonding, so that the first chip, the second chip and the third chip can be stably bonded together, and the reliability and yield of the packaging structure are improved.

Description

Technical Field

[0001] This utility model relates to the semiconductor field, and more particularly to a packaging structure. Background Technology

[0002] Advanced packaging technology, as a driving force for the continued development of the semiconductor industry in the post-Moore's Law era, hinges on improving chip integration and overall performance through methods such as 3D integration. In this technological context, high-density, high-efficiency interconnects between chips are fundamental to achieving multi-chip stacking and system-in-package (SiP).

[0003] As a result, interconnect technology has evolved from traditional wire bonding and flip-chip ball grid array (FCBGA) to higher density solutions. Among them, micro-bump interconnect technology has become the mainstream solution widely used in the current chip stacking field due to its significant advantages in interconnect density and electrical performance.

[0004] The industry has proposed bumpless hybrid bonding technology as the next-generation interconnect solution. This technology abandons the traditional solder bump structure, instead employing a strategy of direct copper-copper bonding supplemented by dielectric material bonding. This technology is expected to increase interconnect density by two orders of magnitude, and due to its near-gap-free connection characteristics, it shows great potential in reducing signal latency and power consumption, and increasing signal transmission bandwidth. However, bumpless hybrid bonding still faces unresolved technical challenges in practical applications. Utility Model Content

[0005] This invention provides a packaging structure to improve the reliability and yield of packaging structures.

[0006] This utility model also provides a packaging structure, including: a first chip, including a first bonding surface, the first bonding surface including an inorganic layer and a plurality of first metal structures, the first bonding surface including a first bonding region and a second bonding region; a second chip, located on the first bonding region; a third chip, located on the second bonding region, the second chip and the third chip both including a second bonding surface, the second bonding surface including a polymer layer and a plurality of second metal structures, the first metal structures and the second metal structures forming a metal bonding structure, the inorganic layer and the polymer layer forming a dielectric bonding structure.

[0007] Optionally, the packaging structure further includes: a redistribution structure located on the side of the second chip and the third chip away from the first chip; a first conductive bump located on the side of the redistribution structure away from the second chip and the third chip; and a substrate located on the side of the first conductive bump away from the redistribution structure.

[0008] Optionally, the packaging structure further includes: a first molding layer located between the first chip and the rewiring structure, and encapsulating the sidewalls of the second chip and the third chip.

[0009] Optionally, the packaging structure further includes one or more storage devices located on the surface of the substrate facing the redistribution structure and spaced apart from the redistribution structure.

[0010] Optionally, the storage device includes: a fourth chip including the first bonding surface; a fifth chip located on the side of the fourth chip away from the substrate, the fifth chip including a first side and a second side opposite to each other, the first side including the first bonding surface, the second side including the second bonding surface, the second bonding surface of the fifth chip being bonded to the first bonding surface of the fourth chip; and a sixth chip located on the side of the fifth chip away from the fourth chip, the sixth chip including the second bonding surface, the second bonding surface of the sixth chip being bonded to the first bonding surface of the fifth chip.

[0011] Optionally, there may be multiple fifth chips, and the multiple fifth chips may be stacked together. Between two adjacent fifth chips, the first bonding surface of the lower fifth chip is bonded to the second bonding surface of the upper fifth chip.

[0012] Optionally, the first bonding surface in the storage device includes an inorganic layer and a plurality of first metal structures, and the second bonding surface in the storage device includes a polymer layer and a plurality of second metal structures.

[0013] Optionally, the second chip includes: a first through-conductive structure located inside the second chip, wherein one end of the first through-conductive structure is electrically connected to the second metal structure of the second bonding surface of the second chip, and the other end is electrically connected to the redistribution structure; the third chip includes: a second through-conductive structure located inside the third chip, wherein one end of the second through-conductive structure is electrically connected to the second metal structure of the second bonding surface of the third chip, and the other end is electrically connected to the redistribution structure; the fifth chip includes: a third through-conductive structure located inside the fifth chip, wherein one end of the third through-conductive structure is electrically connected to the first metal structure of the first bonding surface of the fifth chip, and the other end is electrically connected to the second metal structure of the second bonding surface of the fifth chip.

[0014] Optionally, at the interface between the polymer layer and the inorganic layer, the surface of the polymer layer includes carboxyl functional groups, and the surface of the inorganic layer includes hydroxyl dangling bonds, with chemical bonds formed between the carboxyl functional groups and the hydroxyl dangling bonds.

[0015] Optionally, the first metal structure includes pads, and the second metal structure includes pads.

[0016] Optionally, both the first metal structure and the second metal structure adopt... <111> Nanotwinned copper with crystalline phase.

[0017] Optionally, the inorganic layer comprises silicon carbonitride.

[0018] Optionally, the polymer layer is made of a polymer material with a coefficient of thermal expansion of less than or equal to 50 ppm / K.

[0019] Optionally, the Young's modulus of the inorganic layer is higher than that of the polymer layer.

[0020] Optionally, the Young's modulus of the inorganic layer is from 70 GPa to 300 GPa, and the Young's modulus of the polymer layer is from 0.1 GPa to 3 GPa.

[0021] Optionally, the polymer layer may be made of polyimide.

[0022] Compared with the prior art, the technical solution of the utility model has the following advantages:

[0023] The packaging structure provided in this embodiment includes: a first chip, including a first bonding surface, the first bonding surface including an inorganic layer and a plurality of first metal structures, the first bonding surface including a first bonding region and a second bonding region; a second chip, located on the first bonding region; and a third chip, located on the second bonding region. Both the second chip and the third chip include a second bonding surface, the second bonding surface including a polymer layer and a plurality of second metal structures. The first metal structures and the second metal structures form a metal bonding structure, and the inorganic layer and the polymer layer form a dielectric bonding structure. In this embodiment, the first bonding surface includes an inorganic layer and a plurality of first metal structures, and the second bonding surface includes a polymer layer and a plurality of second metal structures. The first chip, the second chip, and the third chip are bonded through the first bonding surface and the second bonding surface, forming metal-metal bonding and inorganic-polymer dielectric bonding. First, the polymer layer has a lower Young's modulus and higher elasticity and viscoelasticity than the inorganic layer, allowing it to absorb and buffer bonding stress and adapt to microscopic irregularities on the surface of the inorganic layer in the first bonding surface. This results in a larger tolerance window for the inorganic-polymer dielectric bonding structure, leading to more uniform and comprehensive contact between the first and second metal structures and improving the quality of metal bonding. Second, the polymer layer is softer than the inorganic layer, giving the inorganic-polymer dielectric bonding structure both stress buffering and stable mechanical support. This makes the inorganic-polymer dielectric bonding structure less prone to collapse or deformation, ensuring structural stability after bonding between the first and second bonding surfaces. It also ensures a stable contact between the first and second metal structures, further improving the quality of metal bonding. Therefore, the inorganic-polymer dielectric bonding structure in the packaging structure provided by this utility model embodiment has good robustness and interface quality, as well as structural stability, which also indirectly improves the quality of metal bonding, enabling the first chip to be stably bonded to the second and third chips, thereby improving the reliability and yield of the packaging structure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the packaging structure of an embodiment of the present invention;

[0026] Figure 2This is a schematic diagram of the structure of the first chip, the second chip, the third chip, and the rewiring structure in an embodiment of this utility model;

[0027] Figure 3 This is a schematic diagram of the structure of the storage device according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the bonding structure between the fourth and fifth chips in the packaging structure of this utility model embodiment;

[0029] Figure 5 This is a schematic diagram of the bonding structure between the fifth and sixth chips in the packaging structure of this utility model embodiment. Detailed Implementation

[0030] As the background technology indicates, bumpless hybrid bonding still faces significant technical challenges in practical applications. Current mainstream hybrid bonding technologies based on inorganic dielectric materials such as copper / silicon dioxide (Cu / SiO2) still encounter multiple severe challenges at the process implementation level. First, extremely stringent requirements are placed on the physical morphology of the bonding interface. To ensure high-quality bonding, a flat surface must be obtained through chemical mechanical polishing (CMP). Any microscale surface roughness will directly impair bonding strength and interface integrity. Second, during interface preparation, the height difference between the copper (Cu) and the dielectric layer, i.e., the depth and contour of the Cu dishing, must be precisely controlled at the nanometer or even sub-nanometer level. This morphology not only determines the electrical performance of the interconnect structure but also directly affects the final bonding reliability. Furthermore, the entire process is highly sensitive to environmental cleanliness. Micrometer- or even nanometer-sized particulate contaminants can cause fatal connection failures or void defects at the bonding interface, significantly reducing process yield. Finally, the realization of this technical route not only relies on expensive, high-precision bonding alignment equipment, but also on complex processes such as the damascus process and plasma-enhanced chemical vapor deposition (PECVD), resulting in high material and manufacturing costs. In summary, existing copper / inorganic dielectric hybrid bonding technologies face significant challenges in process development due to their narrow process window, extreme requirements for surface quality and cleanliness, and high equipment and process costs, thus hindering their large-scale, low-cost application in industry.

[0031] To address the aforementioned technical problem, the packaging structure provided by this utility model embodiment includes: a first chip, comprising a first bonding surface, the first bonding surface including an inorganic layer and multiple first metal structures, the first bonding surface including a first bonding region and a second bonding region; a second chip, located on the first bonding region; and a third chip, located on the second bonding region. Both the second and third chips include a second bonding surface, the second bonding surface including a polymer layer and multiple second metal structures. The first metal structures and the second metal structures form a metal bonding structure, and the inorganic layer and the polymer layer form a dielectric bonding structure. Because the first bonding surface includes an inorganic layer and multiple first metal structures, and the second bonding surface includes a polymer layer and multiple second metal structures, the first chip, the second chip, and the third chip are bonded through the first and second bonding surfaces, forming metal-to-metal bonds and inorganic-polymer dielectric bonds. First, the polymer layer has a lower Young's modulus and higher elasticity and viscoelasticity than the inorganic layer, allowing it to absorb and buffer bonding stress and adapt to microscopic irregularities on the surface of the inorganic layer in the first bonding surface. This results in a larger tolerance window for the inorganic-polymer dielectric bonding structure, leading to more uniform and comprehensive contact between the first and second metal structures and improving the quality of metal bonding. Second, the polymer layer is softer than the inorganic layer, giving the inorganic-polymer dielectric bonding structure both stress buffering and stable mechanical support. This makes the inorganic-polymer dielectric bonding structure less prone to collapse or deformation, ensuring structural stability after bonding between the first and second bonding surfaces. It also ensures a stable contact between the first and second metal structures, further improving the quality of metal bonding. Therefore, the inorganic-polymer dielectric bonding structure in the packaging structure provided by this utility model embodiment has good robustness and interface quality, as well as structural stability, which also indirectly improves the quality of metal bonding, enabling the first chip to be stably bonded to the second and third chips, thereby improving the reliability and yield of the packaging structure.

[0032] The technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the utility model, and not all embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the utility model.

[0033] Accordingly, this utility model also provides a packaging structure. Figure 1 This is a schematic diagram of the packaging structure of an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of the first chip, the second chip, the third chip, and the rewiring structure in an embodiment of this utility model; Figure 3 This is a schematic diagram of the structure of the storage device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the bonding structure between the fifth and sixth chips in the packaging structure of this utility model embodiment; Figure 5 This is a schematic diagram of the bonding structure between the fourth and fifth chips in the packaging structure of this utility model embodiment.

[0034] refer to Figure 1 and Figure 2 This utility model embodiment provides a packaging structure including: a first chip 100, including a first bonding surface 10, the first bonding surface 10 including an inorganic layer 11 and a plurality of first metal structures 12, the first bonding surface 10 including a first bonding region I and a second bonding region II; a second chip 200, located on the first bonding region I; a third chip 300, located on the second bonding region II, both the second chip 200 and the third chip 300 include a second bonding surface 20, the second bonding surface 20 including a polymer layer 21 and a plurality of second metal structures 22, the first metal structures 12 and the second metal structures 22 forming a metal bonding structure, the inorganic layer 11 and the polymer layer 21 forming a dielectric bonding structure.

[0035] The first bonding surface 10 of this embodiment includes an inorganic layer 11 and a plurality of first metal structures 12, and the second bonding surface 20 includes a polymer layer 21 and a plurality of second metal structures 22. The first chip 100 is bonded to the second chip 200 and the third chip 300 through the first bonding surface 10 and the second bonding surface 20, forming metal-metal bonding and inorganic-polymer dielectric bonding. First, the material of the polymer layer 21 has a lower Young's modulus and higher elasticity and viscoelasticity than the material of the inorganic layer 11, which allows the polymer layer 21 to absorb and buffer bonding pressure and adapt to the microscopic unevenness on the surface of the inorganic layer 11 in the first bonding surface 10. This results in a larger tolerance window for the formed inorganic-polymer dielectric bonding structure, allowing for more uniform and comprehensive contact between the first metal structures 12 and the second metal structures 22, thus improving the formation quality of the metal bonding. Secondly, the polymer layer 21 is relatively soft, while the inorganic layer 11 is relatively hard. This allows the inorganic-polymer dielectric bonding structure to provide both stress buffering and stable mechanical support, making it less prone to collapse or deformation. This ensures the structural stability of the first bonding surface 10 and the second bonding surface 20 after bonding, and also allows for a stable contact between the first metal structure 12 and the second metal structure 22, improving the quality of metal bonding. Therefore, the inorganic-polymer dielectric bonding structure in the packaging structure provided by this embodiment of the invention has good robustness, interface quality, and structural stability, which indirectly improves the quality of metal bonding. This enables the first chip 100 to be stably bonded to the second chip 200 and the third chip 300, contributing to the achievement of high-reliability, high-yield hybrid bonding. In some embodiments, the first chip is a SoC chip, which integrates a processor core, storage, peripheral interfaces, and bus, and is mainly responsible for system-level computation and control. The second chip is an accelerator chip, a hardware module optimized for specific computing tasks. For example, GPUs excel at parallel graphics rendering, while ASICs accelerate encryption operations. The third chip is a logic processing chip, containing general-purpose computing units such as CPUs and GPUs, responsible for serial or parallel processing of basic computational tasks. These three chips work together, interconnecting to achieve higher interconnect density and integration, meeting the development trend of high-performance computing.

[0036] In some embodiments, the packaging structure further includes: a redistribution structure 701 located on the side of the second chip 200 and the third chip 300 away from the first chip 100; a first conductive bump 702 located on the side of the redistribution structure 701 away from the second chip 200 and the third chip 300; and a substrate 900 located on the side of the first conductive bump 702 away from the redistribution structure 701.

[0037] The redistribution structure 701 is disposed on the side of the second chip 200 and the third chip 300 opposite to the first chip 100. It is used to rearrange and fan out the electrical connection points on the second chip 200 and the third chip 300, thereby transforming the chip-level micro-pitch terminals into larger-pitch terminals suitable for interconnection with the substrate 900. Furthermore, the first conductive bump 702 located on the redistribution structure 701 connects to the substrate 900, forming an electrical path from the internal circuitry of the second chip 200 and the third chip 300 to the external substrate 900. This enables the hybrid-bonded chip module to achieve reliable electrical interconnection and mechanical fixation with the external circuit system, improving the reliability and yield of the packaging structure.

[0038] As an example, a redistribution layer (RDL) is a thin-film circuit composed of alternating stacked metal conductive layers and dielectric insulating layers. Specifically, the metal conductive layers are typically made of copper (Cu), and the circuit patterns are formed through processes such as electroplating or sputtering; the dielectric insulating layers are made of polymer materials, such as polyimide (PI) or benzocyclobutene (BCB), to isolate the different metal conductive layers.

[0039] In some embodiments, the second chip 200 includes: a first through-conductive structure 201 (e.g., Figure 2 As shown), located inside the second chip 200, and one end of the first through-conductive structure 201 is electrically connected to the second metal structure 22 of the second bonding surface 20, and the other end is electrically connected to the rewiring structure 701; the third chip 300 includes: a second through-conductive structure 301 (as shown), located inside the second chip 200, and one end of the first through-conductive structure 201 is electrically connected to the second metal structure 22 of the second bonding surface 20, and the other end is electrically connected to the rewiring structure 701; Figure 3 As shown), it is located inside the third chip 300, and one end of the second through conductive structure 301 is electrically connected to the second metal structure 22 of the second bonding surface 20, and the other end is electrically connected to the rewiring structure 701.

[0040] The first through-conductive structure 201 (e.g., through-silicon via, TSV) electrically connects the circuitry of the second chip 200 near the first chip 100 to the circuitry near the redistribution structure 701, creating a vertical electrical path between the first chip 100, the second chip 200, and the redistribution structure 701. This allows for direct signal transmission between different chip levels, which helps reduce signal delay, crosstalk, and power loss. The second through-conductive structure 301 (e.g., TSV) electrically connects the circuitry of the third chip 300 near the first chip 100 to the circuitry near the redistribution structure 701. This also creates a vertical electrical path between the first chip 100, the third chip 300, and the redistribution structure 701, enabling direct signal transmission between different chip levels, which helps reduce signal delay, crosstalk, and power loss.

[0041] In some embodiments, since both the second chip 200 and the third chip 300 have pads on their surfaces near the redistribution structure 701, the pads of the second chip 200 and the third chip 300 are connected to the metal conductive layer in the redistribution structure 701. During operation, the signal from the first chip 100 enters the second chip 200 through the metal bonding between the first metal structure 12 and the second metal structure 22, and is transmitted via the first through-conductive structure 201 (TSV) to the side of the second chip 200 near the redistribution structure 701 (or enters the third chip 300 and is transmitted via the second through-conductive structure 301 (TSV) to the side of the third chip 300 near the redistribution structure 701), and finally reaches the redistribution structure 701.

[0042] In some embodiments, the first conductive bump 702 is a conductive structure disposed on the top surface of the redistribution structure 701, used to connect the redistribution structure 701 to the substrate 900, so as to realize the transmission of signals from the redistribution structure 701 to the substrate 900.

[0043] Specifically, the first conductive bump 702 includes solder (such as a tin-silver-copper alloy) or a copper pillar. When solder is used, it is in the form of a spherical solder ball; when copper pillar is used, it is in the form of a cylindrical copper pillar with a solder cap on top.

[0044] In some embodiments, substrate 900 is a multilayer printed circuit board (PCB).

[0045] The substrate 900 includes multiple layers of wiring for signal transmission, power distribution, and grounding. The surface of the substrate 900 facing the first conductive bump 702 has pads that match the first conductive bump 702, while the surface of the substrate 900 facing away from the first conductive bump 702 has a ball grid array 704 (BGA) for mounting the entire package structure onto an external motherboard.

[0046] In some embodiments, the packaging structure further includes a first molding layer 703 located between the first chip 100 and the redistribution structure 701, and encapsulating the sidewalls of the second chip 200 and the third chip 300.

[0047] As an example, the material of the first molding layer 703 includes epoxy molding compound (EMC).

[0048] The first molding compound 703 fills the space between the first chip 100 and the redistribution structure 701, and encapsulates the sidewalls of the second chip 200 and the third chip 300, thereby providing lateral mechanical support for the second chip 200 and the third chip 300 and isolating them from the external environment. Furthermore, the first molding compound 703 provides longitudinal adhesive force to the first chip 100, the second chip 200, the third chip 300, and the redistribution structure 701. By fixing the relative positions of the first chip 100, the second chip 200, the third chip 300, and the redistribution structure 701, the first molding compound 703 enhances the overall structural rigidity of the package, thereby protecting the bonding interfaces between the first chip 100 and the second and third chips 300, as well as the bonding interfaces between the second and third chips 200 and the redistribution structure 701, from damage caused by moisture, contaminants, and mechanical stress, thus improving the reliability and yield of the package structure.

[0049] like Figure 1 and Figure 3 As shown, the packaging structure further includes one or more memory devices 800 located on the surface of the substrate 900 facing the redistribution structure 701 and spaced apart from the redistribution structure 701.

[0050] The storage device 800, the first chip 100, the second chip 200, and the third chip 300 are located on the same side of the same substrate 900, thereby forming a heterogeneous integrated package. This shortens the physical distance between the first chip 100, the second chip 200, and the third chip 300 and the storage device 800, which is conducive to realizing high-density interconnection between the first chip 100, the second chip 200, and the third chip 300 and the storage device 800. Therefore, it reduces signal transmission delay and power consumption, and improves data exchange bandwidth, enabling the first chip 100, the second chip 200, and the third chip 300 to access data faster.

[0051] In some embodiments, the memory device 800 includes: a fourth chip 400 including the first bonding surface 10; a fifth chip 500 located on the side of the fourth chip 400 opposite to the substrate 900, the fifth chip 500 including a first side and a second side opposite to each other, the first side including the first bonding surface 10, the second side including a second bonding surface 20, the second bonding surface 20 of the fifth chip 500 being bonded to the first bonding surface 10 of the fourth chip 400; and a sixth chip 600 located on the side of the fifth chip 500 opposite to the fourth chip 400, the sixth chip 600 including the second bonding surface 20, the second bonding surface 20 of the sixth chip 600 being bonded to the first bonding surface 10 of the fifth chip 500.

[0052] It should be specifically noted that the first bonding surface 10 in the storage device 800 includes an inorganic layer 11 and a plurality of first metal structures 12, and the second bonding surface 20 in the storage device 800 includes a polymer layer 21 and a plurality of second metal structures 22.

[0053] The storage device 800 includes a stacked fourth chip 400, a fifth chip 500, and a sixth chip 600, with a bonding structure between the fourth chip 400 and the fifth chip 500 (e.g., Figure 4 As shown), and the bonding structure between the fifth chip 500 and the sixth chip 600 (as shown). Figure 5 (As shown) represent the bonding between the first bonding surface 10 and the second bonding surface 20. First, the polymer layer 21 has a lower Young's modulus and higher elasticity and viscoelasticity than the inorganic layer 11, allowing the polymer layer 21 to absorb and buffer bonding pressure and adapt to the microscopic irregularities on the surface of the inorganic layer 11 in the first bonding surface 10. This results in a larger tolerance window for the formed inorganic-polymer dielectric bonding structure, leading to a more uniform and comprehensive contact between the first metal structure 12 and the second metal structure 22, thus improving the quality of metal bonding formation. Second, the polymer layer 21 is softer than the inorganic layer 11, giving the inorganic-polymer dielectric bonding structure both stress buffering and stable mechanical support. This prevents the inorganic-polymer dielectric bonding structure from collapsing or deforming, ensuring the structural stability of the first bonding surface 10 and the second bonding surface 20 after bonding. It also ensures a stable contact between the first metal structure 12 and the second metal structure 22, further improving the quality of metal bonding formation. Therefore, the inorganic-polymer dielectric bonding structure in the packaging structure provided by this utility model embodiment has good robustness and interface quality, as well as structural stability, which also indirectly improves the quality of metal bonding, enabling the fourth chip 400 to be stably bonded together with the fifth chip 500 and the sixth chip 600, which helps to achieve high reliability and high yield hybrid bonding.

[0054] In some embodiments, there are multiple fifth chips 500, and the multiple fifth chips 500 are stacked. Between two adjacent fifth chips 500, the first bonding surface 10 of the lower fifth chip 500 is bonded to the second bonding surface 20 of the upper fifth chip 500.

[0055] Specifically, the first side A of the fifth chip 500 has a first bonding surface 10, and the second side B has a second bonding surface 20. By vertically stacking multiple fifth chips 500 with double-sided asymmetric bonding interfaces, the heterogeneous bonding modes of metal-metal and "inorganic-polymer" are replicated and extended in the stacking direction, thereby constructing a high-density memory chip stack. Therefore, the stacking method of the fifth chip 500 can be directly applied to advanced packaging products (such as HBM) that require multi-layer core chip stacking, enabling memory chips to be tightly integrated, significantly shortening the signal interconnection path, and facilitating the realization of high-performance computing chips with higher bandwidth, lower latency, and lower power consumption.

[0056] In some embodiments, the fifth chip 500 includes a third through conductive structure 503 located inside the fifth chip 500, with one end of the third through conductive structure 503 electrically connected to the first metal structure 12 of the first bonding surface 10 of the fifth chip 500, and the other end electrically connected to the second metal structure 22 of the second bonding surface 20 of the fifth chip 500.

[0057] The third through conductive structure 503 (e.g., TSV) provides an electrical connection path between the first metal structure 12 in the first bonding surface 10 of the fifth chip 500 and the second metal structure 22 in the second bonding surface 20, thereby constructing a vertical electrical path for the memory device 800. This enables direct transmission of signals between different levels of chip devices, which helps to reduce signal delay, crosstalk, and power loss.

[0058] As an example, the fifth chip 500 is a DRAM (Dynamic Random Access Memory) chip, and the fifth chip 500 is the main unit for implementing High Bandwidth Memory (HBM) functionality.

[0059] HBM increases total capacity and bandwidth by adding more storage layers. The fifth chip 500 has a first bonding surface 10 and a second bonding surface 20 on its two sides, which is an optimization for stacking multiple fifth chips 500. Combined with the vertically extending third through-silicon via (TSV) structure 503 in the fifth chip 500, vertical transmission of signals and power between adjacent fifth chips 500 can be achieved. Each fifth chip 500 contributes a portion of the storage capacity, and all fifth chips 500 are addressed and controlled by the bottom logic chip through the third through-silicon via 503.

[0060] As an example, the fifth chip 500 includes: a first substrate 501, the first substrate 501 including a first side A and a second side B opposite to each other, the first side A of the first substrate 501 having a first metal layer 502 and the third through conductive structure 503 located below the first metal layer 502; a first metal structure 12, on the first side A, located on top of the first metal layer 502; a first dielectric layer 5041, on the first side A, located on the first substrate 501 on the side of the first metal structure 12; an inorganic layer 11, located on the first dielectric layer 5041 on the side of the first metal structure 12, the inorganic layer 11 and the first dielectric layer 5041 completely covering the sidewall of the first metal structure 12; a second metal structure 22, on the second side B, located at the end of the third through conductive structure 503 opposite to the first metal layer 502; and a polymer layer 21, on the second side B, located on the first substrate 501 on the side of the second metal structure 22, and the polymer layer 21 covering part of the sidewall of the second metal structure 22.

[0061] In some embodiments, the fifth chip 500 further includes a second dielectric stack 507 located on the second side B between the first substrate 501 and the polymer layer 21.

[0062] As an example, the second dielectric stack 507 includes a silicon nitride layer 5071 and a silicon oxide layer 5072 located between the silicon nitride layer 5071 and the polymer layer 21.

[0063] In some embodiments, the sixth chip 600 includes: a second substrate 601 on which a second metal layer 602 is formed; a second metal structure 22 on the second metal layer 602; and a polymer layer 21 on the second substrate 601 on the side of the second metal structure 22, wherein the polymer layer 21 covers a portion of the sidewall of the second metal structure 22.

[0064] The polymer layer 21 and the second metal structure 22 in the sixth chip 600 serve as flexible bonding surfaces, forming a bonding structure with the inorganic layer 11 and the first metal structure 12 in the fifth chip 500, which serve as rigid bonding surfaces.

[0065] As an example, the sixth chip 600 further includes: a third dielectric layer 603 located between the second substrate 601 and the polymer layer 21; and a seed layer 605 located between the second metal layer 602 and the second metal structure 22.

[0066] In some embodiments, the fourth chip 400 is a logic chip, which performs logic operations and control tasks such as control, timing management, address decoding, and data buffering. The logic chip 400 is bonded to the fifth chip 500 (memory chip) via the first bonding surface 10 to achieve high-density, low-latency electrical interconnection, thereby receiving data from the fifth chip 500 or sending instructions to it.

[0067] As an example, the fourth chip 400 includes: a third substrate 401; a third metal layer 402 located on top of the third substrate 401; a metal pillar 403 located at the bottom of the third metal layer 402 and connected to the bottom of the third metal layer 402; a first metal structure 12 located on top of the third metal layer 402; and an inorganic layer 11 covering the third metal layer 402 and located on the side of the first metal structure 12.

[0068] It should be noted that the storage device 800 further includes a second conductive bump 801, located on the side of the fourth chip 400 opposite to the fifth chip 500. The second conductive bump 801 is used to connect the storage device 800 to the substrate 900.

[0069] It should be noted that the storage device 800 further includes a second molding layer 802, located on the side of the fourth chip 400 facing the fifth chip 500, and covering the sidewalls of the fifth chip 500 and the sixth chip 600.

[0070] As an example, the material of the second molding layer 802 includes epoxy molding compound (EMC).

[0071] In some embodiments, the first bonding surface 10 includes an inorganic layer 11 and a plurality of first metal structures 12.

[0072] In some embodiments, the inorganic layer 11 has a high Young's modulus, and the inorganic layer 11 can suppress deformation or collapse of the bonded structure.

[0073] In some embodiments, the inorganic layer 11 comprises silicon carbonitride.

[0074] Silicon carbonitride (SiCN) is rich in carbon (C), providing higher stiffness and stronger interfacial bonding force at the bonding interface between the inorganic layer 11 and the polymer layer 21. Therefore, the use of SiCN not only enables the bonding structure to have strong mechanical support, but also provides favorable surface conditions for achieving strong dielectric-dielectric chemical bonding, thereby improving the strength and stability of the entire hybrid bonding and facilitating reliable heterogeneous material interface interconnection. Silicon carbonitride also acts as a copper barrier layer, preventing copper atoms from diffusing into the active region of the chip, giving the first bonding surface 10 the functions of structural support, insulation, and anti-diffusion, which is beneficial to improving the overall performance and reliability of the packaging structure and improving the reliability and yield of the packaging structure based on hybrid bonding.

[0075] The second bonding surface 20 includes a polymer layer 21 and multiple second metal structures 22. The polymer layer 21 of the second bonding surface 20 has a lower Young's modulus and higher elasticity and viscoelasticity, which can effectively absorb and buffer externally applied pressure, thereby better adapting to the microscopic unevenness of the inorganic layer 11 surface or accommodating small particles. This relaxes the requirements for the flatness and cleanliness of the first bonding surface 10 and the second bonding surface 20, thus increasing the tolerance window of the bonding process.

[0076] In some embodiments, the Young's modulus of the polymer layer 21 is lower than that of the inorganic layer 11.

[0077] The high Young's modulus of the inorganic layer 11 is used to construct a stable structural framework, thereby preventing the collapse of the polymer-inorganic bonding structure under bonding pressure. The low Young's modulus of the polymer layer 21 provides higher elasticity and viscoelasticity, which can act as a stress buffer, effectively absorbing and buffering bonding pressure. It can also better adapt to the microscopic unevenness on the surface of the inorganic layer 11 in the first bonding surface 10, so that the dielectric bonding of the inorganic-polymer has a larger tolerance window. This is conducive to forming a more uniform and comprehensive contact between the first metal structure 12 and the second metal structure 22, thereby improving the formation quality of the metal bonding.

[0078] In some embodiments, the polymer layer 21 is made of a polymer material with a coefficient of thermal expansion (CTE) of less than or equal to 50 ppm / K.

[0079] By selecting a polymer material with a coefficient of thermal expansion (CTE) of less than or equal to 50 ppm / K to make the polymer layer 21, the interfacial stress caused by thermal mismatch is suppressed during the heating and cooling process of bonding and the thermal cycling during chip operation. This reduces the risk of interface delamination, cracking, or fatigue failure of the first metal structure 12 and the second metal structure 22 caused by stress. Therefore, the polymer is made of a polymer material with a preset low coefficient of thermal expansion (CTE), which helps to reduce the thermomechanical stress inside the bonding structure, making the bonding structure thermally reliable and reducing the probability of warping, delamination, or chip cracking of the package. This is beneficial to improving the reliability and yield of the packaging structure based on hybrid bonding.

[0080] In some embodiments, the Young's modulus of the inorganic layer 11 is between 70 GPa and 300 GPa, for example, 100 GPa or 200 GPa. The inorganic layer 11 acts as a rigid support to prevent collapse or deformation of the viscoelastic polymer layer 21 during bonding. If the Young's modulus of the inorganic layer 11 is below 70 GPa, its stiffness is insufficient, and under the heat and pressure applied during bonding, the inorganic layer 11 is prone to undesirable plastic deformation or creep. This can disrupt the smoothness of the bonding interface between the inorganic layer 11 and the polymer layer 21, which is detrimental to the formation of a stable interconnect structure between the first metal structure 12 and the second metal structure 22. If the Young's modulus of the inorganic layer 11 is above 300 GPa, the inorganic layer 11 becomes brittle. Under the heat and pressure required for bonding, small stress concentrations, such as localized high stress caused by uneven bonding pressure or the presence of small particles at the interface, can easily lead to cracking or brittle fracture of the inorganic layer 11. This contradicts the original intention of this invention to improve process robustness and reduce failure risk by introducing the flexibility of polymers.

[0081] In some embodiments, the Young's modulus of the polymer layer 21 is between 0.1 GPa and 3 GPa, for example, 1 GPa or 2 GPa. When the Young's modulus of the polymer layer 21 is below 0.1 GPa, the polymer layer 21 is relatively soft and lacks the necessary mechanical strength and shape stability. Under the influence of pressure and temperature during the bonding process, the polymer layer 21 is close to a viscous fluid rather than a solid. When the first metal structure 12 and the second metal structure 22 are bonded, the size of the second metal structure 22 protruding from the polymer layer 21 cannot be controlled, which is not conducive to the formation of a stable bond structure between the first metal structure 12 and the second metal structure 22. If the Young's modulus of the polymer layer 21 is higher than 3 GPa, it means that the polymer layer 21 is too hard and does not have the flexible buffering capacity. In this case, the bonding process will become a direct contact between two high-modulus rigid surfaces, which is not conducive to the formation of a stable bond structure between the first metal structure 12 and the second metal structure 22.

[0082] In some embodiments, the polymer layer 21 is made of polyimide.

[0083] In some embodiments, the first metal structure 12 includes pads; the second metal structure 22 includes pads. Both the first metal structure 12 and the second metal structure 22 include pads, which are electrical interconnection paths between the first bonding surface 10 and the second bonding surface 20. This enables high bonding strength between chips while achieving reliable signal transmission, which is beneficial for improving the reliability and yield of the hybrid bonding-based packaging structure.

[0084] In some embodiments, the first metal structure 12 adopts... <111> The crystalline phase of nanotwinned copper, the second metal structure 22 adopts <111> Nanotwinned copper with crystalline phase.

[0085] The first metal structure 12 and the second metal structure 22 adopt the following: <111> Nanotwinned copper with a crystalline phase, meaning the pads use a type of... <111> Nanotwinned copper (Nt-Cu) with crystalline phase has <111> The crystalline phase of nanotwinned copper has an extremely high atomic diffusion rate, which can promote the rapid diffusion of copper atoms across the bonding interface at relatively low temperatures, thereby achieving dense, void-free copper-copper metal bonding. This is beneficial for achieving low-temperature bonding of the first bonding surface 10 and the second bonding surface 20, which significantly reduces the thermal budget of the bonding process. It is also beneficial for achieving high reliability and high yield low-temperature hybrid bonding, thereby improving the reliability and yield of packaging structures based on hybrid bonding.

[0086] In some embodiments, at the interface between the polymer layer 21 and the inorganic layer 11, the surface of the polymer layer 21 includes carboxyl functional groups, and the surface of the inorganic layer 11 includes hydroxyl dangling bonds, forming a chemical bond between the carboxyl functional groups and the hydroxyl dangling bonds. This chemical bond formation enhances the interfacial bonding force between the inorganic layer 11 and the polymer layer 21, thereby improving the strength and reliability of the dielectric bond. Correspondingly, it also improves the bonding strength and stability between the first metal structure 12 and the second metal structure 22, which is beneficial for improving the reliability and yield of the packaging structure based on hybrid bonding.

[0087] While the embodiments of this utility model have been disclosed above, the utility model is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the utility model; therefore, the scope of protection of the utility model should be determined by the scope defined in the claims.

Claims

1. A packaging structure, characterized in that, include: The first chip includes a first bonding surface, the first bonding surface includes an inorganic layer and a plurality of first metal structures, and the first bonding surface includes a first bonding region and a second bonding region. The second chip is located on the first bonding area; The third chip is located on the second bonding region. Both the second chip and the third chip include a second bonding surface. The second bonding surface includes a polymer layer and a plurality of second metal structures. The first metal structure and the second metal structure form a metal bonding structure. The inorganic layer and the polymer layer form a dielectric bonding structure.

2. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes: The rewiring structure is located on the side of the second and third chips opposite to the first chip; The first conductive bump is located on the side of the redistribution structure opposite to the second and third chips; The substrate is located on the side of the first conductive bump that is away from the redistribution structure.

3. The packaging structure as described in claim 2, characterized in that, The packaging structure further includes: A first molding compound is located between the first chip and the rewiring structure, and encapsulates the sidewalls of the second and third chips.

4. The packaging structure as described in claim 2, characterized in that, The packaging structure further includes: One or more storage devices are located on the surface of the substrate facing the redistribution structure and spaced apart from the redistribution structure.

5. The packaging structure as described in claim 4, characterized in that, The storage device includes: The fourth chip includes the first bonding surface; The fifth chip is located on the side of the fourth chip that is away from the substrate. The fifth chip includes a first side and a second side that are opposite to each other. The first side includes a first bonding surface, and the second side includes a second bonding surface. The second bonding surface of the fifth chip is bonded to the first bonding surface of the fourth chip. The sixth chip is located on the side of the fifth chip opposite to the fourth chip. The sixth chip includes a second bonding surface, and the second bonding surface of the sixth chip is bonded to the first bonding surface of the fifth chip.

6. The packaging structure as described in claim 5, characterized in that, There are multiple fifth chips, and the multiple fifth chips are stacked. Between two adjacent fifth chips, the first bonding surface of the lower fifth chip is bonded to the second bonding surface of the upper fifth chip.

7. The packaging structure as described in claim 5, characterized in that, The first bonding surface of the storage device includes an inorganic layer and a plurality of first metal structures, and the second bonding surface of the storage device includes a polymer layer and a plurality of second metal structures.

8. The packaging structure as described in claim 7, characterized in that, The second chip includes: a first through-conductive structure located inside the second chip, wherein one end of the first through-conductive structure is electrically connected to the second metal structure of the second bonding surface of the second chip, and the other end is electrically connected to the redistribution structure; The third chip includes: a second through-conductive structure located inside the third chip, wherein one end of the second through-conductive structure is electrically connected to the second metal structure of the second bonding surface of the third chip, and the other end is electrically connected to the rewiring structure; The fifth chip includes a third through-conductive structure located inside the fifth chip, wherein one end of the third through-conductive structure is electrically connected to the first metal structure of the first bonding surface of the fifth chip, and the other end is electrically connected to the second metal structure of the second bonding surface of the fifth chip.

9. The packaging structure as described in claim 1, characterized in that, At the interface between the polymer layer and the inorganic layer, the surface of the polymer layer includes carboxyl functional groups, and the surface of the inorganic layer includes hydroxyl dangling bonds, with chemical bonds formed between the carboxyl functional groups and the hydroxyl dangling bonds.

10. The packaging structure as described in claim 1, characterized in that, The first metal structure includes pads, and the second metal structure includes pads.

11. The packaging structure as described in claim 1, characterized in that, Both the first metal structure and the second metal structure adopt <111> Nanotwinned copper with crystalline phase.

12. The packaging structure as described in claim 1, characterized in that, The inorganic layer comprises silicon carbonitride.

13. The packaging structure as described in claim 1, characterized in that, The polymer layer is made of a polymer material with a coefficient of thermal expansion of less than or equal to 50 ppm / K.

14. The packaging structure as described in claim 1, characterized in that, The Young's modulus of the inorganic layer is higher than that of the polymer layer.

15. The packaging structure as described in claim 14, characterized in that, The Young's modulus of the inorganic layer is 70 GPa to 300 GPa, and the Young's modulus of the polymer layer is 0.1 GPa to 3 GPa.

16. The packaging structure as described in claim 1, characterized in that, The polymer layer is made of polyimide.

Images