Arbitrary waveform generator

Abstract

This application discloses an arbitrary waveform generator, including an FPGA, a first memory, a dynamic random access memory (DRAM), a high-speed data transmission interface module, and a waveform output module. The DRAM is connected to the FPGA. The high-speed data transmission interface module is used to transmit waveform data through its high-speed data transmission interface. The high-speed data transmission interface of the first memory is connected to one of the high-speed data transmission interfaces in the high-speed data transmission interface module. The high-speed data transmission interface of the FPGA is connected to another high-speed data transmission interface in the high-speed data transmission interface module. The FPGA is also connected to the waveform output module. This arbitrary waveform generator has a longer maximum duration for a single waveform playback, enabling the generation of waveforms with longer durations. It has the ability to generate multi-segment sequences / multi-segment playback capabilities, and can be normally applied in some special scenarios, producing more complex and refined waveforms.

Description

Technical Field

[0001] This application relates to the field of waveform generation technology, and more specifically to an arbitrary waveform generator. Background Technology

[0002] An arbitrary waveform generator is an instrument that can generate electrical signals of arbitrary shape and parameters. It can accurately generate almost any desired waveform according to the user's needs.

[0003] Currently, in existing arbitrary waveform generators (AWGs), FPGAs (Field Programmable Gate Arrays) with external DDR SDRAM play a crucial role in storing massive amounts of waveform data and supplying high-speed data. DDR SDRAM typically comes in two types: DDR3 SDRAM and DDR4 SDRAM. The use of external DDR SDRAM in arbitrary waveform generators fixes the storage depth of the generator, affecting the maximum duration of waveforms that can be played at one time. This makes it impossible to generate signals with relatively long durations and severely limits the ability of arbitrary waveform generators to generate multi-segment sequences / multi-segment playback capabilities, thus restricting the application of arbitrary waveform generators in some scenarios. Utility Model Content

[0004] The main technical problem addressed by this application is that the arbitrary waveform generator uses an FPGA with external DDR SDRAM, which results in a fixed storage depth, affecting the maximum duration of a waveform that can be played at one time. This makes it impossible to generate signals with relatively long durations and severely restricts the ability of the arbitrary waveform generator to generate multi-segment sequences / multi-segment playback, thus limiting the application of the arbitrary waveform generator in some scenarios.

[0005] One embodiment provides an arbitrary waveform generator, including: an FPGA, a first memory, a dynamic random access memory, a high-speed data transmission interface module, and a waveform output module;

[0006] The dynamic random access memory is connected to the FPGA;

[0007] The high-speed data transmission interface module includes at least two high-speed data transmission interfaces, and the high-speed data transmission interface module is used to transmit waveform data through its high-speed data transmission interfaces.

[0008] The first memory has a high-speed data transmission interface, which is connected to a high-speed data transmission interface in the high-speed data transmission interface module. The first memory is used to store waveform data.

[0009] The FPGA has a high-speed data transmission interface, which is connected to another high-speed data transmission interface in the high-speed data transmission interface module. The FPGA is also connected to the waveform output module. The FPGA is used to read waveform data from the first memory in response to a first control signal and store the waveform data read from the first memory into the dynamic random access memory; and to read the waveform data stored in the dynamic random access memory and output it to the waveform output module when outputting waveform data.

[0010] The waveform output module is used to perform at least digital-to-analog conversion on the waveform data output by the FPGA and output analog waveform data.

[0011] In one embodiment, the system further includes a central processing unit (CPU) connected to the FPGA. The CPU is configured to receive externally input waveform data and, when the space occupied by the externally input waveform data is greater than the storage depth of the dynamic random access memory (DRAM), the CPU outputs the first control signal to the FPGA.

[0012] In one embodiment, the central processing unit has a high-speed data transmission interface;

[0013] The high-speed data transmission interface module includes three high-speed data transmission interfaces; the three high-speed data transmission interfaces of the high-speed data transmission interface module are respectively connected to the high-speed data transmission interface of the central processing unit, the high-speed data transmission interface of the first memory, and the high-speed data transmission interface of the FPGA;

[0014] When the length of the required waveform data from the external input is less than or equal to the storage depth of the dynamic random access memory, the central processing unit is also used to generate waveform data and send it to the dynamic random access memory.

[0015] In one embodiment, any two high-speed data transmission interfaces in the high-speed data transmission interface module perform endpoint-to-endpoint transmission during waveform data transmission.

[0016] In one embodiment, the high-speed data transmission interface module is integrated within the FPGA.

[0017] In one embodiment, the high-speed data transmission interface module is a PCIe switch.

[0018] In one embodiment, the dynamic random access memory is a high-bandwidth memory integrated within the FPGA.

[0019] In one embodiment, the dynamic random access memory is a DDR SDRAM array, which includes at least a first DDR SDRAM and a second DDR SDRAM;

[0020] The first DDR SDRAM and the second DDR SDRAM are respectively connected to the FPGA; the working states of the first DDR SDRAM and the second DDR SDRAM include playing the current waveform data state and preloading waveform data state, and the first DDR SDRAM and the second DDR SDRAM alternately switch between the playing the current waveform data state and the preloading waveform data state;

[0021] When the FPGA outputs waveform data, it reads waveform data from the DDR SDRAM in the first DDR SDRAM and the second DDR SDRAM whose working state is the state of playing the current waveform data; when the FPGA stores waveform data in the dynamic random access memory, it stores the waveform data into the DDR SDRAM in the first DDR SDRAM and the second DDR SDRAM whose working state is the state of preloaded waveform data.

[0022] In one embodiment, the first memory includes a solid-state drive (SSD) having a high-speed data transmission interface, and the SSD is connected to a high-speed data transmission interface module via its high-speed data transmission interface.

[0023] In one embodiment, the waveform output module is a digital-to-analog converter.

[0024] According to the arbitrary waveform generator of the above embodiment, since the first memory is a large-capacity, high-transmission-rate memory, the storage depth of the arbitrary waveform generator is increased; the FPGA can read waveform data from the first memory through a high-speed data transmission interface, improving the transmission rate of waveform data, and the dynamic random access memory can perform high-performance processing and computational acceleration on the waveform data; therefore, the maximum duration of a single waveform playback by the arbitrary waveform generator is longer, and waveforms with longer durations can be generated. Furthermore, the arbitrary waveform generator has the ability to generate multiple sequences / multiple playbacks, thus enabling it to be used normally in some special scenarios; in addition, due to the increased storage depth, waveform data can be stored without compression, thereby generating more complex and refined waveforms. Attached Figure Description

[0025] Figure 1 This is a block diagram illustrating the principle of an existing arbitrary waveform generator.

[0026] Figure 2This is a block diagram illustrating the principle of the arbitrary waveform generator in this application;

[0027] Figure 3 This is a block diagram illustrating the principle of an arbitrary waveform generator in one embodiment;

[0028] Figure 4 This is a block diagram of an arbitrary waveform generator in another embodiment;

[0029] Figure 5 This is a block diagram of an arbitrary waveform generator with a high-speed data transmission interface on an FPGA in one embodiment.

[0030] Figure 6 This is a schematic diagram illustrating the reading of waveform data from a DDR SDRAM array in one embodiment.

[0031] Figure 7 This is a schematic diagram of an endpoint-to-endpoint transmission architecture in one embodiment.

[0032] Reference numerals: 100, FPGA; 200, High-speed data transmission interface module; 300, First memory; 301, Solid-state drive; 400, Dynamic Random Access Memory; 401, DDR SDRAM array; 4011, First DDR SDRAM; 4012, Second DDR SDRAM; 402, High-bandwidth memory; 500, Waveform output module; 600, Central Processing Unit; 700, Second memory. Detailed Implementation

[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0034] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments, and the operational steps involved in each embodiment can also be rearranged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the specification and drawings are only for clearly describing a particular embodiment and do not imply that they represent the necessary components and / or order.

[0035] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0036] In traditional arbitrary waveform generators, waveform data is usually stored in DDR SDRAM memory. The capacity of DDR SDRAM memory is usually limited, and the waveform storage depth is usually in the range of 1Gbytes to 16GBytes. When the length of waveform data that the user needs to output exceeds the storage depth of DDR SDRAM, the arbitrary waveform generator cannot output a waveform that meets the user's requirements.

[0037] An arbitrary waveform generator is an instrument capable of generating electrical signals of arbitrary shape and parameters. It can precisely generate almost any desired waveform according to the user's needs. The working principle of an arbitrary waveform generator is based on digital signal processing technology. First, the user sets the parameters of the desired waveform, such as amplitude, frequency, and phase, through computer software or the instrument panel. These parameters are converted into digital signals and stored in the waveform memory of the arbitrary waveform generator. Then, the digital signals in the waveform memory are converted into analog signals by a digital-to-analog converter (DAC). The DAC converts discrete digital values ​​into continuous analog voltage or current signals, thereby outputting the desired waveform.

[0038] With the development of technology, in order to achieve high-precision and high-resolution waveform output, arbitrary waveform generators typically employ advanced digital signal processing algorithms and high-speed digital-to-analog conversion technology. For example, some high-end arbitrary waveform generators have a vertical resolution of up to 16 bits and sampling rates from several GHz to tens of GHz, enabling them to generate very fine high-bandwidth waveforms.

[0039] When achieving high-precision and high-resolution waveform output, storage depth is a key indicator for arbitrary waveform generators. Storage depth refers to the number of sampling points that the waveform memory of an arbitrary waveform generator can store. A larger storage depth allows the arbitrary waveform generator to generate higher sampling rates, higher resolutions, and more complex waveform signals. For example, an arbitrary waveform generator with a 1G sampling point storage depth can store a waveform signal of up to 1 second at a sampling rate of 1G Sa / s. For a 16-bit vertical resolution DAC, this would require 16Gbit of memory. When the DAC's sampling rate reaches 10G Sa / s, storing waveform data for even longer periods requires even greater memory capacity, posing a significant challenge. Of course, besides storage capacity itself, the waveform data transfer rate of the memory itself must also be considered. If the waveform data transfer rate is slow, even a large memory capacity cannot meet the high bandwidth, high sampling rate, and high resolution waveform signal requirements of an arbitrary waveform generator.

[0040] like Figure 1 The diagram shown illustrates the principle structure of an arbitrary waveform generator in current technology. In existing arbitrary waveform generators, external DDR SDRAM plays a crucial role in storing massive amounts of waveform data and providing high-speed data. DDR SDRAM typically comes in two types: DDR3 and DDR4. The use of external DDR SDRAM in arbitrary waveform generators via FPGAs results in a fixed storage depth, affecting the maximum duration of waveforms that can be played at one time. This limits the generation of waveforms with longer durations and severely restricts the ability to generate multi-segment sequences / playbacks. Consequently, the application of arbitrary waveform generators is limited in certain scenarios, such as radar pulse sequences, long-duration communication protocol simulations (e.g., complete data packet sequences), and other complex testing scenarios. Furthermore, the fixed storage depth sometimes leads to waveform data compression, further reducing the complexity and precision of the waveform output by the arbitrary waveform generator.

[0041] In some embodiments of this application, an arbitrary waveform generator is provided. The storage depth is increased, and waveform data is transmitted between the FPGA100 and the first memory 300 through a high-speed data transmission interface. The dynamic random access memory can perform high-performance processing and computational acceleration on the waveform data. Therefore, the maximum duration of a single waveform playback by the arbitrary waveform generator is increased, and waveforms with longer durations can be generated. Furthermore, the arbitrary waveform generator has the ability to generate multi-segment sequences / multi-segment playback, so that it can be used normally in some special scenarios. In addition, due to the increased storage depth, waveform data can be stored without compression, thereby generating more complex and refined waveforms.

[0042] In some embodiments, such as Figure 2 As shown, the arbitrary waveform generator may include a central processing unit 600, an FPGA 100, a first memory 300, a dynamic random access memory 400, a high-speed data transmission interface module 200, and a waveform output module 500; the FPGA 100 is a field-programmable gate array.

[0043] The central processing unit 600 is connected to the FPGA 100. The central processing unit 600 is used to receive the required waveform data from external input. When the space occupied by the externally input waveform data is greater than the storage depth of the dynamic random access memory 400, the central processing unit 600 outputs a first control signal to the FPGA 100.

[0044] Dynamic random access memory 400 is connected to FPGA 100. High-speed data transmission interface module 200 includes at least two high-speed data transmission interfaces, which are used to transmit waveform data.

[0045] The first memory 300 has a high-speed data transmission interface, which can be a PCIe (Peripheral Component Interconnect Express) interface. The high-speed data transmission interface of the first memory 300 is connected to a high-speed data transmission interface in the high-speed data transmission interface module 200. The first memory 300 is used to store waveform data. For those skilled in the art, memories with high-speed data transmission interfaces generally have large storage capacities. In this embodiment, the first memory 300 has a large storage capacity and, because it has a high-speed data transmission interface, can perform high-speed data transmission.

[0046] In some embodiments, such as Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, the first memory 300 may include a solid-state drive 301. The solid-state drive 301 has a high-speed data transmission interface, and the solid-state drive 301 is connected to a high-speed data transmission interface in the high-speed data transmission interface module 200 through its high-speed data transmission interface. In this embodiment, the solid-state drive 301 may be, but is not limited to, an NVMe solid-state drive. The storage capacity of an NVMe solid-state drive is between hundreds of GB and thousands of GB, and with the development of technology, the read speed of the PCIe interface is also getting faster and faster, reaching tens of GB / s.

[0047] FPGA100 has a high-speed data transmission interface, which is connected to another high-speed data transmission interface in high-speed data transmission interface module 200. FPGA100 is also connected to waveform output module 500. FPGA100 is used to read waveform data from first memory 300 in response to a first control signal and store the waveform data read from first memory 300 in dynamic random access memory 400; and to read the waveform data stored in dynamic random access memory 400 and output it to waveform output module 500 when outputting waveform data.

[0048] The waveform output module 500 is used to perform at least digital-to-analog conversion on the waveform data output by the FPGA 100 and output analog waveform data. In some embodiments, the waveform output module 500 may be a digital-to-analog converter, which performs digital-to-analog conversion on the waveform data output by the FPGA 100 and outputs analog waveform data.

[0049] The first memory 300 is connected to one of the high-speed data transmission interfaces in the high-speed data transmission interface module 200 through its high-speed data transmission interface, and the FPGA 100 is connected to another high-speed data transmission interface in the high-speed data transmission interface module 200 through its high-speed data transmission interface, thus realizing the connection between the first memory 300 and the FPGA 100.

[0050] In some embodiments, the arbitrary waveform generator may be equipped with a touch panel, through which the user can input the required waveform data, which may include amplitude, frequency, phase, etc. The central processing unit 600 can receive the required waveform data input via the touch panel. The central processing unit 600 further compares the space occupied by the waveform data input by the user via the touch panel with the storage depth of the dynamic random access memory 400. When the space occupied by the waveform data input by the user via the touch panel is greater than the storage depth of the dynamic random access memory, the central processing unit 600 outputs a first control signal to the FPGA 100. At this time, the FPGA 100 reads the waveform data from the first memory 300. After buffering through its internal FIFO (First-In, First-Out) buffer, the FPGA 100 stores the waveform data read from the first memory 300 into the dynamic random access memory 400. When outputting waveform data, the FPGA 100 reads the waveform data from the dynamic random access memory 400 through its internal FIFO buffer and outputs it to the waveform output module 500. The waveform output module 500 performs digital-to-analog conversion on the waveform data output by the FPGA 100 and outputs analog waveform data.

[0051] In some embodiments, users can also customize the settings so that the FPGA100 reads waveform data from the first memory 300. That is, whenever an arbitrary waveform generator is used to generate analog waveform data, the FPGA100 reads waveform data from the first memory 300.

[0052] In this embodiment, because the first memory 300 is a large-capacity, high-transmission-rate memory, the storage depth of the arbitrary waveform generator is increased. The FPGA 100 can read waveform data from the first memory 300 through a high-speed data transmission interface, improving the transmission rate of waveform data. Furthermore, the dynamic random access memory (DRAM) can perform high-performance processing and computational acceleration on the waveform data. Therefore, the maximum duration of a single waveform playback by the arbitrary waveform generator is longer, enabling the generation of waveforms with longer durations. This further enables the arbitrary waveform generator to generate multi-segment sequences / multi-segment playback capabilities, allowing for normal application in some special scenarios. Additionally, due to the increased storage depth, waveform data can be stored without compression, thereby generating more complex and refined waveform signals (analog waveform data output by the digital-to-analog converter). In other words, the arbitrary waveform generator can output long-duration, highly complex waveform signals. That is, the arbitrary waveform generator can generate high-bandwidth, high-sampling-rate, and high-resolution waveform signals.

[0053] In some embodiments, such as Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, the central processing unit 600 has a high-speed data transmission interface; the high-speed data transmission interface module 200 includes three high-speed data transmission interfaces; the three high-speed data transmission interfaces of the high-speed data transmission interface module 200 are respectively connected to the high-speed data transmission interface of the central processing unit 600, the high-speed data transmission interface of the first memory 300, and the high-speed data transmission interface of the FPGA 100; when the length of the required waveform data input from the outside is less than or equal to the storage depth of the dynamic random access memory 400, the central processing unit 600 is also used to generate waveform data and send it to the dynamic random access memory 400.

[0054] like Figure 2 As shown, the high-speed data transmission interface module 200 can be a module with three high-speed data transmission interfaces. When the central processing unit 600 connects to the FPGA 100 through the high-speed data transmission interface module 200, it is also equipped with a high-speed data transmission interface. It connects to one of the high-speed data transmission interfaces of the high-speed data transmission interface module 200 through its high-speed data transmission interface, thereby connecting to the FPGA 100.

[0055] In some embodiments, when the space occupied by the waveform data required by the user input through the touch panel is less than the storage depth of the dynamic random access memory 400, the central processing unit 600 directly sends the waveform data in the second memory 700 to the dynamic random access memory 400 through the high-speed data transmission interface module 200. The second memory 700 may be DDR SDRAM directly connected to the central processing unit 600.

[0056] In some embodiments, any two high-speed data transmission interfaces in the high-speed data transmission interface module 200 perform endpoint-to-end transmission during waveform data transmission.

[0057] In some embodiments, such as Figure 4 As shown, the high-speed data transmission interface module 200 can be, but is not limited to, a PCIe switch. A PCIe switch is a high-speed data exchange hardware device based on the PCIExpress protocol. Its core function is to expand the PCIe connectivity of the host system through a multi-port interconnect architecture, enabling dynamic data routing between multiple endpoints and the root complex. In this embodiment, the PCIe switch has three high-speed data transmission interfaces, which are respectively connected to the high-speed data transmission interfaces of the central processing unit 600, the first memory 300, and the FPGA 100. The PCIe switch supports end-to-end transmission between two high-speed data transmission interfaces, for example... Figure 4 The transmission between the solid-state drive 301 and the FPGA 100 is described. End-to-end transmission, also known as P2P transmission, refers to a communication mode in which data is exchanged directly between endpoint devices connected to the same high-speed data transmission interface module 200 through the internal routing mechanism of the PCIe switch. P2P transmission achieves a decentralized path, with the data flow bypassing the root complex (in this embodiment, the root complex refers to the central processing unit 600) and the system main memory (in this embodiment, the system main memory refers to the second memory 700 connected to the central processing unit 600). The PCIe switch directly forwards the data to the peer device according to the target address, eliminating the bandwidth bottleneck of the central processing unit 600 and memory, and improving the transmission efficiency of waveform data.

[0058] like Figure 7 The diagram shown is a schematic of an endpoint-to-end transmission architecture. Figure 7As can be seen, FPGA100 can directly access waveform data in the first memory 300 through the PCIe switch. In other words, waveform data transmission between the first memory 300 and FPGA100 does not need to go through the PCIe interface of the central processing unit 600, which improves the transmission efficiency of waveform data.

[0059] In some embodiments, such as Figure 5 As shown, the high-speed data transmission interface module 200 is integrated within the FPGA 100. In other words, when the FPGA 100 integrates a high-speed data transmission interface capable of connecting to the central processing unit 600 and a high-speed data transmission interface capable of connecting to the first memory 300, the high-speed data transmission interface module 200 does not need to be configured; the central processing unit 600 and the first memory 300 can be connected via the high-speed data transmission interface module 200 integrated on the FPGA 100.

[0060] In some embodiments, such as Figure 3 As shown, the dynamic random access memory 400 can be a high-bandwidth memory 402 (HBM) integrated inside the FPGA 100. The high-bandwidth memory 402 provides a large-capacity, high-speed memory (expanding the storage depth of the arbitrary waveform generator), enabling the FPGA 100 to not only read waveform data from the first memory 300 at a high speed, but also to ensure that the data flow of the digital-to-analog converter (DAC) is uninterrupted and outputs stably and continuously.

[0061] In some embodiments, such as Figure 4 , Figure 5 As shown, the Dynamic Random Access Memory 400 can also be a DDR SDRAM array, which includes DDR SDRAM. When an arbitrary waveform generator outputs waveform data, the data stream output by the digital-to-analog converter must be uninterrupted and able to output stably and continuously. DDR SDRAM can quickly respond to the waveform data transmission needs of the FPGA100. The transmission latency of DDR SDRAM is generally in the nanosecond range (e.g., 10–100 ns), and it supports high-concurrency waveform data requirements. In contrast, the latency of the first memory 300 with a PCIe interface is generally in the microsecond range (e.g., 20–100 μs). Based on the deterministic bandwidth provided by the DDR SDRAM array connected to the FPGA100 and the ability of the first memory 300 to store large amounts of waveform data, the DDR SDRAM array adopts a hierarchical storage architecture to expand the storage depth of the arbitrary waveform generator through hierarchical storage.

[0062] In some embodiments, the DDR SDRAM array includes at least a first DDR SDRAM 4011 and a second DDR SDRAM 4012. The first DDR SDRAM 4011 and the second DDR SDRAM 4012 are respectively connected to FPGA 100. Both the first DDR SDRAM 4011 and the second DDR SDRAM 4012 have operating states including a current waveform data playback state and a preload waveform data state, and the first DDR SDRAM 4011 and the second DDR SDRAM 4012 alternately switch between these two states. That is, when the first DDR SDRAM 4011 is in the current waveform data playback state, the second DDR SDRAM 4012 is in the preload waveform data state.

[0063] When outputting waveform data, FPGA100 reads waveform data from the DDR SDRAM of the first DDR SDRAM 4011 and the second DDR SDRAM 4012 that is in the state of playing the current waveform data; when FPGA100 stores waveform data into the dynamic random access memory 400, it stores the waveform data into the DDR SDRAM of the first DDR SDRAM 4011 and the second DDR SDRAM 4012 that is in the state of preloading waveform data.

[0064] In one specific embodiment, such as Figure 6 As shown, the DDR SDRAM array includes a first DDR SDRAM 4011 and a second DDR SDRAM 4012. The operating states of the first DDR SDRAM 4011 and the second DDR SDRAM 4012 alternate between playing the current waveform data and preloading waveform data. That is, when the first DDR SDRAM 4011 is in the playing current waveform data state, the second DDR SDRAM 4012 is in the preloading waveform data state. Conversely, when the first DDR SDRAM 4011 is in the preloading waveform data state, the second DDR SDRAM 4012 is in the playing current waveform data state.

[0065] When outputting waveform data, the ultra-long waveform in the first memory 300 is transmitted to the DDR SDRAM array 401 via a PCIe switch using a P2P transmission method. The first DDR SDRAM 4011 stores one segment of waveform, and the second DDR SDRAM 4012 stores another segment. That is, the DDR SDRAM array stores the currently playing waveform and the pre-loaded next waveform. Figure 6 As shown, the DDR SDRAM array contains two waveform data segments.

[0066] The following explanation uses the example of a waveform data stored in the first DDR SDRAM4011 and the second DDR SDRAM4012, with the first DDR SDRAM4011 in the state of playing the current waveform data and the second DDR SDRAM4012 in the state of preloading waveform data.

[0067] When outputting waveform data, FPGA100 reads waveform data from the first DDR SDRAM4011 and fills it into its internal on-chip FIFO. FPGA100 uses its internal Block RAM (embedded block memory) or UltraRAM (ultra-embedded memory) to implement high-speed FIFO buffering. Then, the waveform data on the FIFO is output to the digital-to-analog converter (DAC) through a high-speed output channel. At this time, the second DDR SDRAM4012 has finished preloading waveform data and its working state switches to playing the current waveform data. FPGA100 switches from reading waveform data from the first DDR SDRAM4011 to reading waveform data from the second DDR SDRAM4012 to the DAC. At the same time, FPGA100 also reads a segment of waveform data from the first memory 300 into the first DDR SDRAM4011 through its memory controller. After reading waveform data from the second DDR SDRAM 4012, waveform data is read again from the first DDR SDRAM 4011. Simultaneously, waveform data is read from the first memory 300 and transferred to the second DDR SDRAM 4012. This alternating process ensures that the digital-to-analog converter (DAC) outputs a continuous, stable, and low-jitter data stream, completely offsetting the access latency of the DDR SDRAM. In other words, even if the DDR SDRAM array has low latency and burstiness, as long as the FPGA's on-chip FIFO has sufficient depth and the prefetch strategy is appropriate, the DAC can output a continuous, stable, and low-jitter data stream, completely offsetting the access latency of the DDR SDRAM. Here, an appropriate prefetch strategy means that the data buffered in the FPGA's FIFO can continuously supply the DAC.

[0068] In summary, this application provides an arbitrary waveform generator with the following beneficial effects:

[0069] The arbitrary waveform generator increases the maximum duration of a single waveform playback, enabling the generation of waveforms with longer durations. Furthermore, it enables the arbitrary waveform generator to generate multi-segment sequences / multi-segment playback capabilities, thus allowing it to be used normally in some special scenarios. In addition, due to the increased storage depth, waveform data can be stored without compression, thereby generating more complex and refined waveforms.

[0070] The above-described specific examples are for illustrative purposes only and are not intended to limit the scope of this invention. Those skilled in the art to which this invention pertains can make various simple deductions, modifications, or substitutions based on the concept of this invention.

Claims

1. An arbitrary waveform generator, characterized in that, include: FPGA, first memory, dynamic random access memory, high-speed data transmission interface module and waveform output module; The dynamic random access memory is connected to the FPGA; The high-speed data transmission interface module includes at least two high-speed data transmission interfaces, and the high-speed data transmission interface module is used to transmit waveform data through its high-speed data transmission interfaces. The first memory has a high-speed data transmission interface, which is connected to a high-speed data transmission interface in the high-speed data transmission interface module. The first memory is used to store waveform data. The FPGA has a high-speed data transmission interface, which is connected to another high-speed data transmission interface in the high-speed data transmission interface module. The FPGA is also connected to the waveform output module. The FPGA is used to read waveform data from the first memory in response to a first control signal and store the waveform data read from the first memory into the dynamic random access memory. And when outputting waveform data, read the waveform data stored in the dynamic random access memory and output it to the waveform output module; The waveform output module is used to perform at least digital-to-analog conversion on the waveform data output by the FPGA and output analog waveform data.

2. The arbitrary waveform generator as described in claim 1, characterized in that, Also includes: A central processing unit (CPU) is connected to the FPGA. The CPU is used to receive required waveform data from external input. When the space occupied by the required waveform data from external input is greater than the storage depth of the dynamic random access memory (DRAM), the CPU outputs the first control signal to the FPGA.

3. The arbitrary waveform generator as described in claim 2, characterized in that, The central processing unit has a high-speed data transmission interface; The high-speed data transmission interface module includes three high-speed data transmission interfaces; the three high-speed data transmission interfaces of the high-speed data transmission interface module are respectively connected to the high-speed data transmission interface of the central processing unit, the high-speed data transmission interface of the first memory, and the high-speed data transmission interface of the FPGA; When the length of the required waveform data from the external input is less than or equal to the storage depth of the dynamic random access memory, the central processing unit is also used to generate waveform data and send it to the dynamic random access memory.

4. The arbitrary waveform generator as described in claim 3, characterized in that, Any two high-speed data transmission interfaces in the high-speed data transmission interface module perform endpoint-to-endpoint transmission during waveform data transmission.

5. The arbitrary waveform generator as described in claim 4, characterized in that, The high-speed data transmission interface module is integrated within the FPGA.

6. The arbitrary waveform generator as described in claim 3 or 4, characterized in that, The high-speed data transmission interface module is a PCIe switch.

7. The arbitrary waveform generator as described in claim 3 or 4, characterized in that, The dynamic random access memory is a high-bandwidth memory integrated inside the FPGA.

8. The arbitrary waveform generator as described in claim 3 or 4, characterized in that, The dynamic random access memory is a DDR SDRAM array, which includes at least a first DDR SDRAM and a second DDR SDRAM. The first DDR SDRAM and the second DDR SDRAM are respectively connected to the FPGA; the working states of the first DDR SDRAM and the second DDR SDRAM include playing the current waveform data state and preloading waveform data state, and the first DDR SDRAM and the second DDR SDRAM alternately switch between the playing the current waveform data state and the preloading waveform data state; When the FPGA outputs waveform data, it reads waveform data from the DDR SDRAM in the first DDR SDRAM and the second DDR SDRAM whose working state is the state of playing the current waveform data; when the FPGA stores waveform data in the dynamic random access memory, it stores the waveform data in the DDR SDRAM in the first DDR SDRAM and the second DDR SDRAM whose working state is the state of preloaded waveform data.

9. The arbitrary waveform generator as described in claim 1 or 2, characterized in that, The first memory includes a solid-state drive (SSD), which has a high-speed data transmission interface and is connected to a high-speed data transmission interface module through its high-speed data transmission interface.

10. The arbitrary waveform generator as described in claim 1 or 2, characterized in that, The waveform output module is a digital-to-analog converter.

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