PCIe expansion circuitry, computer motherboards, and computer equipment

Abstract

This application relates to the field of circuit technology, specifically to PCIe expansion circuits, computer motherboards, and computer devices. The PCIe expansion circuit includes: a main control circuit; a PCIe switching circuit electrically connected to the main control circuit; a first PCIe interface circuit electrically connected to the PCIe switching circuit; a second PCIe interface circuit electrically connected to the PCIe switching circuit; and an embedded controller electrically connected to the PCIe switching circuit, configured to control the PCIe switching circuit to select a target PCIe interface circuit between the first and second PCIe interface circuits, so that PCIe data from the main control circuit is transmitted to the target PCIe interface circuit through the PCIe switching circuit. This application embodiment dynamically controls the selection state of the PCIe switching circuit through the embedded controller, realizing the transmission from the main control circuit to the target PCIe interface circuit, ensuring the user's autonomy in selecting PCIe functions, and improving the flexibility and applicability of the device.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a PCIe expansion circuit, a computer motherboard, and a computer device. Background Technology

[0002] In modern computer systems, servers, embedded devices, and various terminals, the PCIe bus has become the mainstream standard interface for connecting System-on-Chip (SoC) and high-performance peripherals (such as graphics cards, high-speed network cards, solid-state drives (SSDs), and data acquisition cards) due to its advantages such as high speed, point-to-point connection, and hot-swapping. As a highly integrated core processing device, the total number of PCIe lanes that a SoC can provide is a limited hardware resource.

[0003] In existing technical solutions, the implementation of PCIe functionality typically relies on a Bill of Materials (BOM)-controlled approach, which predetermines the hardware configuration on the motherboard to define the functional type of the PCIe interface. This approach has significant limitations: users cannot independently select or switch PCIe device types based on actual usage needs, resulting in fixed device functionality and poor flexibility and scalability. Summary of the Invention

[0004] One objective of this application is to provide a PCIe expansion circuit, a computer motherboard, and a computer device to solve the technical problem that the total amount of PCIe channel resources in a system-on-a-chip (SoC) is limited, while users have a high demand for functional expansion of PCIe devices.

[0005] In a first aspect, embodiments of this application provide a PCIe expansion circuit, comprising: Main control circuit; The PCIE switching circuit is electrically connected to the main control circuit. The first PCIe interface circuit is electrically connected to the PCIe switching circuit. The second PCIe interface circuit is electrically connected to the PCIe switching circuit. An embedded controller, electrically connected to the PCIe switching circuit, is configured to control the PCIe switching circuit to select a target PCIe interface circuit between the first PCIe interface circuit and the second PCIe interface circuit, so that the PCIe data of the main control circuit is transmitted to the target PCIe interface circuit through the PCIe switching circuit.

[0006] Optionally, the PCIe switching circuit includes: A pull-up circuit, electrically connected to the embedded controller, is configured to be controlled by the embedded controller and outputs a target selection signal; The PCIe switching unit is electrically connected to the pull-up circuit, the main control circuit, the first PCIe interface circuit, and the second PCIe interface circuit, respectively, and is configured to select a target PCIe interface circuit between the first PCIe interface circuit and the second PCIe interface circuit in response to the target selection signal.

[0007] Optionally, the PCIe switching unit includes: The first PCIe switching chip includes a first differential pair pin set, a second differential pair pin set, a third differential pair pin set, and a first selection pin; The second PCIe switching chip includes a fourth differential pair pin set, a fifth differential pair pin set, a sixth differential pair pin set, and a second selection pin. The first PCIe interface circuit is electrically connected to the first differential pair pin set and the fourth differential pair pin set, respectively. The second PCIe interface circuit is electrically connected to the second differential pair pin set and the fifth differential pair pin set, respectively. The main control circuit is electrically connected to the third differential pair pin set and the sixth differential pair pin set, respectively. The pull-up circuit is electrically connected to the first selection pin and the second selection pin, respectively.

[0008] Optionally, the pull-up circuit includes a first resistor, a first end of which is subjected to a preset voltage, and a second end of which is electrically connected to the embedded controller, the first selection pin, and the second selection pin, respectively.

[0009] Optionally, the first PCIe interface circuit includes: The first PCIe interface chip is electrically connected to the PCIe switching circuit. The first interface power supply circuit is electrically connected to the first PCIe interface chip and is configured to provide a first operating voltage to the first PCIe interface chip in response to the input of a first external power supply.

[0010] Optionally, the first interface power supply circuit includes: The first voltage regulator circuit is electrically connected to the first PCIe interface chip and is configured to regulate the first external power supply to obtain a first operating voltage and provide the first operating voltage to the first PCIe interface chip. The first filter circuit, electrically connected to the first voltage regulator circuit, is configured to filter the first external power supply.

[0011] Optionally, the first voltage regulator circuit includes a first capacitor, a first terminal of which is electrically connected to the first external power supply, and a second terminal of which is grounded. The first capacitor is configured to filter and store energy in the first external power supply to smooth voltage fluctuations. The first filter circuit includes a second capacitor, a first terminal of which is electrically connected to the output terminal of the first voltage regulator circuit, and a second terminal of which is grounded. The second capacitor is configured to filter the first operating voltage to reduce high-frequency noise in the first operating voltage.

[0012] Optionally, the second PCIe interface circuit includes: The second PCIe interface chip is electrically connected to the PCIe switching circuit. The second interface power supply circuit is electrically connected to the second PCIe interface chip and is configured to provide a second operating voltage to the second PCIe interface chip in response to the input of a second external power supply. The third interface power supply circuit, which is electrically connected to the second PCIe interface chip, is configured to provide a third operating voltage to the second PCIe interface chip in response to the input of a third external power supply.

[0013] In a second aspect, embodiments of this application provide a computer motherboard including the aforementioned PCIe expansion circuit.

[0014] In a third aspect, embodiments of this application provide a computer device including the aforementioned computer motherboard.

[0015] The embodiments of this application can achieve the following technical effects: The PCIe expansion circuit provided in the embodiments of this application includes: a main control circuit; a PCIe switching circuit electrically connected to the main control circuit; a first PCIe interface circuit electrically connected to the PCIe switching circuit; a second PCIe interface circuit electrically connected to the PCIe switching circuit; and an embedded controller electrically connected to the PCIe switching circuit, configured to control the PCIe switching circuit to select a target PCIe interface circuit between the first and second PCIe interface circuits, so that the PCIe data of the main control circuit is transmitted to the target PCIe interface circuit through the PCIe switching circuit. The embedded controller dynamically controls the selection state of the PCIe switching circuit to realize the transmission from the main control circuit to the target PCIe interface circuit, ensuring the user's independent selection of PCIe functions and improving the flexibility and applicability of the device. At the same time, the unified hardware design of the embodiments of this application avoids the need for multiple BOMs and production processes, which can reduce the complexity of supply chain management, production costs, and shorten the product delivery cycle; in addition, by reusing the PCIe channels and PCB resources of the SoC to serve different functions, the utilization rate of hardware resources can be improved and waste can be reduced. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic block diagram of a PCIe expansion circuit provided for an embodiment of this application; Figure 2 A schematic block diagram of another PCIe expansion circuit provided in an embodiment of this application; Figure 3 A circuit schematic diagram of the first PCIe switching chip provided in an embodiment of this application; Figure 4 A circuit schematic diagram of the second PCIe switching chip provided in an embodiment of this application; Figure 5 This is a schematic block diagram of another PCIe expansion circuit provided in an embodiment of this application; Figure 6 This is a schematic block diagram of another PCIe expansion circuit provided in an embodiment of this application; Figure 7 This is a circuit diagram of the first interface power supply circuit provided in the embodiments of this application; Figure 8 This is a schematic block diagram of another PCIe expansion circuit provided in an embodiment of this application; Figure 9 This is a circuit diagram of the second interface power supply circuit provided in the embodiments of this application; Figure 10 This is a circuit diagram of the third interface power supply circuit provided in the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0020] Please see Figure 1 , Figure 1 This application provides a PCIe expansion circuit. The PCIe expansion circuit 100 includes a main control circuit 200, a PCIe switching circuit 300, a first interface circuit 400, a second interface circuit 500, and an embedded controller 600.

[0021] The main control circuit 200 is typically a System-on-a-Chip (SoC) with an integrated PCIe controller, and is the only source in the system capable of generating and processing PCIe protocol data. The SoC provides a limited, fixed number of PCIe lanes through physical pins. The main control circuit 200 provides native PCIe lane resources and protocol processing capabilities. Expansion circuitry solutions, by reusing the limited PCIe lane resources of the main control circuit 200, dynamically serve different interfaces under user control, resolving the issue of balancing resource scarcity and functional flexibility.

[0022] The PCIe switching circuit 300 is electrically connected to the main control circuit 200 and is used to select the target PCIe interface circuit in response to the target selection signal sent by the embedded controller 400.

[0023] The first interface circuit 400 is electrically connected to the PCIe switching circuit 300 and is used to connect solid-state drive devices using the M.2 interface.

[0024] The second interface circuit 500 is electrically connected to the PCIe switching circuit 300 and is used to connect PCIe expansion devices, including but not limited to discrete graphics cards, sound cards, network cards, Wi-Fi / Bluetooth expansion cards, etc.

[0025] The embedded controller 600 is electrically connected to the PCIe switching circuit 300. In response to a user selection signal, it generates a target selection signal and sends it to the PCIe switching circuit, enabling the PCIe switching circuit to select the target PCIe interface circuit. PCIe data from the main control circuit is transmitted to the target PCIe interface circuit through the PCIe switching circuit. The embedded controller 600 is typically driven by software / firmware. Its control behavior can be triggered by the user through the operating system, BIOS / UEFI settings, physical switches, etc. It receives the user selection signal, which indicates whether the selected device function is high-speed storage or a specific PCIe expansion.

[0026] This application embodiment uses an embedded controller to dynamically control the selection state of the PCIe switching circuit, realizing the transmission from the main control circuit to the target PCIe interface circuit, ensuring the user's independent selection of PCIe functions, and improving the flexibility and applicability of the device.

[0027] In some embodiments, please refer to Figure 2 The PCIe switching circuit 300 includes a pull-up circuit 31 and a PCIe switching unit 32.

[0028] The pull-up circuit 31 is electrically connected to the embedded controller 600 and is configured to be controlled by the embedded controller 600 to output a target selection signal.

[0029] PCIe switching unit 32 is electrically connected to pull-up circuit 31, main control circuit 200, first PCIe interface circuit 400 and second PCIe interface circuit 500 respectively, and is configured to select a target PCIe interface circuit between the first PCIe interface circuit 400 and the second PCIe interface circuit 500 in response to a target selection signal.

[0030] The embedded controller 600 typically outputs a low-level GPIO signal (e.g., 3.3V LVCMOS), while the control pins of the PCIe switching unit require a specific driving level (e.g., 1.8V or higher). The pull-up circuit 31, through a level shifter or transistor amplifier circuit (e.g., MOSFET + pull-up resistor), converts the weak control signal from the embedded controller 600 into a high-drive, jitter-free target selection signal required by the PCIe switching unit 32. When the target selection signal is a low-level GPIO signal, the PCIe switching unit 32 activates the first PCIe interface circuit 400, reflecting the user's selection of an M.2 SSD device; when the target selection signal is a high-level GPIO signal, the PCIe switching unit 32 activates the second PCIe interface circuit 500, reflecting the user's selection of a PCIe expansion device.

[0031] In some embodiments, the PCIe switching unit 32 includes a first PCIe switching chip 321 and a second switching chip 322. See also... Figure 3 The first PCIe switching chip 321 includes a first differential pair pin set 3211, a second differential pair pin set 3212, a third differential pair pin set 3213, and a first selection pin 3214. Please refer to [link / reference]. Figure 4 The second PCIe switching chip 322 includes a fourth differential pair pin set 3221, a fifth differential pair pin set 3222, a sixth differential pair pin set 3223, and a second selection pin 3224.

[0032] The first PCIe interface circuit 400 is electrically connected to the first differential pair pin set 3211 and the fourth differential pair pin set 3221 respectively. The second PCIe interface circuit 500 is electrically connected to the second differential pair pin set 3212 and the fifth differential pair pin set 3222 respectively. The main control circuit 200 is electrically connected to the third differential pair pin set 3213 and the sixth differential pair pin set 3223 respectively. The pull-up circuit 31 is electrically connected to the first selection pin 3214 and the second selection pin 3224 respectively.

[0033] In some embodiments, the PCIe switching triad includes a third PCIe switching chip, which includes a seventh differential pair pin set, an eighth differential pair pin set, a ninth differential pair pin set, and a third selection pin. A first PCIe interface circuit is electrically connected to the seventh differential pair pin set, a second PCIe interface circuit is electrically connected to the eighth differential pair pin set, a main control circuit is electrically connected to the ninth differential pair pin set, and a pull-up circuit is electrically connected to the third selection pin.

[0034] In some embodiments, the pull-up circuit 31 includes a first resistor, a first end of which is subjected to a preset voltage, and a second end of which is electrically connected to the embedded controller 600, the first selection pin 3214 and the second selection pin 3224, respectively.

[0035] The preset voltage is 3.3V. Pull-up circuit 31 converts the weak control signal from the embedded controller 600 into a target selection signal with high drive capability required by the PCIe switching unit through a first resistor. Specifically, pull-up circuit 31 converts the EC_PCIE_MUX_SEL signal into a PCIe_MUX_SEL signal through the first resistor. The EC_PCIE_MUX_SEL signal is the signal received by the embedded controller 600 for selecting the target device by the user. The PCIe_MUX_SEL signal is a GPIO signal. Pull-up circuit 31 converts the signal received by the embedded controller 600 for selecting the target device by the user into a high / low GPIO signal, so that the PCIe switching unit 32 can select the target PCIe interface circuit according to the high / low GPIO signal.

[0036] In some embodiments, please refer to Figure 5 The first PCIe interface circuit 400 includes a first PCIe interface chip 41 and a first interface power supply circuit 42. The first PCIe interface chip 41 is electrically connected to the PCIe switching circuit 300. The first interface power supply circuit 42 is electrically connected to the first PCIe interface chip 41 and is configured to provide a first operating voltage to the first PCIe interface chip 41 in response to the input of a first external power supply.

[0037] The first interface chip 41 provides an M.2 SSD interface. The M.2 SSD interface is implemented by the physical layer circuitry and corresponding pin definitions of the first PCIe interface chip 41, supporting NVMe or SATA protocol specifications. It is used for mechanical and electrical connection of M.2 SSD devices, enabling bidirectional transmission of data and control signals. The first external power supply is 3.3V / 1.5A. The first operating voltage is 3V. The first interface power supply circuit 42 is used to connect the 3.3V / 1.5A first external power supply and convert it into a 3V first operating voltage to power the first PCIe interface chip 41.

[0038] In some embodiments, please refer to Figure 6 The first interface power supply circuit 42 includes a first voltage regulator circuit 421 and a first filter circuit 422. The first voltage regulator circuit 421 is electrically connected to the first PCIe interface chip and is configured to regulate the voltage of the first external power supply to obtain a first operating voltage, and provide the first operating voltage to the first PCIe interface chip 41. The first filter circuit 422 is electrically connected to the first voltage regulator circuit and is configured to filter the first external power supply.

[0039] In some embodiments, the first voltage regulator circuit 421 includes a first capacitor, a first terminal of which is electrically connected to a first external power supply, and a second terminal of which is grounded. The first capacitor is configured to filter and store energy from the first external power supply to smooth voltage fluctuations. The first filter circuit 422 includes a second capacitor, a first terminal of which is electrically connected to the output terminal of the first voltage regulator circuit, and a second terminal of which is grounded. The second capacitor is configured to filter the first operating voltage to reduce high-frequency noise in the first operating voltage.

[0040] Please see Figure 7The first interface power supply circuit 42 receives a 3.3V input from the first external power supply +3.3V_S0, with a maximum current of 1.5A. After passing through the second resistor R2 (a voltage divider resistor with overcurrent protection and impedance matching function), the output is sent to the power supply network to power the first operating voltage +3V3_SSD2 network, establishing the basic power supply link. The power supply network includes a first voltage regulator circuit and a first filter circuit. The first voltage regulator circuit includes multiple first capacitors C1, each configured as 10uF / 6.3V. One end of the first capacitor C1 is connected to the +3V3_SSD2 power supply line, and the other end is grounded (GND). Utilizing the charging and discharging characteristics of capacitors, when the voltage of the first external power supply experiences instantaneous fluctuations (such as small voltage fluctuations caused by sudden load changes), the first capacitor C1 can absorb or release charge, smoothing the voltage change and providing a stable first operating voltage for subsequent circuits. This serves as power supply filtering and voltage regulation, compensating for voltage fluctuations and ensuring the normal operation of the first PCIe interface chip. Similarly, the first filter circuit includes multiple second capacitors C2, each configured to 100nF / 16V. One end of each second capacitor C2 is connected to the output of the first voltage regulator circuit, and the other end is grounded (GND). The second capacitors C2 are used to filter out high-frequency noise in the power supply. When the electronic circuit operates, it generates high-frequency interference signals. The second capacitors C2 can short-circuit these high-frequency noise signals to ground, purifying the power supply voltage, making the output DC voltage smoother, reducing the interference of high-frequency noise on the first PCIe interface chip 41, and improving the overall anti-interference capability and operational stability of the circuit.

[0041] Understandably, combinations of capacitors with different capacities and materials can cover noise filtering across different frequency bands. The third capacitor, C3, is configured as 1uF / 6.3V. Similar to the voltage regulator and filter capacitors mentioned above, it is part of the power supply filtering network. Combining multiple capacitors with different parameters (different capacities, voltage ratings, and materials) can create a wider frequency range of filtering effects, effectively suppressing noise from low to high frequencies and comprehensively optimizing power supply quality. For example, the fourth capacitor, C4, is configured as 10pF / 50V and is used for fine filtering, adapting to components suitable for specific high-frequency scenarios.

[0042] In some embodiments, please refer to Figure 8 The second PCIe interface circuit 500 includes a second PCIe interface chip 51, a second interface power supply circuit 52, and a third interface power supply circuit 53. The second PCIe interface chip 51 is electrically connected to the PCIe switching circuit 300. The second interface power supply circuit 52 is electrically connected to the second PCIe interface chip 51 and is configured to provide a second operating voltage to the second PCIe interface chip 51 in response to the input of a second external power supply. The third interface power supply circuit 53 is electrically connected to the second PCIe interface chip 51 and is configured to provide a third operating voltage to the second PCIe interface chip 51 in response to the input of a third external power supply.

[0043] The second PCIe interface chip 51 provides a PCIe x16 slot for connecting various PCIe expansion devices. The second PCIe interface chip 51 provides a standard PCIe x16 physical slot. This PCIe x16 physical slot is compatible with various PCIe expansion devices, including high-performance discrete graphics cards (for accelerated graphics processing, improving display output and 3D rendering performance), professional data acquisition cards (to meet the high-speed acquisition and transmission of multiple signals in industrial and scientific research scenarios), etc. Internally, the second interface chip 51, through signal conditioning and protocol conversion circuits, works in conjunction with the PCIe switching circuit 300 to ensure stable and high-speed data transmission after the PCIe expansion device is connected, adapting to the bandwidth and timing requirements of different devices.

[0044] Please see Figure 9 The second interface power supply circuit 52 is used for voltage regulation and filtering, providing a second operating voltage of 12V to the second PCIe interface chip 51. The second interface power supply circuit 52 includes a fifth capacitor C5 and two sixth capacitors C6. The fifth capacitor is configured as 330μF / 16V, and the sixth capacitors C6 are configured as 100nF / 16V. The fifth capacitor C5 and the two sixth capacitors C6 are connected in parallel between the second external power input and ground. Utilizing the charging and discharging characteristics of the capacitors, the input second external power supply is regulated and filtered to provide a stable 12V second operating voltage to the second PCIe interface chip 51, suppressing power ripple interference and ensuring the chip's power supply quality.

[0045] Please see Figure 10 The third interface power supply circuit 53 supplies 3.3V to the second PCIe interface chip 51. The third interface power supply circuit 53 includes a seventh capacitor C7 and an eighth capacitor C8. The seventh capacitor C7 is configured with 470μF / 6.3V, and the eighth capacitor C8 is configured with 100nF / 16V. The seventh capacitor C7 and the eighth capacitor C8 are connected in parallel between the third external power input +3.3V_S0 and ground. In response to the third external power input, the capacitors smooth the voltage, filter power supply noise, and stably output a third operating voltage of 3.3V, providing a reliable power supply environment for the second PCIe interface chip 51.

[0046] This application also provides a computer motherboard including the aforementioned PCIe expansion circuit. The computer motherboard integrates the aforementioned PCIe expansion circuit, specifically including: a main control circuit, a PCIe switching circuit, a first PCIe interface circuit, a second PCIe interface circuit, and an embedded controller. The main control circuit provides native PCIe channel resources. The PCIe switching circuit is electrically connected to the main control circuit and controlled by the embedded controller; both the first and second PCIe interface circuits are electrically connected to the PCIe switching circuit. Through the selection control of the embedded controller, the PCIe switching circuit can dynamically route the same set of PCIe channel resources of the main control circuit to the first or second PCIe interface circuit, enabling users to independently select and switch target PCIe functions. This computer motherboard design effectively resolves the contradiction between the limited native PCIe resources of the SoC and users' diverse peripheral needs, achieving flexible and variable PCIe function expansion capabilities on a single-board hardware.

[0047] This application also provides a computer device, including the aforementioned computer motherboard. The computer device uses the aforementioned computer motherboard with integrated PCIe expansion circuitry as its core hardware platform. By reusing the native PCIe channel resources of the main control circuit, it achieves dynamic support for multifunctional external devices at the single-board level. Specifically, the embedded controller on the computer motherboard can respond to user commands or system policies, controlling the PCIe switching circuit to route the same set of PCIe channels of the main control circuit to the first PCIe interface or the second PCIe interface in real time, enabling the computer device to flexibly switch core expansion functions in different application scenarios.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A PCIE extension circuit, characterized in that, include: The main control circuit is a SoC with an integrated PCIe controller; The PCIE switching circuit is electrically connected to the main control circuit. A first PCIe interface circuit is electrically connected to the PCIe switching circuit. The first PCIe interface circuit includes an M.2 SSD interface and is configured to connect a solid-state drive device. The second PCIe interface circuit is electrically connected to the PCIe switching circuit. The second PCIe interface circuit includes a PCIe x16 slot and is configured to connect a PCIe expansion device. An embedded controller, electrically connected to the PCIe switching circuit, is configured to control the PCIe switching circuit to select a target PCIe interface circuit between the first PCIe interface circuit and the second PCIe interface circuit, so that the PCIe data of the main control circuit is transmitted to the target PCIe interface circuit through the PCIe switching circuit.

2. The PCIE extension circuit of claim 1, wherein, The PCIe switching circuit includes: A pull-up circuit, electrically connected to the embedded controller, is configured to be controlled by the embedded controller and outputs a target selection signal; The PCIe switching unit is electrically connected to the pull-up circuit, the main control circuit, the first PCIe interface circuit, and the second PCIe interface circuit, respectively, and is configured to select a target PCIe interface circuit between the first PCIe interface circuit and the second PCIe interface circuit in response to the target selection signal.

3. The PCIE extension circuit of claim 2, wherein, The PCIe switching unit includes: The first PCIe switching chip includes a first differential pair pin set, a second differential pair pin set, a third differential pair pin set, and a first selection pin; The second PCIe switching chip includes a fourth differential pair pin set, a fifth differential pair pin set, a sixth differential pair pin set, and a second selection pin. The first PCIe interface circuit is electrically connected to the first differential pair pin set and the fourth differential pair pin set, respectively. The second PCIe interface circuit is electrically connected to the second differential pair pin set and the fifth differential pair pin set, respectively. The main control circuit is electrically connected to the third differential pair pin set and the sixth differential pair pin set, respectively. The pull-up circuit is electrically connected to the first selection pin and the second selection pin, respectively.

4. The PCIE extension circuit of claim 3, wherein, The pull-up circuit includes a first resistor, a first end of which is subjected to a preset voltage, and a second end of which is electrically connected to the embedded controller, the first selection pin, and the second selection pin.

5. The PCIE extension circuit of any one of claims 1 to 4, wherein, The first PCIe interface circuit includes: The first PCIe interface chip is electrically connected to the PCIe switching circuit. The first interface power supply circuit is electrically connected to the first PCIe interface chip and is configured to provide a first operating voltage to the first PCIe interface chip in response to the input of a first external power supply.

6. The PCIE extension circuit of claim 5, wherein, The first interface power supply circuit includes: The first voltage regulator circuit is electrically connected to the first PCIe interface chip and is configured to regulate the first external power supply to obtain a first operating voltage and provide the first operating voltage to the first PCIe interface chip. The first filter circuit, electrically connected to the first voltage regulator circuit, is configured to filter the first external power supply.

7. The PCIE extension circuit of claim 6, wherein, The first voltage regulator circuit includes a first capacitor, a first terminal of which is electrically connected to the first external power supply, and a second terminal of which is grounded. The first capacitor is configured to filter and store energy in the first external power supply to smooth voltage fluctuations in the first external power supply. The first filter circuit includes a second capacitor. The first end of the second capacitor is electrically connected to the output end of the first voltage regulator circuit, and the second end of the second capacitor is grounded. The second capacitor is configured to filter the first operating voltage and reduce high-frequency noise in the first operating voltage.

8. The PCIE extension circuit of any one of claims 1-4, wherein, The second PCIe interface circuit includes: The second PCIe interface chip is electrically connected to the PCIe switching circuit. The second interface power supply circuit is electrically connected to the second PCIe interface chip and is configured to provide a second operating voltage to the second PCIe interface chip in response to the input of a second external power supply. The third interface power supply circuit, which is electrically connected to the second PCIe interface chip, is configured to provide a third operating voltage to the second PCIe interface chip in response to the input of a third external power supply.

9. A computer motherboard, characterized by Includes the PCIe expansion circuit as described in any one of claims 1 to 8.

10. A computer device, comprising: Includes the computer motherboard as described in claim 9.

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