A cpu power down delay monitoring circuit

Abstract

This invention provides a CPU power-down delay monitoring circuit, including a power supply unit, an energy storage capacitor, a sampling unit, and a control unit. The power supply unit supplies power to the control unit, the sampling unit, and the control unit, and charges the energy storage capacitor. The energy storage capacitor stores electrical energy and provides backup power to the control unit and the sampling unit when the power supply unit fails. The sampling unit collects voltage data from the energy storage capacitor and transmits it to the control unit. The control unit evaluates the state of the energy storage capacitor based on the data collected by the sampling unit, and uses the electrical energy provided by the energy storage capacitor to complete data saving and control the AGV system to perform a safe shutdown operation when power fails. By monitoring the voltage data of the energy storage capacitor in real time through the sampling unit, the system can intelligently prioritize data saving and perform safe shutdown operations of the AGV based on the actual condition of the capacitor when the power supply suddenly fails, solving the problems of data loss and equipment safety hazards caused by capacitor aging or failure in traditional power-down protection systems.

Description

Technical Field

[0001] This utility model relates to the field of circuits, specifically to a CPU power-down delay monitoring circuit. Background Technology

[0002] Currently, in industrial control systems, especially AGV systems, to prevent data loss and system shutdown failure due to sudden power outages, a common approach is to add an energy storage capacitor to the external input terminal of the circuit. This solution relies on the energy storage capacitor to provide temporary power after a power outage, giving the control system sufficient time to save critical data and perform a safe shutdown operation. However, traditional power-down storage monitoring systems have significant shortcomings: as the energy storage capacitor's usage time increases, its capacity gradually decreases, and it may even experience sudden failure. The system lacks a real-time monitoring mechanism for the capacitor's status and cannot predict whether the capacitor will still provide sufficient backup power during a power outage. This leads to the risk that the system cannot complete data saving and safe shutdown operations during power outages when capacitor performance deteriorates or fails, seriously threatening data security and equipment safety.

[0003] In addition, most existing power failure protection systems use fixed design parameters and lack intelligent monitoring and management mechanisms. They cannot dynamically adjust system behavior according to the actual state of the capacitors, nor can they provide early warning information so that maintenance personnel can replace aging capacitors in a timely manner. Utility Model Content

[0004] The purpose of this invention is to solve the technical problems of AGV systems failing to stop safely when power suddenly fails, critical data failing to be saved in a timely manner, and the status of energy storage capacitors being difficult to monitor effectively.

[0005] This utility model provides a CPU power-down delay monitoring circuit, including a power supply unit, an energy storage capacitor, a sampling unit, and a control unit; The power supply unit is used to supply power to the control unit, the sampling unit and the control unit, and to charge the energy storage capacitor; The energy storage capacitor is used to store electrical energy and provide backup power to the control unit and the sampling unit when the power supply unit loses power. The sampling unit collects the voltage data of the energy storage capacitor and transmits it to the control unit; The control unit is used to evaluate the state of the energy storage capacitor based on the data collected by the sampling unit, and to save data and control the AGV system to perform a safe stopping operation by using the power provided by the energy storage capacitor when the power is lost.

[0006] Furthermore, the power supply unit includes a regulated power supply and a control switch, wherein the control switch is a MOSFET; The first output terminal of the regulated power supply is connected to the drain of the MOSFET, and the second output terminal of the regulated power supply is grounded. A first capacitor is connected in parallel between the first output terminal and the second output terminal of the regulated power supply.

[0007] Furthermore, the gate of the MOS transistor is connected to one end of the first resistor and the second resistor, the other end of the first resistor is connected to the drain of the MOS transistor, and the other end of the second resistor is connected to the collector of the transistor. The emitter of the transistor is grounded, the base of the transistor is connected to one end of the third resistor and the fourth resistor respectively, the other end of the third resistor is grounded, and the other end of the fourth resistor is connected to the control unit.

[0008] Furthermore, one end of the energy storage capacitor is grounded, and the other end is connected to the first output terminal of the regulated power supply through a fifth resistor.

[0009] Furthermore, the other end of the energy storage capacitor is connected to the negative terminal of a diode, and the positive terminal of the diode is connected to the control unit and the external power supply terminal respectively.

[0010] Furthermore, the sampling unit includes a capacitor voltage sampling circuit and a capacitor temperature sampling circuit; The capacitor voltage sampling circuit is used to monitor the voltage value of the energy storage capacitor in real time and convert the voltage signal into a digital signal and transmit it to the control unit. The capacitor temperature sampling circuit is used to monitor the temperature status of the energy storage capacitor in real time and convert the temperature signal into a digital signal for transmission to the control unit.

[0011] Furthermore, the capacitor temperature sampling circuit includes a thermistor, one end of which is grounded, and the other end is connected to one end of a sixth resistor and a seventh resistor respectively. The other end of the sixth resistor is connected to one end of a control unit and a second capacitor respectively. The other end of the second capacitor is grounded, and the other end of the seventh resistor is connected to an external power supply.

[0012] Furthermore, the capacitor voltage sampling circuit includes an eighth resistor, one end of which is connected to the energy storage capacitor, and the other end is connected to one end of a ninth resistor and a tenth resistor respectively. The other end of the ninth resistor is grounded, and the other end of the tenth resistor is connected to one end of a third capacitor and the control unit respectively. The other end of the third capacitor is grounded.

[0013] Compared with existing technologies, this utility model has at least the following beneficial effects: By monitoring the voltage data of the energy storage capacitor in real time through the sampling unit, the control unit can accurately assess the capacitor status. When the power supply suddenly fails, it can intelligently arrange the data saving priority and AGV safe stopping operation according to the actual condition of the capacitor. This effectively solves the problem of data loss and equipment safety hazards caused by capacitor aging or failure in traditional power failure protection systems. At the same time, the circuit structure is simple, low-cost, and easy to integrate. Through the capacitor status early warning function, the system maintenance is transformed from passive response to active prevention, improving the data security and operational reliability of the AGV system under abnormal power failure conditions. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a CPU power-down delay monitoring circuit in one embodiment of the present invention; Figure 2 This is a circuit diagram of a CPU power-down delay monitoring system according to one embodiment of the present invention. Wherein, C1 is the energy storage capacitor; C2 is the first capacitor; C3 is the second capacitor; C4 is the third capacitor; R1 is the first resistor; R2 is the second resistor; R3 is the third resistor; R4 is the fourth resistor; R5 is the fifth resistor; R6 is the sixth resistor; R7 is the seventh resistor; R8 is the eighth resistor; R9 is the ninth resistor; R10 is the tenth resistor; Rt1 is the thermistor; Q1 is the MOSFET; Q2 is the transistor; and D1 is the diode. Detailed Implementation

[0016] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being broadly known to those skilled in the art and is not intended to limit the present invention.

[0017] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0018] The present invention will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0019] This embodiment provides a CPU power-down delay monitoring circuit. Please refer to [link / reference]. Figure 1 and Figure 2 It includes a power supply unit, an energy storage capacitor C1, a sampling unit, and a control unit; The power supply unit is used to supply power to the control unit, the sampling unit and the control unit, and to charge the energy storage capacitor C1. The energy storage capacitor C1 is used to store electrical energy and provide backup power to the control unit and the sampling unit when the power supply unit loses power. The sampling unit collects the voltage data of the energy storage capacitor C1 and transmits it to the control unit; The control unit is used to evaluate the state of the energy storage capacitor C1 based on the data collected by the sampling unit, and to save data and control the AGV system to perform a safe stopping operation by using the power provided by the energy storage capacitor C1 when the power is lost.

[0020] The power supply unit can be implemented using a linear regulator or a switching regulator. Linear regulators offer low noise, while switching regulators offer higher efficiency. The energy storage capacitor C1 is preferably an electrolytic capacitor or a supercapacitor. Electrolytic capacitors are less expensive, while supercapacitors offer longer lifespan and larger capacity. The sampling unit may include an analog-to-digital converter to convert analog voltage signals into digital signals for processing by the control unit. The control unit can be implemented using a microcontroller or a programmable logic device (PLD). Microcontrollers are easier to program for complex algorithms, while PLDs offer faster response times.

[0021] By monitoring the state of the energy storage capacitor C1 in real time, this solution addresses the problem of traditional power-down protection systems being unable to predict capacitor performance degradation. When insufficient capacitor capacity is detected, the system can issue an early warning, ensuring reliable operation even during a true power outage. Compared to existing technologies, this solution adds a state monitoring function, enabling timely detection of capacitor aging issues and preventing data loss or system malfunction due to capacitor failure. The control unit dynamically adjusts system behavior based on monitoring data, such as shortening data retention time or initiating a safety shutdown procedure earlier when capacitor performance deteriorates, improving system reliability. The sampling unit simultaneously monitors voltage and temperature parameters, providing a more comprehensive assessment of the capacitor's state; temperature monitoring, in particular, helps detect potential faults such as abnormal internal heating within the capacitor.

[0022] Furthermore, the power supply unit includes a regulated power supply and a control switch, wherein the control switch is a MOSFET Q1; The first output terminal of the regulated power supply is connected to the drain of the MOSFET Q1, and the second output terminal of the regulated power supply is grounded. A first capacitor C2 is connected in parallel between the first output terminal and the second output terminal of the regulated power supply.

[0023] Specifically, MOSFET Q1 acts as a control switch to achieve rapid on / off control, with its gate connected to transistor Q2 via a resistor network to form a drive circuit. In a preferred embodiment, MOSFET Q1 can be an N-channel enhancement-mode MOSFET, with its drain directly connected to the output of the regulated power supply and its source grounded. The regulated power supply can be implemented using a linear regulator or a switching regulator, where the first capacitor C2 is preferably an electrolytic capacitor with a capacitance value between 100μF and 1000μF, used to filter high-frequency noise from the power supply. Furthermore, multiple capacitors of different capacitance values ​​can be connected in parallel between the first and second output terminals to optimize the power supply filtering effect.

[0024] By coordinating the design of MOSFET Q1 and the regulated power supply, precise control of power on / off is achieved. The high switching speed of MOSFET Q1 ensures rapid disconnection of the main power supply path during power failure, preventing reverse current. The combination of the regulated power supply and the filter capacitor guarantees the stability of the control unit's power supply. Compared with traditional switching devices such as mechanical relays, this solution offers advantages such as fast response speed, no contact wear, and long service life, effectively improving the reliability of the power-down protection system. In practical implementation, the selection of MOSFET Q1 needs to be determined based on the system operating current; typically, a model with an on-resistance of less than 50mΩ is chosen to ensure low conduction losses.

[0025] Furthermore, the gate of the MOS transistor Q1 is connected to one end of the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is connected to the drain of the MOS transistor Q1, and the other end of the second resistor R2 is connected to the collector of the transistor Q2. The emitter of transistor Q2 is grounded, and the base of transistor Q2 is connected to one end of the third resistor R3 and the fourth resistor R4, respectively. The other end of the third resistor R3 is grounded, and the other end of the fourth resistor R4 is connected to the control unit.

[0026] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider network to adjust the gate voltage of the MOSFET Q1. The transistor Q2, as a switching element, controls the conduction state of the collector-emitter path through its base current, thereby indirectly controlling the turn-on and turn-off of the MOSFET Q1. The third resistor R3 limits the base current of the transistor Q2, and the fourth resistor R4 acts as a pull-up resistor to ensure effective transmission of the control signal. The MOSFET Q1 is preferably an N-channel enhancement-mode MOSFET, and the transistor Q2 is preferably an NPN silicon transistor. In a preferred embodiment, the resistance ratio of the first resistor R1 to the second resistor R2 is 1:2, the resistance of the third resistor R3 ranges from 1kΩ to 10kΩ, and the resistance of the fourth resistor R4 ranges from 4.7kΩ to 47kΩ.

[0027] By leveraging the synergistic effect of a resistor network and transistor Q2, precise control of the gate voltage of MOSFET Q1 is achieved. Compared to existing solutions that directly drive MOSFET Q1 with a control signal, this design offers higher anti-interference capabilities and more stable switching characteristics. Specifically, the voltage divider network effectively suppresses the impact of power supply fluctuations on the operating state of MOSFET Q1, the transistor Q2 drive circuit provides sufficient drive current to ensure rapid switching of MOSFET Q1, and the thermal stability of the resistor network helps maintain the consistency of circuit parameters. This design is particularly suitable for industrial control environments requiring long-term reliable operation, effectively preventing malfunctions caused by component parameter drift.

[0028] Furthermore, one end of the energy storage capacitor C1 is grounded, and the other end is connected to the first output terminal of the regulated power supply through the fifth resistor R5.

[0029] The other end of the energy storage capacitor C1 is connected to the first output terminal of the regulated power supply via a fifth resistor R5. The fifth resistor R5 limits the charging current to prevent excessive charging current from damaging the energy storage capacitor C1. The resistance value of the fifth resistor R5 can be selected according to actual needs, for example, a resistor with a resistance value of 10 ohms to 100 ohms. The ground terminal of the energy storage capacitor C1 is directly connected to the system ground to ensure the stability of the reference potential. As a preferred embodiment, the fifth resistor R5 can be a metal film resistor or a carbon film resistor, which has high accuracy and stability. Furthermore, the energy storage capacitor C1 can be an electrolytic capacitor or a supercapacitor. The specific capacity can be selected according to the required maintenance time after a power outage, for example, an electrolytic capacitor with a capacity of 1000μF to 10000μF can be selected.

[0030] By connecting the energy storage capacitor C1 to the regulated power supply via the fifth resistor R5, the charging current of C1 is limited, preventing capacitor damage or shortened lifespan due to excessive charging current. Simultaneously, the grounding connection of C1 ensures the uniformity of the system reference potential, which is beneficial for improving voltage sampling accuracy. Compared with existing technologies, this solution extends the capacitor's lifespan and improves system reliability under power failure conditions while ensuring reliable charging of C1. Specifically, by appropriately selecting the value of the fifth resistor R5, a balance can be achieved between charging speed and capacitor protection, thereby optimizing system performance.

[0031] Furthermore, the other end of the energy storage capacitor C1 is also connected to the negative terminal of the diode D1, and the positive terminal of the diode D1 is connected to the control unit and the external power supply terminal respectively.

[0032] Specifically, the anode of diode D1 is connected to the control unit and the external power supply, while the cathode is connected to the energy storage capacitor C1. Diode D1 can be a silicon-based Schottky diode or a fast recovery diode, and its reverse breakdown voltage must be higher than the maximum operating voltage of the energy storage capacitor C1. In a preferred embodiment, the forward voltage drop of diode D1 should be less than 0.7V, and the reverse recovery time should not exceed 100ns. Thus, when the power supply is operating normally, the external power supply charges the energy storage capacitor C1 through diode D1; when the power supply fails, diode D1 prevents the energy in the energy storage capacitor C1 from flowing back into the power supply terminal, ensuring that the power is only supplied to the control unit.

[0033] By adding diode D1, unidirectional conduction control of the power path is achieved, effectively solving the problem of potential energy leakage from the energy storage capacitor C1 through the power supply terminal in traditional solutions. The specific working principle is as follows: Under normal power supply conditions, diode D1 is forward biased, allowing the external power supply to simultaneously power the control unit and charge the energy storage capacitor C1; when a power failure occurs, diode D1 automatically switches to reverse cutoff, blocking the discharge circuit of the energy storage capacitor C1 from flowing to the power supply terminal, thus ensuring that all the energy of the energy storage capacitor C1 is dedicated to maintaining the operation of the control unit. Compared with existing technologies, this solution improves the energy utilization rate of the energy storage capacitor C1, extends the system uptime after a power failure, and provides more reliable power protection for data storage and safe shutdown operations.

[0034] Furthermore, the sampling unit includes a capacitor voltage sampling circuit and a capacitor temperature sampling circuit; The capacitor voltage sampling circuit is used to monitor the voltage value of the energy storage capacitor C1 in real time and convert the voltage signal into a digital signal and transmit it to the control unit. The capacitor temperature sampling circuit is used to monitor the temperature status of the energy storage capacitor C1 in real time and convert the temperature signal into a digital signal and transmit it to the control unit.

[0035] Furthermore, the capacitor temperature sampling circuit includes a thermistor Rt1, one end of which is grounded, and the other end is connected to one end of the sixth resistor R6 and the seventh resistor R7 respectively. The other end of the sixth resistor R6 is connected to one end of the control unit and the second capacitor C3 respectively. The other end of the second capacitor C3 is grounded, and the other end of the seventh resistor R7 is connected to an external power supply.

[0036] Furthermore, the capacitor voltage sampling circuit includes an eighth resistor R8, one end of which is connected to the energy storage capacitor C1, and the other end is connected to one end of the ninth resistor R9 and the tenth resistor R10 respectively. The other end of the ninth resistor R9 is grounded, and the other end of the tenth resistor R10 is connected to one end of the third capacitor C4 and the control unit respectively. The other end of the third capacitor C4 is grounded.

[0037] Specifically, the thermistor Rt1, as a temperature-sensitive element, changes its resistance with temperature. By forming a voltage divider circuit with the thermistor Rt1, the sixth resistor R6, and the seventh resistor R7, the temperature change can be converted into a voltage signal. The second capacitor C3 is used to filter out high-frequency interference and ensure the stability of signal transmission. The control unit can obtain the temperature status of the energy storage capacitor C1 in real time by detecting the voltage value at the voltage divider point. As a preferred embodiment, the thermistor Rt1 can be a negative temperature coefficient type, whose resistance decreases as the temperature increases, thereby generating a voltage signal inversely proportional to temperature in the voltage divider circuit. The resistance values ​​of the sixth resistor R6 and the seventh resistor R7 can be matched and selected according to the temperature range and signal acquisition accuracy requirements of the specific application scenario.

[0038] In this embodiment, an internal ambient temperature sampling circuit is added. The CPU monitors and collects the system temperature, and the collected temperature is combined with the working life of the electrolytic capacitor for calculation. The reference formula for calculating the working life of the capacitor is as follows:

[0039] Among them, L0 specifies the capacitor's working life at rated temperature, L is the estimated capacitor life, T0 specifies the maximum working temperature value, and T is the actual working temperature value in °C.

[0040] In this embodiment, the selected capacitor is Jianghai CD287GC, with a capacitance of 1000uF / 10V and a service life of 3000h@105degC. Based on the actual measured capacitor temperature of 55degC, the calculated service life is:

[0041] The preliminary assessment of the capacitor's theoretical lifespan is 10.95 years.

[0042] The capacitor is automatically discharged every month, and the discharge time is recorded to confirm the degree of capacitance decay. Theoretically, this is calculated using the following formula: T = C x U / I; Where C is the capacitance value, U is the actual usable discharge voltage, I is the actual capacitor discharge current, and T is the discharge time to ensure the system supply voltage. The actual discharge time requirement T = 1000 x 1.5 / 0.5 = 3ms > the actual required discharge time of 2ms. If a value < 2ms is detected, the calculated capacitance is < 667uF. Based on the above capacitance calculation, the system control board capacitor status is promptly reported to remind the customer of the potential lifespan of the capacitors in the circuit, necessitating timely replacement or repair of the control board.

[0043] By setting up a dedicated capacitor temperature sampling circuit, real-time monitoring of the operating temperature of the energy storage capacitor C1 is achieved. The design using a thermistor Rt1 combined with a voltage divider circuit converts temperature changes into a measurable electrical signal, facilitating acquisition and processing by the control unit. Furthermore, the introduction of a second capacitor C3 for filtering effectively suppresses noise interference during signal transmission, improving the accuracy of temperature detection. Compared with existing technologies, this solution can promptly detect abnormal temperature rises in the energy storage capacitor C1, providing crucial information for assessing its performance and preventing the loss of power-off protection due to capacitor overheating failure.

[0044] Specifically, the eighth resistor R8 is used to sample the voltage of the energy storage capacitor C1 by voltage division. The eighth resistor R8 and the ninth resistor R9 form a voltage divider circuit, converting the high voltage of the energy storage capacitor C1 into a low voltage signal suitable for processing by the control unit. The tenth resistor R10 is used for current limiting to prevent excessive current from entering the control unit. The third capacitor C4 is used to filter out high-frequency interference signals, ensuring that the voltage signal transmitted to the control unit is stable and reliable. In a preferred embodiment, the resistance value of the eighth resistor R8 is in the range of 10kΩ to 100kΩ, the resistance value of the ninth resistor R9 is in the range of 1kΩ to 10kΩ, the resistance value of the tenth resistor R10 is in the range of 1kΩ to 5kΩ, and the capacitance value of the third capacitor C4 is in the range of 0.1μF to 1μF. Further, the eighth resistor R8 can be a metal film resistor with an accuracy of 1%, the ninth resistor R9 and the tenth resistor R10 can be carbon film resistors with an accuracy of 5%, and the third capacitor C4 can be a ceramic capacitor or a film capacitor.

[0045] The high voltage of the energy storage capacitor C1 is converted into a low voltage signal suitable for processing by the control unit through a voltage divider circuit, and interference is eliminated through a filter circuit, thereby achieving accurate monitoring of the voltage of the energy storage capacitor C1. Compared with existing technologies, this solution has the advantages of simple circuit structure, low cost, and high reliability. It can effectively solve the problem of traditional power failure protection systems lacking real-time monitoring of capacitor status, ensuring that the energy storage capacitor C1 can provide sufficient backup power when the power supply fails.

[0046] In this embodiment, when the system input voltage is normal, the regulated power supply outputs power to the control unit and other circuits. Simultaneously, the energy storage capacitor C1 is charged with current limiting through the first resistor R1. The control unit monitors the voltage of the energy storage capacitor C1 in real time through the sampling unit, and can also monitor the real-time temperature data of the energy storage capacitor C1. During the AGV system power-down process, the control unit detects the discharge time of the energy storage capacitor C1, calculates the capacity value of the energy storage capacitor C1 using the charge formula, confirms whether the energy storage capacitor C1 is abnormal and whether the capacity decay meets the requirements, and reports the status of the energy storage capacitor C1 to the host computer, serving as a timely reminder to the user. When the regulated power supply input voltage is abnormal or disconnected, the regulated power supply input voltage drops. At this time, the energy storage capacitor C1 will supply power to the control unit and other circuits through diode D1 with zero switching time, waiting to ensure CPU data saving, fault information upload, and control process completion.

[0047] The above-described specific examples are for illustrative purposes only and are not intended to limit the scope of this invention. Those skilled in the art to which this invention pertains can make various simple deductions, modifications, or substitutions based on the concept of this invention.

Claims

1. A CPU power-down delay monitoring circuit, characterized in that, Includes a power supply unit, energy storage capacitor, sampling unit, and control unit; The power supply unit is used to supply power to the control unit, the sampling unit and the control unit, and to charge the energy storage capacitor; The energy storage capacitor is used to store electrical energy and provide backup power to the control unit and the sampling unit when the power supply unit loses power. The sampling unit collects the voltage data of the energy storage capacitor and transmits it to the control unit; The control unit is used to evaluate the state of the energy storage capacitor based on the data collected by the sampling unit, and to save data and control the AGV system to perform a safe stopping operation by using the power provided by the energy storage capacitor when the power is lost.

2. The CPU power-down delay monitoring circuit as described in claim 1, characterized in that, The power supply unit includes a regulated power supply and a control switch, wherein the control switch is a MOSFET. The first output terminal of the regulated power supply is connected to the drain of the MOSFET, and the second output terminal of the regulated power supply is grounded. A first capacitor is connected in parallel between the first output terminal and the second output terminal of the regulated power supply.

3. The CPU power-down delay monitoring circuit as described in claim 2, characterized in that, The gate of the MOS transistor is connected to one end of a first resistor and a second resistor, the other end of the first resistor is connected to the drain of the MOS transistor, and the other end of the second resistor is connected to the collector of the transistor. The emitter of the transistor is grounded, the base of the transistor is connected to one end of the third resistor and the fourth resistor respectively, the other end of the third resistor is grounded, and the other end of the fourth resistor is connected to the control unit.

4. The CPU power-down delay monitoring circuit as described in claim 2, characterized in that, One end of the energy storage capacitor is grounded, and the other end is connected to the first output terminal of the regulated power supply through a fifth resistor.

5. The CPU power-down delay monitoring circuit as described in claim 4, characterized in that, The other end of the energy storage capacitor is also connected to the negative terminal of a diode, and the positive terminal of the diode is connected to the control unit and the external power supply terminal respectively.

6. The CPU power-down delay monitoring circuit as described in claim 1, characterized in that, The sampling unit includes a capacitor voltage sampling circuit and a capacitor temperature sampling circuit. The capacitor voltage sampling circuit is used to monitor the voltage value of the energy storage capacitor in real time and convert the voltage signal into a digital signal and transmit it to the control unit. The capacitor temperature sampling circuit is used to monitor the temperature status of the energy storage capacitor in real time and convert the temperature signal into a digital signal for transmission to the control unit.

7. The CPU power-down delay monitoring circuit as described in claim 6, characterized in that, The capacitor temperature sampling circuit includes a thermistor, one end of which is grounded, and the other end is connected to one end of a sixth resistor and a seventh resistor respectively. The other end of the sixth resistor is connected to one end of a control unit and a second capacitor respectively. The other end of the second capacitor is grounded, and the other end of the seventh resistor is connected to an external power supply.

8. The CPU power-down delay monitoring circuit as described in claim 6, characterized in that, The capacitor voltage sampling circuit includes an eighth resistor, one end of which is connected to the energy storage capacitor, and the other end is connected to one end of a ninth resistor and a tenth resistor respectively. The other end of the ninth resistor is grounded, and the other end of the tenth resistor is connected to one end of a third capacitor and the control unit respectively. The other end of the third capacitor is grounded.

Images