Cell structure of semiconductor device and semiconductor device

Abstract

The application provides a cell structure of a semiconductor device and the semiconductor device. The cell structure comprises: a base including a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate; a JFET structure including a first sub-JFET structure and a second sub-JFET structure, the second sub-JFET structure protruding from the epitaxial layer, a surface of the substrate in contact with the epitaxial layer being a first surface, the second sub-JFET structure having a first projection on the first surface, the first sub-JFET structure having a second projection on the first surface, the first projection being located in the second projection, and the width of the first projection being smaller than the width of the second projection in a first direction; and a gate structure including a first part and a second part, the first part and the second part being respectively located on two sides of the second sub-JFET structure in the first direction, and the first part and the second part being further located on a side of the epitaxial layer away from the substrate, thereby solving the problem of increased on-resistance caused by improved switching speed of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a cell structure and a semiconductor device. Background Technology

[0002] The split-gate design of SiC MOSFETs optimizes gate voltage control by introducing multiple independent gate structures on the gate, thereby reducing the overall gate size, lowering gate capacitance, and ultimately improving the device's switching speed. However, with the increasing demand for higher switching frequencies and lower power consumption, the limitations of traditional split-gate designs are becoming increasingly apparent. On the one hand, while reducing the gate size effectively reduces gate capacitance, it inevitably increases on-resistance. On the other hand, the electron storage and flow paths in the JFET region (i.e., the junction field-effect transistor region) often suffer from carrier congestion in a single horizontal structure, limiting device performance.

[0003] Therefore, while pursuing high-speed switching and low power consumption, existing SiC MOSFET devices face the technical challenge of achieving low on-resistance.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Utility Model Content

[0005] The main objective of this application is to provide a cellular structure for a semiconductor device and a semiconductor device in order to solve the problem of increased on-resistance caused by increasing the switching speed of semiconductor devices in the prior art.

[0006] To achieve the above objectives, according to one aspect of this application, a cellular structure for a semiconductor device is provided, comprising: a substrate, including a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate; a JFET structure, including a first sub-JFET structure and a second sub-JFET structure, the first sub-JFET structure being located in the epitaxial layer, the second sub-JFET structure protruding from the epitaxial layer, the surface of the substrate in contact with the epitaxial layer being a first surface, the second sub-JFET structure having a first projection on the first surface, the first sub-JFET structure having a second projection on the first surface, the first projection being located within the second projection, and in a first direction, the width of the first projection being smaller than the width of the second projection; and a gate structure, including a first portion and a second portion, the first portion and the second portion being located on opposite sides of the second sub-JFET structure in a first direction, the first portion and the second portion also being located on the side of the epitaxial layer facing away from the substrate, the first direction being perpendicular to the thickness direction of the substrate.

[0007] Optionally, the first projection and the second projection share a symmetry axis in a second direction, which is perpendicular to the first direction and also perpendicular to the thickness direction of the substrate.

[0008] Optionally, the cell structure further includes a source region structure located in the epitaxial layer and on both sides of the first sub-JFET structure in the first direction, and the gate structure located on the side of the source region structure away from the substrate.

[0009] Optionally, the source region structure includes a first doped region, a second doped region, and a third doped region, wherein the first doped region contacts both sides of the first sub-JFET structure in the first direction, and the first doped region has a first doping type; the second doped region is located on the side of the first doped region away from the first sub-JFET structure, and is located on the side of the third doped region close to the first sub-JFET structure, the second doped region has a second doping type, the third doped region has the aforementioned first doping type, and the gate structure contacts a portion of the first doped region and the second doped region.

[0010] Optionally, the surface of the epitaxial layer facing away from the substrate is a second surface. The gate structure includes a gate oxide layer, a polysilicon gate, and a gate electrode. A portion of the gate oxide layer is located between the polysilicon gate and the second sub-JFET structure, and another portion of the gate oxide layer is located on the side of the polysilicon gate closer to the epitaxial layer. The maximum distance between the polysilicon gate and the second surface is greater than the maximum distance between the second sub-JFET structure and the second surface. The gate electrode is located on the side of the polysilicon gate facing away from the substrate.

[0011] Optionally, the polysilicon gate includes a first sub-polysilicon gate and a second sub-polysilicon gate. The first sub-polysilicon gate is located on the side of the second sub-polysilicon gate and the gate oxide layer away from the substrate. The gate electrode is located on the side of the second sub-polysilicon gate away from the substrate. A portion of the gate oxide layer is located between the second sub-polysilicon gate and the second sub-JFET structure, and another portion of the gate oxide layer is located on the side of the second sub-polysilicon gate near the epitaxial layer.

[0012] Optionally, the side surface of the second sub-polysilicon gate near the gate oxide layer is located in the same plane as the side surface of the first sub-JFET structure, and the side surface of the gate oxide layer and the side surface of the first sub-JFET structure are located on the same side in the first direction.

[0013] Optionally, the cell structure further includes a source electrode, a drain electrode, and an ohmic contact layer, wherein the ohmic contact layer covers the source region structure, the source electrode covers the ohmic contact layer and is located on the side of the gate structure away from the substrate, and the drain electrode is located on the side of the substrate away from the epitaxial layer.

[0014] Optionally, the maximum distance between the second sub-JFET structure and the surface of the epitaxial layer facing away from the substrate is 0.1 to 0.3 μm.

[0015] According to another aspect of this application, a semiconductor device is provided, comprising at least one cellular structure of a semiconductor device.

[0016] Applying the technical solution of this application, the cell structure includes a substrate, a JFET structure, and a gate structure. The JFET structure includes a first sub-JFET structure and a second sub-JFET structure. The first sub-JFET structure is located in the epitaxial layer, and the second sub-JFET structure protrudes from the epitaxial layer. By setting the JFET structure of the cell structure to a mesa shape to form the second sub-JFET structure, the mesa structure provides additional electron flow paths, reducing electron congestion in the JFET region and thus lowering the on-resistance. This structure optimizes electron storage and flow paths, solving the carrier congestion problem. This allows for increased switching speed while maintaining low on-resistance, achieving a dual optimization of high switching frequency and low on-resistance. It also solves the problem of increased on-resistance caused by increased switching speed in existing semiconductor devices. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A cross-sectional schematic diagram of the cell structure of a semiconductor device according to an embodiment of this application is shown;

[0019] Figure 2 It shows Figure 1 A schematic diagram of a partial cross-sectional structure of region A in the diagram.

[0020] The above figures include the following reference numerals:

[0021] 10. Substrate; 11. Substrate; 12. Epitaxial layer; 20. JFET structure; 21. First sub-JFET structure; 22. Second sub-JFET structure; 30. Gate structure; 31. Gate oxide layer; 32. Polysilicon gate; 321. First sub-polysilicon gate; 322. Second sub-polysilicon gate; 33. Gate electrode; 40. Source region structure; 41. First doped region; 42. Second doped region; 43. Third doped region; 50. Gate dielectric layer; 60. Source electrode; 70. Drain electrode; 80. Ohmic contact layer. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the utility model described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0026] As described in the background section, existing SiC MOSFET devices face the technical challenge of achieving both high-speed switching and low power consumption while simultaneously maintaining low on-resistance. To address the issue of increased on-resistance due to improved switching speed in semiconductor devices, embodiments of this application provide a cellular structure and a semiconductor device.

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.

[0028] According to one aspect of the embodiments of this application, a cell structure for a semiconductor device is provided, such as... Figure 1 As shown, it includes: a substrate 10, including a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 being located on one side of the substrate 11; a JFET structure 20, including a first sub-JFET structure 21 and a second sub-JFET structure 22, the first sub-JFET structure 21 being located in the epitaxial layer 12, the second sub-JFET structure 22 protruding from the epitaxial layer 12, the surface of the substrate 11 in contact with the epitaxial layer 12 being a first surface, the second sub-JFET structure 22 having a first projection on the first surface, the first sub-JFET structure 21 having a second projection on the first surface, the first projection being located in the second projection, and in the first direction X, the width of the first projection being smaller than the width of the second projection; a gate structure 30, including a first part and a second part, the first part and the second part being located on opposite sides of the second sub-JFET structure in the first direction, the first part and the second part also being located on the side of the epitaxial layer 12 away from the substrate 11, the first direction X being perpendicular to the thickness direction of the substrate 10.

[0029] By setting the cell-structured JFET structure to a mesa shape, a second sub-JFET structure is formed. The mesa structure provides additional electron flow paths, reducing electron congestion in the JFET region and thus lowering the on-resistance. This structure optimizes electron storage and flow paths, solving the carrier congestion problem. This allows for increased switching speed with a smaller gate structure while maintaining low on-resistance, achieving a dual optimization of high switching frequency and low on-resistance. It also solves the problem of increased on-resistance caused by increased switching speed of semiconductor devices in existing technologies.

[0030] In the above embodiments, the substrate consists of a substrate and an epitaxial layer, both of which can be made of N-type SiC. The epitaxial layer will bear the main breakdown voltage, and its resistivity can be 0.02 ± 20% Ωcm, with a doping concentration of 1E+15 to 1E+16 cm⁻¹. -3 The thickness is adjusted according to the product voltage level. For example, for a 1200V MOSFET, the thickness of the epitaxial layer can be designed to be 9-11μm; for a 650V MOSFET, the thickness is 5-7μm.

[0031] In the above embodiments, the split-gate structure allows for a smaller gate size compared to a single-gate structure, reducing gate capacitance. This reduction in gate size and distance between the gate electrode and the P-type source region further lowers gate capacitance, improving switching speed and directly reducing switching losses. Furthermore, introducing multiple gate structures on the MOSFET gate optimizes gate voltage control, reduces gate size, decreases gate capacitance, and improves device switching speed. The thickness of the second sub-JFET structure can be 0.1-0.3 μm, providing more pathways for electron flow and resolving carrier congestion in the JFET region with a split gate, thus reducing the device's on-resistance.

[0032] In the above embodiments, the second sub-JFET structure can have one sidewall flush with one sidewall of the first sub-JFET structure, and the other sidewall recessed inwards compared to the sidewall of the first sub-JFET structure; alternatively, both sidewalls of the second sub-JFET structure can be recessed inwards relative to the sidewalls of the first sub-JFET structure. In the original planar horizontal structure, when the device is turned on, the carriers are mainly concentrated in the inversion layer formed on the semiconductor surface of the P-type structure region near the source region of the JFET region. Adding the protruding mesa structure to the JFET region provides an additional flow path for the carriers in the upper half of the region. The mesa sidewalls also form an inversion layer, which, compared to the original planar structure, effectively increases the area of ​​the inversion layer, allowing for a larger flow area for the carriers. This solves the problem of carrier congestion in the original JFET region and improves the on-resistance. The aforementioned inversion layer is formed by applying a negative gate voltage to the surface of the P-type structure region of the source region, attracting the previously scarce free electrons to the surface.

[0033] In the above embodiments, the implanted element in the JFET structure can be an N-type element, and its implantation dose can be 1E18±50%cm. -3 The implantation depth can be 0.8–0.9 μm to form an N-type doped region, which can reduce the on-resistance.

[0034] In some alternative implementations, such as Figure 1As shown, the first projection and the second projection share a common axis of symmetry in the second direction Y. The second direction Y is perpendicular to the first direction X and also perpendicular to the thickness direction of the substrate 10. This allows both sidewalls of the second sub-JFET structure 22 in the first direction X to be recessed inward. This can be achieved by etching both sides of the protruding second sub-JFET structure 22 inward during fabrication. The step at the recessed area then forms the subsequent gate structure. This helps optimize the uniformity of gate voltage control, ensuring that current flows uniformly through the JFET structure when the device is turned on, reducing the risk of localized overheating, and improving the long-term stability and durability of the device.

[0035] In some alternative implementations, such as Figure 1 As shown, the cell structure also includes a source region structure 40, which is located in the epitaxial layer 12 and on both sides of the first sub-JFET structure 21 in the first direction X. The gate structure 30 is located on the side of the source region structure 40 facing away from the substrate 11. The source region structure 40 forms a tight electrical connection with the JFET structure 20 and the gate structure 30. This layout optimizes the contact between the source region structure 40 and the JFET structure 20, further enhancing the carrier flow efficiency and optimizing the on-resistance of the device.

[0036] In some alternative implementations, such as Figure 1 As shown, the source region structure 40 includes a first doped region 41, a second doped region 42, and a third doped region 43. The first doped region 41 contacts both sides of the first sub-JFET structure 21 in the first direction X, and has a first doping type. The second doped region 42 is located on the side of the first doped region 41 facing away from the first sub-JFET structure 21, and on the side of the third doped region 43 close to the first sub-JFET structure 21. The second doped region 42 has a second doping type, and the third doped region 43 has the aforementioned first doping type. The gate structure 30 contacts a portion of the first doped region 41 and the second doped region 42. The P-type doping of the first doped region 41 helps to form a stable source contact because it can suppress the lateral expansion of the N-type region, prevent the source electrode from directly contacting the drift region, and thus avoid short circuits. Furthermore, the first doped region 41 (P-well) can also reduce the parasitic capacitance between the source and the drift region to a certain extent, optimize gate voltage control, and improve the switching speed of the device. The second doped region 42 is an N-type doped region that forms a PN junction structure with the first doped region 41. Current can flow into the substrate 10 through this PN junction and then to the drain. The doping type of the third doped region 43 is the same as that of the first doped region 41 and the opposite of that of the second doped region 42, which can prevent the parasitic transistor of the device from turning on.

[0037] In the above optional embodiments, the doping type of the first doped region 41 can be p-type, the implanted element can be Al, and the amount of implantant can be 1E17±50%cm. -3 The implantation depth can be 0.7–0.8 μm, allowing control over the conductivity and threshold voltage of the source region structure 40. The second doped region 42 can be N-type, with the implanted element being nitrogen, and the implantation dose can be 1E19–1E20 cm⁻¹. -3 The implantation depth can be 0.2–0.3 μm. The lateral distance between the edges of the second doped region 42 and the first doped region 41 is the channel width. The width of the second doped region 42 can be adjusted according to design requirements, and the channel width can be 0.3–0.6 μm. The doping type of the third doped region 43 can be P-type, and the implanted element can be Al, with an implantation dose of 1E19 ± 50% cm⁻¹. -3 The injection depth can be 0.2–0.3 μm.

[0038] In some alternative implementations, such as Figure 1 As shown, the surface of the epitaxial layer 12 facing away from the substrate 11 is the second surface. The gate structure 30 includes a gate oxide layer 31, a polysilicon gate 32, and a gate electrode 33. A portion of the gate oxide layer 31 is located between the polysilicon gate 32 and the second sub-JFET structure 22, while another portion is located on the side of the polysilicon gate 32 closest to the epitaxial layer 12. The maximum distance between the polysilicon gate 32 and the second surface is greater than the maximum distance between the second sub-JFET structure 22 and the second surface. The gate electrode 33 is located on the side of the polysilicon gate 32 facing away from the substrate 11. The gate oxide layer 31 (also called the gate oxide layer) is an insulating layer located between the polysilicon gate 32 and the semiconductor material (source structure 40, drift region, etc.). Its main function is to provide an electric field isolation, ensuring that the gate voltage can effectively control the movement of charge carriers in the semiconductor material, forming or cutting off the conductive channel. The polysilicon gate 32 is a layer of polysilicon deposited on the gate oxide layer 31, used to establish the connection between the gate electrode 33 and the underlying semiconductor material. It controls the formation or shutdown of the channel by attracting or repelling charge carriers in the semiconductor through controlling the voltage (gate voltage) applied to it. The gate electrode 33 is the metal contact in the device used to apply the gate voltage. It is connected to the polysilicon gate 32 and controls the conductivity state of the channel by changing its voltage, thereby controlling the switching behavior of the MOSFET. The thickness of the gate oxide layer can be... The thickness of the polysilicon gate can be

[0039] In some alternative implementations, such as Figure 1 and Figure 2As shown, the polysilicon gate 32 includes a first sub-polysilicon gate 321 and a second sub-polysilicon gate 322. The first sub-polysilicon gate 321 is located on the side of the second sub-polysilicon gate 322 and the gate oxide layer 31 facing away from the substrate 11. The gate electrode 33 is located on the side of the second sub-polysilicon gate 322 facing away from the substrate 11. A portion of the gate oxide layer 31 is located between the second sub-polysilicon gate 322 and the second sub-JFET structure 22, and another portion of the gate oxide layer 31 is located on the side of the second sub-polysilicon gate 322 closer to the epitaxial layer 12. The split gate design can significantly reduce the gate capacitance by reducing the size of each gate portion. Reducing the gate capacitance helps improve the switching speed of the device and reduce switching losses, which is particularly advantageous for high-frequency applications. The layout of the first sub-polysilicon gate 321 and the second sub-polysilicon gate 322, as well as the position of the gate oxide layer 31, allows the gate structure 30 to more precisely control the electron flow in the JFET structure 20, improving the gate voltage control efficiency and ensuring the stability and reliability of the device during high-frequency operation. Although split-gate designs typically lead to increased on-resistance, the precise layout described above, especially the optimized shape of the second sub-JFET structure and the formation of a mesa structure between the first sub-polysilicon gate 321 and the second sub-polysilicon gate 322, effectively reduces on-resistance.

[0040] In some alternative implementations, such as Figure 1 and Figure 2 As shown, the surface of the second sub-polysilicon gate 322 near the gate oxide layer 31 is in the same plane as the surface of the first sub-JFET structure 21, and the surface of the gate oxide layer 31 and the surface of the first sub-JFET structure 21 are on the same side in the first direction X. The second sub-JFET structure 22 has mesa structures on both sides in the first direction X, reserving space for the subsequent growth of the gate structure 30. This ensures that the edge of the subsequently fabricated gate structure 30 is aligned with the edge of the first doped region 41 as much as possible, within the limits of process precision. This minimizes the lateral dimension of the gate structure 30, thereby reducing the gate capacitance and improving the switching speed of the device. The width of the additional etching in the unimplanted area near the first doped region 41 should be adjusted according to the thickness of the subsequent gate dielectric layer, and is typically less than 0.1 μm.

[0041] The second sub-JFET structure has mesa structures on both sides in the first direction. The length of this mesa structure in the first direction can be the thickness of the gate oxide, and the thickness of the gate oxide can be... The size of this split gate structure can be compressed to just the length of the channel plus the length of the second doping, which can be 0.3-0.6μm, further improving the switching speed of the device and reducing losses.

[0042] In the above optional implementations, such as Figure 1As shown, the cell structure also includes a gate dielectric layer 50, which covers the gate structure 30 and the second sub-JFET structure 22. The material can be SiO2 or SiN. x The thickness can be 600-1000nm, and the gate dielectric layer 50 is used to isolate the JFET structure 20 and the gate structure 30 from the source electrode 60.

[0043] In some optional embodiments, the cell structure further includes a source electrode 60, a drain electrode 70, and an ohmic contact layer 80. The ohmic contact layer 80 covers the source region structure 40, the source electrode 60 covers the ohmic contact layer 80 and is located on the side of the gate structure 30 facing away from the substrate 11, and the drain electrode 70 is located on the side of the substrate 11 facing away from the epitaxial layer 12. The source electrode 60 serves as the electrical interface between the external circuit and the source region structure 40, responsible for introducing current into the device. It covers the ohmic contact layer 80, ensuring good electrical contact with the source region structure 40, thereby optimizing current input efficiency. The drain electrode 70, located on the side of the substrate 11 facing away from the epitaxial layer 12, is mainly responsible for leading out current and forming an electrical connection with the external circuit; it is a crucial part of the MOSFET device's current output. The main function of the ohmic contact layer 80 is to provide a low-resistance contact, enabling the source electrode 60 to form an effective electrical connection with the doped regions in the source region structure 40.

[0044] In the above optional embodiments, the source electrode can be made of aluminum (Al), copper (Cu), or silver (Ag). In some cases, to enhance reliability or adapt to special operating conditions, metals with better oxidation resistance or high-temperature stability, such as titanium (Ti), molybdenum (Mo), or nickel (Ni), may be selected. The material selection for the drain electrode 70 is similar to that of the source electrode, tending to use metals with high conductivity, such as aluminum (Al), copper (Cu), or silver (Ag). In certain power devices, composite materials such as aluminum-silicon alloys or copper-tungsten alloys may be used to increase the contact area between the electrode and the substrate and improve current carrying capacity. The ohmic contact layer can be made of Ni, Ti, or other materials, with a thickness of...

[0045] In some alternative implementations, the maximum distance between the second sub-JFET structure and the epitaxial layer's surface facing away from the substrate is 0.1–0.3 μm. Controlling the distance between the second sub-JFET structure and the epitaxial layer to 0.1–0.3 μm ensures that charge carriers (electrons or holes) can be rapidly and efficiently transported from the source region to the drift region and then through the channel to the drain region in the on-state. This optimized distance helps to create shorter electron paths, reducing resistance during electron transport and thus lowering the device's on-resistance. Furthermore, the shorter spacing helps to reduce the device's internal capacitance, especially the gate capacitance, which is crucial for improving the MOSFET's switching speed. Increased switching speed means reduced switching losses and improved overall energy efficiency in high-frequency applications. Providing appropriate space between the second sub-JFET structure and the epitaxial layer avoids excessive concentration of charge carriers in this region, reducing the so-called "carrier congestion" phenomenon, thereby ensuring a uniform distribution of charge carriers within the device and improving current transport efficiency and stability.

[0046] According to another aspect of the embodiments of this application, a semiconductor device is provided, including at least one cellular structure of a semiconductor device.

[0047] By employing at least one of the aforementioned cell structures to form a semiconductor device, the JFET structure of each cell structure in the semiconductor device is configured as a mesa shape to form a second sub-JFET structure. The mesa structure provides additional electron flow paths, reducing electron congestion in the JFET region and thus lowering the on-resistance. This structure optimizes electron storage and flow paths, solving the carrier congestion problem. This allows for increased switching speed while maintaining low on-resistance, achieving a dual optimization of high switching frequency and low on-resistance. It also solves the problem of increased on-resistance caused by increased switching speed of semiconductor devices in the prior art.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A cellular structure for a semiconductor device, characterized in that, include: A substrate, comprising a substrate and an epitaxial layer, wherein the epitaxial layer is located on one side of the substrate; The JFET structure includes a first sub-JFET structure and a second sub-JFET structure. The first sub-JFET structure is located in the epitaxial layer, and the second sub-JFET structure protrudes from the epitaxial layer. The surface of the substrate that contacts the epitaxial layer is a first surface. The second sub-JFET structure has a first projection on the first surface, and the first sub-JFET structure has a second projection on the first surface. The first projection is located in the second projection. In a first direction, the width of the first projection is smaller than the width of the second projection. The gate structure includes a first part and a second part, the first part and the second part being located on opposite sides of the second sub-JFET structure in a first direction, and the first part and the second part being located on the side of the epitaxial layer away from the substrate, the first direction being perpendicular to the thickness direction of the substrate.

2. The cell structure of the semiconductor device according to claim 1, characterized in that, The first projection and the second projection share a symmetry axis in a second direction, which is perpendicular to the first direction and also perpendicular to the thickness direction of the substrate.

3. The cell structure of the semiconductor device according to claim 1, characterized in that, The cell structure further includes a source region structure located in the epitaxial layer and on both sides of the first sub-JFET structure in the first direction, and the gate structure located on the side of the source region structure away from the substrate.

4. The cell structure of the semiconductor device according to claim 3, characterized in that, The source region structure includes a first doped region, a second doped region, and a third doped region, wherein, The first doped region is in contact with both sides of the first sub-JFET structure in the first direction, and the first doped region has a first doping type; The second doped region is located on the side of a portion of the first doped region away from the first sub-JFET structure, and on the side of the third doped region close to the first sub-JFET structure. The second doped region has a second doping type, and the third doped region has the aforementioned first doping type. The gate structure is in contact with a portion of the first doped region and the second doped region.

5. The cell structure of the semiconductor device according to claim 1, characterized in that, The surface of the epitaxial layer facing away from the substrate is a second surface. The gate structure includes a gate oxide layer, a polysilicon gate, and a gate electrode. A portion of the gate oxide layer is located between the polysilicon gate and the second sub-JFET structure, and another portion of the gate oxide layer is located on the side of the polysilicon gate closer to the epitaxial layer; The maximum distance between the polysilicon gate and the second surface is greater than the maximum distance between the second sub-JFET structure and the second surface; The gate electrode is located on the side of the polysilicon gate opposite to the substrate.

6. The cell structure of the semiconductor device according to claim 5, characterized in that, The polysilicon gate includes a first sub-polysilicon gate and a second sub-polysilicon gate. The first sub-polysilicon gate is located on the side of the second sub-polysilicon gate and the gate oxide layer away from the substrate. The gate electrode is located on the side of the second sub-polysilicon gate away from the substrate. A portion of the gate oxide layer is located between the second sub-polysilicon gate and the second sub-JFET structure, and another portion of the gate oxide layer is located on the side of the second sub-polysilicon gate near the epitaxial layer.

7. The cell structure of the semiconductor device according to claim 6, characterized in that, The second sub-polysilicon gate has its side surface near the gate oxide layer in the same plane as the side surface of the first sub-JFET structure, and the side surface of the gate oxide layer and the side surface of the first sub-JFET structure are on the same side in the first direction.

8. The cell structure of the semiconductor device according to claim 3, characterized in that, The cell structure further includes a source electrode, a drain electrode, and an ohmic contact layer, wherein the ohmic contact layer covers the source region structure, the source electrode covers the ohmic contact layer and is located on the side of the gate structure away from the substrate, and the drain electrode is located on the side of the substrate away from the epitaxial layer.

9. The cell structure of the semiconductor device according to claim 1, characterized in that, The maximum distance between the second sub-JFET structure and the epitaxial layer on the side facing away from the substrate is 0.1 to 0.3 μm.

10. A semiconductor device, characterized in that, It includes at least one cellular structure of a semiconductor device according to any one of claims 1 to 9.

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