A MOS transistor structure with high reliability

Abstract

The utility model discloses a high reliability's MOS transistor structure belongs to MOS transistor field, including semiconductor substrate, its characterized in that, the middle part of semiconductor substrate top is equipped with the groove, and the both sides of semiconductor substrate top are equipped with source slot and drain slot respectively, and the inside of source slot is provided with source level part, and the inside of drain slot is provided with drain level part, gate component, including the polycrystalline silicon gate of setting in the groove inside, and the polycrystalline silicon gate is equipped with gate oxide layer between semiconductor substrate, and the both sides of polycrystalline silicon gate are equipped with side wall isolation structure, and the top of polycrystalline silicon gate is equipped with gate metal layer. Through gate component, the setting of side wall isolation structure reduces the electric leakage risk between gate and source, drain, improves the electrical performance stability of device, and the covering of passivation layer effectively prevents the damage of external environmental factors to device, strengthens the moisture resistance and corrosion resistance of device, thereby improves the overall reliability and stability of device.

Description

Technical Field

[0001] This utility model relates to the field of MOS transistor technology, and in particular to a highly reliable MOS transistor structure. Background Technology

[0002] A transistor is a single component based on semiconductor materials. Transistors have multiple functions, including detection, rectification, amplification, switching, voltage regulation, and signal modulation. They can be used in a wide variety of digital and analog applications. Transistors are one of the most critical components in modern electrical appliances. The reason transistors can be used on a large scale is because they can be mass-produced at extremely low unit cost.

[0003] Traditional MOS transistors perform poorly in terms of moisture and corrosion resistance, and are prone to failure in humid or corrosive environments, reducing device reliability. Furthermore, existing MOS transistor structures have certain defects in the layout and isolation methods of the gate, source, and drain, making them susceptible to leakage current. Utility Model Content

[0004] The purpose of this invention is to address the shortcomings of traditional MOS transistors in terms of moisture and corrosion resistance, which make them prone to failure in humid or corrosive environments, thus reducing device reliability. Furthermore, existing MOS transistor structures have certain deficiencies in the layout and isolation methods of the gate, source, and drain, making them susceptible to leakage current problems. Therefore, this invention proposes a highly reliable MOS transistor structure.

[0005] To achieve the above objectives, the present invention employs the following technology: a highly reliable MOS transistor structure, comprising a semiconductor substrate, characterized in that a trench is formed in the middle of the top of the semiconductor substrate, and a source trench and a drain trench are formed on both sides of the top of the semiconductor substrate, respectively, a source portion is provided inside the source trench, and a drain portion is provided inside the drain trench.

[0006] The gate assembly includes a polysilicon gate disposed inside a trench, a gate oxide layer disposed between the polysilicon gate and a semiconductor substrate, sidewall isolation structures disposed on both sides of the polysilicon gate, a gate metal layer disposed on top of the polysilicon gate, and a passivation layer connected to the top of the gate metal layer.

[0007] As a further description of the above technical solution: the semiconductor substrate has grooves on both sides, and a heat dissipation mechanism is provided inside the grooves.

[0008] As a further description of the above technical solution: the heat dissipation mechanism includes a heat-conducting plate disposed inside the groove, and a heat sink is disposed on the other side of the heat-conducting plate.

[0009] As a further description of the above technical solution: the passivation layer is a bilayer composite structure of silicon nitride and polyimide.

[0010] As a further description of the above technical solution: the heat-conducting plate is made of a material with high thermal conductivity, such as copper or graphite.

[0011] As a further description of the above technical solution: a substrate is connected to the bottom of the semiconductor substrate.

[0012] As a further description of the above technical solution: the sidewall isolation structure is composed of an inner layer of silicon nitride and an outer layer of silicon oxide, with a total thickness of 30-80nm.

[0013] In summary, due to the adoption of the above technical solution, the beneficial effects of this utility model are:

[0014] By configuring the gate assembly, the sidewall isolation structure reduces the risk of leakage between the gate and the source / drain, improving the electrical performance stability of the device. The passivation layer effectively prevents damage to the device from external environmental factors, enhances the device's resistance to moisture and corrosion, thereby improving the overall reliability and stability of the device. Attached Figure Description

[0015] Figure 1 A schematic diagram of the overall structure according to an embodiment of the present utility model is shown;

[0016] Figure 2 A schematic diagram of a gate assembly structure according to an embodiment of the present invention is shown;

[0017] Figure 3 A schematic diagram of the heat dissipation mechanism provided according to an embodiment of the present invention is shown.

[0018] Legend:

[0019] 1. Semiconductor substrate; 2. Trench; 3. Source trench; 4. Drain trench; 5. Source section; 6. Gate assembly; 601. Polysilicon gate; 602. Gate oxide layer; 603. Sidewall isolation structure; 604. Gate metal layer; 605. Passivation layer; 7. Heat dissipation mechanism; 701. Heat-conducting plate; 702. Heat sink; 8. Substrate; 9. Drain section. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0021] Reference Figures 1-3 The embodiment provides a highly reliable MOS transistor structure, including a semiconductor substrate 1, a trench 2 formed in the middle of the top of the semiconductor substrate 1, a source trench 3 and a drain trench 4 formed on both sides of the top of the semiconductor substrate 1, a source part 5 is provided inside the source trench 3, and a drain part 5 is provided inside the drain trench 4.

[0022] The gate assembly 6 includes a polysilicon gate 601 disposed inside the trench 2, a gate oxide layer 602 disposed between the polysilicon gate 601 and the semiconductor substrate 1, sidewall isolation structures 603 disposed on both sides of the polysilicon gate 601, a gate metal layer 604 disposed on the top of the polysilicon gate 601, and a passivation layer 605 connected to the top of the gate metal layer 604.

[0023] The sidewall isolation structure 603 reduces the risk of leakage between the gate and the source and drain, and improves the electrical performance stability of the device. The passivation layer 605 effectively prevents damage to the device from external environmental factors, enhances the device's resistance to moisture and corrosion, and thus improves the overall reliability and stability of the device.

[0024] Specifically, such as Figure 1 and Figure 3 As shown, grooves are formed on both sides of the semiconductor substrate 1, and a heat dissipation mechanism 7 is provided inside the grooves.

[0025] The semiconductor substrate 1 is effectively cooled by the heat dissipation mechanism 7.

[0026] Specifically, such as Figure 1 and Figure 3 As shown, the heat dissipation mechanism 7 includes a heat-conducting plate 701 disposed inside the groove, and a heat sink 702 disposed on the other side of the heat-conducting plate 701.

[0027] The heat generated by the semiconductor substrate 1 is conducted to the heat-conducting plate 701, and then diffused out through the heat sink 702 for heat dissipation.

[0028] Specifically, such as Figure 2 As shown, the passivation layer 605 is a bilayer composite structure of silicon nitride and polyimide.

[0029] The silicon nitride and polyimide double-layer composite structure effectively blocks external moisture and impurities, protecting the internal structure of the device from external environmental influences and improving the long-term stability and reliability of the device.

[0030] Specifically, such as Figure 3 As shown, the heat-conducting plate 701 is made of a material with high thermal conductivity, such as copper or graphite.

[0031] Among them, when the device generates heat under high frequency and high power conditions, the heat dissipation layer can quickly conduct the heat through the heat conduction plate 701, effectively reducing the operating temperature of the device and improving its reliability and service life.

[0032] Specifically, such as Figure 1 As shown, a substrate 8 is connected to the bottom of the semiconductor substrate 1.

[0033] Specifically, such as Figure 2 As shown, the sidewall isolation structure 603 consists of an inner layer of silicon nitride and an outer layer of silicon oxide, with a total thickness of 30-80 nm.

[0034] Among them, a passivation layer 605 is covered above the polysilicon gate 601 using processes such as chemical vapor deposition. The passivation layer 605 is composed of an inner silicon nitride layer and an outer silicon oxide layer, giving it good resistance to moisture and corrosion.

[0035] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A highly reliable MOS transistor structure, comprising a semiconductor substrate (1), characterized in that, A trench (2) is provided in the middle of the top of the semiconductor substrate (1), and a source trench (3) and a drain trench (4) are provided on both sides of the top of the semiconductor substrate (1). A source part (5) is provided inside the source trench (3), and a drain part (9) is provided inside the drain trench (4). The gate assembly (6) includes a polysilicon gate (601) disposed inside the trench (2), a gate oxide layer (602) disposed between the polysilicon gate (601) and the semiconductor substrate (1), sidewall isolation structures (603) disposed on both sides of the polysilicon gate (601), a gate metal layer (604) disposed on the top of the polysilicon gate (601), and a passivation layer (605) connected to the top of the gate metal layer (604).

2. The high-reliability MOS transistor structure according to claim 1, characterized in that, The semiconductor substrate (1) has grooves on both sides, and a heat dissipation mechanism (7) is provided inside the grooves.

3. The highly reliable MOS transistor structure according to claim 2, characterized in that, The heat dissipation mechanism (7) includes a heat-conducting plate (701) disposed inside the groove, and a heat sink (702) is disposed on the other side of the heat-conducting plate (701).

4. The high-reliability MOS transistor structure according to claim 1, characterized in that, The passivation layer (605) is a bilayer composite structure of silicon nitride and polyimide.

5. A high-reliability MOS transistor structure according to claim 3, characterized in that, The heat-conducting plate (701) is made of a material with high thermal conductivity, such as copper or graphite.

6. The highly reliable MOS transistor structure according to claim 1, characterized in that, The bottom of the semiconductor substrate (1) is connected to a substrate (8).

7. The high-reliability MOS transistor structure according to claim 1, characterized in that, The sidewall isolation structure (603) consists of an inner layer of silicon nitride and an outer layer of silicon oxide, with a total thickness of 30-80 nm.

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