Half-bridge VTT bidirectional current active clamp circuit and electronic equipment

Abstract

The utility model provides a kind of half-bridge VTT bidirectional current initiative buffer circuit and electronic equipment, by voltage dividing circuit, power voltage is divided and is provided to the positive pole of operational amplifier as reference voltage reference after being divided, the first output end of VTT power supply circuit is fed back to the negative pole of operational amplifier actual VTT voltage and forms closed-loop control, operational amplifier is exported control signal to the control end of feedback regulation circuit by comparing the difference of reference voltage and actual VTT voltage, when DDR memory needs forward power supply, VTT power supply circuit provides current to memory power supply end through its second output end through filter circuit;When DDR memory generates reverse filling current and causes VTT voltage to rise, feedback regulation circuit under the driving of operational amplifier control signal will excess current be guided to ground through its output end, so as to realize the bidirectional regulation of VTT voltage. Effectively solved the technical defects that traditional unidirectional power supply scheme cannot handle reverse filling current.

Description

Technical Field

[0001] This utility model relates to the field of power electronics, and in particular to a half-bridge VTT bidirectional current active buffer circuit and electronic equipment. Background Technology

[0002] In computer systems, DDR (Double Data Rate) memory is a crucial storage device, requiring a stable power supply for proper operation. Besides the core voltage VDDQ, DDR3 / DDR4 memory also needs a VTT termination voltage to provide termination matching for the data bus. The VTT voltage is typically set to VDDQ / 2 to terminate the DDR data lines, ensuring the integrity of high-speed signal transmission.

[0003] Traditional VTT power supply schemes typically use low-dropout linear regulators (LDOs) to directly power the VTT pin of DDR memory. However, in practical applications, because the DDR data lines switch rapidly during read and write operations, the load current at the VTT pin switches quickly between Source and Sink. When the data line switches from high to low, current needs to be drawn from the VTT pin; conversely, when the data line switches from low to high, current needs to be supplied to the VTT pin.

[0004] In existing technologies, ordinary LDO power supplies can only provide unidirectional current output and cannot effectively handle reverse current flow. When the DDR data line flips rapidly, generating reverse current, this current directly impacts the internal circuitry of the LDO, causing an abnormal rise in VTT voltage. Over long-term operation, reverse current may damage the power devices inside the LDO chip, potentially leading to chip burnout. Even without permanent damage, voltage fluctuations caused by reverse current can affect the stability of DDR operation, leading to data transmission errors and reduced system reliability. Furthermore, traditional LDOs have limited transient response speed and cannot quickly respond to sudden load changes, resulting in significant overshoot or undershoot of VTT voltage during load switching, further impacting DDR stability.

[0005] In view of the above, this application is hereby submitted. Utility Model Content

[0006] In their practical experience designing computer motherboard power supplies, the inventors discovered that unstable DDR memory operation often manifests as intermittent data errors or system crashes. These faults are difficult to reproduce, posing significant challenges to problem localization. By precisely measuring the VTT voltage with a high-speed oscilloscope, the inventors observed a crucial phenomenon: during burst read / write operations on DDR memory, the VTT voltage exhibits significant overshoot and undershoot, with peak deviations exceeding ±15%, far exceeding the ±5% tolerance allowed by the DDR specification.

[0007] After in-depth analysis, the inventors discovered the root cause of the problem: when DDR data lines undergo level transitions within nanoseconds, they generate bidirectional transient large currents. When multiple data lines transition simultaneously, the VTT terminal needs to switch rapidly between sinking and providing current. Traditional LDO power supply solutions can only output current in one direction and cannot effectively handle this bidirectional current demand.

[0008] The inventors paid particular attention to a phenomenon long overlooked by the industry: under Sink current conditions, current flows backward from the VTT terminal into the LDO, creating a "reverse current" phenomenon. This not only causes the LDO's control loop to fail, leading to uncontrolled output voltage, but also generates additional power consumption within the LDO, accelerating device aging. Experiments have confirmed that on some motherboards, after several months of continuous operation, the VTT-powered LDO experienced performance degradation or even complete failure.

[0009] This utility model discloses a half-bridge VTT bidirectional current active buffer circuit and electronic device, which aims to solve the problem that the VTT power supply line of DDR memory cannot handle forward power supply and reverse current sinking at the same time.

[0010] The first embodiment of this utility model provides a half-bridge VTT bidirectional current active buffer circuit, including: an operational amplifier, a voltage divider circuit, a VTT power supply circuit, a feedback adjustment circuit, and a filter circuit; The input terminal of the voltage divider circuit is used to connect to the power supply, and the output terminal of the voltage divider circuit is electrically connected to the positive terminal of the operational amplifier. The input terminal of the VTT power supply circuit is electrically connected to the power supply, the first output terminal of the VTT power supply circuit is electrically connected to the negative terminal of the operational amplifier, and the second output terminal of the VTT power supply circuit is connected to the power supply terminal of the memory through the filter circuit. The input terminal of the feedback adjustment circuit is electrically connected to the negative terminal of the operational amplifier, the control terminal of the feedback adjustment circuit is electrically connected to the output terminal of the operational amplifier, and the output terminal of the feedback adjustment circuit is grounded. The feedback adjustment circuit is configured to actively open the current discharge channel according to the error correction control signal of the operational amplifier when reverse current is generated by capacitive coupling and signal reflection caused by signal line level jumps during high-speed data transmission in memory.

[0011] Preferably, the voltage divider circuit is configured to divide the input power supply voltage according to a preset ratio to provide a comparison reference for the operational amplifier to supply the VTT target voltage.

[0012] Preferably, the voltage divider circuit includes a first resistor and a second resistor; Wherein, the first end of the first resistor is electrically connected to the voltage, the second end of the first resistor is grounded through the second resistor, and the second end of the first resistor is electrically connected to the positive terminal of the operational amplifier.

[0013] Preferably, the VTT power supply circuit is configured to actively push compensation current from the power supply terminal to the VTT output terminal according to the control signal of the operational amplifier when the VTT voltage drops due to dynamic changes in the DDR memory load, and at the same time feed back the real-time VTT output voltage to the operational amplifier to form a closed-loop control.

[0014] Preferably, the VTT power supply circuit includes a PMOS transistor, a third resistor, a fourth resistor, and a first diode; The source (S) terminal of the PMOS transistor is electrically connected to the power supply, the drain (D) terminal of the PMOS transistor is electrically connected to the negative terminal of the operational amplifier and the input terminal of the filter circuit, the third resistor is connected in parallel across the drain (D) and gate (G) terminals of the PMOS transistor, the gate (G) terminal of the PMOS transistor is electrically connected to the positive terminal of the first diode, the source (S) terminal of the PMOS transistor is electrically connected to the negative terminal of the first diode, and the fourth resistor is connected in parallel across the first diode.

[0015] Preferably, the feedback adjustment circuit includes an NMOS transistor, a fifth resistor, a sixth resistor, and a second diode; The drain (D) of the NMOS transistor is electrically connected to the negative terminal of the operational amplifier. The output terminal of the operational amplifier is electrically connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is electrically connected to the gate (G) of the NMOS transistor. The second terminal of the fifth resistor is grounded through the sixth resistor. The output terminal of the operational amplifier is grounded to the negative terminal of the second diode, and the positive terminal of the second diode is grounded.

[0016] Preferably, the operational amplifier is configured to output a high level when its negative voltage is greater than its positive voltage, so as to reduce the VTT voltage.

[0017] Preferably, the operational amplifier is configured to output a low level when its negative voltage is less than its positive voltage, so as to increase the VTT voltage.

[0018] The second embodiment of this utility model provides an electronic device, characterized in that it includes a power supply, a memory module, and a half-bridge VTT bidirectional current active buffer circuit as described in any one of the above, wherein the power supply supplies power to the memory module through the half-bridge VTT terminal bidirectional current active buffer circuit.

[0019] This invention provides a half-bridge VTT bidirectional current active buffer circuit and electronic device. The power supply voltage is divided by a voltage divider circuit and provided to the positive terminal of the operational amplifier as a reference voltage. The first output of the VTT power supply circuit feeds back the actual VTT voltage to the negative terminal of the operational amplifier, forming a closed-loop control. The operational amplifier compares the difference between the reference voltage and the actual VTT voltage and outputs a control signal to the control terminal of the feedback adjustment circuit. When the DDR memory requires forward power, the VTT power supply circuit provides current to the memory power supply terminal through its second output and a filter circuit. When the DDR memory generates reverse current, causing the VTT voltage to rise, the feedback adjustment circuit, driven by the operational amplifier control signal, directs the excess current through its output terminal to ground, thus achieving bidirectional adjustment of the VTT voltage. The entire circuit, through the real-time comparison of the operational amplifier and the bidirectional current processing capability of the feedback adjustment circuit, ensures that the VTT voltage remains stable at the set value, effectively solving the technical defect of traditional unidirectional power supply schemes that cannot handle reverse current. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a half-bridge VTT bidirectional current active buffer circuit provided by this utility model. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Therefore, the following detailed description of the embodiments of this utility model provided in the accompanying drawings is not intended to limit the scope of the claimed utility model, but merely represents selected embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0022] The specific embodiments of this utility model are described in detail below with reference to the accompanying drawings.

[0023] This utility model discloses a half-bridge VTT bidirectional current active buffer circuit and electronic device, which aims to solve the problem that the VTT power supply line of DDR memory cannot handle forward power supply and reverse current sinking at the same time.

[0024] Please see Figure 1The first embodiment of this utility model provides a half-bridge VTT bidirectional current active buffer circuit, including: operational amplifier U1, voltage divider circuit 1, VTT power supply circuit 2, feedback adjustment circuit 3, and filter circuit 4; The input terminal of the voltage divider circuit 1 is used to connect to the power supply, and the output terminal of the voltage divider circuit 1 is electrically connected to the positive terminal of the operational amplifier. The input terminal of the VTT power supply circuit 2 is electrically connected to the power supply, the first output terminal of the VTT power supply circuit 2 is electrically connected to the negative terminal of the operational amplifier, and the second output terminal of the VTT power supply circuit 2 is connected to the power supply terminal of the memory through the filter circuit 4. The input terminal of the feedback adjustment circuit 3 is electrically connected to the negative terminal of the operational amplifier, the control terminal of the feedback adjustment circuit 3 is electrically connected to the output terminal of the operational amplifier, and the output terminal of the feedback adjustment circuit 3 is grounded.

[0025] In this embodiment, the voltage divider circuit 1 consists of a first resistor and a second resistor connected in series. Its input terminal is connected to the VDDQ power supply, which powers the DDR4 core and typically has a value of 1.2V. One end of the first resistor is connected to VDDQ, and the other end is connected to one end of the second resistor to form a voltage divider node. The other end of the second resistor is grounded. The voltage divider node outputs a reference voltage VREF, which has a value of VDDQ / 2, or 0.6V. The reference voltage VREF is connected to the positive input terminal of the operational amplifier U1. The first and second resistors are high-precision resistors, such as 1% precision surface mount resistors, with a resistance value of 10kΩ, to ensure that the operational amplifier obtains a stable reference voltage.

[0026] In one possible embodiment of this utility model, the VTT power supply circuit 2 includes a PMOS transistor Q2, a third resistor R3, a fourth resistor R4, and a first diode D1.

[0027] In this circuit structure, PMOS transistor Q2 serves as the primary current source, with its source (S) directly connected to the VDDQ power supply to ensure sufficient current supply. The drain (D) of PMOS transistor Q2 is connected to the VTT output node (filter circuit 4), which is also connected to the negative input terminal of operational amplifier U1, forming a voltage feedback path. A third resistor R3 is connected in parallel between the drain and gate of PMOS transistor Q2. Its main function is to provide bias during circuit startup, ensuring the PMOS transistor remains reliably off when there is no control signal. The resistance value of the third resistor R3 is typically chosen between 10kΩ and 100kΩ, providing sufficient bias current without excessively affecting the gate drive during normal operation.

[0028] The first diode, D1, is a Schottky diode. Its anode is connected to the gate of the PMOS transistor Q2, and its cathode is connected to the source of the PMOS transistor, forming an important protection mechanism: when the operational amplifier outputs a high level to attempt to turn off the PMOS transistor, the gate voltage rises. However, due to the clamping effect of the first diode D1, the gate-source voltage VGS is limited to approximately -0.3V (the forward voltage drop of the Schottky diode), effectively preventing gate overvoltage breakdown. The fourth resistor, R4, is connected in parallel across the first diode D1, i.e., between the source and gate of the PMOS transistor. Together with R3, it pulls the gate potential to the source potential in the static state, ensuring reliable turn-off of the PMOS transistor. The fourth resistor R4 also has a current-limiting function; when the operational amplifier drives the gate, it can limit the drive current, protecting the output stage of the operational amplifier. The typical value of R4 is 1kΩ to 10kΩ, requiring a balance between drive capability and protection effect.

[0029] In one possible embodiment of this invention, the feedback regulation circuit 3 employs a symmetrical NMOS transistor control structure to achieve efficient sink current absorption capability. The feedback regulation circuit 3 includes an NMOS transistor Q1, a fifth resistor R5, a sixth resistor R6, and a second diode D2. The drain (D) of the NMOS transistor Q1 is connected to the VTT node and electrically connected to the negative input terminal of the operational amplifier U1, allowing direct monitoring of changes in the VTT voltage. The output terminal of the operational amplifier U1 is connected to the gate of the NMOS transistor Q1 through the fifth resistor R5. The fifth resistor R5 serves to limit current and provide isolation, preventing overload of the operational amplifier output stage and suppressing gate ringing. The resistance value of the fifth resistor R5 is typically chosen from 100Ω to 1kΩ and needs to be optimized based on the input capacitance of the NMOS transistor and the required switching speed.

[0030] The sixth resistor, R6, is connected between the gate and source (ground) of the NMOS transistor Q1, providing a pull-down path for the gate. When the circuit is not operating or the operational amplifier output is in a high-impedance state, the sixth resistor, R6, ensures that the gate potential of the NMOS transistor is 0V, keeping it in the off state. The resistance value of the sixth resistor, R6, is typically chosen between 10kΩ and 100kΩ to ensure a reliable pull-down effect without creating excessive shunt current to the normal gate drive.

[0031] The connection method of the second diode D2 requires special explanation. Based on the actual requirements of the circuit, the anode of D2 is connected to the gate of the NMOS transistor Q1, and the cathode is connected to the drain (VTT node) of the NMOS transistor. This provides another form of gate protection: when the VTT voltage rises abnormally, if the gate voltage is relatively low, D2 will conduct, clamping the gate potential at the level of VTT voltage minus one diode voltage drop, preventing excessive VGS reverse voltage from damaging the NMOS transistor. This is especially important when the circuit encounters abnormal transients.

[0032] The working principle of the circuit is as follows: In the initial state, after the VDDQ power supply is powered on, the voltages at the source and gate of the PMOS transistor Q2 are equal, VGS is 0, and the PMOS transistor is in an off state. At the same time, the gate of the NMOS transistor Q1 is grounded through the sixth resistor R6, VGS is also 0, and the NMOS transistor is also off. At this time, the VTT terminal is in a high-impedance state (during power-on, the voltage at the VTT output terminal is 0V, VREF = VDDQ / 2 = 0.6V. Since VTT(0V) < VREF(0.6V), the operational amplifier outputs a low level, the PMOS transistor Q2 is turned on to start supplying power to the VTT terminal, and the VTT voltage gradually rises to around 0.6V).

[0033] After the circuit enters the working state, the operational amplifier U1 continuously compares the actual VTT voltage with the reference voltage VREF. When the VTT voltage is higher than VREF, it indicates that a reverse injection current flows into the VTT terminal, and the operational amplifier outputs a high level. Since the operational amplifier is powered by 1.8V, its output high level is approximately 1.8V. At this time, the gate voltage of the NMOS transistor Q1 rises. When VGS exceeds the threshold voltage (approximately 0.7V), the NMOS transistor is turned on to conduct the excess current to the ground, so that the VTT voltage drops. During this process, the gate voltage of the PMOS transistor Q2 also rises, but due to the clamping effect of the first diode D1, its VGS is limited to approximately -0.3V (the forward voltage drop of the Schottky diode), and the PMOS transistor Q2 remains in the off state.

[0034] Conversely, when the VTT voltage is lower than VREF, it indicates that the load needs to draw current from the VTT terminal, and the operational amplifier outputs a low level. When the output voltage drops below 0.5V, the VGS of the PMOS transistor Q2 increases to exceed its threshold voltage (approximately -0.7V), the PMOS transistor Q2 is turned on to supply current from the VDDQ power supply to the VTT terminal, so that the VTT voltage rises. At this time, the gate voltage of the NMOS transistor Q1 decreases, VGS is close to 0V, and the NMOS transistor Q1 is turned off.

[0035] Through the negative feedback control mechanism, the circuit can dynamically adjust the VTT output voltage to keep it stable around VREF all the time. When the high-speed toggling of the DDR data line causes the current direction at the VTT terminal to change rapidly, the circuit can respond quickly, providing Source current through the PMOS transistor Q2 or absorbing Sink current through the NMOS transistor, which effectively prevents the impact of reverse injection current on the power supply system and ensures the stable operation of the DDR memory.

[0036] Further, in a possible embodiment of the present utility model, The filter circuit 4 includes output capacitors C1, C2, and C3 connected in parallel between the VTT output terminal and ground, forming a multi-level filter network. This parallel configuration fully utilizes the frequency characteristics of different types of capacitors. C1 is typically a large-capacity electrolytic capacitor, such as a 100μF / 6.3V surface-mount aluminum electrolytic capacitor or tantalum capacitor. Its main function is to provide large energy storage capacity, quickly providing or absorbing charge during sudden changes in load current, reducing the fluctuation amplitude of the VTT voltage. C2 is a medium-capacitance ceramic capacitor, such as a 1μF / 6.3V X7R type MLCC (multilayer ceramic capacitor), which has low equivalent series resistance (ESR) and equivalent series inductance (ESL), providing good filtering performance in the mid-to-high frequency range. C3 is a small-capacitance ceramic capacitor, such as a 0.1μF / 6.3V C0G type MLCC, specifically designed to filter high-frequency noise. Its extremely low ESL allows it to maintain good filtering characteristics even at tens of MHz or higher frequencies.

[0037] Decoupling capacitors C4, C5, and C6 are connected between different power supply terminals and ground, providing localized decoupling for each power rail. C4 is connected to the VDDQ power supply terminal, primarily providing decoupling for the source power supply of PMOS transistor Q2. Since the PMOS transistor draws pulse current from VDDQ when conducting, C4 provides instantaneous current to prevent voltage drops caused by parasitic inductance on the power line. C4 is typically a 10μF ceramic capacitor paired with a 0.1μF high-frequency decoupling capacitor. C5 is connected to the 1.8V power supply terminal, providing a stable operating power supply for the operational amplifier. Although the operational amplifier has low power consumption, it is sensitive to power supply noise. The presence of C5 filters out high-frequency interference on the power line, ensuring the output accuracy of the operational amplifier. C5 is generally a combination of 1μF and 0.01μF capacitors. C6 can be connected to other relevant power supply nodes as needed, such as the power supply terminals of other auxiliary circuits.

[0038] The second embodiment of this utility model provides an electronic device, including a power supply, a memory module, and a half-bridge VTT bidirectional current active buffer circuit as described in any one of the above, wherein the power supply supplies power to the memory module through the half-bridge VTT terminal bidirectional current active buffer circuit.

[0039] This invention provides a half-bridge VTT bidirectional current active buffer circuit and electronic device. The power supply voltage is divided by a voltage divider circuit and provided to the positive terminal of the operational amplifier as a reference voltage. The first output of the VTT power supply circuit feeds back the actual VTT voltage to the negative terminal of the operational amplifier, forming a closed-loop control. The operational amplifier compares the difference between the reference voltage and the actual VTT voltage and outputs a control signal to the control terminal of the feedback adjustment circuit. When the DDR memory requires forward power, the VTT power supply circuit provides current to the memory power supply terminal through its second output and a filter circuit. When the DDR memory generates reverse current, causing the VTT voltage to rise, the feedback adjustment circuit, driven by the operational amplifier control signal, directs the excess current through its output terminal to ground, thus achieving bidirectional adjustment of the VTT voltage. The entire circuit, through the real-time comparison of the operational amplifier and the bidirectional current processing capability of the feedback adjustment circuit, ensures that the VTT voltage remains stable at the set value, effectively solving the technical defect of traditional unidirectional power supply schemes that cannot handle reverse current.

[0040] The above are merely preferred embodiments of this utility model. The protection scope of this utility model is not limited to the above embodiments. All technical solutions that fall within the scope of this utility model's concept are protected by this utility model.

Claims

1. A half-bridge VTT bidirectional current active buffer circuit, characterized in that, include: Operational amplifier, voltage divider circuit, VTT power supply circuit, feedback adjustment circuit, and filter circuit; The input terminal of the voltage divider circuit is used to connect to the power supply, and the output terminal of the voltage divider circuit is electrically connected to the positive terminal of the operational amplifier. The input terminal of the VTT power supply circuit is electrically connected to the power supply, the first output terminal of the VTT power supply circuit is electrically connected to the negative terminal of the operational amplifier, and the second output terminal of the VTT power supply circuit is connected to the power supply terminal of the memory through the filter circuit. The input terminal of the feedback adjustment circuit is electrically connected to the negative terminal of the operational amplifier, the control terminal of the feedback adjustment circuit is electrically connected to the output terminal of the operational amplifier, and the output terminal of the feedback adjustment circuit is grounded. The feedback adjustment circuit is configured to actively open the current discharge channel according to the error correction control signal of the operational amplifier when reverse current is generated by capacitive coupling and signal reflection caused by signal line level jumps during high-speed data transmission in memory.

2. The half-bridge VTT bidirectional current active buffer circuit according to claim 1, characterized in that, The voltage divider circuit is configured to divide the input power supply voltage according to a preset ratio to provide a comparison reference for the operational amplifier to supply the VTT target voltage.

3. The half-bridge VTT bidirectional current active buffer circuit according to claim 2, characterized in that, The voltage divider circuit includes a first resistor and a second resistor; Wherein, the first end of the first resistor is electrically connected to the voltage, the second end of the first resistor is grounded through the second resistor, and the second end of the first resistor is electrically connected to the positive terminal of the operational amplifier.

4. The half-bridge VTT bidirectional current active buffer circuit according to claim 1, characterized in that, The VTT power supply circuit is configured to actively push compensation current from the power supply terminal to the VTT output terminal according to the control signal of the operational amplifier when the VTT voltage drops due to dynamic changes in the DDR memory load, and at the same time feed back the real-time VTT output voltage to the operational amplifier to form a closed-loop control.

5. The half-bridge VTT bidirectional current active buffer circuit according to claim 4, characterized in that, The VTT power supply circuit includes a PMOS transistor, a third resistor, a fourth resistor, and a first diode; The source (S) terminal of the PMOS transistor is electrically connected to the power supply, the drain (D) terminal of the PMOS transistor is electrically connected to the negative terminal of the operational amplifier and the input terminal of the filter circuit, the third resistor is connected in parallel across the drain (D) and gate (G) terminals of the PMOS transistor, the gate (G) terminal of the PMOS transistor is electrically connected to the positive terminal of the first diode, the source (S) terminal of the PMOS transistor is electrically connected to the negative terminal of the first diode, and the fourth resistor is connected in parallel across the first diode.

6. The half-bridge VTT bidirectional current active buffer circuit according to claim 1, characterized in that, The feedback regulation circuit includes an NMOS transistor, a fifth resistor, a sixth resistor, and a second diode; The drain (D) of the NMOS transistor is electrically connected to the negative terminal of the operational amplifier. The output terminal of the operational amplifier is electrically connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is electrically connected to the gate (G) of the NMOS transistor. The second terminal of the fifth resistor is grounded through the sixth resistor. The output terminal of the operational amplifier is grounded to the negative terminal of the second diode, and the positive terminal of the second diode is grounded.

7. The half-bridge VTT bidirectional current active buffer circuit according to claim 1, characterized in that, The operational amplifier is configured to output a high level when its negative voltage is greater than its positive voltage, so as to reduce the VTT voltage.

8. The half-bridge VTT bidirectional current active buffer circuit according to claim 1, characterized in that, The operational amplifier is configured to output a low level when its negative voltage is less than its positive voltage, so as to increase the VTT voltage.

9. An electronic device, characterized in that, The device includes a power supply, a memory module, and a half-bridge VTT bidirectional current active buffer circuit as described in any one of claims 1 to 8, wherein the power supply supplies power to the memory module through the half-bridge VTT terminal bidirectional current active buffer circuit.

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