Control circuit and integrated chip
Patent Information
- Application Number
- CN202522614230.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-12-09
AI Technical Summary
In existing technologies, the frequency of low-frequency oscillators in low-power mode cannot be accurately controlled, resulting in insufficient operating accuracy, mainly due to large errors caused by semiconductor manufacturing processes.
By employing the synergistic effect of a high-frequency oscillator and a low-frequency correction circuit, the frequency of the low-frequency oscillator is dynamically adjusted through a feedback loop and error calculation method, and compensation is performed using temperature and voltage sensors to achieve rapid frequency correction.
In low-power mode, accurate control of the low-frequency oscillator frequency is achieved, ensuring working accuracy, and overall power consumption is reduced through dynamic power management.
Smart Images
Figure CN224935664U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuits, and in particular to a control circuit and an integrated chip. Background Technology
[0002] In the existing technology, the frequency of low-frequency oscillators in low-power mode cannot be made accurate because the operating current is low in low-power mode, and the error caused by semiconductor manufacturing process is large, so sufficient working accuracy cannot be guaranteed. Utility Model Content
[0003] The embodiments of this application provide a control circuit and an integrated chip.
[0004] The control circuit of this application includes a low-frequency oscillator, a low-frequency main control circuit, a high-frequency oscillator, and a low-frequency frequency correction circuit. The output terminal of the low-frequency oscillator is connected to the first input terminal of the low-frequency main control circuit; the first output terminal of the low-frequency main control circuit is connected to the input terminal of the high-frequency oscillator; the second output terminal of the low-frequency main control circuit is connected to the first input terminal of the low-frequency frequency correction circuit; the output terminal of the high-frequency oscillator is connected to the second input terminal of the low-frequency frequency correction circuit; the output terminal of the low-frequency oscillator is connected to the third input terminal of the low-frequency frequency correction circuit; and the output terminal of the low-frequency frequency correction circuit is connected to the input terminal of the low-frequency oscillator, for controlling the frequency of the low-frequency oscillator.
[0005] In some embodiments, the control circuit includes a timing divider circuit, the first input of which is connected to the output of the low-frequency oscillator, the second input of which is connected to the third output of the low-frequency main control circuit, and the output of which is connected to the second input of the low-frequency main control circuit.
[0006] In some embodiments, the timing and frequency division circuit includes a frequency division module and a timing module. The frequency division module performs frequency division processing on the low-frequency clock output by the low-frequency oscillator. The timing module performs timing based on the frequency division result and sends the frequency-divided clock to the low-frequency main control circuit. The low-frequency main control circuit is used to wake up the high-frequency oscillator and the low-frequency correction circuit according to the frequency-divided clock at a preset period.
[0007] In some embodiments, the third input terminal of the low-frequency main control circuit is connected to an external wake-up source signal input pin. When the third input terminal of the low-frequency main control circuit detects a valid wake-up signal, the first output terminal of the low-frequency main control circuit is used to send a start signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to start. The second output terminal of the low-frequency main control circuit is used to send a wake-up signal to an external control circuit. The fourth input terminal of the low-frequency main control circuit is used to receive a sleep signal from an external circuit. When the fourth input terminal of the low-frequency main control circuit receives a sleep signal from an external circuit, the first output terminal of the low-frequency main control circuit is used to send a shutdown signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to shut down.
[0008] In some embodiments, the low-frequency correction circuit is used to acquire the low-frequency clock signal output from the output terminal of the low-frequency oscillator and the high-frequency clock signal output from the output terminal of the high-frequency oscillator, and generate a low-frequency oscillator control signal based on the phase difference between the low-frequency clock signal and the high-frequency clock signal to correct the low-frequency oscillator.
[0009] The integrated chip in this application includes a main control circuit and a control circuit. The main control circuit is electrically connected to the control circuit. The control circuit includes a low-frequency oscillator, a low-frequency main control circuit, a high-frequency oscillator, and a low-frequency frequency correction circuit. The output terminal of the low-frequency oscillator is connected to the first input terminal of the low-frequency main control circuit. The first output terminal of the low-frequency main control circuit is connected to the input terminal of the high-frequency oscillator. The second output terminal of the low-frequency main control circuit is connected to the first input terminal of the low-frequency frequency correction circuit. The output terminal of the high-frequency oscillator is connected to the second input terminal of the low-frequency frequency correction circuit. The output terminal of the low-frequency oscillator is connected to the third input terminal of the low-frequency frequency correction circuit. The output terminal of the low-frequency frequency correction circuit is connected to the input terminal of the low-frequency oscillator for controlling the frequency of the low-frequency oscillator.
[0010] In some embodiments, the control circuit includes a timing divider circuit, the first input terminal of which is connected to the output terminal of the low-frequency oscillator, the second input terminal of which is connected to the third output terminal of the low-frequency main control circuit, and the output terminal of which is connected to the second input terminal of the low-frequency main control circuit.
[0011] In some embodiments, the timing and frequency division circuit includes a frequency division module and a timing module. The frequency division module performs frequency division processing on the low-frequency clock output by the low-frequency oscillator. The timing module performs timing based on the frequency division result and sends the frequency-divided clock to the low-frequency main control circuit. The low-frequency main control circuit is used to wake up the high-frequency oscillator and the low-frequency correction circuit according to the frequency-divided clock at a preset period.
[0012] In some embodiments, the third input terminal of the low-frequency main control circuit is connected to an external wake-up source signal input pin. When the third input terminal of the low-frequency main control circuit detects a valid wake-up signal, the first output terminal of the low-frequency main control circuit is used to send a start signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to start. The second output terminal of the low-frequency main control circuit is used to send a wake-up signal to an external control circuit. The fourth input terminal of the low-frequency main control circuit is used to receive a sleep signal from an external circuit. When the fourth input terminal of the low-frequency main control circuit receives a sleep signal from an external circuit, the first output terminal of the low-frequency main control circuit is used to send a shutdown signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to shut down.
[0013] In some embodiments, the low-frequency correction circuit is used to acquire the low-frequency clock signal output from the output terminal of the low-frequency oscillator and the high-frequency clock signal output from the output terminal of the high-frequency oscillator, and generate a low-frequency oscillator control signal based on the phase difference between the low-frequency clock signal and the high-frequency clock signal to correct the low-frequency oscillator.
[0014] The control circuit and integrated chip of the present application embodiment can quickly correct the low-frequency oscillator using a high-frequency oscillator and a low-frequency correction circuit, even in low-power mode, so as to obtain an accurate low-frequency frequency and ensure working accuracy.
[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a circuit diagram of the control circuit according to an embodiment of this application. Detailed Implementation
[0017] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0018] Please see Figure 1The control circuit 100 of this embodiment includes a low-frequency oscillator 10, a low-frequency main control circuit 20, a high-frequency oscillator 30, and a low-frequency frequency correction circuit 40. The output terminal 101 of the low-frequency oscillator 10 is connected to the first input terminal 201 of the low-frequency main control circuit 20. The first output terminal 202 of the low-frequency main control circuit 20 is connected to the input terminal 301 of the high-frequency oscillator 30. The second output terminal 203 of the low-frequency main control circuit 20 is connected to the first input terminal 401 of the low-frequency frequency correction circuit 40. The output terminal 302 of the high-frequency oscillator 30 is connected to the second input terminal 402 of the low-frequency frequency correction circuit 40. The output terminal 101 of the low-frequency oscillator 10 is connected to the third input terminal 403 of the low-frequency frequency correction circuit 40. The output terminal 404 of the low-frequency frequency correction circuit 40 is connected to the input terminal 102 of the low-frequency oscillator 10, for controlling the frequency of the low-frequency oscillator 10.
[0019] Thus, even in low-power mode, the low-frequency oscillator 10 is quickly corrected using the high-frequency oscillator 30 and the low-frequency correction circuit 40 to obtain an accurate low-frequency frequency and ensure working accuracy.
[0020] Specifically, rapid frequency correction of the low-frequency oscillator 10 is achieved through the synergistic effect of the high-frequency oscillator 30 and the low-frequency correction circuit 40. In some embodiments, the high-frequency oscillator 30 may employ an internal RC oscillator, which has the advantages of low cost and fast start-up. In some embodiments, the high-frequency oscillator 30 may also employ an external crystal oscillator, which has the advantage of high stability. The low-frequency oscillator 10 may be selected as an ultra-low-power architecture (e.g., consuming approximately 1 μA of current) to ensure continuous operation in low-power mode. The output terminal 101 of the low-frequency oscillator 10 is connected to the first input terminal 201 of the low-frequency main control circuit 20. The input terminal 102 of the low-frequency oscillator 10 is connected to the output terminal 404 of the low-frequency correction circuit 40, forming a feedback loop for dynamically adjusting the low-frequency clock signal of the low-frequency oscillator 10. The low-frequency main control circuit 20 is capable of receiving and processing the low-frequency clock signal generated by the low-frequency oscillator 10. The first output terminal 202 of the low-frequency main control circuit 20 is connected to the input terminal 301 of the high-frequency oscillator 30. The low-frequency main control circuit 20 can send control signals to the high-frequency oscillator 30 to control the high-frequency oscillator 30 to turn it on or off. When the high-frequency oscillator 30 is on, it can output a high-frequency clock signal. The second output terminal 203 of the low-frequency main control circuit 20 is connected to the first input terminal 401 of the low-frequency frequency correction circuit 40 for auxiliary correction.
[0021] In some embodiments, the control circuit 100 is connected to an external control circuit. The low-frequency main control circuit 20 sends a signal to start the high-frequency oscillator 30 and wake up the external control circuit. After the external control circuit finishes its work, it sends a sleep signal to the low-frequency main control circuit 20 to shut down the high-frequency oscillator 30 and the external control circuit, thereby reducing power consumption. Based on this, the low-frequency correction circuit 40 adjusts the frequency of the low-frequency oscillator 10 to adjust the low-frequency clock signal using various error calculation methods. For example, the period counting method uses the high-frequency clock signal of the high-frequency oscillator 30 to count the periods of the low-frequency oscillator 10, compares the actual period error with the target period error to generate a correction signal; or the phase comparison method measures the phase difference and quickly adjusts the frequency; in addition, data from temperature sensors or voltage sensors can be combined for compensation to improve stability in complex environments. In this embodiment, the control circuit 100 performs dynamic power consumption management, further reducing overall power consumption by shutting down unnecessary operating phases of the high-frequency oscillator 30, and can switch between different correction algorithms as needed, balancing accuracy and efficiency. While ensuring the accuracy of the low-frequency clock signal generated by the low-frequency oscillator 10, ultra-low power consumption operation is achieved.
[0022] Please continue reading. Figure 1 In some embodiments, the control circuit 100 includes a timing frequency divider circuit 50, the first input terminal 501 of the timing frequency divider circuit 50 is connected to the output terminal 101 of the low-frequency oscillator 10, the second input terminal 502 of the timing frequency divider circuit 50 is connected to the third output terminal 204 of the low-frequency main control circuit 20, and the output terminal 503 of the timing frequency divider circuit 50 is connected to the second input terminal 205 of the low-frequency main control circuit 20.
[0023] Specifically, the control circuit 100 includes a timing divider circuit 50, which is connected to the low-frequency oscillator 10 and the low-frequency main control circuit 20. The timing divider circuit 50 can generate the timing signal required by the low-frequency main control circuit 20 according to the low-frequency clock signal generated by the low-frequency oscillator 10 and the selection of the low-frequency main control circuit 20.
[0024] Please continue reading. Figure 1 In some embodiments, the control circuit 100 includes a timing and frequency division circuit 50, which includes a frequency division module and a timing module. The frequency division module performs frequency division processing on the low-frequency clock output by the low-frequency oscillator 10, and the timing module performs timing according to the frequency division result and sends the frequency-divided clock to the low-frequency main control circuit 20. The low-frequency main control circuit 20 is used to wake up the high-frequency oscillator 30 and the low-frequency frequency correction circuit 40 according to the frequency-divided clock at a preset period.
[0025] Specifically, the timing and frequency division circuit 50 includes a frequency division module and a timing module. Through the coordinated action of the frequency division module and the timing module, it provides a frequency-divided clock signal to the low-frequency main control circuit 20 to support the periodic wake-up and calibration operations of the high-frequency oscillator 30 and the low-frequency frequency correction circuit 40. In one embodiment, the timing and frequency division circuit 50 divides and times the low-frequency clock signal generated by the low-frequency oscillator, generating wake-up clocks with selectable period levels such as 4ms, 8ms, 16ms, and 32ms, and correction clocks with selectable levels. Thus, through the coordination of the frequency division module and the timing module, the timing and frequency division circuit 50 achieves flexible frequency division and precise timing, providing a programmable wake-up and calibration mechanism for the low-frequency main control circuit 20. Its multi-level frequency division capability and dynamic configuration characteristics significantly improve the adaptability and performance of the control circuit 100 in low-power, high-precision scenarios.
[0026] Please continue reading. Figure 1 In some embodiments, the third input terminal 206 of the low-frequency main control circuit 20 is connected to an external wake-up source signal input pin. When the third input terminal 206 of the low-frequency main control circuit 20 detects a valid wake-up signal, the first output terminal 202 of the low-frequency main control circuit 20 is used to send a start signal to the input terminal 301 of the high-frequency oscillator 30 to control the high-frequency oscillator 30 to start. The second output terminal 203 of the low-frequency main control circuit 20 is used to send a wake-up signal to the external control circuit 100. The fourth input terminal 207 of the low-frequency main control circuit 20 is used to receive an external circuit sleep signal. When the fourth input terminal 207 of the low-frequency main control circuit 20 receives the external circuit sleep signal, the first output terminal 202 of the low-frequency main control circuit 20 is used to send a shutdown signal to the input terminal 301 of the high-frequency oscillator 30 to control the high-frequency oscillator 30 to shut down.
[0027] Specifically, the low-frequency main control circuit 20 further integrates external wake-up source detection and sleep control functions. Through its third input terminal 206, fourth input terminal 207, output terminal 202, and second output terminal 203, the low-frequency main control circuit 20 responds to external wake-up and sleep signals, thereby dynamically controlling the start and stop of the high-frequency oscillator 30 and the external control circuit. The high-frequency oscillator 30 only starts when needed, significantly reducing overall system power consumption. Through the coordinated control of its third input terminal 206 and fourth input terminal 207, the low-frequency main control circuit 20 achieves efficient response to external wake-up signals and external circuit sleep signals, dynamically managing the start and stop of the high-frequency oscillator 30 and the external control circuit. This results in low power consumption, high response speed, and flexible adaptability.
[0028] Please continue reading. Figure 1In some embodiments, the control circuit 100 includes a low-frequency correction circuit 40, which is used to acquire the low-frequency clock signal output from the output terminal 101 of the low-frequency oscillator 10 and the high-frequency clock signal output from the output terminal 302 of the high-frequency oscillator 30, and generate a low-frequency oscillator control signal based on the phase difference between the low-frequency clock signal and the high-frequency clock signal to correct the low-frequency oscillator 10.
[0029] Specifically, the control circuit 100 includes a low-frequency correction circuit 40. The low-frequency correction circuit 40 detects the phase difference between the output signals of the low-frequency oscillator 10 and the high-frequency oscillator 30, and generates a control signal to dynamically adjust the frequency of the low-frequency oscillator 10, thereby achieving high-precision frequency correction. In one embodiment, the output terminal 101 of the low-frequency oscillator 10 outputs a low-frequency clock signal to be corrected, and the output terminal 302 of the high-frequency oscillator 30 provides a high-precision high-frequency clock signal for reference. The low-frequency correction circuit 40 detects the phase difference between the low-frequency clock signal and the high-frequency clock signal, calculates the frequency deviation based on the phase difference, and generates an error signal. The error signal is converted into a control signal for the low-frequency oscillator 10 to adjust its oscillation parameters. Through phase difference detection and dynamic control, the low-frequency correction circuit 40 achieves high-precision, low-power frequency correction of the low-frequency oscillator 10. Its closed-loop feedback mechanism and real-time adjustment capability significantly improve the stability and reliability of the control circuit 100 in complex environments.
[0030] This application discloses an integrated chip, which includes a main control circuit and a control circuit 100. The main control circuit is electrically connected to the control circuit 100. The control circuit 100 includes a low-frequency oscillator 10, a low-frequency main control circuit 20, a high-frequency oscillator 30, and a low-frequency frequency correction circuit 40. The output terminal 101 of the low-frequency oscillator 10 is connected to the first input terminal 201 of the low-frequency main control circuit 20. The first output terminal 202 of the low-frequency main control circuit 20 is connected to the input terminal 301 of the high-frequency oscillator 30. The second output terminal 203 of the low-frequency main control circuit 20 is connected to the first input terminal 401 of the low-frequency frequency correction circuit 40. The output terminal 302 of the high-frequency oscillator 30 is connected to the second input terminal 402 of the low-frequency frequency correction circuit 40. The output terminal 101 of the low-frequency oscillator 10 is connected to the third input terminal 403 of the low-frequency frequency correction circuit 40. The output terminal 404 of the low-frequency frequency correction circuit 40 is connected to the input terminal 102 of the low-frequency oscillator 10, for controlling the frequency of the low-frequency oscillator 10.
[0031] The integrated chip in this application includes a main control circuit and a control circuit 100. Even in low power mode, the low frequency oscillator 10 is quickly corrected by the high frequency oscillator 30 and the low frequency correction circuit 40 to obtain an accurate low frequency and ensure working accuracy.
[0032] Specifically, rapid frequency correction of the low-frequency oscillator 10 is achieved through the synergistic effect of the high-frequency oscillator 30 and the low-frequency correction circuit 40. In some embodiments, the high-frequency oscillator 30 may employ an internal RC oscillator, which has the advantages of low cost and fast start-up. In some embodiments, the high-frequency oscillator 30 may also employ an external crystal oscillator, which has the advantage of high stability. The low-frequency oscillator 10 may be selected as an ultra-low-power architecture (e.g., consuming approximately 1 μA of current) to ensure continuous operation in low-power mode. The output terminal 101 of the low-frequency oscillator 10 is connected to the first input terminal 201 of the low-frequency main control circuit 20. The input terminal 102 of the low-frequency oscillator 10 is connected to the output terminal 404 of the low-frequency correction circuit 40, forming a feedback loop for dynamically adjusting the low-frequency clock signal of the low-frequency oscillator 10. The low-frequency main control circuit 20 is capable of receiving and processing the low-frequency clock signal generated by the low-frequency oscillator 10. The first output terminal 202 of the low-frequency main control circuit 20 is connected to the input terminal 301 of the high-frequency oscillator 30. The low-frequency main control circuit 20 can send control signals to the high-frequency oscillator 30 to control the high-frequency oscillator 30 to turn it on or off. When the high-frequency oscillator 30 is on, it can output a high-frequency clock signal. The second output terminal 203 of the low-frequency main control circuit 20 is connected to the first input terminal 401 of the low-frequency frequency correction circuit 40 for auxiliary correction.
[0033] In some embodiments, the control circuit 100 is connected to an external control circuit. The low-frequency main control circuit 20 sends a signal to start the high-frequency oscillator 30 and wake up the external control circuit. After the external control circuit finishes its work, it inputs a sleep signal through the external circuit to notify the low-frequency main control circuit 20 to shut down the high-frequency oscillator 30 and the external control circuit, thereby reducing power consumption. Based on this, the low-frequency frequency correction circuit 40 adjusts the frequency of the low-frequency oscillator 10 to adjust the low-frequency clock signal through various error calculation methods. For example, the period counting method is used to count the period of the low-frequency oscillator 10 using the high-frequency clock signal of the high-frequency oscillator 30, and the error between the actual period and the target period is compared to generate a correction signal; or the phase difference is measured by the phase comparison method and the frequency is quickly adjusted; in addition, data from temperature / voltage sensors can be combined for compensation to improve stability in complex environments. The control circuit 100 in this embodiment performs dynamic power consumption management, further reducing overall power consumption by shutting down the unnecessary working phase of the high-frequency oscillator 30, and can switch different correction algorithms as needed, balancing accuracy and efficiency. While ensuring the accuracy of the low-frequency clock signal generated by the low-frequency oscillator 10, ultra-low power consumption operation is achieved.
[0034] Please continue reading. Figure 1In some embodiments, the integrated chip includes a control circuit 100, which includes a timing and frequency divider circuit 50. The first input terminal 501 of the timing and frequency divider circuit 50 is connected to the output terminal 101 of the low-frequency oscillator 10, the second input terminal 502 of the timing and frequency divider circuit 50 is connected to the third output terminal 204 of the low-frequency main control circuit 20, and the output terminal 503 of the timing and frequency divider circuit 50 is connected to the second input terminal 205 of the low-frequency main control circuit 20.
[0035] Specifically, the integrated chip includes a control circuit 100, which includes a timing divider circuit 50. The timing divider circuit 50 is connected to the low-frequency oscillator 10 and the low-frequency main control circuit 20, respectively. The timing divider circuit 50 can generate the timing signal required by the low-frequency main control circuit 20 according to the low-frequency clock signal generated by the low-frequency oscillator 10 and the selection of the low-frequency main control circuit 20.
[0036] Please continue reading. Figure 1 In some embodiments, the integrated chip includes a control circuit 100, which includes a timing and frequency division circuit 50. The timing and frequency division circuit 50 includes a frequency division module and a timing module. The frequency division module performs frequency division processing on the low-frequency clock output by the low-frequency oscillator 10. The timing module performs timing according to the frequency division result and sends the frequency-divided clock to the low-frequency main control circuit 20. The low-frequency main control circuit 20 is used to wake up the high-frequency oscillator 30 and the low-frequency frequency correction circuit 40 according to the frequency-divided clock at a preset period.
[0037] Specifically, the integrated chip includes a control circuit 100, which includes a timing and frequency divider circuit 50. The timing and frequency divider circuit 50 includes a frequency divider module and a timing module. Through the coordinated action of the frequency divider module and the timing module, a frequency-divided clock signal is provided to the low-frequency main control circuit 20 to support the periodic wake-up and calibration operations of the high-frequency oscillator 30 and the low-frequency correction circuit 40. In one embodiment, the timing and frequency divider circuit 50 divides and times the low-frequency clock signal generated by the low-frequency oscillator, generating wake-up clocks with selectable period levels such as 4ms, 8ms, 16ms, and 32ms, and correction clocks with selectable levels. Thus, through the coordination of the frequency divider module and the timing module, the timing and frequency divider circuit 50 achieves flexible frequency division and precise timing, providing a programmable wake-up and calibration mechanism for the low-frequency main control circuit 20. Its multi-level frequency division capability and dynamic configuration characteristics significantly improve the adaptability and performance of the integrated chip in low-power, high-precision scenarios.
[0038] Please continue reading. Figure 1In some embodiments, the integrated chip includes a control circuit 100, which includes a low-frequency main control circuit 20. The third input terminal 206 of the low-frequency main control circuit 20 is connected to an external wake-up source signal input pin. When the third input terminal 206 of the low-frequency main control circuit 20 detects a valid wake-up signal, the first output terminal 202 of the low-frequency main control circuit 20 sends a start signal to the input terminal 301 of the high-frequency oscillator 30 to control the high-frequency oscillator 30 to start. The second output terminal 203 of the low-frequency main control circuit 20 sends a wake-up signal to the external control circuit 100. The fourth input terminal 207 of the low-frequency main control circuit 20 receives an external circuit sleep signal. When the fourth input terminal 207 of the low-frequency main control circuit 20 receives the external circuit sleep signal, the first output terminal 202 of the low-frequency main control circuit 20 sends a stop signal to the input terminal 301 of the high-frequency oscillator 30 to control the high-frequency oscillator 30 to stop.
[0039] Specifically, the low-frequency main control circuit 20 further integrates external wake-up source detection and sleep control functions. Through its third input terminal 206, fourth input terminal 207, output terminal 202, and second output terminal 203, the low-frequency main control circuit 20 responds to external wake-up and sleep signals, thereby dynamically controlling the start and stop of the high-frequency oscillator 30 and the external control circuit. The high-frequency oscillator 30 only starts when needed, significantly reducing overall system power consumption. Through the coordinated control of its third input terminal 206 and fourth input terminal 207, the low-frequency main control circuit 20 achieves efficient response to external wake-up signals and external circuit sleep signals, dynamically managing the start and stop of the high-frequency oscillator 30 and the external control circuit. This results in low power consumption, high response speed, and flexible adaptability.
[0040] Please continue reading. Figure 1 In some embodiments, the integrated chip includes a control circuit 100, which includes a low-frequency correction circuit 40. The low-frequency correction circuit 40 is used to acquire the low-frequency clock signal output from the output terminal 101 of the low-frequency oscillator 10 and the high-frequency clock signal output from the output terminal 302 of the high-frequency oscillator 30, and generate a low-frequency oscillator control signal based on the phase difference between the low-frequency clock signal and the high-frequency clock signal to correct the low-frequency oscillator 10.
[0041] Specifically, the control circuit 100 includes a low-frequency correction circuit 40. The low-frequency correction circuit 40 detects the phase difference between the output signals of the low-frequency oscillator 10 and the high-frequency oscillator 30, and generates a control signal to dynamically adjust the frequency of the low-frequency oscillator 10, thereby achieving high-precision frequency correction. In one embodiment, the output terminal 101 of the low-frequency oscillator 10 outputs a low-frequency clock signal to be corrected, and the output terminal 302 of the high-frequency oscillator 30 provides a high-precision high-frequency clock signal for reference. The low-frequency correction circuit 40 detects the phase difference between the low-frequency clock signal and the high-frequency clock signal, calculates the frequency deviation based on the phase difference, and generates an error signal. The error signal is converted into a control signal for the low-frequency oscillator 10 to adjust its oscillation parameters. Through phase difference detection and dynamic control, the low-frequency correction circuit 40 achieves high-precision, low-power frequency correction of the low-frequency oscillator 10. Its closed-loop feedback mechanism and real-time adjustment capability significantly improve the stability and reliability of the control circuit 100 in complex environments.
[0042] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of those different embodiments or examples, without contradiction.
[0043] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connections, detachable connections, or integral connections; it can include direct connections or indirect connections through an intermediate medium; and it can also include internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0045] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0046] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.
[0047] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A control circuit, characterized in that, The control circuit includes: Low-frequency oscillator; A low-frequency main control circuit, wherein the output terminal of the low-frequency oscillator is connected to the first input terminal of the low-frequency main control circuit; A high-frequency oscillator, wherein the first output terminal of the low-frequency main control circuit is connected to the input terminal of the high-frequency oscillator; A low-frequency correction circuit is provided, wherein the second output terminal of the low-frequency main control circuit is connected to the first input terminal of the low-frequency correction circuit, the output terminal of the high-frequency oscillator is connected to the second input terminal of the low-frequency correction circuit, the output terminal of the low-frequency oscillator is connected to the third input terminal of the low-frequency correction circuit, and the output terminal of the low-frequency correction circuit is connected to the input terminal of the low-frequency oscillator, for controlling the frequency of the low-frequency oscillator.
2. The control circuit according to claim 1, characterized in that, The control circuit includes a timing frequency divider circuit, the first input terminal of which is connected to the output terminal of the low-frequency oscillator, the second input terminal of which is connected to the third output terminal of the low-frequency main control circuit, and the output terminal of which is connected to the second input terminal of the low-frequency main control circuit.
3. The control circuit according to claim 2, characterized in that, The timing and frequency division circuit includes a frequency division module and a timing module. The frequency division module performs frequency division processing on the low-frequency clock output by the low-frequency oscillator. The timing module performs timing based on the frequency division result and sends the frequency-divided clock to the low-frequency main control circuit. The low-frequency main control circuit is used to wake up the high-frequency oscillator and the low-frequency frequency correction circuit according to the frequency-divided clock at a preset period.
4. The control circuit according to claim 1, characterized in that, The third input terminal of the low-frequency main control circuit is connected to the external wake-up source signal input pin. When the third input terminal of the low-frequency main control circuit detects a valid wake-up signal, the first output terminal of the low-frequency main control circuit is used to send a start signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to start. The second output terminal of the low-frequency main control circuit is used to send a wake-up signal to the external control circuit. The fourth input terminal of the low-frequency main control circuit is used to receive an external circuit sleep signal. When the fourth input terminal of the low-frequency main control circuit receives an external circuit sleep signal, the first output terminal of the low-frequency main control circuit is used to send a shutdown signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to shut down.
5. The control circuit according to claim 1, characterized in that, The low-frequency correction circuit is used to acquire the low-frequency clock signal output from the output terminal of the low-frequency oscillator and the high-frequency clock signal output from the output terminal of the high-frequency oscillator, and generate a low-frequency oscillator control signal based on the phase difference between the low-frequency clock signal and the high-frequency clock signal to correct the low-frequency oscillator.
6. An integrated chip, characterized in that, The integrated chip includes a main control circuit and a control circuit, wherein the main control circuit is electrically connected to the control circuit, and the control circuit includes: Low-frequency oscillator; A low-frequency main control circuit, wherein the output terminal of the low-frequency oscillator is connected to the first input terminal of the low-frequency main control circuit; A high-frequency oscillator, wherein the first output terminal of the low-frequency main control circuit is connected to the input terminal of the high-frequency oscillator; A low-frequency correction circuit is provided, wherein the second output terminal of the low-frequency main control circuit is connected to the first input terminal of the low-frequency correction circuit, the output terminal of the high-frequency oscillator is connected to the second input terminal of the low-frequency correction circuit, the output terminal of the low-frequency oscillator is connected to the third input terminal of the low-frequency correction circuit, and the output terminal of the low-frequency correction circuit is connected to the input terminal of the low-frequency oscillator, for controlling the frequency of the low-frequency oscillator.
7. The integrated chip according to claim 6, characterized in that, The control circuit includes a timing frequency divider circuit, the first input terminal of which is connected to the output terminal of the low-frequency oscillator, the second input terminal of which is connected to the third output terminal of the low-frequency main control circuit, and the output terminal of which is connected to the second input terminal of the low-frequency main control circuit.
8. The integrated chip according to claim 7, characterized in that, The timing and frequency division circuit includes a frequency division module and a timing module. The frequency division module performs frequency division processing on the low-frequency clock output by the low-frequency oscillator. The timing module performs timing based on the frequency division result and sends the frequency-divided clock to the low-frequency main control circuit. The low-frequency main control circuit is used to wake up the high-frequency oscillator and the low-frequency frequency correction circuit according to the frequency-divided clock at a preset period.
9. The integrated chip according to claim 6, characterized in that, The third input terminal of the low-frequency main control circuit is connected to the external wake-up source signal input pin. When the third input terminal of the low-frequency main control circuit detects a valid wake-up signal, the first output terminal of the low-frequency main control circuit is used to send a start signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to start. The second output terminal of the low-frequency main control circuit is used to send a wake-up signal to the external control circuit. The fourth input terminal of the low-frequency main control circuit is used to receive an external circuit sleep signal. When the fourth input terminal of the low-frequency main control circuit receives an external circuit sleep signal, the first output terminal of the low-frequency main control circuit is used to send a shutdown signal to the input terminal of the high-frequency oscillator to control the high-frequency oscillator to shut down.
10. The integrated chip according to claim 6, characterized in that, The low-frequency correction circuit is used to acquire the low-frequency clock signal output from the output terminal of the low-frequency oscillator and the high-frequency clock signal output from the output terminal of the high-frequency oscillator, and generate a low-frequency oscillator control signal based on the phase difference between the low-frequency clock signal and the high-frequency clock signal to correct the low-frequency oscillator.