Wireless debugging circuit structure adaptive to MT7916 and MT7976 suite piece scheme

Abstract

The utility model relates to a kind of wireless debugging circuit structure suitable for MT7916 and MT7976 set piece scheme, the circuit structure includes 2.4G link or 5G link, 2.4G link includes chip end, first Π type link, primary wave trap filter module, second Π type matching link, third Π type matching link and combiner;5G link includes chip end, first Π type link, primary wave trap filter module, second Π type matching link and combiner;The signal output end of chip end is connected with the input end of first Π type matching link, and the output end of first Π type link is connected with primary wave trap filter module.Adopted the wireless debugging circuit structure suitable for MT7916 and MT7976 set piece scheme of the utility model, the parameter of link matching is adjusted, the wireless performance under MT7916+MT7976 set piece built-in power amplification scheme is optimized, the influence of 2.4G second harmonic to 5G link is solved, the flatness within operating bandwidth and EVM problem are solved, and anti-interference capability is greatly improved.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency technology, and more particularly to the field of wireless performance, specifically referring to a wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset solutions. Background Technology

[0002] With the rapid development of communication technology, the MT7916+MT7976 chipset with built-in power amplifier has gradually become the mainstream design solution for WiFi-6. However, due to the limited PCB space, complex design, and numerous types of signals and power supplies, crosstalk from various signals interferes with the wireless link, and the wireless test performance fails to meet the requirements. A technical solution is needed to address this problem. Utility Model Content

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a wireless debugging circuit structure with built-in power amplifier that is simple in structure, has strong anti-interference ability, and is widely applicable to MT7916 and MT7976 chipset solutions.

[0004] To achieve the above objectives, the wireless debugging circuit structure of this utility model, adapted to the MT7916 and MT7976 chipset solutions, is as follows: This wireless debugging circuit structure, adapted to the MT7916 and MT7976 chipset solutions, is characterized by comprising either a 2.4G link or a 5G link. The 2.4G link includes a chip, a first-stage notch filter module, a second-stage notch filter, a third-stage notch filter, and a combiner. The 5G link also includes a chip, a first-stage notch filter, a second-stage notch filter, a third-stage notch filter, and a combiner. In the 2.4G link, the signal output terminal of the chip is connected to the input terminal of the first-stage notch filter, and the output of the first-stage notch filter... The chip terminal in the 5G link is connected to the input of the first-stage notch filter module. The output of the first-stage notch filter module is connected to the input of the second Π-type matching link. The output of the second Π-type link is connected to the input of the third Π-type link. The output of the third Π-type link is connected to the combiner.

[0005] Preferably, the circuit structure further includes a reserved Π-type matching link, the input end of which is connected to the combiner, and the output end of which is connected to the wireless output IPEX connector.

[0006] This invention employs a wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset. By adjusting the link matching parameters, the wireless performance of the MT7916+MT7976 chipset's built-in power amplifier scheme is optimized. A notch filter is used, and the simple LC circuit eliminates the need for traditional filters, reducing costs and minimizing the impact of 2.4G and its second harmonic on the 5G link. Secondly, a vector network analyzer is used to adjust the link matching, bringing the impedance of the 2.4G and 5G links to around 50 ohms, reducing in-band loss, improving the flatness of the 2.4G and 5G channel output power, and optimizing the edge channel's EVM index by 3dB. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the chip-side signal output of the wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset schemes of this utility model.

[0008] Figure 2a and 2b This is a schematic diagram of a 2.4G link for the wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset solutions of this utility model.

[0009] Figure 3a and 3b This is a schematic diagram of a 5G link for a wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset solutions of this utility model.

[0010] Figure 4a and 4b This is a schematic diagram of the wireless output link of the wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset solutions of this utility model.

[0011] Figure 5 This is a schematic diagram of a notch filter model on a 2.4G link, which is adapted to the wireless debugging circuit structure of the MT7916 and MT7976 chipset schemes of this utility model.

[0012] Figure 6 This is a schematic diagram of a notch filter model for a 5G link, which is adapted to the wireless debugging circuit structure of the MT7916 and MT7976 chipset solutions. Detailed Implementation

[0013] To more clearly describe the technical content of this utility model, the following description is provided in conjunction with specific embodiments.

[0014] This utility model discloses a wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset solutions. The circuit structure includes a 2.4G link or a 5G link. The 2.4G link includes a chip terminal, a first P-type matching link, a first-stage notch filter module, a second P-type matching link, a third P-type matching link, and a combiner. The 5G link includes a chip terminal, a first P-type matching link, a first-stage notch filter module, a second P-type matching link, and a combiner. In the 2.4G link, the signal output terminal of the chip terminal is connected to the input terminal of the first P-type matching link, and the output terminal of the first P-type matching link is connected to... The first-stage notch filter module is connected to the input of the second Π-type matching link, the output of the second Π-type link is connected to the input of the third Π-type link, and the output of the third Π-type link is connected to the combiner. In the 5G link, the signal output of the chip is connected to the input of the first Π-type matching link, the output of the first Π-type link is connected to the first-stage notch filter module, the output of the first-stage notch filter module is connected to the input of the second Π-type matching link, and the output of the second Π-type link is connected to the combiner.

[0015] In a preferred embodiment of this utility model, the circuit structure further includes a reserved Π-type link, the input end of which is connected to the combiner, and the output end of which is connected to the wireless output end.

[0016] In the specific embodiments of this utility model, essential technologies for single-board design, such as radio frequency technology and wireless performance design, are involved. It primarily addresses the MT7916+MT7976 chipset integrated power amplifier scheme, which has strict wireless performance requirements and faces limited PCB space. This utility model proposes a link matching solution for products using this scheme that fail to meet wireless performance specifications.

[0017] The purpose of this invention is to propose a radio frequency link matching adjustment scheme based on the built-in power amplifier scheme of the MT7916+MT7976 chipset, so as to achieve the expected wireless performance.

[0018] This invention, based on actual circuit testing, performs matching adjustments to the RF links of 2.4G, 5G, and the combined circuit.

[0019] After the 2.4G signal comes out of the chip, it first passes through the first Π-type link, where the impedance is adjusted at the chip end. Then it passes through a first-stage notch filter module with a resonant frequency of 4.8 to 5.5G to filter out the harmonic signal and reduce spurious signals. Next, it passes through the second Π-type link, where the impedance of the filter module is adjusted. Finally, it passes through the third Π-type link before the combiner, where the impedance is adjusted at the combiner end.

[0020] Similar to 5G signals, the signal first passes through a first Π-shaped link, where the impedance is adjusted at the chip level. Then it passes through a first-stage notch filter module with a resonant frequency of 2.4–3 GHz, which filters out 2.4 GHz signals and low-frequency signals to reduce spurious signals. Next, it passes through a second Π-shaped link, where the impedance of the filter module is adjusted. Finally, it passes through a third Π-shaped link before the combiner, where the impedance is adjusted at the combiner end.

[0021] After passing through the combiner, a primary Π-type matching link is reserved at the wireless output end, providing a debugging location. Specific capacitance values ​​can be adjusted through testing on a vector network analyzer, and then adjusted at the wireless output end based on the test results.

[0022] like Figure 2a , 2b Figures 3a, 3b, 4a, and 4b show the RF matching link based on the built-in power amplifier scheme of the MT7616+MT7676 chipset. The specific values ​​can be fine-tuned according to the actual test results on the board.

[0023] For the specific implementation scheme of this embodiment, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0024] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0025] It should be noted that in the description of this utility model, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this utility model, unless otherwise stated, "a plurality of" means at least two.

[0026] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0027] This invention employs a wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset. By adjusting the link matching parameters, the wireless performance of the MT7916+MT7976 chipset's built-in power amplifier scheme is optimized, reducing low-frequency spurious signals to meet requirements. Matching brings the link impedance to around 50 ohms, resulting in more stable in-band signals and improved sideband signal quality. Wireless EVM test data is optimized by 3dBm to meet specifications. An LC notch filter is used, eliminating the need for traditional filters and reducing costs. Filtering of the 2.4G frequency multiplier signal at 4.8G reduces its impact on 5G.

[0028] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A wireless debugging circuit structure adapted to MT7916 and MT7976 chipset solutions, characterized in that, The circuit structure includes a 2.4G link or a 5G link. The 2.4G link includes a chip, a first-type Π link, a first-stage notch filter module, a second-type Π matching link, a third-type Π matching link, and a combiner. The 5G link includes a chip, a first-type Π link, a first-stage notch filter module, a second-type Π matching link, and a combiner. In the 2.4G link, the signal output terminal of the chip is connected to the input terminal of the first-type Π matching link, and the output terminal of the first-type Π link is connected to the first-stage notch filter module. The output of the filter module is connected to the input of the second Π-type matching link, the output of the second Π-type link is connected to the input of the third Π-type link, and the output of the third Π-type link is connected to the combiner; the signal output of the chip in the 5G link is connected to the input of the first Π-type matching link, the output of the first Π-type link is connected to the first-stage notch filter module, the output of the first-stage notch filter module is connected to the input of the second Π-type matching link, and the output of the second Π-type link is connected to the combiner.

2. The wireless debugging circuit structure adapted to the MT7916 and MT7976 chipset scheme according to claim 1, characterized in that, The circuit structure also includes a reserved Π-type matching link, the input end of which is connected to the combiner, and the output end of which is connected to the IPEX connector of the wireless output end.

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