A three-layer switch and replaceable module card
Patent Information
- Application Number
- CN202522671106.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-12-17
AI Technical Summary
The existing switch ports are not flexibly configured and lack high-precision clock synchronization capabilities, resulting in high upgrade costs and unstable data transmission.
Design a three-layer switch with a modular structure. The PHY chip is placed on a pluggable module card, and a high-precision synchronous clock circuit is integrated, including a temperature-compensated crystal oscillator and a clock generator, to provide a high-precision clock reference signal.
It enables flexible port configuration and low-cost upgrades, and ensures the stability and reliability of data transmission, making it particularly suitable for application scenarios with strict time synchronization requirements.
Smart Images
Figure CN224935693U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of network switching technology, specifically relating to a three-layer switch and a replaceable module card. Background Technology
[0002] Layer 3 switches are core devices in building modern computer networks, responsible for routing and switching high-speed data packets between different network segments. With the development of network technology and the diversification of application scenarios, users are placing higher demands on the flexibility and performance of switching equipment.
[0003] However, existing switches, especially some rack-mount switches, typically have the following shortcomings: First, the type and number of their communication ports are fixed at the factory; for example, the entire unit is designed with a fixed all-electrical or all-optical port configuration. When the network environment changes or service requirements upgrade, necessitating the introduction of different types of interfaces (such as changing from electrical ports to optical ports), users have to replace the entire switch, leading not only to high upgrade costs but also creating inventory pressure for equipment manufacturers due to multiple models. Second, in applications with high time synchronization requirements, such as industrial control, financial transactions, or scientific data acquisition, precise data transmission timing is crucial. Many conventional switches lack built-in high-precision clock synchronization mechanisms, such as Synchronous Ethernet (SyncE) functionality, which can cause jitter or delays in packet transmission, affecting the stability and reliability of the entire system.
[0004] Therefore, how to provide a switch with flexible port configuration, low expansion cost, and high-precision clock synchronization capability is a technical problem that urgently needs to be solved in this field. Utility Model Content
[0005] To address the aforementioned problems in the existing technology, namely the inflexible port configuration and lack of high-precision clock synchronization in existing switches, this utility model provides a three-layer switch and a replaceable module card.
[0006] In a first aspect, this utility model proposes a three-layer switch, comprising:
[0007] The device host includes a motherboard and at least one module card slot;
[0008] The core switching chip is located on the motherboard;
[0009] At least one module card, the module card being adapted to the module card slot for pluggable connection to the motherboard; the module card is provided with a PHY chip, wherein the core switching chip and the PHY chip communicate with each other via a high-speed data channel;
[0010] A synchronous clock circuit, comprising a temperature-compensated crystal oscillator and a clock generator; the clock generator is electrically connected to the temperature-compensated crystal oscillator and the core switching chip, and is used to provide a clock reference signal to the core switching chip.
[0011] Furthermore, the module card includes a high-speed connector that mates with the motherboard, and a high-speed data channel between the core switching chip and the PHY chip is established through the high-speed connector.
[0012] Furthermore, the module card is at least one of the following: an all-electric interface module card, an all-optical interface module card, and an optoelectronic hybrid interface module card.
[0013] Furthermore, when the module card is a hybrid optoelectronic interface module card, it is provided with a first PHY chip and a second PHY chip; the first PHY chip is connected to a first RJ45 connector, and the second PHY chip is connected to an optical cage.
[0014] Furthermore, the first PHY chip is connected to the first RJ45 connector via the first transformer.
[0015] Furthermore, the core switching chip also has a clock receiving pin, which is used to receive the recovered clock signal and transmit it to the clock generator.
[0016] Furthermore, the clock reference signal provided by the clock generator to the core switching chip is a 156.24MHz clock signal at LVDS level.
[0017] Furthermore, the device host is also used to identify the module card ID of the module card, so as to configure the corresponding port configuration according to the module card ID.
[0018] Furthermore, the host device also includes a fixed high-speed optical transmission interface, which is electrically connected to the core switching chip.
[0019] In a second aspect, this utility model provides a replaceable module card for a Layer 3 switch, comprising:
[0020] Card body, which is adapted to the module card slot of a Layer 3 switch;
[0021] The PHY chip is located on the card body;
[0022] A high-speed connector is provided on the card body for pluggable connection to the motherboard of the Layer 3 switch;
[0023] The PHY chip is adapted to establish a high-speed data channel with the core switching chip located on the motherboard via the high-speed connector.
[0024] The beneficial effects of this utility model are:
[0025] This invention separates interface functionality from the switch host by placing the PHY chip, which determines the physical interface type, on a pluggable module card instead of fixing it to the motherboard. When users need to change the port configuration (e.g., from an electrical port to an optical port) or expand ports, they only need to replace or add the corresponding module card, without replacing the entire switch device. This modular structure makes port configuration extremely flexible, significantly reducing users' subsequent network upgrade and maintenance costs. It also allows equipment manufacturers to effectively simplify their product lines, reduce inventory types, and lower production and warehousing costs by producing a single host and multiple module cards.
[0026] This invention integrates a dedicated synchronous clock circuit within the switch. This circuit consists of a highly stable temperature-compensated crystal oscillator and a clock generator, providing the core switching chip with a high-precision clock reference signal unaffected by ambient temperature changes. This enables the switch to support hardware-level Synchronous Ethernet (SyncE), fundamentally ensuring low jitter and low latency in data transmission, significantly improving the stability and reliability of the entire communication system. It is particularly suitable for applications with stringent time synchronization requirements, such as industrial control and high-frequency trading. Attached Figure Description
[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0028] Figure 1 This is a schematic diagram of the external structure of a three-layer switch according to this utility model;
[0029] Figure 2 This is a system block diagram of a three-layer switch according to the present invention;
[0030] Figure 3 This is a clock block diagram of a three-layer switch according to this utility model. Detailed Implementation
[0031] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0032] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0033] The first embodiment of this utility model proposes a three-layer switch, which includes:
[0034] The device host 100 includes a motherboard and at least one module card slot 110;
[0035] The core switching chip 130 is mounted on the motherboard;
[0036] At least one module card 200, the module card 200 being adapted to the module card slot 110 for pluggable connection to the motherboard;
[0037] The module card 200 is equipped with a PHY chip 210, wherein the core switching chip 130 and the PHY chip 210 communicate via a high-speed data channel.
[0038] A synchronous clock circuit 300 includes a temperature-compensated crystal oscillator 310 and a clock generator 320; the clock generator 320 is electrically connected to the temperature-compensated crystal oscillator 310 and the core switching chip 130, and is used to provide a clock reference signal to the core switching chip 130.
[0039] In this embodiment, to achieve complete switch functionality, the core switching chip 130 located on the motherboard 110 also integrates multiple control and management interfaces. Specifically, the core switching chip 130 is connected to the memory 410 via the DDR interface 131 for high-speed data caching and program execution; it is connected to the memory 420 via the eMMC interface 132 for storing operating system firmware and configuration files; it communicates with the clock generator 320 and the temperature sensor 430 via the I2C bus interface 133, the temperature sensor 430 being used to monitor the internal operating temperature of the device; and it is connected to the debug interface 440 via the UART0 interface 134, providing serial port access for device development and maintenance. Furthermore, the core switching chip 130 also drives multiple indicator lights 450 via its LED interface 135 to visually display the operating status of the device and each port.
[0040] Specifically, refer to Figure 1 and Figure 2The host device 100 of this Layer 3 switch is a monolithic structure, such as a standard 1U rackmount enclosure. Inside the host device 100 is a motherboard, which is the core circuit board of the system. The core switching chip 130, the core unit responsible for data switching and routing processing, is located on this motherboard. The front panel of the host device 100 has at least one module card slot 110, in this embodiment, three. Each module card slot 110 is used to accommodate and connect to one module card 200.
[0041] Module card 200 is a functional daughter card that independently designs the physical layer interface circuit, namely the PHY chip 210 and its peripheral circuits. It can be easily inserted into or removed from module card slot 110. The core switching chip 130 is responsible for processing data at layers 2 and 3 of the OSI model, while the PHY chip 210 is responsible for signal encoding, decoding, and transmission at layer 1. The two communicate through a high-speed data channel, which can be specifically implemented as a SerDes serializer / deserializer interface. In addition, a synchronous clock circuit 300 is integrated on the motherboard. This circuit provides a highly stable clock reference for the entire system, especially for the high-speed operation of the core switching chip 130, to support applications with high time accuracy requirements, such as Synchronous Ethernet (SyncE) technology. This solution achieves modularization of physical ports by separating the PHY chip from the motherboard to a replaceable module card. At the same time, the built-in dedicated synchronous clock circuit ensures the synchronization accuracy of data transmission, thereby effectively solving the problems of fixed configuration and insufficient clock performance in existing switches.
[0042] The module card 200 includes a high-speed connector 120 that mates with the motherboard. A high-speed data channel between the core switching chip 130 and the PHY chip 210 is established through the high-speed connector 120. Specifically, to ensure high-speed and reliable data transmission between the core switching chip 130 and the PHY chip 210 on the module card 200, a high-density, high-frequency high-speed connector 120 is provided at the insertion edge of the module card 200, and a matching slot-type connector is provided at the bottom of the module card slot 110 on the motherboard. When the module card 200 is inserted into the module card slot 110, the two are precisely aligned and engaged, thereby establishing a robust physical and electrical connection. Multiple high-speed interfaces 136 of the core switching chip 130 are connected to this slot-type connector via wiring on the motherboard, while the PHY chip 210 is connected to the connector on the board edge via wiring on the module card 200. In this way, a high-speed data channel, i.e., a SerDes channel, is established between the two. This design, employing a dedicated high-speed connector 120, ensures impedance matching and signal integrity for differential signals, effectively suppresses signal reflection and crosstalk, and provides a reliable physical link guarantee for data exchange at speeds up to several Gbps or even higher.
[0043] In a preferred embodiment, the module card 200 is at least one of a fully electrical interface module card 220, a fully optical interface module card 230, and a hybrid optoelectronic interface module card 240. This means that users can flexibly select different types of interface modules for the switch according to their actual networking needs. Taking an 8-port electrical module card as an example, this fully electrical interface module card 220 has multiple RJ45 interfaces on its panel for connecting standard twisted-pair network cables. Another type, the fully optical interface module card 230, such as an 8-port optical module card, has multiple optical transceiver slots, such as SFP or SFP+ optical cages 231, for accessing optical fibers. The hybrid optoelectronic interface module card 240, such as a module card that provides both 4 electrical ports and 4 optical ports, provides both RJ45 interfaces and optical transceiver slots. Users can freely combine and match different types of module cards in the three module card slots 110 of the device host 100. For example, they can configure an 8-Electronic port card, an 8-Optical port card, and a 4-Optical-4-Electronic port card to obtain a customized switch with 12 Electrical ports and 12 Optical ports. This design greatly improves the applicability and flexibility of the device, meets diverse port requirements, and avoids the huge cost waste caused by replacing the entire device due to port type mismatch.
[0044] When the module card 200 is a hybrid optoelectronic interface module card 240, it is equipped with a first PHY chip 211 and a second PHY chip 212. The first PHY chip 211 is connected to the first RJ45 connector 221, and the second PHY chip 212 is connected to the optical cage 231. Taking a 4-optical-4-electric hybrid interface module card as an example, this module card integrates at least two PHY chips with different functions. The first PHY chip 211 is specifically used for processing electrical signals, and its output / input pins are connected to the first RJ45 connector 221 to form an electrical port. The second PHY chip 212 is specifically used for processing optical signals, and its output / input pins are connected to the SFP optical transceiver slot, i.e., the optical cage 231, to form an optical port. Both PHY chips establish a high-speed data channel with the core switching chip 130 on the motherboard through the high-speed connector 120 on the module card. This design, which integrates two different physical media interfaces on a single module card, achieves functional fusion within a single card, further improving the density and flexibility of port configuration, and enabling richer interface combinations within a limited number of slots.
[0045] The first PHY chip 211 is connected to the first RJ45 connector 221 via a first transformer 222. In the design of the electrical port, to ensure safety and signal quality, the PHY chip and the external first RJ45 connector 221 are typically not directly connected, but rather coupled through a network isolation first transformer 222. This first transformer 222 plays several crucial roles: firstly, it provides electrical isolation, forming a potential isolation barrier between the PHY chip and the external network cable to prevent high voltage damage to the PHY chip caused by lightning strikes, static electricity, or line faults; secondly, it performs impedance matching, matching the output impedance of the PHY chip with the characteristic impedance of the twisted pair to reduce signal reflection; and finally, it effectively suppresses common-mode interference. Therefore, by adding the first transformer 222, the stability and reliability of the electrical port can be significantly enhanced, meeting the requirements of the Ethernet physical layer standard.
[0046] When the module card 200 is a fully electric interface module card 220, the high-speed connector 120 is connected to the third PHY chip 213, the third PHY chip 213 is connected to the second transformer 223, and the second transformer 223 is connected to two second RJ45 connectors 224.
[0047] When the module card 200 is an all-optical interface module card 230, the high-speed connector 120 is connected to the fourth PHY chip 214 and the fifth PHY chip 215, and the fourth PHY chip 214 and the fifth PHY chip 215 are connected to the gigabit optical cage 216.
[0048] One of the high-speed interfaces 136 on the core switching chip 130 is connected to the 10 Gigabit optical cage 137.
[0049] The core switching chip 130 also has a clock receiving pin, which is used to receive the recovered clock signal and transmit it to the clock generator 320.
[0050] Reference Figure 3The clock block diagram illustrates this crucial link for implementing synchronous Ethernet functionality. When the switch receives data from upstream devices in the network, the PHY chip 210 at the receiving end can recover the original clock signal from the data stream. This signal, known as the recovered clock signal, carries the clock information of the upstream device. To synchronize the switch with the upstream device, this recovered clock signal is transmitted to dedicated clock receiving pins of the core switching chip 130, such as RECV_CLK0, RECV_CLK1, and RECV_CLK2. The core switching chip 130 then routes these clock signals to the inputs of the clock generator 320, specifically the IN0P, IN1P, and IN2P pins. The phase-locked loop (PLL) circuit inside the clock generator 320 can select one of the recovered clocks as a reference and adjust its own oscillation frequency, thereby synchronizing the clock generated by the entire switch with the network's master clock. This design allows the switch to learn the clock from the network, ensuring clock uniformity across the entire network.
[0051] The clock reference signal provided by the clock generator 320 to the core switching chip 130 is a 156.24MHz clock signal at LVDS level. The clock generator 320 generates a high-quality, low-jitter clock signal by using the output of a high-stability temperature-compensated crystal oscillator 310 (TCXO) as a reference and selectively being calibrated by an externally recovered clock.
[0052] In this embodiment, as Figure 3 As shown, the output pins of clock generator 320, such as OUT1P / OUT1N, OUT2P / OUT2N, and OUT3P / OUT3N, generate multiple differential clock signals and provide them to multiple high-speed reference clock input pins of core switching chip 130, specifically HSS_REFCLK_P / N, HSS_S0_REFCLK_P / N, and HSS_S1_REFCLK_P / N. These clock signals use LVDS (Low Voltage Differential) level, which has excellent noise immunity and low electromagnetic interference, making it very suitable for transmission on high-speed PCBs. Its frequency is 156.24MHz, a commonly used reference frequency for high-speed SerDes interfaces. Providing such high-quality clock reference signals is fundamental to ensuring stable, low-error-rate data communication between the core switching chip and each PHY chip, as well as between the core switching chip and the high-speed optical port.
[0053] The host device 100 is also used to identify the module card ID 500 of the module card 200, so as to configure the corresponding port configuration according to the module card ID 500. To achieve plug-and-play functionality, each module card 200 stores unique identification information. This ID can be implemented by setting an EEPROM memory or a specific combination of ID resistors. When the module card 200 is inserted into the module card slot 110, the management interface of the microcontroller or core switching chip 130 within the host device 100, such as the I2C bus, will read the module card ID 500. The switch's operating system can automatically identify whether the currently inserted module card is an 8-port, 8-port, or 4-port / 4-fiber module card based on a preset ID-to-module card type mapping table. Subsequently, the system will automatically load the corresponding driver and configure the internal ports of the core switching chip 130 to correctly interface with the PHY chip 210 on the module card. This automated process eliminates the tedious manual setup by the user, greatly simplifying device deployment and maintenance.
[0054] The host device 100 also includes a fixed high-speed optical transmission interface, which is electrically connected to the core switching chip 130.
[0055] like Figure 1 and Figure 2 As shown, in addition to the three replaceable module card slots 110, the front panel of the device host 100 also integrates a set of fixed, non-replaceable high-speed optical transmission interfaces, such as eight 10 Gigabit optical interfaces. These fixed interfaces are typically used as uplink ports. Their corresponding PHY functions are usually integrated inside the core switching chip 130, or their high-speed SerDes interfaces are directly connected to the SFP+ optical cage 231 on the motherboard. This design balances flexibility and performance, providing customizable access layer interfaces through modular slots while ensuring stable, high-bandwidth connections to the network backbone through fixed high-speed interfaces.
[0056] The second embodiment of this utility model proposes a replaceable module card for a Layer 3 switch, comprising: a card body adapted to a module card slot 110 of the Layer 3 switch; a PHY chip 210 disposed on the card body; and a high-speed connector 120 disposed on the card body for pluggable connection to the motherboard of the Layer 3 switch; wherein the PHY chip 210 is adapted to establish a high-speed data channel with a core switching chip 130 disposed on the motherboard via the high-speed connector 120. This replaceable module card is the core component for realizing the flexible configuration function of the Layer 3 switch. Its card body is a PCB board, whose physical size and shape allow it to slide into and be fixed in the module card slot 110 of the switch host. The card body carries all the circuitry for implementing specific physical interface functions, with at least one PHY chip 210 at its core. A high-speed connector 120 is disposed on the inner edge of the card body for mating with the slot on the motherboard. When the module card is inserted, the PHY chip 210 can establish a high-speed data channel with the core switching chip 130 on the motherboard through the connector. Depending on the type of PHY chip and the different peripheral circuits, this module card can provide various interface forms such as all electrical ports, all optical ports, or hybrid optical-electrical ports. As an independent functional unit, it greatly facilitates the functional expansion, maintenance, and upgrade of the switch.
[0057] The terms “first”, “second”, etc., are used to distinguish similar objects, not to describe or indicate a specific order or sequence.
[0058] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent in such process, method, article, or apparatus / device.
[0059] The technical solution of this utility model has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the protection scope of this utility model is obviously not limited to these specific embodiments. Without departing from the principle of this utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of this utility model.
Claims
1. A Layer 3 switch, characterized in that, include: The device host (100) includes a motherboard and at least one module card slot (110). The core switching chip (130) is mounted on the motherboard; At least one module card (200) is adapted to the module card slot (110) for pluggable connection to the motherboard; the module card (200) is provided with a PHY chip (210), wherein the core switching chip (130) and the PHY chip (210) communicate via a high-speed data channel. A synchronous clock circuit (300) includes a temperature-compensated crystal oscillator (310) and a clock generator (320); the clock generator (320) is electrically connected to the temperature-compensated crystal oscillator (310) and the core switching chip (130) and is used to provide a clock reference signal to the core switching chip (130).
2. The Layer 3 switch according to claim 1, characterized in that, The module card (200) includes a high-speed connector (120) that works with the motherboard, and a high-speed data channel between the core switching chip (130) and the PHY chip (210) is established through the high-speed connector (120).
3. The Layer 3 switch according to claim 1, characterized in that, The module card (200) is at least one of the following: an all-electric interface module card (220), an all-optical interface module card (230), and an optoelectronic hybrid interface module card (240).
4. The Layer 3 switch according to claim 3, characterized in that, When the module card (200) is a photoelectric hybrid interface module card (240), it is provided with a first PHY chip (211) and a second PHY chip (212); the first PHY chip (211) is connected to the first RJ45 connector (221), and the second PHY chip (212) is connected to the optical cage (231).
5. The Layer 3 switch according to claim 4, characterized in that, The first PHY chip (211) is connected to the first RJ45 connector (221) via the first transformer (222).
6. The Layer 3 switch according to claim 1, characterized in that, The core switching chip (130) also has a clock receiving pin, which is used to receive the recovered clock signal and transmit it to the clock generator (320).
7. The Layer 3 switch according to claim 6, characterized in that, The clock reference signal provided by the clock generator (320) to the core switching chip (130) is a 156.24MHz clock signal at LVDS level.
8. The Layer 3 switch according to claim 1, characterized in that, The device host (100) is also used to identify the module card ID (500) of the module card (200) in order to configure the corresponding port configuration according to the module card ID (500).
9. The Layer 3 switch according to claim 1, characterized in that, The host device (100) also includes a fixed high-speed optical transmission interface, which is electrically connected to the core switching chip (130).
10. A replaceable module card for a Layer 3 switch, characterized in that, include: Card body, which is adapted to the module card slot (110) of a Layer 3 switch. A PHY chip (210) is disposed on the card body; A high-speed connector (120) is disposed on the card body for pluggable connection to the motherboard of the Layer 3 switch; The PHY chip (210) is adapted to establish a high-speed data channel with the core switching chip (130) disposed on the motherboard via the high-speed connector (120).