Semiconductor package structure and electronic device

Abstract

The present disclosure relates to a semiconductor packaging structure and an electronic device, the semiconductor packaging structure comprising a substrate, a chip and a sealing structure, the chip being arranged on the substrate; the sealing structure comprising a heat dissipation cover connected to the chip, and a cooling cavity formed between the heat dissipation cover and the chip for the cooling medium to flow through to exchange heat with the chip; wherein a first side wall of the heat dissipation cover towards the chip forms part of the inner wall surface of the cooling cavity, a second side wall of the chip away from the substrate forms part of the inner wall surface of the cooling cavity, and the first side wall and the second side wall are both provided with flow channels communicating with the cooling cavity. Through the above technical solution, the semiconductor packaging structure provided by the present disclosure can improve the heat dissipation effect of the chip, help to ensure that the chip operates stably and with high performance at a safe temperature, and achieve the purpose of improving the performance and reliability of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and an electronic device. Background Technology

[0002] In related technologies, as the demand for computing power in chips increases, the power consumption of chips also rises sharply, resulting in an unprecedented increase in the heat flux density inside the chip. The heat dissipation bottleneck has become a key factor restricting the improvement of chip performance and reliability. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor packaging structure and electronic device that can improve the heat dissipation of the chip, helping to ensure that the chip operates stably and with high performance at a safe temperature.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a semiconductor packaging structure, comprising: substrate; A chip is disposed on the substrate; and The sealing structure includes a heat sink, which is connected to the chip, and a cooling cavity is formed between the heat sink and the chip for a cooling medium to flow through and exchange heat with the chip. The heat dissipation cover forms a portion of the inner wall surface of the cooling cavity on the first sidewall facing the chip, and the chip forms a portion of the inner wall surface of the cooling cavity on the second sidewall facing away from the substrate. Both the first sidewall and the second sidewall are provided with flow channels communicating with the cooling cavity.

[0005] In some possible implementations, the flow channel includes a first flow channel segment disposed on the first sidewall, the number of the first flow channel segments is multiple, and the multiple first flow channel segments are arranged at intervals along a first direction, and each first flow channel segment extends along a second direction perpendicular to the first direction.

[0006] In some possible implementations, the flow channel includes a first flow channel segment disposed on the first sidewall; Wherein, the structural dimensions of the first flow channel section along the first direction are 10μm-20μm; and / or, The structural dimensions of the first flow channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the first flow channel section along a third direction perpendicular to the plane containing the first and second directions are 100μm-200μm.

[0007] In some possible implementations, the chip has a second flow channel segment recessed downwards from the second sidewall of the substrate, the flow channel including the second flow channel segment; or, The chip has multiple thermally conductive protrusions connected to a second sidewall away from the substrate. Each thermally conductive protrusion extends towards the side away from the second sidewall, and the gap between two adjacent thermally conductive protrusions forms a third flow channel segment. The flow channel includes the third flow channel segment; or... The chip has a plurality of second flow channel segments recessed downward from the second sidewall away from the substrate, and the second sidewall is thermally connected to a plurality of thermally conductive protrusions. Each of the thermally conductive protrusions extends toward the side away from the second sidewall. The gap between two adjacent thermally conductive protrusions forms a third flow channel segment. The flow channel includes the second flow channel segment and the third flow channel segment.

[0008] In some possible implementations, a plurality of second flow channel segments are arranged at intervals along a first direction, and each second flow channel segment extends along a second direction perpendicular to the first direction.

[0009] In some possible implementations, the structural dimensions of the second flow channel section along the first direction are 10 μm-20 μm; and / or, The structural dimensions of the second flow channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the second flow channel section along a third direction perpendicular to the plane containing the first and second directions are 5μm-200μm.

[0010] In some possible implementations, the thermally conductive protrusion has a gap between the top wall of the sealing structure and the inner wall of the sealing structure; and / or, The thermally conductive protrusion is provided with a notch; and / or, The plurality of said thermally conductive protrusions are arranged in rows and spaced apart along a first direction, and / or arranged in columns and spaced apart along a second direction perpendicular to the first direction; and / or, Multiple second flow channel sections are arranged at intervals, and the heat-conducting protrusions are provided between two adjacent second flow channel sections.

[0011] In some possible implementations, the thermally conductive protrusion has a structural dimension of 10 μm-20 μm along the first direction; and / or, The thermally conductive protrusion has a structural dimension of 10mm-30mm along the second direction; and / or, The thermally conductive protrusion has a structural dimension of 100μm-200μm along a third direction perpendicular to the plane containing the first and second directions.

[0012] In some possible implementations, the thermally conductive protrusion is cylindrical or rectangular; and / or, The thermally conductive protrusion is made of copper.

[0013] In some possible implementations, a first structural layer is provided between the chip and the thermally conductive bump, and the thermally conductive bump is connected to the chip through the first structural layer.

[0014] In some possible implementations, the first structural layer is made of titanium or a titanium alloy.

[0015] In some possible implementations, the sealing structure further includes a second structural layer disposed between the heat sink and the chip, and the second structural layer is arranged in a ring around the outer periphery of the chip. The heat sink is connected to the chip through the second structural layer, so that the heat sink, the second structural layer and the chip together form the cooling cavity. The heat sink is provided with an inlet and an outlet communicating with the cooling cavity.

[0016] In some possible implementations, the second structural layer is formed of sealant.

[0017] In some possible implementations, the sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

[0018] In some possible implementations, the heat sink includes a manifold and a cover plate stacked in a third direction, and the cover plate is connected to the chip through the second structural layer. The cover plate is provided with a first fluid channel and a second fluid channel. The manifold is provided with an inlet, an outlet, a third fluid channel, and a fourth fluid channel. The inlet is connected to the cooling cavity through the first fluid channel and the third fluid channel, and the outlet is connected to the cooling cavity through the second fluid channel and the fourth fluid channel.

[0019] In some possible implementations, the sealing structure further includes a connecting structure through which the manifold plate and the cover plate are connected.

[0020] In some possible implementations, the connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

[0021] In some possible implementations, the substrate is provided with an annular protrusion arranged around the chip, and a second adhesive layer is provided between the sealing structure and the annular protrusion, the sealing structure being connected to the annular protrusion through the second adhesive layer.

[0022] In some possible implementations, the number of chips is one or more, and each chip is selected from either memory chips or logic chips.

[0023] In some possible implementations, the semiconductor package structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

[0024] A second aspect of this disclosure provides an electronic device including the semiconductor package structure provided in the first aspect above.

[0025] The semiconductor packaging structure provided in this disclosure utilizes the aforementioned technical solution. By connecting a heat sink with a sealing structure to the chip, a cooling cavity is formed between the heat sink and the chip. This arrangement allows for heat exchange between the heat sink and the chip via a cooling medium flowing through the cavity, thereby achieving the goal of cooling the chip. Furthermore, since both the first sidewall of the heat sink facing the chip and the second sidewall of the chip facing away from the substrate are provided with channels (microchannels) communicating with the cooling cavity, the heat exchange area is increased by adding these channels (microchannels) to the inner wall of the cooling cavity. This improves the overall heat exchange efficiency, enabling rapid heat dissipation within the cooling cavity and reducing the risk of localized heat accumulation in the cooling medium, thus enhancing the heat dissipation effect on the chip. Therefore, the semiconductor packaging structure provided in this disclosure improves the heat dissipation effect on the chip, helping to ensure stable and high-performance operation of the chip at a safe temperature, thereby improving chip performance and reliability.

[0026] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0027] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 Cross-sectional view at position AA; Figure 3 yes Figure 1 A partially enlarged schematic diagram of position B in the middle shows that the heat sink has a first flow channel section, the chip has a second flow channel section, and the chip has thermally conductive bumps. Figure 4This is a partial schematic diagram of a semiconductor packaging structure provided in the second embodiment of the present disclosure, wherein a first flow channel section is provided on the heat sink and a second flow channel section is provided on the chip; Figure 5 This is a schematic diagram of the packaging structure provided in related technologies.

[0028] Explanation of reference numerals in the attached figures 1-Substrate; 2-Chip; 210-Memory chip; 220-Logic chip; 3-Sealing structure; 310-Heat sink; 311-Inlet; 312-Outlet; 313-Manifold board; 314-Cover plate; 320-Second structural layer; 330-First fluid channel; 340-Second fluid channel; 350-Third fluid channel; 360-Fourth fluid channel; 370-Connecting structure; 371-First adhesive layer; 372-First channel; 373-Second channel; 374-Connecting bolt; 4-Cooling chamber; 5-Flow channel; 510-First flow channel section; 520-Second flow channel section; 530-Third flow channel section; 6-Thermal conductive protrusion; 7-Bottom filler adhesive; 8-Gap; 9-Notch; 10-First structural layer; 11-Annular protrusion; 12-Second adhesive layer; 13-Intermediate layer; 14-Thermal conductive layer; 15-Liquid cooling plate. Detailed Implementation

[0029] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0030] In this disclosure, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to upper and lower within the space of the semiconductor package structure when it is in use. "Inner" and "outer" refer to inner and outer relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same elements.

[0031] In related technologies, refer to Figure 5As shown, chip 2 is thermally connected to liquid cooling plate 15 through thermal conductive layer 14, so that chip 2 can be indirectly cooled by the cooling medium in liquid cooling plate 15. However, this configuration requires the use of thermal interface material (TIM) at thermal conductive layer 14 to achieve heat exchange between chip 2 and liquid cooling plate 15. As a result, due to the arrangement of the multi-layer heat transfer path of the overall packaging structure, the thermal interface resistance at thermal interface material and other interfaces is significantly increased, resulting in poor heat dissipation effect on chip 2. This leads to an unprecedented increase in heat flux density inside chip 2, which is not conducive to the stable and high-performance operation of chip 2 at a safe temperature.

[0032] Based on this, according to the first aspect of this disclosure, a semiconductor packaging structure is provided, with reference to... Figures 1 to 4 As shown, the semiconductor packaging structure includes a substrate 1, a chip 2, and a sealing structure 3. The chip 2 is disposed on the substrate 1. The sealing structure 3 includes a heat sink 310, which is connected to the chip 2. A cooling cavity 4 is formed between the heat sink 310 and the chip 2 for the cooling medium to flow through and exchange heat with the chip 2. The heat sink 310 forms a portion of the inner wall surface of the cooling cavity 4 facing the first sidewall of the chip 2, and the chip 2 forms a portion of the inner wall surface of the cooling cavity 4 facing away from the substrate 1. Both the first and second sidewalls are provided with flow channels 5 communicating with the cooling cavity 4.

[0033] Through the above-described technical solution, namely the semiconductor packaging structure provided in this disclosure, the heat dissipation cap 310 of the sealing structure 3 is connected to the chip 2, and a cooling cavity 4 is formed between the heat dissipation cap 310 and the chip 2. This arrangement allows heat exchange between the heat dissipation cap 310 and the chip 2 via the cooling medium flowing through the cooling cavity 4, thereby achieving the purpose of cooling the chip 2. Furthermore, since the first sidewall of the heat dissipation cap 310 facing the chip 2 and the second sidewall of the chip 2 facing away from the substrate 1 are both provided with flow channels 5 (microchannels) communicating with the cooling cavity 4, the heat exchange area can be increased by adding flow channels 5 (microchannels) to the inner wall of the cooling cavity 4, thereby improving the overall heat exchange efficiency, enabling rapid heat dissipation within the cooling cavity 4, reducing the risk of localized heat accumulation in the cooling medium within the cooling cavity 4, and improving the heat dissipation effect on the chip 2. Therefore, the semiconductor packaging structure provided in this disclosure can improve the heat dissipation effect on the chip 2, helping to ensure that the chip 2 operates stably and with high performance at a safe temperature, thus improving the performance and reliability of the chip 2.

[0034] Exemplarily, in some possible implementations, references Figures 1 to 4As shown, the flow channel 5 may include a first flow channel section 510 disposed on the first side wall. Thus, by providing the first flow channel section 510 on the first side wall of the heat dissipation cover 310 located in the cooling cavity 4, the flow channel 5 (e.g., the first flow channel section 510) can be provided on the side wall of the sealing structure 3 (e.g., the heat dissipation cover 310) located inside the cooling cavity 4. This can increase the heat exchange area, thereby improving the overall heat exchange efficiency, enabling rapid heat diffusion inside the cooling cavity 4, reducing the risk of local heat accumulation in the cooling medium inside the cooling cavity 4, and improving the heat dissipation effect on the chip 2. This ensures that the chip 2 operates stably and with high performance at a safe temperature, thereby improving the performance and reliability of the chip 2.

[0035] The first flow channel section 510 can be adaptively designed according to actual application requirements. For example, in some possible implementations, refer to... Figures 1 to 4 As shown, there can be multiple first flow channel sections 510, and these multiple first flow channel sections 510 are along a first direction (see reference). Figure 1 The first flow channel sections 510 are arranged at intervals along the left and right directions of the middle drawing, and each first flow channel section 510 is arranged along a second direction perpendicular to the first direction (refer to the direction perpendicular to the first direction). Figure 1 The arrangement extends in the direction shown in the figure. This arrangement can increase the heat exchange area and improve the overall heat exchange efficiency. At the same time, the overall structure is relatively simple and it is convenient to process and prepare the first flow channel section 510 on site.

[0036] It should be noted that the specific shape, structure and dimensions of each of the first flow channel sections 510 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to increase the heat exchange area, improve the overall heat exchange efficiency, realize the rapid diffusion of heat inside the cooling cavity 4, reduce the risk of local heat accumulation in the cooling medium inside the cooling cavity 4, and improve the heat dissipation effect on the chip 2.

[0037] In addition, the specific external shape and structural dimensions of each first flow channel section 510 can be the same to facilitate on-site processing and preparation. It is understood that those skilled in the art can also adapt the specific external shape and structural dimensions of each first flow channel section 510 to be different according to actual application needs. This disclosure does not make specific limitations in this regard.

[0038] Exemplarily, in some implementations, reference is made to Figures 1 to 4 As shown, the first flow channel section 510 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, the first flow channel section 510 along the first direction (refer to...) Figure 1The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0039] Additionally, in some implementations, references Figures 1 to 4 As shown, the first flow channel section 510 is along the second direction (which can be referenced as perpendicular to the direction of flow). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm-30mm. For example, the first flow channel section 510 is along the second direction (which can be referenced to the direction perpendicular to the drawing). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm, 15mm, 20mm, 25mm, 30mm, etc. This disclosure is not limited thereto.

[0040] Furthermore, in some implementations, references Figures 1 to 4 As shown, the first flow channel segment 510 is along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm-200μm. For example, the first flow channel segment 510 has a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. This disclosure is not limited thereto.

[0041] In some possible implementations, refer to Figures 1 to 4 As shown, the specific external structure of each first flow channel section 510 can be constructed as, for example, a rectangular groove, which has a simple overall structure and is easy to process and manufacture. It is understood that the specific external structure of each first flow channel section 510 can also be constructed as, for example, a "V" shaped groove or a semi-circular groove, etc. This disclosure does not make specific limitations in this regard, and those skilled in the art can design it adaptively according to actual application needs.

[0042] Furthermore, each of the first flow channel sections 510 can be manufactured by machining methods such as laser or micro-milling, which are suitable in the art, and will not be described in detail here. In addition, the multiple first flow channel sections 510 can be arranged at equal or unequal intervals, and this disclosure does not make a specific limitation in this regard. Those skilled in the art can design them adaptively according to actual application needs.

[0043] Furthermore, the specific embodiment in which the aforementioned plurality of first flow channel segments 510 are arranged at intervals along the first direction and extend along the second direction is exemplary. In other alternative embodiments not shown, the aforementioned first flow channel segments 510 may also be constructed as, for example, multiple branch flow channel segments formed on the heat dissipation cover 310 and arranged in a "well" shape. This disclosure is not limited to this. The purpose is to increase the heat exchange area, thereby improving the overall heat exchange efficiency, realizing the rapid diffusion of heat inside the cooling cavity 4, reducing the risk of local heat accumulation of the cooling medium inside the cooling cavity 4, and improving the heat dissipation effect on the chip 2. Those skilled in the art can design it adaptively according to actual application requirements.

[0044] In some possible implementations, refer to Figures 1 to 4 As shown, the second sidewall of the chip 2 away from the substrate 1 can be recessed downward to form a second flow channel section 520. The flow channel 5 can include the second flow channel section 520. Thus, by providing the second flow channel section 520 on the second sidewall of the chip 2 located in the cooling cavity 4, the flow channel 5 (e.g., the second flow channel section 520) can be provided on the sidewall of the chip 2 located inside the cooling cavity 4. This can increase the heat exchange area between the cooling medium and the chip 2 located in the cooling cavity 4, which is beneficial to improving the heat dissipation effect of the cooling medium on the chip 2 and achieving the purpose of improving the overall heat exchange efficiency. Furthermore, since the second flow channel section 520 is directly formed on the second sidewall of the chip 2, the cooling medium can directly act on the chip 2, achieving direct contact between the cooling medium and the chip 2 and heat exchange with the chip 2. This can effectively shorten the heat transfer path, facilitate efficient cooling and temperature reduction of the chip 2 by the cooling medium, effectively improve the heat dissipation effect of the cooling medium on the chip 2, and help ensure that the chip 2 can operate stably and with high performance at a safe temperature.

[0045] The second flow channel section 520 can be adaptively designed according to actual application requirements. For example, in some possible implementations, refer to... Figures 1 to 4 As shown, there can be multiple second flow channel sections 520, and these multiple second flow channel sections 520 are along the first direction (see reference). Figure 1 The second flow channel sections 520 are arranged at intervals along the left and right directions of the central image, and each second flow channel section 520 is along a second direction perpendicular to the first direction (refer to the direction perpendicular to the first direction). Figure 1 The arrangement extends in the direction shown in the figure. This arrangement helps to ensure a high heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2, while the overall structure is relatively simple and convenient for on-site processing and fabrication of the second flow channel section 520.

[0046] It should be noted that the specific shape, structure and dimensions of each of the second flow channel sections 520 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to ensure that there is a high heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2.

[0047] In addition, the specific shape and size of each second flow channel section 520 can be the same to facilitate on-site processing. It is understood that those skilled in the art can also adapt the specific shape and size of each second flow channel section 520 to be different according to actual application needs. For example, the shape and size of some second flow channel sections 520 in the high heat area of ​​the chip 2 can be made larger than those of the remaining areas of the chip 2 to ensure a higher heat dissipation effect on the chip 2. This disclosure does not make specific limitations in this regard.

[0048] Exemplarily, in some implementations, reference is made to Figures 1 to 4 As shown, the second flow channel section 520 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, the second flow channel section 520 along the first direction (refer to...) Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0049] Additionally, in some implementations, references Figures 1 to 4 As shown, the second flow channel section 520 is along the second direction (which can be referenced as perpendicular to the direction of flow). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm-30mm. For example, the second flow channel section 520 is along the second direction (refer to the direction perpendicular to the drawing). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm, 15mm, 20mm, 25mm, 30mm, etc. This disclosure is not limited thereto.

[0050] Furthermore, in some implementations, references Figures 1 to 4 As shown, the second flow channel segment 520 is along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can range from 5μm to 200μm. For example, the second flow channel segment 520 has a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 5μm, 20μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, etc. This disclosure is not limited thereto.

[0051] It should be noted that the specific structural dimensions of the second flow channel segment 520 formed on the chip 2 can also be adaptively designed according to different types of chip 2. For example, when there are multiple chips 2 and they include memory chips 210 and logic chips 220, the specific structural dimensions of the corresponding second flow channel segment 520 on the memory chips 210 and logic chips 220 can be adaptively designed according to the actual application requirements of different chips 2. This disclosure will not elaborate further here.

[0052] Additionally, in some implementations, references Figures 1 to 4 As shown, the specific external structure of each second flow channel section 520 can be constructed as, for example, a rectangular groove, which has a simple overall structure and is easy to process and manufacture. It is understood that the specific external structure of each second flow channel section 520 can also be constructed as, for example, a "V" shaped groove or a semi-circular groove, etc. This disclosure does not make specific limitations in this regard, and those skilled in the art can design it adaptively according to actual application needs.

[0053] Furthermore, each of the second flow channel sections 520 can be fabricated using any suitable fabrication process in the art, such as etching or laser micromachining, which will not be elaborated upon here.

[0054] Optionally, in some embodiments, the plurality of second flow channel segments 520 arranged at intervals along the first direction can be arranged at equal intervals. Such an arrangement can improve the uniformity of heat dissipation of the cooling medium in the cooling cavity 4 to the chip 2, ensuring a higher heat dissipation effect. Alternatively, the plurality of second flow channel segments 520 arranged at intervals along the first direction can also be arranged at unequal intervals. For example, some of the second flow channel segments 520 in the areas with higher heat on the chip 2 can be arranged more densely (i.e., the distance between two adjacent second flow channel segments 520 is smaller), while some of the second flow channel segments 520 in the remaining areas with lower heat on the chip 2 can be arranged more dispersedly (i.e., the distance between two adjacent second flow channel segments 520 is larger). This disclosure does not specifically limit this.

[0055] Additionally, it should be noted that the specific embodiment in which the aforementioned second flow channel section 520 includes a plurality of second flow channel sections 520 arranged at intervals along the first direction, and each second flow channel section 520 extends along the second direction, is exemplary. In other alternative embodiments not shown, the aforementioned second flow channel section 520 may also be constructed as, for example, multiple branch flow channel sections formed on the second sidewall of the chip 2 and arranged in a "well" shape. This disclosure is not limited to this. The purpose is to ensure that the cooling medium located in the cooling cavity 4 and the chip 2 have a high heat exchange area through the arrangement of the second flow channel section 520. Those skilled in the art can design it adaptively according to actual application requirements.

[0056] Alternatively, in some other possible implementations, refer to Figures 1 to 4 As shown, the chip 2 has multiple thermally conductive protrusions 6 connected to the second sidewall away from the substrate 1. Each thermally conductive protrusion 6 extends towards the side away from the second sidewall. The gap between two adjacent thermally conductive protrusions 6 forms a third flow channel section 530. The flow channel 5 includes the third flow channel section 530. That is, the sealing structure 3, the chip 2, and the thermally conductive protrusions 6 can be used to jointly define the inner wall surface of the cooling cavity 4. In this way, the heat generated at the chip 2 can be transferred to the thermally conductive protrusions 6 through the setting of the thermally conductive protrusions 6, and the heat can be carried away by the cooling medium located in the cooling cavity 4. This achieves the purpose of cooling the chip 2, which helps to ensure that the chip 2 operates stably and with high performance at a safe temperature, thereby improving the performance and reliability of the chip 2.

[0057] It should be noted that by thermally connecting the thermally conductive protrusion 6 to the second sidewall of the chip 2 away from the substrate 1, the heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2 can be increased, thereby improving the overall heat exchange efficiency. For example, in some possible implementations, the thermally conductive protrusion 6 can extend towards the side away from the second sidewall of the chip 2 and abut against the inner wall surface of the sealing structure 3 (e.g., the heat sink 310 facing the first sidewall of the chip 2). This ensures a high heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2, which is beneficial for improving the heat dissipation effect on the chip 2.

[0058] Additionally, in some implementations, references Figures 1 to 4 As shown, a notch 9 can be provided on the heat-conducting protrusion 6. For example, a notch 9 can be provided on the top wall of the heat-conducting protrusion 6 facing the sealing structure 3. In addition, a notch 9 can also be provided on the side wall of the heat-conducting protrusion 6. In this way, by providing the notch 9, the cooling medium in the cooling cavity 4 can flow through the notch 9 through multiple heat-conducting protrusions 6, which is beneficial to improving heat dissipation efficiency.

[0059] It is understood that the specific embodiment in which the heat-conducting protrusion 6 extends toward the side opposite to the second sidewall of the chip 2 and abuts against the inner wall surface of the sealing structure 3 (e.g., the heat sink 310 toward the first sidewall of the chip 2) is exemplary. For example, in some alternative embodiments, the heat-conducting protrusion 6 toward the top wall of the sealing structure 3 may also have a gap 8 between it and the inner wall of the sealing structure 3. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs, with the aim of improving the heat dissipation effect on the chip 2.

[0060] In addition, the aforementioned multiple heat-conducting protrusions 6 can be arranged in rows and spaced apart along the first direction, and / or arranged in columns and spaced apart along a second direction perpendicular to the first direction. In this way, by setting multiple heat-conducting protrusions 6, it can be ensured that there is a high heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2, which is beneficial to improving the heat dissipation effect on the chip 2.

[0061] The spacing between any two adjacent thermally conductive bumps 6 is not specifically limited in this disclosure. Those skilled in the art can design it adaptively according to actual application requirements. For example, it can be designed according to the power consumption of chip 2. For instance, the spacing between two adjacent thermally conductive bumps 6 can be 1.5 times the thickness of the thermally conductive bump 6 along the first or second direction. In addition, multiple thermally conductive bumps 6 can be arranged in an array, that is, multiple thermally conductive bumps 6 can be arranged at equal intervals. Alternatively, multiple thermally conductive bumps 6 can also be arranged at unequal intervals. For example, some thermally conductive bumps 6 in the high-heat areas of chip 2 can be arranged more densely (i.e., the spacing between two adjacent thermally conductive bumps 6 is smaller), while some thermally conductive bumps 6 in the remaining low-heat areas of chip 2 can be arranged more dispersedly (i.e., the spacing between two adjacent thermally conductive bumps 6 is larger). This disclosure does not specifically limit this.

[0062] Alternatively, in some other possible implementations, refer to Figures 1 to 4 As shown, the chip 2 has multiple second flow channel sections 520 formed by a downward recess in the second sidewall away from the substrate 1, and multiple heat-conducting protrusions 6 are thermally connected to the second sidewall. Each heat-conducting protrusion 6 extends towards the side away from the second sidewall. The gap between two adjacent heat-conducting protrusions 6 forms a third flow channel section 530. The flow channel 5 includes the second flow channel section 520 and the third flow channel section 530. This arrangement can also ensure that the cooling medium in the cooling cavity 4 has a high heat exchange area with the chip 2, which is beneficial to improving the heat dissipation effect of the chip 2.

[0063] It is understood that, based on the first flow channel section 510 provided on the first side wall of the cooling cavity 4 of the heat sink 310, a second flow channel section 520 may be provided only on the chip 2; or, based on the first flow channel section 510 provided on the first side wall of the cooling cavity 4 of the heat sink 310, a thermally conductive protrusion 6 may be provided only on the chip 2, so that a third flow channel section 530 is formed through the gap between two adjacent thermally conductive protrusions 6; or, based on the first flow channel section 510 provided on the first side wall of the cooling cavity 4 of the heat sink 310, both the first flow channel section 510 and the thermally conductive protrusion 6 may be provided on the chip 2. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to increase the heat exchange area by adding a flow channel 5 inside the cooling cavity 4, thereby improving the overall heat exchange efficiency and ensuring that the chip 2 operates stably and with high performance at a safe temperature.

[0064] Furthermore, it should be noted that when, for example, chip 2 is simultaneously provided with a second flow channel section 520 and a thermally conductive protrusion 6, multiple second flow channel sections 520 can be arranged at intervals, and a thermally conductive protrusion 6 can be provided between two adjacent second flow channel sections 520. This arrangement ensures that the cooling medium in the cooling cavity 4 has a high heat exchange area with chip 2, which is beneficial to improving the heat dissipation effect on chip 2. In addition, when multiple first flow channel sections 510 are provided on the first side wall of the cooling cavity 4 on the heat sink 310, and multiple second flow channel sections 520 are provided on chip 2, at least some of the second flow channel sections 520 can be arranged opposite to the corresponding first flow channel sections 510.

[0065] The specific shape, number, location, and dimensions of the aforementioned heat-conducting protrusions 6 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application requirements. The purpose is to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 4 and the heat-conducting protrusions 6, so as to achieve rapid cooling of the chip 2.

[0066] In addition, the specific shape and size of the multiple heat-conducting bumps 6 can be the same to facilitate on-site processing. It is understood that those skilled in the art can also adapt the specific shape and size of the multiple heat-conducting bumps 6 to be different according to actual application needs. For example, the shape and size of some heat-conducting bumps 6 in the high-heat area of ​​the chip 2 can be made larger than those of some heat-conducting bumps 6 in the remaining area of ​​the chip 2, so as to ensure a higher heat dissipation effect on the chip 2. This disclosure does not make specific limitations in this regard.

[0067] Exemplarily, in some implementations, reference is made to Figures 1 to 4As shown, the thermally conductive protrusion 6 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, the thermally conductive protrusion 6 along the first direction (refer to...) Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0068] Additionally, in some implementations, references Figures 1 to 4 As shown, the thermally conductive protrusion 6 is along the second direction (which can be referenced as perpendicular to the direction of the second direction). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm-30mm. For example, the thermally conductive protrusion 6 along the second direction (which can be referenced to the direction perpendicular to the drawing) Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm, 15mm, 20mm, 25mm, 30mm, etc. This disclosure is not limited thereto.

[0069] Furthermore, in some implementations, references Figures 1 to 4 As shown, the heat-conducting protrusion 6 is along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm-200μm. For example, the thermally conductive protrusion 6 can be located in a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. This disclosure is not limited thereto.

[0070] In some possible implementations, refer to Figures 1 to 4 As shown, the specific external structure of the thermally conductive protrusion 6 can be constructed as, for example, a rectangle, so as to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 4 and the thermally conductive protrusion 6, thereby achieving the purpose of rapid cooling of the chip 2, and having the advantages of simple overall structure and easy processing and fabrication.

[0071] Alternatively, in other alternative embodiments, the specific external shape of the thermally conductive protrusion 6 can also be constructed as, for example, a cylindrical shape or other external shape. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application requirements. The purpose is to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 4 and the thermally conductive protrusion 6, so as to achieve rapid cooling of the chip 2.

[0072] In order to ensure that the thermally conductive bump 6 has high thermal conductivity so that the heat generated at the chip 2 can be quickly transferred to the thermally conductive bump 6 and then quickly removed by the cooling medium, in some possible embodiments, the thermally conductive bump 6 can be made of copper. This arrangement can ensure that the thermally conductive bump 6 has high thermal conductivity, so as to achieve the goal of quickly transferring the heat generated at the chip 2 to the thermally conductive bump 6 and then quickly removing the heat by the cooling medium. This is beneficial to improving the cooling effect of the chip 2. Furthermore, using copper to prepare the thermally conductive bump 6 is also convenient for on-site processing, easy to process and highly reliable.

[0073] It is understood that in other alternative embodiments, the material of the above-mentioned heat-conducting protrusion 6 may also be a material with thermal conductivity, such as aluminum or aluminum alloy. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the heat generated at the chip 2 to be transferred to the heat-conducting protrusion 6, and to be directly acted on by the cooling medium located in the cooling cavity 4 to remove the heat, thereby achieving the purpose of cooling the chip 2.

[0074] In some possible implementations, refer to Figure 1 As shown, a first structural layer 10 can be provided between the chip 2 and the thermally conductive bump 6. The thermally conductive bump 6 is connected to the chip 2 through the first structural layer 10. This arrangement can ensure that the thermally conductive bump 6 can be stably connected to the chip 2, which is easy to process and has high reliability. It is beneficial to ensure efficient and stable cooling of the chip 2, and helps to improve the performance and reliability of the chip 2.

[0075] For example, the first structural layer 10 can be a coating structure coated on the second sidewall of the chip 2, or alternatively, the first structural layer 10 can be a connecting film structure disposed on the second sidewall of the chip 2. This disclosure does not specifically limit this, and those skilled in the art can design it adaptively according to actual application needs.

[0076] It should be noted that, in this disclosure, the first structural layer 10 is described along a third direction (see reference). Figure 1 The thickness dimension (in the vertical direction of the middle drawing) is not specifically limited. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that the heat-conducting protrusion 6 can be stably connected to the chip 2, and at the same time, to enable the heat generated at the chip 2 to be quickly transferred to the heat-conducting protrusion 6 and then quickly carried away by the cooling medium.

[0077] Furthermore, the specific fabrication process of the first structural layer 10, for example, being a coating structure coated on the second sidewall of the chip 2 or a connecting thin film structure disposed on the second sidewall of the chip 2, can be adapted by referring to existing processing and fabrication processes, and this disclosure will not elaborate further on this.

[0078] Furthermore, since the cooling medium can directly exchange heat with the heat-conducting protrusions 6 disposed in the cooling cavity 4 after flowing through the cooling cavity 4, and since the thickness of the first structural layer 10 is thinner than the thickness of the heat-conducting layer 14 and the liquid cooling plate 15 in the related art, this disclosure can effectively shorten the heat transfer path and improve the heat dissipation effect of the cooling medium on the chip 2 compared with the multi-layer heat transfer path cooling method in the related art.

[0079] It should be noted that, for example, when the chip 2 is provided with both the second flow channel section 520 and the thermally conductive bump 6, the first structural layer 10 described above can be provided on the chip 2 in advance, and then the second flow channel section 520 and the thermally conductive bump 6 described above can be provided on the chip 2 to facilitate on-site processing and fabrication.

[0080] In some possible implementations, the first structural layer 10 can be made of titanium. This arrangement allows the first structural layer 10, made of titanium, to be placed on the chip 2, so that the aforementioned thermally conductive bumps 6 can be electroplated on the chip 2. This ensures that the thermally conductive bumps 6 can be stably connected to the chip 2, and at the same time, it can also quickly transfer the heat generated at the chip 2 to the thermally conductive bumps 6 and quickly remove the heat through the cooling medium, thereby achieving the purpose of efficient and stable cooling of the chip 2.

[0081] It is understood that in other alternative embodiments, the material of the first structural layer 10 may also be, for example, titanium alloy. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that the thermally conductive protrusion 6 can be stably connected to the chip 2, and at the same time, the chip 2 can be cooled efficiently and stably.

[0082] It should be noted that those skilled in the art can adaptively design the specific structure of the flow channel 5 according to actual application requirements. For example, the flow channel 5 may include, but is not limited to, at least one of, such as the first flow channel section 510, the second flow channel section 520, and the third flow channel section 530. That is, it can be understood that the inner wall surface of the cooling cavity 4 may only have the first flow channel section 510 connected to the cooling cavity 4, or the inner wall surface of the cooling cavity 4 may only have the second flow channel section 520 connected to the cooling cavity 4, or the inner wall surface of the cooling cavity 4 may only have the third flow channel section 530 connected to the cooling cavity 4, or... Alternatively, the inner wall of the cooling chamber 4 may be provided with a first flow channel section 510 and a second flow channel section 520 communicating with the cooling chamber 4, or the inner wall of the cooling chamber 4 may be provided with a first flow channel section 510 and a third flow channel section 530 communicating with the cooling chamber 4, or the inner wall of the cooling chamber 4 may be provided with a second flow channel section 520 and a third flow channel section 530 communicating with the cooling chamber 4, or the inner wall of the cooling chamber 4 may be provided with a first flow channel section 510, a second flow channel section 520 and a third flow channel section 530 communicating with the cooling chamber 4. This disclosure does not make specific limitations in this regard.

[0083] In some possible implementations, refer to Figure 1 As shown, the sealing structure 3 may further include a second structural layer 320. The second structural layer 320 is disposed between the heat sink 310 and the chip 2, and the second structural layer 320 is arranged in a ring around the outer periphery of the chip 2. The heat sink 310 is connected to the chip 2 through the second structural layer 320, so that the heat sink 310, the second structural layer 320 and the chip 2 together form a cooling cavity 4. This arrangement allows the heat sink 310 to be stably connected to the chip 2 through the second structural layer 320. Since the second structural layer 320 is constructed to be arranged in a ring around the outer periphery of the chip 2, the cooling cavity 4 formed between the heat sink 310, the second structural layer 320 and the chip 2 can be guaranteed to have high sealing performance and reliability. This is beneficial to ensure that the cooling medium located in the cooling cavity 4 can efficiently and stably cool and reduce the temperature of the chip 2.

[0084] Additionally, the heat dissipation cover 310 may be provided with an inlet 311 and an outlet 312 connected to the cooling chamber 4, so as to facilitate the replenishment and discharge of cooling medium, for example, within the cooling chamber 4. For instance, the inlet 311 and outlet 312 of the sealing structure 3 may be connected to a cooling medium supply device (not shown), thereby achieving the purpose of replenishing and discharging cooling medium within the cooling chamber 4. The cooling medium supply device (not shown) can be adaptively designed with reference to any suitable cooling medium supply device in the art, and will not be described in detail here.

[0085] It should be noted that the cooling medium mentioned above may include, but is not limited to, deionized water. Since deionized water has weak conductivity and weak corrosiveness, it can safely and efficiently cool down the chip 2. This disclosure is not limited to this. For example, the cooling medium mentioned above may also include coolants with weak conductivity and weak corrosiveness, such as electronic fluorinated liquid. The purpose is to achieve safe and efficient cooling down of the chip 2 through the cooling medium. Those skilled in the art can design it adaptively according to actual application requirements.

[0086] In some possible implementations, the second structural layer 320 can be formed of sealant. This arrangement, since the sealant is compressible and stretchable, can cover the effects of warping during the chip 2 packaging process. This not only improves the overall reliability of the packaging structure, but also ensures that, for example, the heat sink 310 is stably connected to the chip 2, and ensures that the cooling cavity 4 has high sealing performance, thereby achieving efficient and stable cooling of the chip 2.

[0087] The sealant can be adaptively designed according to actual application requirements. For example, in some possible embodiments, the sealant material can be polydimethylsiloxane (PDMS) or epoxy-based negative photoresist (SU-8). This arrangement can ensure that, for example, the heat sink 310 is stably connected to the chip 2, while also ensuring that the cooling cavity 4 has high sealing performance, thereby achieving the purpose of stable and efficient cooling of the chip 2. This disclosure is not limited thereto.

[0088] In addition, the thickness of the sealant along the first or second direction can be no less than 500 μm, and the height of the sealant along the third direction can be, for example, 250 μm-300 μm, so as to ensure that the sealant has high structural strength while improving the overall reliability of the encapsulation structure.

[0089] The heat sink 310 can be adaptively designed according to actual application requirements; for example, in some possible implementations, refer to... Figure 1 As shown, the heat sink 310 may include components along a third direction (see reference). Figure 1In the diagram (top to bottom), a manifold plate 313 and a cover plate 314 are stacked, with the cover plate 314 connected to the chip 2 via a second structural layer 320. The cover plate 314 is provided with a first fluid channel 330 and a second fluid channel 340. The manifold plate 313 is provided with an inlet 311, an outlet 312, a third fluid channel 350, and a fourth fluid channel 360. The inlet 311 is connected to the cooling chamber 4 via the interconnected first fluid channel 330 and the third fluid channel 350, and the outlet 312 is connected to the cooling chamber 4 via the interconnected second fluid channel 340 and the fourth fluid channel 360. That is, the first fluid channel 330 and the third fluid channel 350 are interconnected. The cooling chamber 4 is configured to form an inlet channel communicating with the inlet 311, and the second fluid channel 340 and the fourth fluid channel 360 are connected to form an outlet channel communicating with the outlet 312. This arrangement facilitates the replenishment and discharge of the cooling medium in the cooling chamber 4. Furthermore, by constructing the heat sink 310 as including a stacked manifold plate 313 and a cover plate 314, and by fabricating interconnected fluid channels on the manifold plate 313 and the cover plate 314 respectively, the overall structure of the heat sink 310 can be simplified, the complexity of the heat sink 310 can be reduced, and the heat sink 310 (e.g., manifold plate 313 and cover plate 314) can be easily fabricated on-site.

[0090] In this disclosure, the specific arrangement of the fluid channels (such as the first fluid channel 330, the second fluid channel 340, the third fluid channel 350 and the fourth fluid channel 360) on the manifold plate 313 and the cover plate 314 is not specifically limited. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to facilitate the replenishment and discharge of the cooling medium in the cooling chamber 4.

[0091] Furthermore, considering the need to ensure a high level of connection reliability between the manifold plate 313 and the cover plate 314, in some possible implementations, reference is made to... Figure 1 As shown, the sealing structure 3 may also include a connecting structure 370, through which the manifold plate 313 and the cover plate 314 are connected. This arrangement enables a stable connection between the manifold plate 313 and the cover plate 314 via the connecting structure 370, which is highly reliable and also facilitates the assembly and connection of the manifold plate 313 and the cover plate 314 on site.

[0092] The connection structure 370 can be arranged in any suitable manner; for example, in some possible embodiments, refer to... Figure 1As shown, the connection structure 370 may include a first adhesive layer 371 disposed between the manifold plate 313 and the cover plate 314. The first adhesive layer 371 is provided with a first cavity 372 connecting the first fluid cavity 330 and the third fluid cavity 350, and a second cavity 373 connecting the second fluid cavity 340 and the fourth fluid cavity 360. In this way, the first adhesive layer 371 can achieve a stable connection between the manifold plate 313 and the cover plate 314, while also ensuring a high degree of sealing between the first fluid cavity 330 and the third fluid cavity 350 connected by the first cavity 372, and between the second fluid cavity 340 and the fourth fluid cavity 360 connected by the second cavity 373. This reduces the risk of cooling medium leakage and facilitates the replenishment and discharge of cooling medium in the cooling chamber 4.

[0093] Alternatively, in some implementations, refer to Figure 1 As shown, the connection structure 370 may also include a connecting bolt 374. The manifold plate 313 and the cover plate 314 are connected by the connecting bolt 374. This arrangement allows for a stable connection between the manifold plate 313 and the cover plate 314, and the overall structure is simple and easy to assemble on site.

[0094] It should be noted that the above-mentioned connection structure 370 may be constructed to include only the first adhesive layer 371, or alternatively, the above-mentioned connection structure 370 may be constructed to include only the connecting bolt 374, or alternatively, the above-mentioned connection structure 370 may include both the first adhesive layer 371 and the connecting bolt 374. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to achieve a stable connection and fixation between the manifold plate 313 and the cover plate 314.

[0095] Furthermore, this disclosure does not specifically limit the specific structure of the first adhesive layer 371 and the connecting bolt 374. For example, the first adhesive layer 371 can be formed by any suitable sealant or structural adhesive in the art, the purpose of which is to ensure a stable connection between the manifold plate 313 and the cover plate 314 through the first adhesive layer 371. Similarly, the connecting bolt 374 can be adapted to any suitable bolt structure in the art, the purpose of which is to ensure a stable connection between the manifold plate 313 and the cover plate 314 through the connecting bolt 374. This disclosure is not limited thereto.

[0096] Furthermore, it should be noted that the specific embodiment in which the heat dissipation cover 310 may include a manifold plate 313 and a cover plate 314 stacked along a third direction is exemplary. For example, in some alternative embodiments not shown, the heat dissipation cover 310 may also be constructed as a single cover plate structure, for example, not shown. The single cover plate structure may together with the second structural layer 320 and the chip 2 to form the cooling cavity 4. The single cover plate structure may also be provided with the inlet 311, the outlet 312, a fluid channel that connects the inlet 311 to the cooling cavity 4, and a fluid channel that connects the outlet 312 to the cooling cavity 4, so as to achieve efficient cooling of the chip 2. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs.

[0097] In some possible implementations, refer to Figure 1 As shown, an annular protrusion 11 can be provided on the substrate 1, surrounding the chip 2. A second adhesive layer 12 is provided between the sealing structure 3 and the annular protrusion 11. The sealing structure 3 is connected to the annular protrusion 11 through the second adhesive layer 12. With this arrangement, by connecting the heat dissipation cover 310 (e.g., cover plate 314) of the sealing structure 3 to the annular protrusion 11 connected to the substrate 1, not only can the connection reliability of the heat dissipation cover 310 be improved, but the structural strength of the substrate 1 can also be enhanced. This reduces the possibility of warping risk of the substrate 1 due to the difference in thermal expansion coefficient during, for example, the packaging process, which helps to improve the packaging yield and the overall reliability of the packaging structure.

[0098] This disclosure does not specifically limit the specific shape, structure, and material of the substrate 1, the specific structure, structure, and material of the annular protrusion 11, or the connection and fixing method between the substrate 1 and the annular protrusion 11. Those skilled in the art can design them adaptively according to actual application needs. This disclosure will not elaborate further here. For example, the substrate 1 and the annular protrusion 11 can be fixedly connected by a third adhesive layer.

[0099] Additionally, in some possible implementations, refer to Figures 1 to 4 As shown, the number of chips 2 can be one or more, and each chip 2 is selected from either the memory chip 210 or the logic chip 220. This arrangement allows for the adaptive design of the number and type of chips 2 according to the usage requirements of, for example, the package structure, to meet the application layout requirements in scenarios with complex package structures, thereby improving the performance and applicability of the package structure. Furthermore, since the chip 2 can be safely and efficiently cooled by the cooling medium located within the cooling cavity 4, it can be ensured that the chip 2 can still operate stably and with high performance at a safe temperature even under high power consumption, resulting in high reliability.

[0100] Chip 2 may include a silicon chip, that is, it is understood that chip 2 may be made of, but is not limited to, silicon. Thus, by opening flow channels 5 (e.g., second flow channel segment 520) on chip 2 made of silicon, the chip 2 can be cooled by a cooling medium, which helps to ensure that chip 2 operates stably and with high performance at a safe temperature, thereby improving the performance and reliability of chip 2.

[0101] Understandably, reference Figure 2 As shown, multiple chips 2 can be arranged in a row along the first direction, or alternatively, multiple chips 2 can be arranged in a column along the second direction, or alternatively, multiple chips 2 can be arranged in a row along the first direction and multiple chips in a column along the second direction at the same time. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs.

[0102] It should be noted that this disclosure does not specifically limit the specific structure, specific arrangement position on the substrate 1, or specific number of the aforementioned chips 2 (e.g., memory chip 210 and logic chip 220). Those skilled in the art can adapt the design according to actual application requirements. For example, the aforementioned memory chip 210 may include, but is not limited to, high-bandwidth memory chips (HBM), and the aforementioned logic chip 220 may include, but is not limited to, system-on-a-chip (SOC). This disclosure is not limited to these. Its purpose is to meet the application arrangement requirements in scenarios with complex packaging structures, and to improve the performance and applicability of the packaging structure.

[0103] Furthermore, in some embodiments not shown, when the number of chips 2 is, for example, one, the heat sink 310 may be provided with one of the aforementioned inlet 311 and outlet 312. And when the heat sink 310 is connected to the chip 2 via the second structural layer 320, so that the aforementioned cooling cavity 4 is formed between the heat sink 310, the second structural layer 320, and the chip 2, the fluid channels provided on the heat sink 310 (e.g., the first fluid channel 330, the second fluid channel 340, the third fluid channel 350, and the fourth fluid channel 360, etc.) can be adaptively designed as one or more, i.e. Each inlet 311 can be connected to the cooling chamber 4 through a corresponding fluid channel, or each inlet 311 can be connected to the cooling chamber 4 simultaneously through multiple fluid channels. Similarly, each outlet 312 can be connected to the cooling chamber 4 through a corresponding fluid channel, or each outlet 312 can be connected to the cooling chamber 4 simultaneously through multiple fluid channels. This disclosure does not make specific limitations in this regard. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the replenishment and discharge of cooling medium in the cooling chamber 4 so as to achieve cooling and temperature reduction of the chip 2.

[0104] Furthermore, in some possible implementations, when the number of chips 2 is arranged in multiples, the heat sink 310 may also be provided with one of the aforementioned inlet 311 and outlet 312. Multiple second structural layers 320 may be adaptively arranged corresponding to the number of chips 2, and each second structural layer 320 may be arranged in a ring around the outer periphery of the corresponding chip 2 between the chip 2 and the heat sink 310. This allows a cooling cavity 4 to be formed between each chip 2, each second structural layer 320, and the heat sink 310 for the cooling medium to flow through and exchange heat with the corresponding chip 2. When multiple cooling cavities 4 are designed, the heat sink 310 is provided with... When the inlet 311 is connected to one of the multiple cooling chambers 4, the inlet 311 can be connected to one of the multiple cooling chambers 4 through one or more fluid channels on the heat sink 310. Similarly, when the outlet 312 on the heat sink 310 is connected to one of the multiple cooling chambers 4, the outlet 312 can be connected to one of the multiple cooling chambers 4 through one or more fluid channels on the heat sink 310. This disclosure is not limited to this. Its purpose is to enable the simultaneous replenishment and discharge of cooling medium in multiple cooling chambers 4, so as to simultaneously cool and reduce the temperature of multiple chips 2.

[0105] In some possible implementations, refer to Figure 1As shown, the semiconductor packaging structure may also include an interposer 13 disposed between the chip 2 and the substrate 1. The chip 2 is connected to the substrate 1 through the interposer 13. In this way, by integrating one or more chips 2 on the interposer 13, high bandwidth and low latency data interconnection can be achieved, achieving the purpose of high-density interconnection of the overall packaging structure, which is conducive to meeting the high performance design requirements of the packaging structure.

[0106] It should be noted that one or more chips 2 can be integrated onto the interposer layer 13, for example, via a top-mount or flip-chip configuration. Furthermore, micro-bumps on the chip 2 can form signal connections with corresponding pads on the interposer layer 13. This disclosure does not impose specific limitations on this; those skilled in the art can adapt the design according to actual application requirements, with the aim of achieving signal connections between the chip 2 and the interposer layer 13. Additionally, the specific design of the chip 2 integrated onto the interposer layer 13 can be adapted by referring to existing technologies such as CoWoS (Chip-on-Wafer-on-Substrate) packaging structures, which will not be elaborated upon here.

[0107] In addition, the aforementioned interposer 13 may include, but is not limited to, a silicon interposer, so that when one or more chips 2 are integrated on the interposer 13, high bandwidth and low latency data interconnection can be achieved, thereby achieving the purpose of high-density interconnection of the overall package structure.

[0108] Furthermore, an underfill 7 can be provided between the aforementioned interposer 13 and the substrate 1 to fill the gap between the interposer 13 and the substrate 1. This arrangement can improve the connection reliability between the interposer 13 and the substrate 1, and also isolate air, reduce the risk of surface oxidation, and help extend the overall service life of the packaging structure. This disclosure is not limited thereto.

[0109] According to a second aspect of this disclosure, an electronic device is provided, comprising the semiconductor packaging structure provided in the first aspect. Furthermore, the electronic device also possesses all the beneficial effects of the aforementioned semiconductor packaging structure, which will not be elaborated further herein.

[0110] In some possible implementations, the aforementioned electronic devices may include, but are not limited to, general-purpose computing devices or professional computing devices, such as computers, mobile phones, tablets, workstations, smartwatches, AI servers, cloud computing servers, data center equipment, etc.

[0111] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0112] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0113] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; The chip is disposed on the substrate; as well as The sealing structure includes a heat sink, which is connected to the chip, and a cooling cavity is formed between the heat sink and the chip for a cooling medium to flow through and exchange heat with the chip. The heat dissipation cover forms a portion of the inner wall surface of the cooling cavity on the first sidewall facing the chip, and the chip forms a portion of the inner wall surface of the cooling cavity on the second sidewall facing away from the substrate. Both the first sidewall and the second sidewall are provided with flow channels communicating with the cooling cavity.

2. The semiconductor packaging structure according to claim 1, characterized in that, The flow channel includes a first flow channel segment disposed on the first sidewall. There are multiple first flow channel segments, and the multiple first flow channel segments are arranged at intervals along a first direction. Each first flow channel segment extends along a second direction perpendicular to the first direction.

3. The semiconductor packaging structure according to claim 1, characterized in that, The flow channel includes a first flow channel segment disposed on the first sidewall; Wherein, the structural dimensions of the first flow channel section along the first direction are 10μm-20μm; and / or, The structural dimensions of the first flow channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the first flow channel section along a third direction perpendicular to the plane containing the first and second directions are 100μm-200μm.

4. The semiconductor packaging structure according to claim 1, characterized in that, The chip has a second flow channel segment formed by a downward inward recess on the second sidewall away from the substrate, and the flow channel includes the second flow channel segment; or, The chip has multiple thermally conductive protrusions connected to a second sidewall away from the substrate. Each thermally conductive protrusion extends towards the side away from the second sidewall, and the gap between two adjacent thermally conductive protrusions forms a third flow channel segment. The flow channel includes the third flow channel segment; or... The chip has a plurality of second flow channel segments recessed downward from the second sidewall away from the substrate, and the second sidewall is thermally connected to a plurality of thermally conductive protrusions. Each of the thermally conductive protrusions extends toward the side away from the second sidewall. The gap between two adjacent thermally conductive protrusions forms a third flow channel segment. The flow channel includes the second flow channel segment and the third flow channel segment.

5. The semiconductor packaging structure according to claim 4, characterized in that, Multiple second flow channel segments are arranged at intervals along the first direction, and each second flow channel segment extends along a second direction perpendicular to the first direction.

6. The semiconductor packaging structure according to claim 4, characterized in that, The structural dimensions of the second flow channel section along the first direction are 10μm-20μm; and / or, The structural dimensions of the second flow channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the second flow channel section along a third direction perpendicular to the plane containing the first and second directions are 5μm-200μm.

7. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusion faces a gap between the top wall of the sealing structure and the inner wall of the sealing structure; and / or, The thermally conductive protrusion is provided with a notch; and / or, The plurality of said thermally conductive protrusions are arranged in rows and spaced apart along a first direction, and / or arranged in columns and spaced apart along a second direction perpendicular to the first direction; and / or, Multiple second flow channel sections are arranged at intervals, and the heat-conducting protrusions are provided between two adjacent second flow channel sections.

8. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusion has a structural dimension of 10μm-20μm along the first direction; and / or, The thermally conductive protrusion has a structural dimension of 10mm-30mm along the second direction; and / or, The thermally conductive protrusion has a structural dimension of 100μm-200μm along a third direction perpendicular to the plane containing the first and second directions.

9. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusions are cylindrical or rectangular; and / or, The thermally conductive protrusion is made of copper.

10. The semiconductor packaging structure according to claim 4, characterized in that, A first structural layer is provided between the chip and the thermally conductive bump, and the thermally conductive bump is connected to the chip through the first structural layer.

11. The semiconductor packaging structure according to claim 10, characterized in that, The first structural layer is made of titanium or a titanium alloy.

12. The semiconductor packaging structure according to any one of claims 1-11, characterized in that, The sealing structure further includes a second structural layer, which is disposed between the heat sink and the chip, and the second structural layer is arranged in a circle around the outer periphery of the chip. The heat sink is connected to the chip through the second structural layer, so that the heat sink, the second structural layer and the chip together form the cooling cavity. The heat sink is provided with an inlet and an outlet communicating with the cooling cavity.

13. The semiconductor packaging structure according to claim 12, characterized in that, The second structural layer is formed of sealant.

14. The semiconductor packaging structure according to claim 13, characterized in that, The sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

15. The semiconductor packaging structure according to claim 12, characterized in that, The heat dissipation cover includes a manifold plate and a cover plate stacked in a third direction, and the cover plate is connected to the chip through the second structural layer. The cover plate is provided with a first fluid channel and a second fluid channel. The manifold plate is provided with an inlet, an outlet, a third fluid channel and a fourth fluid channel. The inlet is connected to the cooling cavity through the first fluid channel and the third fluid channel, and the outlet is connected to the cooling cavity through the second fluid channel and the fourth fluid channel.

16. The semiconductor packaging structure according to claim 15, characterized in that, The sealing structure also includes a connecting structure, through which the manifold plate and the cover plate are connected.

17. The semiconductor packaging structure according to claim 16, characterized in that, The connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

18. The semiconductor packaging structure according to claim 1, characterized in that, The substrate has an annular protrusion arranged around the chip, and a second adhesive layer is disposed between the sealing structure and the annular protrusion. The sealing structure is connected to the annular protrusion through the second adhesive layer.

19. The semiconductor packaging structure according to claim 1, characterized in that, The number of chips is one or more, and each chip is selected from either memory chips or logic chips.

20. The semiconductor packaging structure according to claim 1 or 19, characterized in that, The semiconductor packaging structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

21. An electronic device, characterized in that, Includes the semiconductor packaging structure described in any one of claims 1-20.

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