Circuit arrangement for signal recording and generation and method for operating this circuit arrangement

Abstract

Circuit arrangement (CA) for signal recording and generation, with at least one timer module (TM) for providing a time base to a plurality of time control modules (TC1 ... TCx) connected thereto, and with a time routing unit (TRU) which is connected to the said modules (TM, TC1 ... TCx) and their signals for interconnecting them.

Description

State of the art

[0001] The present invention relates to a circuit arrangement for signal recording and generation according to claim 1 and to a method for operating this circuit arrangement according to claim 10.

[0002] Such circuits can be implemented, for example, as timer modules in microcontrollers. These modules are designed as individual components or peripheral modules of the controller, providing more or less powerful functions for signal acquisition and generation in a time-dependent manner based on one or more clock cycles.

[0003] Today, various concepts are used to implement timers in microcontrollers. A basic distinction can be made between complex and less complex implementations.

[0004] The MTU (Multi-function Timer pulse Unit) of the Renesas™ controller SH7741 - HD6417641, for example, falls into the category of less complex timers. This offers the user five timing units connected to 16 I / O pins. Timing units are modules that change their internal state, such as a counter, store times from one or more time bases, and / or output signal waveforms depending on one or more clocks and / or input signals. The MTU can, for example, evaluate eight clock sources and record patterns. In addition, a PWM (Pulse Width Modulated) signal of up to 12 phases can be generated. PWM signals are input or output signals that change their signal level after specific signal durations, which can be determined, among other things, by the timing units. With a 12-phase PWM signal, for example, up to 12 signal levels of different lengths are active on one line.With these components, only limited timer functions can be represented on a few I / O pins, which makes the controllers cost-effective but requires a lot of software interaction to implement complex applications.

[0005] In addition to these simple timer components, there are more complex components, such as the eTPU (Enhanced Time Processing Unit) from Freescale™ and the GPTA (General Purpose Timer Array) from Infineon. In addition to dedicated timer hardware, the eTPU features a programmable microprocessor. The eTPU has 32 timing units equipped with dedicated hardware for signal acquisition and generation. Each channel is connected to dedicated I / O pins. Freescale expands its resources by doubling the entire unit of 32 timing units along with the microprocessor. Another concept for a complex timer component is the GPTA. This represents a pure hardware implementation of a timer component. The control software runs either on the TriCore™ microcontroller or its coprocessor, the PCP (Peripheral Control Processor).In addition to hardware for signal acquisition and generation, the GPTA has modules for filtering and generating digital clocks, and the individual units can work with up to 8 clock sources. The GPTA units are divided into 32 GTCs (Global Timer Cells) and 63 LTCs (Local Timer Cells), each of which is arranged in an array. In an array, the elements are arranged one after the other and can each communicate with their predecessor and successor. The first element in an array can only communicate with its successor, and the last element only with its predecessor. GTCs are based on two global 24-bit timebases and can be connected to their respective neighbors in the array and to I / O pins. The assignment of I / O pins and GTCs is done via a multiplexer circuit. Multiplexers are networks that switch one or more input signals to one or more output signals depending on control lines.This allows each GTC to be connected to any I / O pin. The LTCs are 16-bit based and, unlike GTCs, also respond to the eight clock sources. The LTCs can receive and compare signals, and act as counters. The LTCs also control I / O pins via a multiplexer.

[0006] US 6,813,674 B1 discloses a FIFO interface, US 2004 / 0107323 A1 discloses a multiprocessor system, WO 89 / 06011 discloses interlocking management, and US 2004 / 0148153 A1 discloses memory rewinding and reconstruction for a hardware emulator.

[0007] The simpler timer components are inexpensive to implement due to their limited functionality, but require a lot of computing power from the microcontroller to implement complex functionality. The more complex timer components, on the other hand, are expensive and have limited scalability. For example, Freescale doubles the entire eTPU, and Infineon doubles the entire GPTA or LTC array to make more resources available. This can lead to some resources being underutilized. In the eTPU, the I / O pins are also assigned to dedicated timing units. The GPTA circumvents this limitation by multiplexing the I / O pins to the GTCs and LTCs. However, this implementation requires a lot of logic resources. Furthermore, due to their geographical arrangement in an array, the GTCs and LTCs can only communicate directly with adjacent cells, for example to generate a complex PWM signal. Disclosure of the invention

[0008] It is an object of the present invention to provide a circuit arrangement for signal recording and generation which allows high scalability, communication flexibility and processing speed, and which can also be implemented simply and cost-effectively.

[0009] This object is achieved on the device side by a circuit arrangement which comprises at least one timer module for providing a time base to a plurality of time control modules connected thereto, and a time routing unit which is connected to interconnect said modules and their signals.

[0010] The term "signal" refers to any type of representation of information through the value or value progression of a physical quantity. The term "data," used below, however, refers to the elements of this information represented in a recognizable form that can be processed in systems.

[0011] A key aspect of the circuit arrangement according to the invention is its flexible connection structure. The central element of this structure is the time routing unit, or router, to which modules can be flexibly connected. The router interconnects the modules and their signals. Since the number of modules can be varied depending on requirements, particularly fine-grained scalability of the circuit is possible. Furthermore, it allows I / O pins and time control units to be interconnected as desired without the need for a resource-intensive multiplexer circuit. Unlike the GPTA, the multiplexer for controlling the I / O pins can be replaced by the router. The individual modules can then communicate flexibly with one or more I / O modules via this router.The router also eliminates the need to use timer cells as routing resources, allowing for more flexible interconnection.

[0012] Preferred developments of the circuit arrangement according to the invention are specified in subclaims 2 to 8.

[0013] According to an advantageous embodiment of the circuit, the time routing unit is adjustable with respect to the number of modules connected to it. Such a programmable central router enables finer granularity and adaptability to the assigned tasks. In contrast, the eTPU is expanded by an entire microprocessor and 32 timing control units, and the GTPA by a complete component or an LTC array. The resulting lower gate count allows for cost savings.

[0014] The time-routing unit preferably has a memory area for writing and reading the data transmitted between modules. This allows the signals transmitted between modules to be held, thus enabling time-shifted, e.g., cyclical operation of the modules by the router. However, the forwarding of data to the respective addressed module can also be priority-controlled to optimize communication.

[0015] Particularly simple storage is achieved by the time routing unit containing a fixed write address in the memory area for each connected module. Depending on the memory size, this makes it particularly easy to connect additional modules without having to change the memory allocation for already connected modules.

[0016] The memory area of ​​the time routing unit preferably contains memory locations that contain a fixed value or no available data. This ensures that the connected modules are in a defined state during a system reset.

[0017] To analyze and manipulate the memory area of ​​the time routing unit, it is advantageous to provide an interface for a debugger. This interface is preferably connected to the internal bus of an overall system containing the circuitry. This makes the memory area accessible via the interface to this system.

[0018] In a further advantageous embodiment of the circuit, a read address for data to be read by the time routing unit can be set on timer or time control modules via a register of the module. This enables flexible connection of the modules to the router without having to reconfigure the router itself.

[0019] It is preferred if a timer or time control module is designed to stop its internal data processing if data is not available at the time routing unit. The module then blocks and only starts up again when data is available. This reduces the communication load within the circuit and increases its processing speed. Furthermore, a defined state of the modules can be set upon system reset.

[0020] The object mentioned at the outset is also achieved by an operating method for the circuit arrangement in which the time routing unit communicates cyclically with the timer and time control modules, wherein data is written by a transmitting module into a memory area of ​​the unit and read by a receiving module from this memory area.

[0021] A key aspect of the method according to the invention is the simple communication processing via the time routing unit, which allows for unlimited scalability of the circuit through flexible connection of additional modules. Interconnection via the router simultaneously creates a high degree of communication flexibility between the modules. Since direct connection of the modules via the router is always possible, high processing speed is guaranteed. At the same time, the method is simple and cost-effective to implement.

[0022] In an advantageous embodiment of the method, the timer and time control modules stop their internal data processing when data is not available at the time routing unit. This allows the modules to be reset to a defined state during a system shutdown. Furthermore, the communication load in the circuit is reduced and its processing speed is increased.

[0023] The circuit arrangement is preferably used, for example, as a timer module for controlling the engine of a motor vehicle. Short description of the drawings

[0024] The circuit according to the invention and its operating method are explained in more detail below using an exemplary embodiment. Identical or equivalent parts are provided with the same reference numerals. In the drawings: Fig. 1 a time control module for explaining the principle of time-dependent processing and generation of signals in the prior art; Fig. 2 is a block diagram of a first embodiment of the circuit arrangement according to the invention to explain its mode of operation; Fig. 3 a block diagram of a second embodiment of the circuit arrangement according to the invention for explaining the signal switching, and Fig. 4 a schematic representation of the time-dependent signal processing in modules of a circuit arrangement according to the invention. Embodiment of the invention

[0025] The Fig. Figure 1 shows a time controller module TCx (Time Controller) for explaining the principle of time-dependent signal processing and generation in the prior art. In the TCx module, one or more input signals SI (Signal In) are received and / or counted depending on a clock pulse CLKx (CLocK), and one or more output signals SO (Signal Out) are generated based on this.

[0026] The Fig. Figure 2 shows a block diagram of a first embodiment of the circuit arrangement CA (Circuit Arrangement) according to the invention to explain its operation. A time routing unit TRU (Timer Routing Unit) enables efficient signal evaluation and / or generation based on one or more time bases TM (Timer Module), as described in Fig. 1. The time bases TM are connected to time control modules TC1 ... TC4 (Time Controller) via fixed wires W1 ... W4 (Wiring). In a time control module TC1 ... TC4, the Fig. The signal switching described in section 1 is carried out. One or more timing units can also be interconnected to process and / or output more complex signals.

[0027] This connection is made by the central TRU and is in Fig. 2. Within the TRU is a memory area S through which data and signals can be transferred between the connected modules TC1 ... TC4. The number of addressable modules depends on the size of the memory S and the data rate at which the application must operate. The number of TRU memory addresses depends inversely on the number of connected modules TCx.

[0028] Each module connected to the TRU has a fixed write address such as TC3-W (for module TC3) or TC4-W (for module TC4). This write address can be written to if the memory location is empty. This can be signaled using a special flag. The read address can be set using a register such as TC3-REG (for module TC3) or TC4-REG (for module TC4) in the respective module. The modules TC1 ... TC4 are then operated cyclically by the TRU by storing data or signals to be written in the memory area S and transferring available data from the memory area S to the respective module, e.g. via the address TC3-R (for module TC3) or TC4-R (for module TC4).

[0029] When a TCx module reads data, two special memory locations in the TRU either return a predefined value or no data. For example, memory location VD (Value Defined) returns a fixed value, while memory location ED (Empty Defined) returns no available data. The two memory locations VD and ED are not module-specific and can be addressed via the respective registers of the connected TCx modules, for example via TC3-REG or TC4-REG. This ensures that modules TC1 ... TC4 are in a defined state during a system reset. If no data is present, the modules block and stop internal processing. This can be achieved during a system reset by reading memory location ED, which contains no data. For example, the read register TC4-REG of module TC4 points to the empty memory location ED, thus blocking its execution.

[0030] To access the memory area S, which is necessary for debugging the TRU, for example, the TRU is equipped with an interface I (interface). To ensure easy accessibility, this interface can be connected, for example, to the internal bus of the entire system.

[0031] The Fig. 3 shows a block diagram of a second embodiment of the circuit arrangement according to the invention for explaining signal switching. It shows a time-dependent signal processing path with signal input SI and signal output SO. In the example, a TC5 module represents an I / O module to which an input and an output pin are connected. A TC6 module blocks until the TC5 module has written a value to its memory address TC5-W. This value is then further processed by the TC6 module, which addresses the memory location TC6-R. The TC6 module could, for example, count a counter as a function of a clock pulse CLK6 and then write a value to the memory location TC6-W at a previously programmed counter reading. A TC7 module, in turn, blocks at this memory location TC7-R and starts running as soon as a data item is available. After a certain period of time has elapsed, another value is written to the memory location TC7-W of the TC7 module.This memory location TC7-W is then read again by the TC5 module via TC5-R and the level of the signal is output.

[0032] For the mechanism described above, certain timing conditions must be met. The frequency of the TRU clock CLK depends on two factors: first, the maximum frequency of a data stream or signal that must be passed through the timer without being processed, and second, the maximum frequency of a data stream or signal that can be processed by the module with the longest runtime. The time t TRU-ZyklusThe time elapsed between two successive TRU accesses to a TC5 ... TC7 module is called the TRU cycle. To ensure no data is lost, this TRU cycle must be higher than the maximum frequency of the input and output signals SI and SO. For this purpose, the number of clock cycles required for each of the connected TC5 ... TC7 modules to have read and write access to the TRU must be determined. The following equation then results for the TRU cycle: tTRU_Zylkus=#TaktefSystem

[0033] From this, the necessary clock frequency for the TRU can be determined using the following inequality: fmax<1tTRU_cycle and thus: fSystem>fmax*#cycles

[0034] For example, if the modules TC5, TC6, TC7, and TM require 3 clock cycles to read and 2 clock cycles to write data, in the worst case, 20 clock cycles are required for the TRU to process all modules in one TRU cycle. With a maximum possible frequency of the input and output signals SI and SO of 1 MHz, the TRU would have to be operated with a clock cycle of 20 MHz. This applies if the signals SI and SO are only routed through the circuit but not processed. If the data or signals must be processed in a module TC5 ... TC7, the processing time of the module TCx, which requires the most time for processing, must be taken into account. This scenario is shown in Fig. 4 shown.

[0035] The Fig.Figure 4 shows a schematic representation of the time-dependent signal processing in modules TCx of a circuit arrangement according to the invention. At times t1 ... t3 (time), data and signals with a frequency F (frequency) arrive at the input pins. In the worst case, the TRU completes one cycle with the time period p1 (period) before a module TCx can read the data. After that, in the worst case, it takes the time periods p2 + p3 until the module TCx can write its data back to the TRU. Time period p2 represents the calculation time, and time period p1 represents the time for one TRU cycle. From this, the required system clock for the TRU can be determined as follows: tp2=#TakteBerechnungfSystem tp1=#TakteTRU−UmlauffSystem tF=1fF 2*tf>2*tp1+tp2 and 2fF>2*#TakeTRU−CirculationfSystem+#TakteBerechtungfSystem=(2*#TakteTRU−Circulation)+#TakteBerechtungfSystem

[0036] This results in the system clock with: fSystem>fF*((2*#TakteTRU−Umlauf)+#TakteBerechnung2)

[0037] For example, the TRU described here can be used in a timer for engine control units. Due to the scalable and programmable architecture of the TRU, a circuit arrangement based on it can be configured extremely flexibly, is responsive, reliable, and also cost-effective.

Claims

[1] Circuit arrangement (CA) for signal recording and generation, with at least one timer module (TM) for providing a time base to a plurality of time control modules (TC1 ... TCx) connected thereto, and with a time routing unit (TRU) which is connected to the said modules (TM, TC1 ... TCx) and their signals for interconnecting them. [2] Time routing unit (TRU) in a circuit arrangement (CA) according to claim 1, wherein the number of modules (TM, TC1 ... TCx) connected thereto is adjustable. [3] Time routing unit (TRU) according to claim 1 or 2, which has a memory area (S) for writing and reading data transmitted between the modules (TM, TC1 ... TCx). [4] Time routing unit (TRU) according to claim 3, wherein a fixed write address (TCx-W) is provided in the memory area (S) for each module (TM, TC1 ... TCx) connected thereto. [5] Time routing unit (TRU) according to one of claims 3 or 4, wherein the memory area (S) has memory locations (VD, ED) containing a fixed value or no available data. [6] Time routing unit (TRU) according to one of claims 3 to 5, comprising an interface (I) for debugging and manipulating the memory area (S). [7] Time routing unit (TRU) according to claim 6, wherein the interface (I) is connected to the internal bus of an overall system containing the circuit arrangement (CA). [8] Timer or time control module (TM, TC1 ... TCx) in a circuit arrangement (CA) according to one of the preceding claims, in which a read address (TCx-R) for data to be read at the time routing unit (TRU) can be set via a register (TCx-REG) of the module (TM, TC1 ... TCx). [9] Timer or time control module (TM, TC1 ... TCx) according to claim 8, which is designed to stop its internal data processing when data is not available at the time routing unit (TRU). [10] Method for operating a circuit arrangement (CA) for signal recording and generation according to one of the preceding claims, in which the time routing unit (TRU) communicates cyclically with a timer and time control module (TM, TC1 ... TCx), wherein data is written by a transmitting module (TM, TC1 ... TCx) into a memory area of ​​the unit (TRU) and read by a receiving module (TM, TC1 ... TCx) from this memory area (S). [11] Method according to claim 10, wherein the timer and time control modules (TM, TC1 ... TCx) stop their internal data processing when data is not available at the time routing unit (TRU). [12] Use of a circuit arrangement (CA) according to one of the preceding claims for controlling the engine of a motor vehicle.

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