Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

Abstract

Method for producing an optoelectronic semiconductor chip comprising the steps: - providing an n-conducting layer (2), - arranging a p-conducting layer (4) on the n-conducting layer (2), - arranging a metal layer sequence (5) on the p-conductive layer (4), - arranging a mask (6) on the side of the metal layer sequence (5) facing away from the p-conductive layer (4), - removing the metal layer sequence (5) in places and exposing the p-conductive layer (4) using the mask (6), and - locally neutralizing or removing the exposed regions (4a) of the p-conducting layer (4) up to the n-conducting layer (2) using the mask (6), wherein - the metal layer sequence (5) comprises at least one mirror layer (51) and one barrier layer (52), - the mirror layer (51) of the metal layer sequence (5) faces the p-conductive layer (4), - an insulating layer (7) is formed which covers exposed regions of the n-conducting layer (2) as well as all exposed outer surfaces of the p-conducting layer (4), an active zone (3) and the metal layer sequence (5) in a form-fitting manner, wherein the active zone (3) is formed between the n-conducting layer (2) and the p-conducting layer (4) and is provided for receiving or emitting electromagnetic radiation during operation of the optoelectronic semiconductor chip, - the insulating layer (7) is opened by creating openings (71) towards the n-conducting layer (2), and - a metal layer (8) is applied to the insulating layer (7), wherein the metal layer (8) is electrically conductively connected to the n-conducting layer (2) through the openings (71) of the insulating layer (7), and the insulating layer (7) is surrounded by the metal layer (8), so that the metal layer sequence (5) with the mirror layer (51) is encapsulated all the way around by the metal layer (8).

Description

[0001] A method for producing an optoelectronic semiconductor chip is specified. Furthermore, an optoelectronic semiconductor chip is specified.

[0002] Document DE 10 2007 062 046 A1 describes a method for producing a light-emitting component, which comprises providing a substrate wafer and creating a layer sequence with an active layer suitable for light generation on the substrate wafer. Connection contacts are formed to the active layer on a side opposite a main radiating surface. An auxiliary carrier is also applied to the opposite side, which contains a number of contact holes machined in a matrix for contacting the connection contacts. Finally, the substrate wafer is detached from the layer sequence.

[0003] Documents WO 2010 / 056083 A2 and US 2009 / 0283787 A1 each describe a light-emitting diode, in particular a vertical light-emitting diode. One object to be achieved is to provide a method for the particularly cost-effective production of an optoelectronic semiconductor chip. Furthermore, another object to be achieved is to provide an optoelectronic semiconductor chip that can be produced particularly easily and thus cost-effectively.

[0004] This object is achieved by a method according to claim 1 and by an optoelectronic semiconductor chip according to claim 2. Further developments of the semiconductor chip are the subject of the dependent claims.

[0005] According to at least one embodiment of the method for producing an optoelectronic semiconductor chip, the method comprises the following steps: - Providing an n-conducting layer, - Arranging a p-type layer on the n-type layer, - Arranging a metal layer sequence on the p-conducting layer, - Arranging a mask on the side of the metal layer sequence facing away from the p-conducting layer, - removing the metal layer sequence in places and exposing the p-type layer using the mask, and - locally neutralising or removing the exposed areas of the p-type layer down to the n-type layer using the mask, whereby - the metal layer sequence comprises at least one mirror layer and one barrier layer, - the mirror layer of the metal layer sequence faces the p-conducting layer, - an insulating layer is formed which covers exposed regions of the n-conducting layer as well as all exposed outer surfaces of the p-conducting layer, an active zone and the metal layer sequence in a form-fitting manner, wherein the active zone is formed between the n-conducting layer and the p-conducting layer and is intended for receiving or emitting electromagnetic radiation during operation of the optoelectronic semiconductor chip, - the insulating layer is opened by creating openings to the n-conducting layer, - a metal layer is applied to the insulating layer, wherein the metal layer is electrically conductively connected to the n-conducting layer through the openings of the insulating layer, and the insulating layer is surrounded by the metal layer, so that the metal layer sequence with the mirror layer is circumferentially encapsulated by the metal layer.

[0006] In a first process step, an n-type layer is provided. The n-type layer is formed, for example, with an n-doped semiconductor material. The n-type layer can, for example, be deposited epitaxially on a growth substrate.

[0007] In a subsequent process step, for example, a p-type layer is arranged on the n-type layer. The p-type layer is formed, for example, by a p-doped semiconductor layer, which is also deposited epitaxially.

[0008] At least one active zone is formed between the n-conducting layer and the p-conducting layer, which is intended for receiving and / or emitting electromagnetic radiation during operation of the optoelectronic semiconductor chip.

[0009] The semiconductor layers of the optoelectronic semiconductor chip, for example, the n-type layer, the p-type layer, and the active zone, are based on a nitride semiconductor. This means that the layers or at least parts thereof, in particular the active zone, contain a nitride compound semiconductor material such as Al. n Ga m In 1-n-m N or consist of this material, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n + m ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, it can, for example, contain one or more dopants as well as additional components. For the sake of simplicity, however, the above formula only includes the essential components of the crystal lattice, even if these may be partially replaced and / or supplemented by small amounts of other substances.

[0010] In a further process step, a metal layer sequence is deposited on the p-type layer. The metal layer sequence can be deposited directly on the p-type layer, but it is also possible to have one or more intermediate layers between the metal layer sequence and the p-type layer.

[0011] The metal layer sequence comprises at least one mirror layer and at least one barrier layer, wherein the mirror layer of the metal layer sequence faces the p-conducting layer. The mirror layer of the metal layer sequence is formed, for example, with silver, i.e., in this case, the mirror layer contains silver or is made of silver. The barrier layer can directly follow the mirror layer on its surface facing away from the p-conducting layer. The barrier layer serves, for example, to inhibit or suppress the diffusion of silver. In particular, the barrier layer also suppresses the diffusion of other materials into the mirror layer. For example, the barrier layer contains or is made of TiWN or TiN. Furthermore, it is possible for the barrier layer to contain or consist of a transparent, conductive oxide. For example, the barrier layer then contains ZnO or the barrier layer is made of ZnO.

[0012] A mask is placed on the side of the metal layer sequence facing away from the p-type layer. The mask is structured, for example, from a photoresist and can have closed areas where it covers the metal layer sequence, as well as open areas where the metal layer sequence is freely accessible.

[0013] The metal layer sequence is removed in places using the mask, for example, where the metal layer sequence is not covered by the mask. This removal exposes the p-type layer at the locations where the metal layer sequence is removed. For example, the metal layer sequence can be patterned using wet chemical methods or by back-sputtering.

[0014] The exposed areas of the p-type layer are neutralized or removed in places. This neutralization or removal occurs without defining an additional mask. Instead, the mask already used for patterning the metal layer sequence is used to neutralize or remove the exposed areas of the p-type layer. Alternatively, the remaining areas of the metal layer sequence can be used as a mask for patterning the p-type layer.

[0015] It is important that the structuring of the metal layer sequence and the structuring of the p-type layer take place without the definition of an additional mask between the two process steps, i.e., the structuring of the metal layer sequence and the structuring of the p-type layer are carried out using the same phototechnology. The structuring of the p-type layer is therefore advantageously self-aligned to the already structured metal layer sequence. Overall, the elimination of an additional phototechnology proves to be a way to reduce the production effort for the manufacture of the optoelectronic semiconductor chip, which leads to reduced costs in the manufacture of the optoelectronic semiconductor chip.

[0016] The neutralization or removal of the exposed regions of the p-type layer is achieved, for example, by back-sputtering with Ar ions and / or hydrogen ions. When neutralizing the p-type layer, the p-type dopant in the p-type layer is neutralized, so that the neutralized regions of the p-type layer are electrically isolated. The neutralization or removal of the exposed regions of the p-type layer extends down to the n-type layer, making it contactable via the neutralized or removed regions.

[0017] If the p-type layer is removed, contact can be made directly to the n-type layer. If the p-type layer is neutralized, the neutralized region of the p-type layer can, for example, be doped with n-type doping in places so that contact with the n-type layer is made through the neutralized region. When the exposed regions of the p-type layer are neutralized or removed, an edge is created in the p-type layer adjacent to the neutralized or removed regions. When the p-type layer is removed, the edge forms an angle of, for example, approximately 60° to the underlying n-type layer. In particular, the edge is then not perpendicular to the underlying n-type layer.

[0018] Furthermore, an optoelectronic semiconductor chip is specified. The optoelectronic semiconductor chip can be produced using the method described here. This means that the features disclosed for the method are also disclosed for the optoelectronic semiconductor chip, and vice versa.

[0019] An optoelectronic semiconductor chip is specified with a metal layer sequence comprising at least one mirror layer and one barrier layer, and a p-conductive layer, wherein - the mirror layer of the metal layer sequence faces the p-conducting layer, - the p-conducting layer extends laterally beyond the mirror layer, - the lateral projection of the p-conducting layer over the mirror layer is not more than 5 µm, - an insulating layer is formed which covers exposed regions of an n-conducting layer as well as all exposed outer surfaces of the p-conducting layer, an active zone and the metal layer sequence in a form-fitting manner, wherein the active zone is formed between the n-conducting layer and the p-conducting layer and is provided for receiving or emitting electromagnetic radiation during operation of the optoelectronic semiconductor chip, - the insulating layer has openings to the n-conducting layer, and - a metal layer is applied to the insulating layer, wherein the metal layer is electrically conductively connected to the n-conducting layer through the openings of the insulating layer, and the insulating layer is surrounded by the metal layer, so that the metal layer sequence with the mirror layer is circumferentially encapsulated by the metal layer.

[0020] The optoelectronic semiconductor chip thus comprises the metal layer sequence, which includes at least a mirror layer and a barrier layer, and the p-type layer. The mirror layer of the metal layer sequence faces the p-type layer, and the p-type layer projects laterally beyond the mirror layer. In other words, the mirror layer is laterally recessed relative to the p-type layer. "Laterally" or "lateral direction" refers to directions that run, for example, perpendicular to a growth direction of the epitaxially produced layers.

[0021] The lateral projection of the p-conducting layer over the mirror layer is, for example, at most 5 µm, preferably at most 3 µm, for example at most 2 µm.

[0022] The fact that the p-conducting layer projects beyond the mirror layer at least in places is due to the fact that the removal of the metal layer sequence and the neutralization or removal of the areas of the p-conducting layer exposed by the removal take place in one work step, for example using the same mask.

[0023] It is possible for the protrusion of the p-conducting layer relative to layers of the metal layer sequence other than the mirror layer to be smaller than the protrusion relative to the mirror layer. For example, the barrier layer can project laterally beyond the mirror layer of the metal layer sequence, so that the p-conducting layer projects laterally beyond the barrier layer by a smaller amount than the mirror layer, or the barrier layer and the p-conducting layer are even flush with each other, at least in places. For example, the barrier layer projects laterally beyond the mirror layer, with the barrier layer projecting beyond the mirror layer by a maximum of 1 µm. The barrier layer projecting beyond the mirror layer can be due, for example, to the fact that an etching agent used to structure the metal layer sequence attacks the mirror layer more severely than the barrier layer.

[0024] The p-type layer preferably projects beyond the mirror layer along all edges of the p-type layer where it borders on regions where the p-type layer is removed or neutralized.

[0025] The following describes embodiments that relate both to the method described here for producing an optoelectronic semiconductor chip and to the optoelectronic semiconductor chip described here. This means that the following features are disclosed for both the method and the optoelectronic semiconductor chip.

[0026] An opening is formed that extends through the n-conducting layer and the p-conducting layer. This means that the n-conducting layer and the p-conducting layer are partially removed in the region of the opening. For example, the opening extends from the n-conducting layer through the p-conducting layer to the metal layer sequence, so that a layer of the metal layer sequence is exposed at a bottom surface of the opening. For example, the opening can taper from the n-conducting layer towards the metal layer sequence. A connection area for electrically contacting the semiconductor chip is formed at the bottom surface of the opening, i.e. towards the exposed layer of the metal layer sequence.

[0027] In other words, a layer of the metal layer sequence can serve as a bond pad for electrically contacting the semiconductor chip. It is also possible for metallization to be applied directly to the metal layer sequence, forming the bond pad. In any case, the metal layer sequence, or at least the exposed layer of the metal layer sequence, serves to imprint and, if necessary, distribute current in the optoelectronic semiconductor chip. This makes it possible to dispense with the separate definition of a bond pad during the optoelectronic semiconductor chip manufacturing process, which in turn reduces production costs and thus enables particularly cost-effective manufacture of the optoelectronic semiconductor chip.

[0028] According to at least one embodiment, the opening extends at least partially through the mirror layer of the metal layer sequence, wherein side surfaces of the opening are completely covered by a passivation layer, at least in the region of the mirror layer. This means that the mirror layer of the metal layer sequence can be removed in the region of the opening. For example, the barrier layer or another layer of the metal layer sequence is then exposed at the bottom surface of the opening. In order to protect the mirror layer from harmful atmospheric gases and moisture, the areas of the mirror layer exposed in the region of the opening must be completely covered with a passivation layer. For example, the passivation layer is produced using an ALD (Atomic Layer Deposition) process.An ALD process is particularly well-suited for conformal forming of the mirror layer without creating channels in the passivation layer through which material can leak from the mirror layer to the outside or to the mirror layer. This means that the passivation layer produced in this way protects the mirror from contaminants such as gases and / or moisture. Furthermore, the passivation layer hinders or prevents the migration of components of the mirror layer—for example, silver ions—into adjacent areas of the semiconductor chip.

[0029] The production of the passivation layer using an ALD process can be clearly distinguished, for example, by electron microscopy images from passivation layers produced by other manufacturing processes such as CVD (chemical vapor deposition). The characteristic that the passivation layer is produced using an ALD process is therefore also a physical characteristic and not a purely process characteristic.

[0030] According to at least one embodiment, the p-type layer projects laterally beyond the mirror layer in the opening. The p-type layer preferably projects laterally beyond the mirror layer all the way around, with a projection of at least 500 nm, for example, 1 µm, and at most, for example, 4 µm. If the passivation layer is produced using an ALD process, the passivation extends below the projection of the p-type layer, across the mirror layer, and up to the mirror layer itself, covering it in a form-fitting manner.

[0031] It is possible for the cavity formed by the protrusion of the p-conducting layer above the mirror layer to be completely filled with the material of the passivation layer. However, particularly when using an ALD process to produce the passivation layer, it is also possible for a concave groove to form beneath the p-conducting layer. The passivation layer then has, for example, a U-shaped cross-section. It completely covers the p-conducting layer in the region of the protrusion on its side facing the metal layer sequence, the mirror layer in the region of the side surface of the opening, and the exposed layer of the metal layer sequence facing the p-conducting layer in the region of the protrusion.

[0032] According to at least one embodiment, the thickness of the passivation layer is between 20 nm and 100 nm, in particular between 35 nm and 70 nm. The thickness of the passivation layer is to be measured in particular in a direction parallel to a growth direction of the passivation layer. If the passivation layer has several coalesced partial regions, the thickness is to be determined in particular for each individual partial region, for example up to a seam at which the individual partial regions adjoin one another. The mirror layer preferably has a thickness of between 100 nm and 200 nm, in particular between 100 nm and 150 nm.

[0033] According to at least one embodiment, the passivation layer comprises or consists of a silicon oxide, an aluminum oxide, and / or a zirconium oxide. Likewise, the passivation layer may comprise or consist of one of the following materials: TiO2, HfO2, SnO2, SiC, Zr(SiO4), Pb3(Si2O7), Na(AlSiO4), Si3N4, AlN, GaN. Other transparent, moisture-stable oxides, carbides, and / or nitrides may also be used for the passivation layer.

[0034] According to at least one embodiment, at least two openings are formed, extending through the n-conducting layer and the p-conducting layer to a layer of the metal layer sequence. A connection pad for n-side contacting of the semiconductor chip is formed in one of the openings, and a connection pad for p-side contacting of the semiconductor chip is formed in the other of the openings. In other words, in this embodiment, the semiconductor chip is contacted through at least two openings. The connection pads differ in their electrical connection to differently conductive regions of the optoelectronic semiconductor chip.

[0035] According to at least one embodiment, side surfaces of the metal layer sequence, apart from the opening(s), border at least indirectly on a metal layer that is electrically conductively connected to n-conducting semiconductor material. At least indirectly means that an electrically insulating layer can be arranged between the metal layer sequence and the metal layer that is electrically conductively connected to the n-conducting semiconductor material. However, this insulating layer is not exposed, for example, at the edges of the optoelectronic semiconductor chip, but rather is surrounded all around, i.e., at all edges of the semiconductor chip, by the metal layer that is electrically conductively connected to the n-conducting semiconductor material. In this way, the metal layer sequence with the mirror layer is encapsulated all around by the metallic n-contact, resulting in a mechanically and chemically particularly stable optoelectronic semiconductor chip.Only in the area of ​​the openings is the mirror layer of the metal layer sequence not metallically encapsulated, but covered, for example, by the passivation layer mentioned above.

[0036] According to at least one embodiment, at least one of the openings, which extends from the n-conducting layer to a layer of the metal layer sequence, is completely surrounded laterally by the active zone of the optoelectronic semiconductor chip. Preferably, all openings are completely surrounded laterally by the active zone. This means that the opening or openings via which electrical contact is made with the optoelectronic semiconductor chip are surrounded, in the case of a radiation-emitting optoelectronic semiconductor chip, by the luminous surface of the optoelectronic semiconductor chip. The electrical current for generating radiation in the active zone is preferably distributed largely or completely below the active zone, so that the optoelectronic semiconductor chip has a particularly large radiating surface.

[0037] According to at least one embodiment, the semiconductor chip has an ESD subregion comprising parts of the metal layer sequence, the p-conducting layer, and the n-conducting layer. The ESD subregion is electrically connected antiparallel to the rest of the semiconductor chip. This means that an ESD subregion is formed in the semiconductor chip by structuring the metal layer sequence, the p-conducting layer, and the n-conducting layer. This ESD subregion forms a diode that is connected antiparallel to the rest of the semiconductor chip and thus acts as an ESD protection diode for the rest of the semiconductor chip. The ESD subregion is preferably completely surrounded laterally by the active zone, so that the ESD subregion is located within the luminous area in the case of a radiation-emitting optoelectronic semiconductor chip.In the ESD sub-area, no electromagnetic radiation is generated during operation of the optoelectronic semiconductor chip, but it is generated around the ESD sub-area.

[0038] According to at least one embodiment, the semiconductor chip is divided into at least two active subregions that are electrically connected in series. In other words, the semiconductor chip comprises at least two pixels, the active subregions, which can in principle be operated independently of one another. In the optoelectronic semiconductor chip, the subregions are electrically connected in series, so that the semiconductor chip has, for example, a single n-type connection point and a single p-type connection point.

[0039] According to at least one embodiment, at least one electrical connection between the active regions is arranged below the radiation exit surface of the semiconductor chip. This means that the active subregions of the semiconductor chip are not connected in series outside the optoelectronic semiconductor chip or above the radiation exit surface, i.e., in the beam path of the optoelectronic semiconductor chip, but rather below the radiation exit surface. Preferably, all electrical connections between the active subregions of the semiconductor chip are arranged below the radiation exit surface.

[0040] According to at least one embodiment of the optoelectronic semiconductor chip, at least 2 V of voltage drops in each active sub-region during operation of the semiconductor chip. Preferably, at least 3 V of voltage drops across each active sub-region. If, for example, the semiconductor chip has 28 active sub-regions, the semiconductor chip is operated with a voltage of approximately 90 V, whereby a current of approximately 0.6 mA can flow through the semiconductor chip. Such an optoelectronic semiconductor chip with several active sub-regions connected in series can, after rectification and smoothing, also be operated with commercially available alternating current if the number of active sub-regions is suitably selected.Furthermore, it is possible for the semiconductor chip to comprise a first group of pixels connected in series and a second group of pixels connected in series, with the first and second groups connected in antiparallel to each other. In this case, it is possible to operate the semiconductor chip directly with alternating current without rectification.

[0041] In the following, the method described here and the optoelectronic semiconductor chip described here are explained in more detail using exemplary embodiments and the associated figures. Based on the schematic sectional views of the Fig. 1A to 1O, a first embodiment of a method described here is explained in more detail. Based on the schematic sectional view of the Fig. 1O, a first embodiment of an optoelectronic semiconductor chip described here is explained in more detail. Based on the schematic sectional views of the Fig. 2A and Fig. 2B, a further embodiment of a method described here is explained in more detail. Based on the schematic sectional view of the Fig. 2B shows an optoelectronic semiconductor chip described here in more detail. Based on the schematic sectional view of the Fig. 3 a feature of optoelectronic semiconductor chips described here is explained in more detail. Based on the schematic sectional views of the Fig. 4, Fig. 5, Fig. 6 further embodiments of the optoelectronic semiconductor chip described here are explained in more detail.

[0042] Identical, similar, or functionally identical elements are provided with the same reference numerals in the figures. The figures and the relative sizes of the elements depicted in the figures are not to be considered to scale. Rather, individual elements may be exaggerated for clarity and / or clarity.

[0043] Based on the schematic sectional views of the Fig. 1A to 1O, various method steps of an embodiment of a method for producing an optoelectronic semiconductor chip described here are explained in more detail. The schematic sectional view of the Fig. 1O then shows the optoelectronic semiconductor chip produced by the method in a first embodiment.

[0044] As in the Fig. 1A, an n-conducting layer 2 is first applied to a growth substrate 1, for example, deposited epitaxially. The growth substrate 1 is made of sapphire, for example. The n-conducting layer 2 is, for example, an n-doped GaN layer. The n-conducting layer 2 is followed by a p-conducting layer 4. The p-conducting layer 4 is, for example, a p-doped GaN layer. At the interface between the n-conducting layer 2 and the p-conducting layer 4, an active zone 3 is formed, which comprises, for example, a pn junction, a single- or multiple-quantum well structure. The active layer 3 is preferably suitable for emitting electromagnetic radiation from the spectral range of visible light during operation of the optoelectronic semiconductor chip to be produced.

[0045] In a subsequent method step, the metal layer sequence 5 is applied to the side of the p-conducting layer 4 facing away from the n-conducting layer 2. In the present case, the metal layer sequence 5 comprises a mirror layer 51, which consists, for example, of silver. The metal layer sequence 5 further comprises a barrier layer 52, which consists, for example, of TiWN or TiN or ZnO, or contains one or more of these materials. Optionally, the metal layer sequence 5 comprises a reinforcement layer 53, which contains at least one of the following metals or consists of one of these metals: gold, titanium, chromium. The reinforcement layer 53 serves to ensure sufficient current expansion through the metal layer sequence 5 in the optoelectronic semiconductor chip to be produced.

[0046] On the upper side of the metal layer sequence 5 facing away from the p-conductive layer 4, a mask 6 is subsequently formed, which is formed, for example, with a photoresist.

[0047] As from the Fig. As can be seen in Figure 1C, the metal layer sequence 5 and the p-conducting layer 4 are then structured using the mask 6. The metal layer sequence 5 is structured wet-chemically or by back-sputtering.

[0048] The p-conducting layer 4 is structured using the same photographic technology as the structuring of the metal layer sequence 5. This means that the mask 6 is used to structure the metal layer sequence 5 and the p-conducting layer 4. This makes the structuring of the p-conducting layer 4 a self-aligning process that does not require the definition of an additional mask. The structuring of the p-conducting layer 4 is carried out, for example, by neutralizing the regions 4a exposed by the metal layer sequence 5 to form neutralized regions. Alternatively, the p-conducting layer 4 can also be removed in the regions exposed by the metal layer sequence 5. The neutralization or removal is carried out by back-sputtering using argon ions or hydrogen ions for a period of, for example, less than two minutes.By structuring the p-conducting layer 4 up to the n-conducting layer 2, edges of the p-conducting layer 4 are created which are inclined at an angle of 60°, for example, to the plane of the growth surface of the growth substrate 1.

[0049] Based on the schematic sectional view of the Fig. 3 shows a part of the structured metal layer sequence 5 with adjacent p-type layer 4 in more detail. By structuring the metal layer sequence 5, it can have the shape of an inverted step pyramid, wherein the reinforcement layer 53 projects circumferentially beyond the barrier layer 52 by the projection d1. The barrier layer 52 projects laterally, i.e. in the lateral direction, circumferentially beyond the mirror layer 51 by the amount d2. For example, the projections d1 and d2 each amount to a maximum of 1 µm. Fig. The structuring of the metal layer sequence into an inverted step pyramid shown in Figure 3 is carried out in particular by a wet-chemical structuring of the metal layer sequence 5. Due to the subsequent structuring of the p-conducting layer 4 using the same photo technique as the structuring of the metal layer sequence 5, the p-conducting layer 4 protrudes laterally circumferentially by the amount d3 beyond the mirror layer 51. The projection is preferably at most 2 µm. The projection is thereby achieved by the Fig. 1B and Fig. 1C, i.e. the structuring of the metal layer sequence 5 and the p-conducting layer 4 with the same mask 6.

[0050] In a subsequent process step, an insulating layer 7 is applied to the surface facing away from the growth substrate 1. The insulating layer 7 has a thickness of at most 1 µm and preferably of at least 400 nm, for example 450 nm, and consists, for example, of silicon dioxide. The insulating layer 7 is applied, for example, using a TEOS precursor, which is used in a CVD process to improve the overmolding properties. The insulating layer 7 covers the exposed regions of the n-conducting layer as well as all exposed outer surfaces of the p-conducting layer, the active zone 3, and the metal layer sequence 5 in a form-fitting manner.

[0051] In connection with Fig. 1E, the insulating layer 7 is opened towards the n-conducting layer 2 by creating openings 71. The openings can optionally be filled with a metal such as silver, but this can also be done in a subsequent process step when applying the metal layer 8. Openings 71 are introduced between the structured regions of the p-conducting layer 4 and outside the structured p-conducting regions 4. The openings 71 in the insulating layer 7 are, for example, ring-shaped. One of the openings 71 completely surrounds the active zone 3 and, after the introduction of a metal, encapsulates it completely around its circumference. To form the openings 71, a mask is defined, i.e., another photographic technique is used.

[0052] In connection with the Fig. 1F describes a method step in which the metal layer 8 is applied, for example, by vapor deposition of silver onto the side facing away from the growth substrate 1, completely covering the side of the n-conducting layer facing away from the growth substrate 1 and completely enclosing the active zone 3, the p-conducting layer, and the metallic layer sequence 5. If no metal has yet been introduced into the openings 71 to contact the n-conducting layer, the metal layer 8 in the openings 71 serves to contact the n-conducting layer.

[0053] Subsequently, a barrier layer 81 and a reinforcement layer 82 are applied to the side of the metal layer 8 facing away from the growth substrate 1. For example, the following layer sequence is produced in this way: Ti / TiWN / TiN / TiPtAu. The reinforcement layer 82 preferably contains gold.

[0054] Subsequently, the carrier 9 is applied to the side of the reinforcement layer 82 facing away from the growth substrate 1. The carrier 9 can be bonded; it is also possible for the carrier 9 to be produced by a galvanic process. In this case, the carrier 9 is electrically conductive. The carrier 9 can, for example, be formed from or consist of one of the following materials: germanium, silicon, copper, nickel.

[0055] In the following process step described in connection with the Fig. 1I, the growth substrate 1 is detached from the n-conducting layer by a laser detachment process or chemo-mechanically.

[0056] In a further procedural step, see Fig. 1J, the surface of the n-conducting layer 21 facing away from the carrier 9 can be roughened. This means that roughened areas are then present at the radiation exit surface 21, which reduce the probability of total reflection of electromagnetic radiation upon passing through the radiation exit surface.

[0057] In connection with the Fig. In the process step described in Figure 1K, an opening 10 is created that extends through the n-conducting layer 2 and the p-conducting layer 4 to the mirror layer 51 of the metal layer sequence 5. Optionally, a mesa etch can be performed, removing the regions 22. The mesa etching and the creation of the opening 10 are performed using a mask (not shown), i.e., using a photographic technique. For structuring, hot phosphoric acid, for example, is used, which stops on the insulating layer 7 made of silicon dioxide and the mirror layer 51 made of silver. The use of alternative structuring chemicals is also possible.

[0058] In a further process step, the mirror layer 51 and, if applicable, the barrier layer 52 are removed from the bottom surface 10a of the opening 10. Removal is performed, for example, by etching, with the semiconductor layers surrounding the opening—that is, the n-conducting layer 2 and the p-conducting layer 4, as well as the active zone 3—being used as a mask. Removing the mirror layer 51 and, if applicable, the barrier layer 52 creates a projection by which the p-conducting layer 4 protrudes circumferentially beyond the mirror layer 51. The projection is d4 ≤ 4 µm, for example, d4 = 1 µm.

[0059] On the bottom surface 10a of the opening 10, the reinforcing layer 53 is exposed, which consists of gold or contains gold, for example.

[0060] In a subsequent process step, Fig. 1M, the passivation layer 11 is applied to the outer surface facing away from the carrier 9 using an ALD process. The passivation layer 11 can, for example, contain or consist of one of the following materials: an aluminum oxide, a zinc oxide, a titanium oxide, a silicon oxide.

[0061] It is possible for the passivation layer 11 to completely fill the cavity created by the protrusion of the p-type layer 4 over the mirror layer 51. After completion of the deposition of the passivation layer 11, the bottom surface 10a of the opening 10 is also covered with the material of the passivation layer 11.

[0062] In a subsequent process step (see Fig. 1N), in which, for example, a photographic technique using a mask is used, the reinforcement layer 53 is exposed again on the bottom surface 10a of the opening 10, so that a connection surface 54 is created, to which a contact wire (also: bonding wire) can subsequently be attached.

[0063] In the final process step, described in connection with Fig. 1O, is separated into individual optoelectronic semiconductor chips. As can be seen from the Fig. 1O, the optoelectronic semiconductor chip comprises a carrier 9 which is electrically conductive. The carrier 9 is followed by a reinforcement layer 82, on which a barrier layer 81 is formed towards the metal layer 8. The metal layer 8 is electrically conductively connected to the n-conducting region 2 of the optoelectronic semiconductor chip through the openings 71. This means that the metal layer 8 serves for the n-side contacting of the optoelectronic semiconductor chip. The metal layer 8 surrounds the metal layer sequence 5 with the mirror layer 51 laterally, except for the opening 10, so that the mirror layer 51 is at least indirectly metallically encapsulated all around by the metal layer 8. The insulating layer 7, which electrically decouples the metal layer 8 from the p-conducting layer 4, is introduced between the metal layer 8 and the metal layer sequence 5 as well as the p-conducting layer 4.The p-conducting layer 4 can be electrically contacted via the reinforcement layer 53 of the metal layer sequence 5. In the opening 10, in which the reinforcement layer 53 is accessible for electrically contacting the p-conducting layer 4, the mirror layer 51 is completely covered and encapsulated by the passivation layer 11 on the side surfaces 1b of the opening 10.

[0064] Overall, the in conjunction with Fig. 1O can be manufactured using only four photo techniques (compare the description of the Fig. 1B, Fig. 1E, Fig. 1K and Fig. 1N).

[0065] In connection with the Fig. 2A and Fig. 2B shows a further embodiment of a method described here in more detail using schematic sectional views, in which the Fig. 1N described photo technique for opening the passivation layer 11 above the reinforcement layer 53 of the metal layer sequence 5 can be dispensed with. As can be seen from the Fig. 2A, plasma-assisted etching is carried out over the entire surface without prior definition of a mask according to method step 1M. This removes the passivation layer 11 on the upper side of the n-conducting layer 2 facing away from the carrier 9, i.e., the radiation passage area 21. Since the passivation layer 11 is thicker in the region of the projection of the p-conducting layer in the opening 10 above the mirror layer 51 than in other regions of the semiconductor body, the passivation layer 11 remains present there, ensuring sufficient encapsulation of the mirror layer 51 on the side surfaces 10b of the opening 10. Fig. Figure 2B shows the isolated optoelectronic semiconductor chip in a schematic sectional view.

[0066] In conjunction with the schematic sectional view of the Fig. 4, a further embodiment of an optoelectronic semiconductor chip described here is explained in more detail. In contrast to the embodiment described in connection with the Fig. In the optoelectronic semiconductor chip described in FIG. 10, the n-side contacting of the optoelectronic semiconductor chip does not take place via the carrier 9. The carrier 9 can therefore also be formed from an electrically insulating material. Alternatively or additionally, an insulating layer 83, consisting, for example, of silicon dioxide, can be arranged between the carrier 9 and the metal layer 8.

[0067] The electrical contacting of the optoelectronic semiconductor chip is carried out in the embodiment of the Fig. 4 through two openings 10. The p-side contact is made with the optoelectronic semiconductor chip via opening 101. The reinforcement layer 53 of the metal layer sequence 5 serves as the connection surface 54.

[0068] The n-side contacting of the optoelectronic semiconductor chip is effected via the opening 102. For this purpose, an additional opening 711 is formed in the region of the opening 102 between the metal layer sequence 5, i.e. the reinforcement layer 53, and the metal layer 8, in which opening the insulating layer 7 is perforated. This opening can, for example, be used in conjunction with the Fig. 1E described process step in the passivation layer 7, i.e. during the definition of the second mask required in the process. The process step in conjunction with Fig. The optoelectronic semiconductor chip described in Figure 4 can be electrically contacted through the two openings 101, 102 by means of a connecting wire.

[0069] In connection with the Fig. 5 described embodiment of an optoelectronic semiconductor chip described here, the optoelectronic semiconductor chip is, as in the embodiment of the Fig. 10 through the carrier 9 on the n-side. In this exemplary embodiment, however, the optoelectronic semiconductor chip additionally comprises an ESD subregion 13, which is formed in a subregion of the n-conducting layer 2, active zone 3 and p-conducting semiconductor layer 4, as well as metal layer sequence 5, which is circumferentially separated by the opening 102. By means of the metallization 131, which is electrically conductively connected to the reinforcement layer 53 of the metal layer sequence 5 exposed at the bottom surface of the opening 102, and the opening 711 in the insulating layer 7, the ESD subregion is connected antiparallel to the remaining regions of the optoelectronic semiconductor chip. In this way, the ESD subregion 13 forms an ESD protection diode for the optoelectronic semiconductor chip, which is circumferentially surrounded by the radiation-emitting active zone 3.The n-contact 71, like the opening 102, is also designed to be circumferential to prevent a short circuit. For the optoelectronic semiconductor chip according to the embodiment of the . Fig. 5, at least one further photo technique is necessary, which is required for structuring the metallization 131.

[0070] Combined with Fig. 6, a further embodiment of an optoelectronic semiconductor chip described here is explained in more detail. In this embodiment, the optoelectronic semiconductor chip is divided into several active subregions 31. This means that the jointly epitaxially grown layers are divided into several subregions separated in the lateral direction. Fig. 6 shows two active subregions 31, which form two pixels of the optoelectronic semiconductor chip. The active subregions 31 are connected in series with one another by the electrical connections 32, wherein the metal layer 8 for the n-side contacting of the optoelectronic semiconductor chip is interrupted by the insulation 783 between adjacent subregions 31. The optoelectronic semiconductor chip is a Fig. 4, in which the n-side contacting of the chip is not carried out by the carrier 9, but by connection surfaces 54 in the openings 101 and 102. The creation of the openings in the insulating layer 7 required for the electrical connections 32 as well as the creation of an opening for forming the insulation 783 in the metal layer 8 is carried out, for example, together with in conjunction with Fig.1E described opening of the insulating layer 7, i.e. during the second photo technique.

[0071] During operation of the optoelectronic semiconductor chip, a voltage of at least 2 V is dropped across each of the subregions 31. In this way, by connecting several active subregions 31 in series, an optoelectronic semiconductor chip can be produced that can be operated with voltages of 90 V or more.

[0072] Overall, methods for producing optoelectronic semiconductor chips are described here, with which optoelectronic semiconductor chips can be manufactured particularly cost-effectively due to a small number of phototechniques. In addition to their ease of manufacture, the optoelectronic semiconductor chips are characterized, for example, by a circumferential metallic encapsulation of the mirror layer 51 and thus by high mechanical and chemical stability.

Claims

[1] Method for producing an optoelectronic semiconductor chip comprising the steps: - providing an n-conducting layer (2), - arranging a p-conducting layer (4) on the n-conducting layer (2), - arranging a metal layer sequence (5) on the p-conductive layer (4), - arranging a mask (6) on the side of the metal layer sequence (5) facing away from the p-conductive layer (4), - removing the metal layer sequence (5) in places and exposing the p-conductive layer (4) using the mask (6), and - locally neutralizing or removing the exposed regions (4a) of the p-conducting layer (4) up to the n-conducting layer (2) using the mask (6), wherein - the metal layer sequence (5) comprises at least one mirror layer (51) and one barrier layer (52), - the mirror layer (51) of the metal layer sequence (5) faces the p-conductive layer (4), - an insulating layer (7) is formed which covers exposed regions of the n-conducting layer (2) as well as all exposed outer surfaces of the p-conducting layer (4), an active zone (3) and the metal layer sequence (5) in a form-fitting manner, wherein the active zone (3) is formed between the n-conducting layer (2) and the p-conducting layer (4) and is provided for receiving or emitting electromagnetic radiation during operation of the optoelectronic semiconductor chip, - the insulating layer (7) is opened by creating openings (71) towards the n-conducting layer (2), and - a metal layer (8) is applied to the insulating layer (7), wherein the metal layer (8) is electrically conductively connected to the n-conducting layer (2) through the openings (71) of the insulating layer (7), and the insulating layer (7) is surrounded by the metal layer (8), so that the metal layer sequence (5) with the mirror layer (51) is encapsulated all the way around by the metal layer (8). [2] Optoelectronic semiconductor chip with - a metal layer sequence (5) comprising at least one mirror layer (51) and one barrier layer (52), and - a p-conducting layer (4), wherein - the mirror layer (51) of the metal layer sequence (5) faces the p-conductive layer (4), - the p-conducting layer (4) projects laterally beyond the mirror layer (51), - a lateral projection (d3) of the p-conducting layer (4) over the mirror layer (51) is at most 5 µm, - an insulating layer (7) is formed which covers exposed regions of an n-conducting layer (2) as well as all exposed outer surfaces of the p-conducting layer (4), an active zone (3) and the metal layer sequence (5) in a form-fitting manner, wherein the active zone (3) is formed between the n-conducting layer (2) and the p-conducting layer (4) and is provided for receiving or emitting electromagnetic radiation during operation of the optoelectronic semiconductor chip, - the insulating layer (7) has openings (71) to the n-conducting layer (2), - a metal layer (8) is applied to the insulating layer (7), wherein the metal layer (8) is electrically conductively connected to the n-conducting layer (2) through the openings (71) of the insulating layer (7), and the insulating layer (7) is surrounded by the metal layer (8), so that the metal layer sequence (5) with the mirror layer (51) is encapsulated all the way around by the metal layer (8). [3] Optoelectronic semiconductor chip according to claim 2, wherein - a further opening (10) is formed which extends through the n-conducting layer (2) and the p-conducting layer (4), - a layer of the metal layer sequence (5) is exposed on a bottom surface (10a) of the further opening (10), and - a connection surface (54) for electrically contacting the semiconductor chip is formed on the bottom surface (10a). [4] Optoelectronic semiconductor chip according to the preceding claim, wherein - the further opening (10) extends at least partially through the mirror layer (51) of the metal layer sequence (5), and - a side surface (10b) of the further opening (10) is completely covered by a passivation layer (11) at least in the region of the mirror layer (51). [5] Optoelectronic semiconductor chip according to claim 4, wherein the p-conductive layer (4) projects laterally beyond the mirror layer (51) in the further opening (10). [6] Optoelectronic semiconductor chip according to claim 4, wherein the passivation layer (11) is produced by means of an ALD process. [7] Optoelectronic semiconductor chip according to claim 2, wherein - at least two further openings (10, 101, 102) are formed which extend through the n-conducting layer (2) and the p-conducting layer (4), - a connection surface for n-side contacting of the semiconductor chip is formed in one of the further openings (10, 101, 102), and - in another of the openings (10, 101, 102) a connection surface for p-side contacting of the semiconductor chip is formed. [8] Optoelectronic semiconductor chip according to claim 7, wherein side surfaces (5a) of the metal layer sequence (5), apart from the further openings (10, 101, 102), at least indirectly border the metal layer (8) which is electrically conductively connected to the n-conducting layer (2). [9] Optoelectronic semiconductor chip according to one of claims 3 to 8, wherein the further opening (10) or at least one of the further openings (10, 101, 102) is completely surrounded laterally by the active zone (3). [10] Optoelectronic semiconductor chip according to one of claims 2 to 9, wherein - an ESD sub-region (13) of the semiconductor chip, which comprises parts of the metal layer sequence (5), the p-conducting layer (4) and the n-conducting layer (2), is electrically connected antiparallel to the rest of the semiconductor chip, and - the ESD sub-area (13) forms an ESD protection diode for the remaining semiconductor chip. [11] Optoelectronic semiconductor chip according to the preceding claim, wherein the ESD partial region (13) is completely surrounded laterally by the active zone (3). [12] Optoelectronic semiconductor chip according to one of claims 2 to 11, wherein the semiconductor chip is divided into at least two active subregions (31) which are electrically connected in series. [13] Optoelectronic semiconductor chip according to the preceding claim, wherein an electrical connection (32) between the active partial regions (31) is arranged below a radiation exit surface (22) of the semiconductor chip. [14] Optoelectronic semiconductor chip according to one of claims 12 to 13, wherein during operation of the semiconductor chip at least 2 V voltage drops at each active partial region (31).

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