POWER SEMICONDUCT COMPONENTS AND SEMICONDUCT TRANSISTORS PROTECTED FROM HOT LOAD CARRIERS, AND A MANUFACTURING METHOD FOR THEM

Abstract

Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403), comprising: a semiconductor body (40), comprising: a first semiconductor region (1) comprising majority charge carriers of a first charge type; and a dielectric region (30, 31, 81) comprising a first charged dielectric section (81) and a second charged dielectric section (30), wherein the second charged dielectric section (30) comprises solid charges of the first charge type, the first charged dielectric section (81) comprises a first maximum charge carrier density per area, and the second charged dielectric section (30) comprises a second maximum charge carrier density per area of ​​the solid charges, which is greater than the first maximum charge carrier density per area. wherein the first semiconductor region (1) forms an insulator-semiconductor interface (25) with at least the second charged dielectric section (30), and wherein the dielectric region (30, 33, 81) is arranged between the first semiconductor region (1) and a gate electrode (11) and between the first semiconductor region (1) and a field plate (12).

Description

INVENTION AREA

[0001] This specification relates to embodiments of methods for protecting a semiconductor device from degradation induced by hot charge carriers. Furthermore, this specification relates to embodiments of semiconductor devices, in particular field-effect power semiconductor devices, that are protected from the injection of hot charge carriers into a dielectric region, and to a manufacturing method for such devices. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and controlling an electric motor or machine, are based on semiconductor components. It is often desirable for these semiconductor components to operate reliably over extended periods. Long-term high reliability of semiconductor components is also frequently expected in consumer goods, for example, in hi-fi audio amplifier circuits. The characteristics of power semiconductor components, such as power transistors used in amplifier circuits, influence the circuit's performance. Therefore, it is often desirable to prevent or at least delay any deterioration of characteristics such as threshold voltage, reverse voltage, switching time, switching characteristics, or gain.

[0003] Publication US 2008 / 0164516A1 describes a semiconductor device comprising a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each trench of the pair of trenches essentially consists of a dielectric material arranged therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type, and a distance between the trenches defines an electrical property of the semiconductor device.The semiconductor device further comprises a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type. US Patent 2010 / 0084704A1 describes an edge-termination structure with a dielectric trench containing a permanent charge and surrounded by a semiconductor material of the first conductivity type, which in turn is laterally surrounded by a semiconductor material of the second conductivity type. EP Patent 1649501B1 describes a high-k dielectric film having a higher dielectric constant than silicon dioxide and formed for a semiconductor device on a substrate.Furthermore, German patent application DE 38 89 354 T2 describes a semiconductor device comprising a substrate with a zone of first conductivity type and a zone of second conductivity type, which together form a transition extending to a surface of the substrate, an oxide layer on the surface of the substrate covering the transition at the surface, and a zone of charged ions in the oxide layer extending from a location above a section of the zone of second conductivity type across the transition to a location above a section of the zone of first conductivity type, wherein the polarity of the ions in the ion zone is the same as the polarity of the zone of first conductivity type, and wherein the zone of charged ions in the oxide layer generally has a higher concentration next to the transition than above the section of the zone of first conductivity type.

[0004] Power semiconductor devices, in particular, are typically subjected to high stresses during operation. For example, a power semiconductor device, such as a power IGBT (Insulated Gate Bipolar Transistor) operating in a power converter or as a driver or switch of an electric motor, may be subjected to high currents while flood charge and / or overvoltage spikes are dissipated during switching or a duty cycle. In such a case, hot charge carriers, typically hot electrons, can be generated in areas of strong electric field. However, if these hot carriers are injected into a dielectric layer or field dielectric of the IGBT, it can lead to a degradation of transistor characteristics or even complete device failure.

[0005] These effects can also occur outside the active region of power semiconductor devices. Furthermore, hot support injection has been shown to pose a reliability risk to edge termination structures in power semiconductor devices. The observed drift in blocking capability has been attributed to hot electrons injected into the dielectric region of edge termination field plates. Since the probability of hot support-induced degradation of device properties increases with decreasing device size, hot electron-induced degradation also imposes limits on the scaling of dielectrics.

[0006] Furthermore, degradation of semiconductor devices induced by hot electrons can often only be detected in complicated long-term reliability tests such as high-temperature reverse bias (HTRB).

[0007] The field strength near the dielectric regions can be reduced by using appropriately polarized field plates and / or doped regions. However, these measures are not always feasible and impose design limitations. For example, using an additional n-doped semiconductor region beneath a p-doped body region of a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) or an IGBT results in a reduced reverse voltage.

[0008] For these and other reasons, the task is to solve the aforementioned problems.

[0009] The problem is solved by the semiconductor transistor according to claim 1, the power semiconductor devices according to claims 14, 16 and 18, the method for forming a semiconductor device according to claim 22 and the vertical semiconductor transistor according to claim 31. Further embodiments are set forth in the dependent claims. BRIEF DESCRIPTION OF THE INVENTION

[0010] An example provides a method for protecting a semiconductor device from deterioration of its electrical characteristics. The method involves providing a semiconductor device with a first semiconductor region and a charged dielectric layer forming a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer contains fixed charges of the first charge type. The charge carrier density per unit area of ​​the fixed charges is configured such that the charged dielectric layer is shielded from the incorporation of hot majority charge carriers generated in the first semiconductor region.

[0011] According to one embodiment, a semiconductor transistor is provided with a semiconductor body. The semiconductor body contains a dielectric region and a first semiconductor region with majority charge carriers of a first charge type. The dielectric region contains a first charged dielectric section and a second charged dielectric section with fixed charges of the first charge type. The first charged dielectric section has a first maximum charge carrier density per area. The second charged dielectric section has a second maximum charge carrier density per area of ​​the fixed charges. The second maximum charge carrier density per area is greater than the first maximum charge carrier density per area. The first semiconductor region forms an insulator-semiconductor interface with at least the second charged dielectric section.The dielectric region is located between the first semiconductor region and a gate electrode and between the first semiconductor region and a field plate.

[0012] An example describes a method for forming a semiconductor device. The method involves providing a semiconductor body with a first semiconductor region. The majority charge carriers of the first semiconductor region are of a first charge type. The method further involves forming a dielectric region with fixed charges of the first charge type and forming an electrode structure at the dielectric region such that the electrode structure is insulated from the semiconductor body. The first semiconductor region forms a drift region. The electrode structure forms a field plate and / or a gate electrode with a section that is positioned at the dielectric region and configured to function as a field plate.Forming the dielectric region involves depositing a first dielectric layer on the first semiconductor region, depositing a second layer on the first dielectric layer by atomic layer deposition (ALD), and depositing a second dielectric layer on the second layer. The dielectric region is configured such that the dielectric region and the first semiconductor region form an insulator-semiconductor interface.

[0013] An example provides a method for protecting a semiconductor device from deterioration of its electrical characteristics. The method includes providing a semiconductor device with a first semiconductor region and a charged dielectric layer forming a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer contains fixed charges of the first charge type. The method also includes, prior to providing the semiconductor device, configuring a charge carrier density per area of ​​the fixed charges such that the charged dielectric layer is shielded from the incorporation of hot majority charge carriers generated in the first semiconductor region.

[0014] According to one embodiment, a power semiconductor device is provided with a semiconductor body. The semiconductor body comprises an active region and a peripheral region, both of which define a horizontal main surface of the semiconductor body. The semiconductor body also includes an n-type semiconductor layer, a pn junction, and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral region. The pn junction is located between the n-type semiconductor layer and the main surface in the active region. The at least one trench extends in the peripheral region from the main surface into the n-type semiconductor layer and comprises a dielectric layer with fixed negative charges. The dielectric layer is located, in the vertical direction, both below and above the pn junction.Typically, the dielectric layer with fixed negative charges has a net negative charge.

[0015] According to one embodiment, a vertical semiconductor transistor is provided with a semiconductor body. The semiconductor body comprises a first n-type semiconductor region, a second semiconductor region forming a pn junction with the first semiconductor region, and a third semiconductor region. The semiconductor body also comprises a dielectric layer, which includes fixed negative charges in at least one section, adjacent to the second semiconductor region and located between the first and third semiconductor regions. The dielectric layer extends from a major surface of the semiconductor body into the semiconductor body, and the charge carrier density per unit area of ​​the fixed negative charges of the dielectric layer decreases stepwise or continuously with increasing distance from the major surface.The vertical semiconductor transistor further comprises an insulated gate electrode adjacent to the first semiconductor region and the second semiconductor region.

[0016] According to one embodiment, a method for forming a semiconductor device is provided. The method comprises providing a semiconductor body that includes a first n-type semiconductor region. A trench is formed extending from a major surface of the semiconductor body into the first semiconductor region. A dielectric layer with fixed negative charges is formed on a surface of the trench. The formation of the dielectric layer includes at least one atomic layer deposition using an organaluminum as a precursor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a more detailed understanding of embodiments and are incorporated into this specification as a part thereof. The drawings illustrate embodiments and, together with the description, serve to explain the principles of embodiments. Further embodiments and many of the intended advantages of embodiments will readily become apparent when they are better understood by reference to the following detailed description. The elements in the drawings are not necessarily to scale relative to one another. The same reference numerals denote corresponding similar parts. Fig. Figure 1 schematically shows a vertical cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 2 schematically shows a vertical cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 3 schematically shows vertical cross-sections of a semiconductor device according to one or more embodiments. Fig. Figure 4 schematically shows a vertical cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 5 schematically shows a vertical cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 6 schematically shows a vertical cross-section of a lateral semiconductor device according to one or more embodiments. Fig. Figure 7 schematically shows a vertical cross-section of a lateral semiconductor device according to one or more embodiments. Fig. Figure 8 schematically shows a vertical cross-section of a lateral semiconductor device according to one or more embodiments. Fig. Figure 9 schematically shows a vertical cross-section of a lateral semiconductor device according to one or more embodiments. Fig. Figure 10 schematically shows a vertical cross-section of a lateral semiconductor device according to one or more embodiments. Fig. Figures 11-19 show manufacturing processes according to one or more embodiments. Fig. Figure 20 schematically shows a vertical cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 21 schematically shows a vertical cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figures 22-28 show manufacturing processes according to one or more embodiments. Fig. Figures 29-35 show manufacturing processes according to one or more embodiments. Fig. Figure 36 shows the dependence of the breakdown voltage on the net charge of a dielectric of two high-voltage devices according to one or more embodiments. Fig. Figure 37 schematically shows a horizontal cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 38 schematically shows a horizontal cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 39 schematically shows a horizontal cross-section of a vertical semiconductor device according to one or more embodiments. Fig. Figure 40 schematically shows a top view of a vertical semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0018] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be practiced. In this context, directional terminology such as "top," "bottom," "front," "back," "anterior," "rear," etc., is used with reference to the orientation of the described figure(s). Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting.It is understood that other embodiments may be used and structural or logical changes may be made. The following detailed description is therefore not to be understood in a limiting sense, and the scope of protection of the present invention is defined by the attached claims.

[0019] Various embodiments will now be discussed in detail, one or more examples of which are illustrated in the figures. Each example is provided for illustrative purposes and is not intended to limit the invention. For instance, features shown or described as part of one embodiment can be used with or in combination with other embodiments to produce yet another embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific terminology. The drawings are not to scale and are for illustrative purposes only. For the sake of clarity, the same elements or manufacturing steps in the various drawings have been designated with the same references unless otherwise indicated.

[0020] The term "horizontal," as used in this specification, is intended to describe an orientation essentially parallel to a first or primary surface of a semiconductor substrate or body. This could be, for example, the surface of a wafer or a chip.

[0021] The term “vertical”, as used in this specification, is intended to describe an orientation that is essentially perpendicular to the first surface, i.e. parallel to the normal direction of the first surface of the semiconductor substrate or body.

[0022] In this specification, n-doped is referred to as a first conductivity type, while p-doped is referred to as a second conductivity type. The majority charge carriers of an n-doped region and a p-doped region are electrons and holes, respectively. In this specification, a negative charge type is referred to as a first charge type, while a positive charge type is referred to as a second charge type. Of course, semiconductor devices can be designed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Accordingly, the first charge type can also denote the charge type of holes. Furthermore, some figures illustrate relative doping concentrations by indicating "-" or "+" with the doping type. For example, "n" means -“a doping concentration that is smaller than the doping concentration of an “n” doping area, while an “n + The “-doping region has a higher doping concentration than the “n” doping region. However, specifying the relative doping concentration does not mean that doping regions with the same relative doping concentration must have the same absolute doping concentration unless otherwise stated. For example, two different n + -areas have different absolute doping concentrations. The same applies, for example, to an n + - and a p + -Area.

[0023] Specific embodiments described in this specification relate, among other things, to field-effect transistors, in particular power field-effect transistors. The term "field effect," as used in this specification, is intended to describe the formation, mediated by an electric field, of a conducting "channel" of a first conductivity type and / or control of the conductivity and / or a channel shape in a semiconductor region of a second conductivity type, typically a body region of the second conductivity type. Due to the field effect, a unipolar current path through the channel region between a source region of the first conductivity type in ohmic contact with a source electrode and a drain region of the first conductivity type, which is in ohmic contact with a drain electrode, is formed and / or controlled by the electric field.Without an external voltage applied between the gate and source electrodes, the ohmic current path between the source and drain electrodes through the semiconductor device is interrupted or at least exhibits a high resistance in normally-off field-effect devices. In normally-on field-effect devices such as HEMTs (High Electron Mobility Transistors) and normally-on JFETs (Junction FETs), the current path between the source and drain electrodes through the semiconductor device is typically low-resistance even without an external voltage applied between the gate and source electrodes.

[0024] In the context of this specification, the term "field-effect structure" is intended to describe a structure formed in a semiconductor substrate or semiconductor device with a gate electrode for forming and / or shaping a conducting channel in the channel region. The gate electrode is at least isolated from the channel region by a dielectric region or dielectric layer. In the context of this specification, the term "field plate" is intended to describe an electrode located at a semiconductor region, typically a drift region, from which it is isolated, and configured to extend a cleared section in the semiconductor region by applying an appropriate voltage, usually a positive voltage for an n-type drift region. The terms "cleared" and "fully cleared" are intended to describe a semiconductor region that contains substantially no free charge carriers.Typically, insulated field plates are positioned near pn junctions, for example, between a drift region and a body region. This allows the reverse voltage of the pn junction or the semiconductor device to be increased. The dielectric layer or region that insulates the field plate from the drift region is subsequently referred to as a field dielectric layer or region. The gate electrode and the field plate can be at the same electrical potential. Furthermore, a section of the gate electrode can be used as the field electrode. Examples of dielectric materials used to form a dielectric region or layer between the gate electrode or field plate and the drift region include SiO₂, Si₃N₄, and SiO₂. x N yAl₂O₃, ZrO₂, Ta₂O₅, TiO₂, and HfO₂. The term "power field-effect transistor," as used in this specification, is intended to describe a field-effect transistor on a single chip with high-voltage and / or high-current switching capabilities. In other words, power field-effect transistors are designed for high currents, typically in the ampere range, and / or high voltages, typically above 20 V, especially above 400 V. The term "power field-effect transistor," as used herein, is intended to include both unipolar power field-effect transistors, such as power MOSFETs, and bipolar power field-effect transistors, such as power IGBTs.

[0025] Fig. Figure 1 shows an embodiment of a semiconductor device 100 in a section of a vertical cross-section. The semiconductor device 100 comprises a semiconductor body 40 with a first or main surface 15 and a second surface 16 or lower surface 16 arranged opposite the first surface 15. The normal direction e n The first surface 15 runs essentially parallel to the vertical direction, i.e., defines it.

[0026] The following describes embodiments relating to semiconductor devices and manufacturing processes, primarily with reference to silicon (Si) semiconductor devices. Accordingly, a monocrystalline semiconductor domain or monocrystalline semiconductor layer is typically a monocrystalline Si domain or monocrystalline Si layer. However, it is understood that the semiconductor body 40 can be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, among others, elemental semiconductor materials such as silicon (Si) or germanium (Ge) and their alloys (Si). x Ge vGroup IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few. The semiconductor materials mentioned above are also referred to as homojunction semiconductor materials. When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include aluminum gallium nitride (AlGaN) and gallium nitride (GaN) or silicon carbide (Si x C 1-x) and SiGe heterojunction semiconductor material. For power semiconductor applications, Si, SiC, and GaN are currently the most commonly used materials. If the semiconductor body comprises a wide-bandgap material such as SiC or GaN, which exhibits a high breakdown voltage or a high critical electric field strength, and where avalanche multiplication begins, the doping of the respective semiconductor regions can be increased, thus lowering the on-resistance R. on reduced.

[0027] The semiconductor body 40 is typically a wafer 40 or a chip 40. Typically, the semiconductor body 40 contains a first n-type semiconductor region 1, a fifth n-type semiconductor region 5, and a fourth p-type semiconductor region 4 located between the fifth semiconductor region 5 and the first semiconductor region 1. The majority charge carriers of the first n-type semiconductor region 1 are negatively charged electrons. The majority charge carriers of the fourth p-type semiconductor region 4 are positively charged holes. Pn junctions are formed between the fourth semiconductor region 4 and the fifth semiconductor region 5, and between the fourth semiconductor region 4 and the first semiconductor region 1.

[0028] In the exemplary embodiment of Fig. Three vertical trenches 60, 61, and 62 extend from the main surface 15 through the fifth semiconductor region 5, the fourth semiconductor region 4, and partially into the first semiconductor region 1. Typically, the first semiconductor region 1, the fourth semiconductor region 4, and the fifth semiconductor region 5 form a drift region 1, a body region 4, and a source region 5, respectively. Each of the trenches 60 to 62 contains a respective electrode structure with a gate electrode 11, which is insulated from the semiconductor body 40 by a respective dielectric region.

[0029] Each dielectric region typically contains a dielectric plug 82, which insulates the gate electrode 11 from a source metallization 90, and a gate dielectric layer 81 located at the body region 4. The drift region 1 is in ohmic contact with a drain electrode 91 on the back side 16 via an optional field stop layer 2 and a drift contact layer 3. + -Type. In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in contact", and "electrically connected" are intended to describe the existence of an electrically conductive connection or ohmic current path, particularly a connection with a low resistance, between two regions, sections, or parts of a semiconductor device, even when no voltages are applied to the semiconductor device. Typically, the body region 4 is electrically connected to the p via a body contact region 6. +-Type connected to the source electrode 90. The doping concentration of the source area 5 and the body contact area 6 are generally higher than the doping concentration of the drift area 1.

[0030] Due to the short-circuiting of the source region 5 and the body region 4, the semiconductor device 100 blocks current only in one direction. In forward or reverse bias mode, the voltage difference V DS The voltage between drain electrode 91 and source electrode 90 is positive. Furthermore, an n-type channel region (not shown) can be formed in body region 4 by positively driving the gate electrodes 11 relative to body region 4. Accordingly, the semiconductor device 100 can be operated as a field-effect semiconductor device.

[0031] In contrast, the voltage difference V DSIn reverse mode, the voltage is negative. Operating a semiconductor device in reverse mode is subsequently also referred to as operating the semiconductor device in diode mode. In reverse mode, the pn junction formed between drift region 1 and body region 4, also called the body diode, is forward-biased and can conduct a reverse current. Accordingly, the semiconductor device 100 can be operated as a MOSFET with an integrated freewheeling diode. This can be used, for example, to switch inductive loads such as an electric motor. With a high positive voltage difference V DS can hot electrons e - In drift region 1, an avalanche mode of the semiconductor device 100 is generated. The avalanche mode may be desirable, but can lead to device degradation over time. In reverse mode, the voltage difference V DSThe voltage drop across the semiconductor device ranges from the threshold voltage (0.7 V for silicon) at low current densities to several volts at high current densities. In this case, electrons and holes are injected from the drain contact region 3 and the body region 4, respectively, into the drift region 1.

[0032] Accordingly, the electron density and hole density in drift region 1 are essentially equal and usually much higher than the doping concentration. This means that drift region 1 is flooded with charge carriers. When the semiconductor device 100 is commutated, i.e., switched back to forward or reverse bias, in which the body diode is reverse-biased, the accumulated charge carriers in drift region 1 are discharged before and during the formation of a space charge region at the pn junction of the body diode. Due to the lower doping of drift region 1 compared to body region 4, the majority of the reverse voltage typically drops across drift region 1. The electric field strength in the space charge region depends mainly on the charge distribution.During commutation, not only the positive dopant ions but also the positive charge of the holes, which flow through the space charge region to the body region 4, contribute to the electric field strength distribution in the drift region 1. Accordingly, the gradient of the electric field strength is higher for flowing holes. Consequently, an avalanche multiplication of electrons can occur at lower voltages compared to static avalanche conditions in reverse bias. Thus, hot electrons can be generated by avalanche multiplication in reverse bias at high voltages and / or during commutation into reverse bias. The term "avalanche condition," as used in this specification, is intended to encompass both static avalanche conditions during the reverse bias of a semiconductor device and dynamic avalanche conditions during the commutation of a semiconductor device into reverse bias.

[0033] According to one embodiment, the electrode structures of the trenches 60, 61, 62 in their respective lower trench sections 601, 611, 621 are isolated from the drift region 4 by respective negatively charged dielectric sections 30. Accordingly, hot electrons e -The negatively charged dielectric sections 30 repel the electrons generated during the reverse bias of the semiconductor device 100 and / or during its commutation into reverse bias. Hot electrons generated in a similar device, but without negatively charged dielectric sections, can lead to device degradation. In particular, hot electrons generated near an interface between the drift region and the trench insulation can enter the insulation with sufficiently high energy and cause damage. This process is prevented or at least reduced by the negatively charged dielectric sections 30 of the semiconductor device 100.

[0034] The term "hot carrier," as used in this specification, refers to a charge carrier that is not in thermal equilibrium with the lattice. The term "hot carrier," as used in this specification, includes a charge carrier with an energy high enough to penetrate the conduction band of the dielectric region. Within this specification, the protection of semiconductor devices against degradation by hot carriers is primarily discussed with respect to hot electrons, which constitute the majority charge carriers of an n-doped semiconductor region. Of course, the hot carriers can also be hot holes. The injection of hot electrons and hot holes can occur into a dielectric that may border either a p-doped or an n-doped semiconductor region.Hot charge carriers are typically formed in regions of the semiconductor device with a strong electric field. However, they can also be generated thermally and, for example, accelerated in an electric field. The negatively charged dielectric sections 30 contain fixed charges of the same charge type as the majority charge carriers of the drift region 1, i.e., fixed negative charges for the n-doped drift region 1 shown in . Fig. 1. In the case of an adjacent p-doped semiconductor region, fixed positive charges are embedded in the charged dielectric sections 30. Accordingly, the charged dielectric section 30 forms a Coulomb shield against hot majority charge carriers of the adjacent drift region 1. As in Fig. 1. Hot electrons are shown by the dashed arrows. -The electrons are prevented by the Coulomb screen from reaching the charged dielectric section 30 and are guided within the drift region 1 to the drain electrode 91. Typically, hot electrons e - from the semiconductor-insulator interfaces formed in the lower sections 601, 611, 621 of the respective trenches 60, 61, 62. This means that hot electrons e -In avalanche mode, the electrons are deflected by areas of highest electric field strength located near the semiconductor-insulator interface. Accordingly, dielectric sections 30 and typically also dielectric section 81 are protected from the incorporation or entrapment of hot electrons. Thus, a change in the properties of the dielectric layer is generally avoided. Consequently, the switching behavior and / or transistor characteristics of the semiconductor device 100 are generally not, or only minimally, affected by the injection of hot carriers. This, in turn, prevents, for example, the destruction of other parts of the circuit and / or EMC (electromagnetic compatibility) problems that can occur in semiconductor devices over time without a charged dielectric section 30.Furthermore, the injection of hot electrons into dielectric regions can damage them and / or cause the formation of trapped positive charges. The incorporation of positive charges can cause a self-reinforcing change in transistor characteristics and / or switching behavior. In this case, hot electrons generated in a subsequent process are attracted by the trapped positive charges. Because of the negatively charged dielectric section 30, a self-reinforcing change in switching behavior, which can even lead to device destruction, is generally avoided. Thus, the semiconductor device 100 is protected against degradation induced by hot substrates.

[0035] In the presentation of Fig. Figure 1 shows three possible variants of different trench structures 60, 61, 62 with respective charged dielectric sections 30. Each variant can be used for a given embodiment. Each of the three trench structures 60 to 62 can form a unit cell in an active region of a power semiconductor device. Thus, several identical unit cells are typically arranged in the active region of the power semiconductor device 100. In other words, the semiconductor device 100 comprises a semiconductor body 40 with an n-type source region 5, an n-type drift region 1, a p-type body region 4 located between the source region 5 and the drift region 1, and at least one trench 60, 61, 62. The at least one trench 60, 61, 62 extends from the source region 5 through the body region 4 and into the drift region 1 and contains an electrode structure that is insulated from the semiconductor body 40 by a dielectric region.The dielectric region contains a negatively charged dielectric section 30. Of course, the doping relationships and the charge type of the charged dielectric section can also be reversed.

[0036] In the lower section 601 of trench 60, a field plate 12 is arranged, which is insulated from the gate electrode 11 and the drift region 1, respectively, by a further dielectric closure 83 and the negatively charged region 30. In the lower sections 611 and 621 of trenches 61 and 62, respectively, a lower part of the respective gate electrode 11 beneath the body region 4 can be operated as a field plate. Accordingly, the negatively charged region 30 and the lower part of the gate oxide 81 typically form a field dielectric region. Typically, the negatively charged dielectric section 30 is arranged in a section of the field dielectric region that is in an avalanche mode at a region of highest electron current, in order to protect at least those parts of the field dielectric region where the risk of hot charge carrier injection is greatest.The field plate 12 and the lower parts of the gate electrodes 11 can be further used as compensation structures. Accordingly, the drift region 1 can be more heavily doped than the optional layer 2. For example, the drift region can be n-doped and the optional layer 2 can be n-doped. - -doped. In this case, another n-doped semiconductor layer with a higher doping concentration than drift region 1 can be arranged between the optional layer 2 and the drift contact layer 3.

[0037] The semiconductor device 100 can also be described as a semiconductor device 100 comprising a semiconductor body 40 with a first semiconductor region 1 of a first conductivity type and a dielectric region comprising a charged dielectric section 30 with fixed charges and a dielectric section 81. The charge type of the fixed charges is the same as the charge type of the majority charge carriers of the first semiconductor region 1. The dielectric section 81 can be uncharged or also comprise fixed charges with a first maximum charge carrier density per area. The charged dielectric section 30 has a second maximum charge carrier density per area, which is greater than the first maximum charge carrier density per area. Typically, the second maximum charge carrier density per area is greater than about ten times the first maximum charge carrier density per area.In the following, the dielectric section 81 and the charged dielectric section 30 will also be referred to as a first charged dielectric section 81 and a second charged dielectric section 30, respectively.

[0038] According to one embodiment, the dielectric region forms a dielectric-semiconductor interface with the first semiconductor region 1. Typically, the dielectric region is located between the first semiconductor region 1 and a gate electrode 11 and / or between the first semiconductor region 1 and a field plate 12 and / or along a drift region 1 formed by the first semiconductor region 1. As shown in trenches 61 and 62, the charged dielectric section 30 can be located between the gate electrode 11 and the drift region 1. However, the charged dielectric section 30 is generally not located between the gate electrode 11 and a body region 4. This means that the charged dielectric section 30 is generally not part of a gate dielectric layer at a channel region in the body region 4. This is intended to prevent changes to the threshold voltage of the gate electrode 11.In other words, a gate electrode 11 extending into the drift region 1 is typically isolated from the drift region 1 by a charged dielectric section 30 located in a lower part beneath the body region 4, where the gate electrode 11 can operate as a field plate. Accordingly, the charged dielectric section, hereinafter also referred to as the charged dielectric region 30 and charged dielectric layer 30, is generally arranged along the drift region 1 of the semiconductor device 100 and forms a dielectric-semiconductor interface with the drift region 1. Typically, the charged dielectric layer 30 is located near regions with the strongest electric field in the reverse-biased operation of the semiconductor device 100.

[0039] According to embodiments, the n-type drain contact region 3 is replaced by a p-type collector region to form an IGBT, or by a horizontally alternating arrangement of n-type and p-type regions to form an IGBT with an integrated freewheeling diode. Accordingly, electrodes 90 and 91 form an emitter electrode 90 and a collector electrode 91, respectively. Due to the charged dielectric layers 30, hot electrons generated in an avalanche mode of the IGBT are deflected at least from the lower trench sections. Therefore, the IGBT is protected against degradation induced by hot charge carriers.

[0040] Fig. Figure 2 shows an embodiment of a vertical power semiconductor device 200 in a section of a vertical cross-section. In the section of Fig. Figure 2 is only a peripheral region or edge region 220 with an exemplary edge termination shown in detail. The adjacent active region 210 of the semiconductor body 40 typically contains several transistor structures, for example, several field-effect transistor cells, as referred to in Fig. Figure 1 explains. Typically, a first n-type semiconductor region 1, which typically forms a drift region 1 in the active region 210, reaches the main surface 15 in the peripheral region 220. To ensure a high blocking voltage, an edge termination with an insulated field plate 10 is arranged on the main surface 15. The field plate 10 is insulated from the semiconductor body 40 by a field insulation region. The field plate 10 can be electrically floating or connected to a voltage. In the embodiment of Fig. In 2, the field plate 10 is connected to the voltage of the fourth p-type semiconductor region 4. The fourth semiconductor region 4, together with the first semiconductor region 1, forms the blocking pn junction of the semiconductor device 200, which is necessary to establish a blocking capability.

[0041] According to one embodiment, the field insulation region comprises a first dielectric section 80 and a negatively charged dielectric section 30. The first dielectric section 80 can be slightly positively charged, typically uncharged, or charged with negative charge carriers up to a first maximum charge carrier density per area. The negatively charged dielectric section 30 is located at an edge 71 of the field plate 10 and is charged with negative charge carriers up to a maximum charge carrier density per area that is greater than the first maximum charge carrier density per area. Fig. Figure 2 shows the semiconductor device 200 during a blocking mode, in which the first semiconductor region 1 is completely or partially deactivated. During the blocking mode, the voltage difference between the voltage V S between the fourth semiconductor region 4 and the voltage V D The drain electrode 91 is negative, i.e., V S < V D The field plate 10 is typically connected to a fourth p-type semiconductor region 4, which can form a body region 4 in the active region 210 of a MOSFET or an IGBT. Depending on the implemented semiconductor device, planar transistor cells (not shown) or transistor cells with electrode structures arranged in vertical grooves, as e.g. in [reference to a specific example], can be used in addition to or instead of the fourth semiconductor region 4. Fig. As shown in Figure 1, connect. Alternatively, the fourth semiconductor region 4 of the p-type can form the anode of a diode. The field plate 10 provides an equipotential surface. Near the field plate 21, exemplary equipotential lines 20, 21 run essentially parallel to the field plate 10. Thus, the equipotential line 20 intersects in Fig. 2 the main surface 15 of the semiconductor body 40 near edge 71. Due to the negatively charged dielectric section 30, the equipotential lines in the blocking mode of the semiconductor device 200 are redistributed such that a region 17 with the strongest electric field in the semiconductor region 1 at edge 71 of the field plate 10 is avoided. Accordingly, the risk of generating hot electrons is reduced. Furthermore, hot electrons are deflected by the Coulomb screen of the negatively charged dielectric section 30. Consequently, the field-insulating region is protected from degradation induced by hot charge carriers. Of course, the charged dielectric section 30 can also be positively charged if the doping types of the semiconductor regions of the semiconductor device 200 are reversed.

[0042] Typically, the charge carrier density per area of ​​the charged section 30 decreases stepwise or continuously towards the outer edge of the edge termination structure. Accordingly, the maximum field strength in the semiconductor region 1 can be further reduced during the blocking mode. In other embodiments, the charge carrier density per area of ​​the charged section 30 is essentially constant. Fig. In Figure 2, the charges in the charged dielectric section 30 are represented as condensed charges q. Typically, the charge in a horizontal plane in the charged dielectric section 30 is Fig. 2 essentially continuously distributed.

[0043] The first dielectric section 80 can also be negatively charged to better shield against the incorporation of thermally generated hot majority charge carriers when the semiconductor device is in blocking mode.

[0044] In other embodiments, only a uniformly charged field isolation region 30 is used to isolate the field plate 10 and the first semiconductor region 1.

[0045] Fig. Figure 3 shows an embodiment of a vertical power semiconductor device 201 in a section of a vertical cross-section. The power semiconductor device 210 is similar to the power semiconductor device 200 of Fig. 2. The excerpt from Fig. Figure 3, however, only shows the peripheral area 221. Furthermore, the edge closure structure of Fig. 3 a field plate 10 with an additional stage 72. According to one embodiment, a further negatively charged dielectric section 31 with increased charge carrier density per area is additionally arranged at the stage 72. Accordingly, an electric field maximum 17a in the semiconductor region 1 and near the stage 72 can be reduced or even avoided. In the embodiment of Fig. 3. The negative charge carrier density per area of ​​the field insulation region formed by sections 30, 31 and the two less or uncharged sections 80 changes stepwise in the horizontal direction. In other embodiments, the charge carrier density per area of ​​the charged sections changes continuously. For example, the charge carrier density per area can decrease continuously with the horizontal distance to the edge 71 and / or step 72 of the field electrode 10. Alternatively, the charge carrier density per area can also be essentially constant laterally.

[0046] With reference to Fig. Section 4 describes further embodiments. Fig. Figure 4 shows three semiconductor devices 101, 102, and 103 in a section of a vertical cross-section. Semiconductor devices 101 to 103 can correspond to sections of semiconductor devices 100, 200, and 201, which differ with respect to the Fig. 1 to 3 are explained. This means that structures 101 to 103 can be part of the field plate structure or an edge termination structure. However, they can also be arranged along a drift region 1, but further away from electrodes that can be operated as field plates. This is explained below with reference to the Fig. Sections 6 to 9 are explained in more detail. Accordingly, the electrodes shown, 10 to 12, are in Fig. 4 is optional.

[0047] The semiconductor devices 101, 102, 103 have a first semiconductor region 1 and a charged dielectric layer 30, which is arranged at the first semiconductor region 1 and contains fixed charges q. Typically, the charged dielectric layer 30 forms an interface 25 with the first semiconductor region 1. The interface 25 can be a major surface of a semiconductor body, an interface in a trench extending into the first semiconductor region, or an interface of a buried oxide layer. The charge type of the fixed charges q is the same as the charge type of the majority charge carriers of the first semiconductor region 1. In the embodiments of Fig. In section 4, the charged dielectric layer 30 is negatively charged. The charge carrier density per unit area of ​​the charged dielectric layer 30 is chosen such that the charged dielectric layer 30 is shielded against the incorporation of hot majority charge carriers generated in the first semiconductor region 1. In other words, a suitably charged dielectric layer 30 is used to protect the semiconductor device 101 to 103 against degradation induced by hot charge carriers. Due to the Coulomb shielding formed by the fixed charges q in the charged dielectric layer 30, the injection of hot electrons e - the charged dielectric layer 30 is prevented or at least reduced. The hot electrons e -Typically, solid charges are guided within the semiconductor region 1 at a safe distance from the charged dielectric layer 30 until they thermalize, recombine at a pn junction, are discharged at an electrode, or are injected into a non-critical dielectric region where solid charges do not, or hardly, affect the characteristics of the semiconductor device. Accordingly, the degradation of the charged dielectric layer 30 is prevented or at least reduced. This is shown by the dashed arrow for the semiconductor device 101.

[0048] The charged dielectric layer 30 of the semiconductor device 101 is formed by a dielectric layer 8 containing fixed charges q. For clarity, only a few negative charges q are shown in the dielectric layer 8. The dielectric layer 8 has a charge carrier density per unit area of ​​fixed charges q, which can be defined as the integrated charge carrier density of fixed charges per unit volume along a line r through the dielectric layer 8. The charge density per unit volume can vary or be homogeneously distributed along the path perpendicular to the interface 25, depending on the process used to generate charge in the layer 30.In particular, sections with regions of positive and negative charge could alternate along a line r through the dielectric layer 8, the net charge of which—that is, the integration of all charge carriers with the correct sign along line r—causes the described shielding effect against the injection of hot charge carriers. Typically, line r runs perpendicular to the interface 25 between the charged dielectric layer 8 and the first semiconductor region 1. The charge carrier density per unit area of ​​fixed charges q can be constant at least in certain sections or vary along a path s that runs essentially parallel to the interface 25.

[0049] According to one embodiment, the charged dielectric layer 8 is configured as a doped dielectric region with fixed charges. The charged dielectric layer 8 can, for example, be formed from silicon dioxide doped with aluminum, nitrogen, or cesium. Aluminum-doped and nitrogen-doped silicon dioxide is generally negatively charged, whereas cesium-doped silicon dioxide is generally positively charged.

[0050] The charge carrier density per unit area of ​​solid charges q depends on the dopant concentration. The magnitude of the charge carrier density per unit area is typically greater than approximately 10 11 / cm 2 , especially larger than about 10 12 / cm 2Higher charge carrier densities per area ensure better shielding against hot charge carriers. The upper limit of the charge carrier density per area is typically determined by the charge density per area that causes an avalanche multiplication in the adjacent semiconductor material of semiconductor region 1. Depending on the doping concentration, this upper limit is approximately 2 × 10⁻⁶. 12 / cm 2 up to about 4*10 12 / cm 2 For silicon. For SiC and GaN, the upper limit of the charge carrier density per unit area is approximately 2 × 10⁻⁶. 13 / cm 2 .

[0051] The charged dielectric layer 30 of the semiconductor device 102 has similar properties with respect to the fixed charge carrier density per unit area as the charged dielectric layer 30 of the semiconductor device 101. However, the charged dielectric layer 30 of the semiconductor device 102 is formed as a stack of different dielectric layers 8, 9 with fixed charges q, which are arranged between them as surface charges q. A first dielectric layer 8, e.g., a layer of SiO2, is arranged on the first semiconductor region 1, and a second gate dielectric layer 9, e.g., a Si3N4 layer, is arranged on the first gate dielectric layer 8. The charged layer 30 contains an interface 35 formed between the first and second gate dielectric layers 8, 9. Si3N4 has a lower band gap than SiO2. Accordingly, negative charges q are usually trapped in Si3N4 at or near the interface with SiO2.The charged dielectric layer 30 of the semiconductor device 102 can also contain a layer with a higher dielectric constant, such as aluminum oxide, hafnium dioxide, hafnium silicate, or zirconium dioxide. These materials can be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) and allow dielectric constants of over about 7 or even over about 20.

[0052] The charged dielectric layer 30 of the semiconductor device 103 has similar properties with respect to the fixed charge carrier density per area as the charged dielectric layer 30 of the semiconductor device 101 or the semiconductor device 102. It can be formed either from a doped layer 8 or a stack of layers. Since the interface 25 between the semiconductor region 1 and the charged doped layer 8 is curved, the charge carrier density per area of ​​fixed charges is typically determined for a curved path s that runs substantially parallel to the interface 25.The charge carrier density per area of ​​solid charges q is typically also defined as the integrated charge carrier density of solid charges per volume along a line r through the dielectric layer 8, where r is essentially perpendicular to the interface 25 between the charged dielectric layer 8 and the first semiconductor region 1. Accordingly, the charge carrier density per area of ​​the solid charges can change stepwise or continuously along the curved path s in the charged dielectric layer, the curved path s being essentially parallel to the interface 25.

[0053] Typically, the charged dielectric layer 30 is arranged between a field plate 10, 12 and a drift region 1 or between the drift region 1 and a section of a gate electrode 11, which can be operated as a field plate, and / or along the drift region on a main surface of a semiconductor device.

[0054] Fig. Figure 5 shows an embodiment of a vertical power semiconductor device 250 in a section of a vertical cross-section. The power semiconductor device 250 is also a vertical n-channel power semiconductor device, typically a DMOSFET (Double-Diffused Metal-Oxide Semiconductor Field Effect Transistor). As such, the section of Fig. 5 typically a unit cell of an active region of the semiconductor device 250. The power semiconductor device 250 contains a semiconductor body 40 between a main surface 15 and a lower surface 16. An n-type drift region 1 extends to the main surface 15 and contains a partially embedded p-type body region or trough 4, which also extends to the main surface 15 and over a p-type body contact region 6. +-type to a source electrode 90 arranged on the main surface 15. A gate electrode 11 is arranged on the main surface 15 and is insulated from the semiconductor body 40 by a gate dielectric layer 81 and a charged dielectric layer 30. The gate dielectric layer 81 and the charged dielectric layer 30 are arranged side by side in a direction parallel to the current flow in the channel region 50, i.e., in a horizontal direction in the embodiment of Fig. 5. Above a sufficiently high positive threshold voltage between the gate electrode 11 and the source electrode 90, an n-channel region 50 is formed in the body region 4. Accordingly, a current can flow between a source region 5 and the n +-type, which is connected to the source electrode 90, and a drain electrode 91 on the lower surface 16 in a forward current mode. The drain electrode 91 typically protrudes from the n via a drain contact region 3. + -Type in ohmic contact with the drift area 1.

[0055] The gate dielectric layer 81 typically borders the channel region 50 and has a lower maximum charge carrier density per area than the negatively charged dielectric layer 30, which is typically spaced away from the channel region 50. The maximum charge carrier density per area of ​​the gate dielectric layer 81 is typically less than 10 11 / cm 2 , especially under 10 10 / cm 2 Furthermore, the charged dielectric layer 30 is horizontally spaced from the body region 4. Accordingly, a low threshold voltage V is applied. th = V G - V SThe formation of the n-type channel 50 in the canal area 5 has been ensured.

[0056] In contrast, the maximum charge carrier density per area of ​​the negatively charged dielectric layer 30 is typically more than 10 11 / cm 2 , especially more than 10 12 / cm 2 , to ensure a sufficiently strong Coulomb shield for hot majority charge carriers that can be generated in blocking operation in drift area 1.

[0057] According to one embodiment, the semiconductor devices described herein are n-channel field-effect semiconductor devices, each containing a semiconductor body 40 with an active region. The active region comprises an n-type semiconductor region 1 and a negatively charged dielectric region 30, which is arranged at the n-type semiconductor region 1. The negatively charged region 30 has negative charges with a maximum charge carrier density per unit area greater than approximately 10 11 / cm 2 is, especially larger than about 10 12 / cm 2 This applies not only to vertical but also to lateral semiconductor devices, as shown in the following. Fig. 6 to 9 is shown.

[0058] Fig. Figure 6 shows an embodiment of a lateral MOSFET 300 in a section of a vertical cross-section. The lateral MOSFET 300 comprises a gate electrode 11, a source electrode 90, and a drain electrode 91, which are arranged on a main surface 15 of a semiconductor body 40. The MOSFET 300 is typically also a power semiconductor device. In the embodiment of Fig. 6 is a drift region 1 of n-type partially embedded in a body region 4 of p-type, which extends between the main surface 15 and a lower surface 16. The body region 4 is separated from the p-type by a body contact region. + -Type with the source electrode 90 in contact. The drift region 1 is separated from the drain contact region 3 by a drain contact region n. + -Type with drain electrode 91 and via a source region 5 from n + -Type with the source electrode 90 in contact. The drift region 1 extends to the main surface 15.

[0059] According to one embodiment, a negatively charged dielectric layer 30 is arranged on the drift region 1. Accordingly, a gate oxide layer 81, which insulates the gate electrode 11 from the semiconductor body 40, is protected from the injection of hot electrons in a blocking state of the semiconductor device 300. This is shown by the dashed arrow. In the avalanche state, carrier multiplication does not begin near the main surface 15, but buried in the crystal, e.g., at the level of the Fig. 6 electron path shown. In other words, a negatively charged dielectric layer 30 is arranged along at least part of the drift region 1 to prevent or at least reduce device degradation induced by hot supports. The charged dielectric layer 30 reduces the effective specific conductivity in the drift region 1 at the surface, leading to a higher and undesirable on-resistance of the device. This can be easily overcome by slightly increasing the doping of the drift region 1.

[0060] Fig. Figure 7 shows an embodiment of a lateral IGBT 400 in a section of a vertical cross-section. The lateral IGBT 400 is similar to the lateral MOSFET 300 of Fig. 6. Instead of the drain contact area from n + However, the -type is a collector area 3 from p +-type connected to electrode 91 of semiconductor device 400. In addition, body region 4 and drift region 1 are arranged on a common p-type substrate 7, which is also connected to electrode 90 via contact region 6 of the p-type substrate. + -type connected. Furthermore, electrodes 90 and 91 are typically referred to as emitter electrode 90 and collector electrode 91, respectively. Alternatively, contact areas not shown can be connected by p + -Type and n + -Type should be connected to electrode 90 to ensure reverse diode operation. Alternatively, contact area 3 can be connected from p + -Type and / or n + -Type upstream or around contact area 3 from p + -Type and / or n + -Type not shown n-areas may be present which are doped higher than drift area 1 and function as field stops in blocking operation.

[0061] According to one embodiment, a negatively charged dielectric layer 30 is arranged along at least a part of the drift region 1 in order to avoid or at least reduce degradation of the gate dielectric layer 81 induced by hot supports.

[0062] Fig. Figure 8 shows an embodiment of a lateral IGBT 401 in a section of a vertical cross-section. The lateral IGBT 401 is similar to the lateral IGBT 400 of Fig. 7. The semiconductor device 401 is, however, a silicon-on-insulator (SOI) device. Accordingly, a buried oxide layer (“BOX”) 35 is arranged between the common substrate 7 and the other semiconductor regions of the semiconductor body 40. Furthermore, an optional n-type well 2a is arranged between the collector region 3 and the drift region 1.

[0063] According to one embodiment, a further negatively charged dielectric region or layer 32 is formed by the buried oxide layer 35 (“BOX”) of the SOI device 401. Due to the Coulomb shielding generated by the fixed charges of the charged dielectric region layers 30 and 32, hot electron-induced device degradation can at least be reduced. The buried oxide layer 35 typically contains fixed negative charges with a charge carrier density per area of ​​approximately 10 11 / cm 2 or even over 10 12 / cm 2 .

[0064] Fig. Figure 9 shows an embodiment of a lateral IGBT 402 in a section of a vertical cross-section. The lateral IGBT 402 is similar to the lateral IGBT 401 of Fig. 8. However, only one section 32 of the BOX layer 35 is negatively charged. Typically, one section 32 extends horizontally at least between the body region 4 and the n-type trough 2a.

[0065] Fig. Figure 10 shows an embodiment of a lateral IGBT 403 in a section of a vertical cross-section. The lateral IGBT 403 is similar to the lateral IGBT 402 of Fig. 9. However, the IGBT 403 is formed on a partial SOI wafer (partial silicon on insulator wafer) with a charged partial BOX layer 33.

[0066] Of course, the charged dielectric layers of the Fig. 7 to 10 can be combined.

[0067] Regarding the Fig. Figures 11 to 19 describe methods for forming a semiconductor device 207 according to several embodiments. The focus of the layer formation is on the horizontal main surface 15. Without further description, doping regions in the semiconductor can be produced before, during, and / or after the described formation of the charged layer. In a first process, a wafer or substrate 40, comprising a horizontal main surface 15 and a semiconductor layer 1 of a first conductivity type (n-type), is provided. The semiconductor layer 1 extends to the horizontal main surface 15. The substrate 40 can be made of any suitable semiconductor material, such as Si, GaN, or SiC. A heavily doped contact layer 2 of the n-type is then formed. +The p-type can extend from the semiconductor layer 1 to a lower surface 16 located opposite the main surface 15, in order to subsequently form an ohmic connection to a drain metallization. Furthermore, the substrate 40 can already contain embedded body regions of a second conductivity type (p-type).

[0068] A first dielectric layer 8a is then formed on the horizontal main surface 15. The dielectric layer 8a typically contains SiO2 and can be formed by deposition and / or thermal oxidation. SiO2 can be deposited in a CVD process (chemical vapor deposition). Alternatively, silicon can be deposited on the semiconductor body 40 before thermal oxidation. In the case of a Si semiconductor body 40, the layer 8a is typically formed by thermal oxidation, but can also be formed by a CVD process.

[0069] In a subsequent process, a second layer 8b is formed on the first dielectric layer 8a. According to one embodiment, the second layer 8b is formed by atomic layer deposition (ALD). The thickness of layer 8b depends on the amount of charge to be trapped.

[0070] Typically, less than one molecular or atomic layer is deposited in an ALD cycle. One to several ALD cycles are typically used to form a thin film 8b. The resulting semiconductor structure 207 is in Fig. 12 shown.

[0071] A second dielectric layer 8c, e.g., a SiO2 layer, is then formed on the second layer 8b. The resulting semiconductor structure 207 is in Fig. 13 shown.

[0072] Typically, after the deposition of layers 8b and 8c, thermal steps are performed at temperatures of approximately 700°C to approximately 1250°C, particularly from approximately 800°C to approximately 1000°C. Accordingly, a dielectric layer 8 with fixed charges is formed on the main surface 15 and in contact with layer 1. Depending on the desired charge type, the second layer 8b typically contains aluminum or aluminum oxide to form a negatively charged layer 8, or cesium or cesium oxide to form a positively charged layer 8. The charge type of the fixed charges is the same as the charge type of the majority charge carriers of the first semiconductor region 1. The resulting structure 207 is described in Fig. 14 shown. The charged dielectric layer 8 and the first semiconductor region 1 form a dielectric-semiconductor interface at the main surface 15.

[0073] The charged layer 8 typically contains a net charge carrier density per area of ​​over approximately 10 11 / cm 2 and especially about 10 12 / cm 2 .

[0074] In another embodiment, layers 8a, 8b, and 8c form a SiO2-Si3N4-SiO2 sandwich structure with fixed negative charges. In this embodiment, no additional thermal tempering steps are typically performed to form a common layer 8. The sandwich or stacked structure can contain layers with a relative dielectric constant above approximately 7 or even 20. The individual layers can also possess fixed charges of different magnitudes and / or opposite signs.

[0075] In another embodiment, layer 8b is formed only partially on layer 8a. This can be achieved by depositing a structured non-stick layer prior to layer 8b and / or by masked etching of the charged layer 8 and / or by partial etching of the charged layer 8. For example, the charged layer 8 can be etched through a mask to the main surface 15. Accordingly, different charged regions 30 can be formed by the masked etching process, as shown in Fig. Figure 15 shows that the charge carrier density per unit area can vary in the horizontal direction. In another embodiment, the masked etching of the charged layer 8 stops before the main surface 15 is reached. This can also be used to vary the charge carrier density per unit area in the horizontal direction.

[0076] Subsequently, a dielectric region 80 is formed on the main surface 15, for example in a CVD process or by thermal oxidation. The dielectric region 80 typically has a lower charge carrier density per unit area than the charged layer 8, particularly below approximately 10 11 / cm 2 or under about 10 10 / cm 2 .

[0077] Subsequently, a drain electrode 91 is formed on the lower surface 16, and a field plate 10 is formed on the dielectric region 80, e.g., by depositing a metal or highly doped polysilicon. The field plate 10 is insulated from the semiconductor body 40. The resulting semiconductor structure 207 is in Fig. Figure 16 shows that the semiconductor structure 207 typically forms an edge termination structure located in a peripheral region 127 of a power semiconductor device. The fabrication processes are generally carried out such that the charged regions 30 and / or the dielectric region 80 are shielded against the incorporation of hot majority charge carriers generated in the first semiconductor region 1. Fig. Figure 16 describes a MOSFET as an example of the terminal designations. In the case of an IGBT or a diode, the metallization 91 formed on the lower surface 16 can be operated as a collector or cathode electrode.

[0078] The embodiment of Fig. The semiconductor device 207 shown in Figure 17 is similar to the semiconductor device 207 from Fig. 13. However, layer 8b is only partially deposited on layer 8a. This can be achieved, for example, by depositing a structured non-stick layer for the material of layer 8b before the ALD process of forming layer 8b.

[0079] Thermal steps are then carried out, as described in reference to Fig. As explained in section 14, two dielectric regions 30 and 80 with different charge carrier densities per unit area are formed on the main surface 15. The charged dielectric region 30 typically has a higher charge carrier density per unit area than the dielectric region 80. The resulting structure 207 is described in Fig. 18 shown.

[0080] Subsequently, a field plate 10 is formed on the dielectric region 80 and a drain electrode 91 on the lower surface 16. The field plate 10 is insulated from the semiconductor body 40. The resulting semiconductor structure 207 is in Fig. Figure 19 shows that typically the semiconductor structure 207 forms an edge termination structure located in a peripheral region of a power semiconductor device.

[0081] In other embodiments, the charged dielectric region 30 is formed in a lower section of a trench and a dielectric region 80 is formed in an upper section of the trench. The processes of forming the charged dielectric region 30 and the dielectric region 80 can be described similarly to those described with reference to Fig. The processes described in sections 11 to 19 are carried out on a trench surface. After forming a trench by etching in the semiconductor region 1, a conformal first dielectric layer is formed on the semiconductor region 1, at least within the trench. A second layer is then formed on the first dielectric layer by atomic layer deposition in a lower section of the trench. Subsequently, a second dielectric layer is formed on the second layer such that the charge type of the fixed charges is the same as the charge type of the majority charge carriers of the first semiconductor region 1. Thermal processes are then carried out to form a charged dielectric region 30 and a dielectric region 80 in the lower and upper sections of the trench, respectively.

[0082] Subsequently, an electrode structure is formed, at least in the lower section of the trench, such that the electrode structure is insulated from the semiconductor body by the charged dielectric region 30. The electrode structure can be a field plate or a gate electrode with a lower section configured to function as a field plate.

[0083] Typically, the trench is formed in an active region of a power semiconductor device. The charge carrier density per unit area is selected such that at least the charged dielectric region 30 is shielded against the incorporation of hot majority charge carriers generated in the first semiconductor region when the semiconductor device is operated in an avalanche mode. Accordingly, the semiconductor device is protected against degradation induced by hot charge carriers.

[0084] Of course, the charged dielectric region 30 on the trench can also be formed as a stack of different dielectric layers containing fixed charges at or near an interface between the stack of different dielectric layers.

[0085] Furthermore, p-type body contact regions, p-type body regions, and n-type source regions can be formed after or before the formation of the charged layer 8.

[0086] Subsequently, a source metallization in contact with the source regions and the body contact regions is typically formed by physical vapor deposition (PVD) and / or by electroplating.

[0087] Fig. Figure 20 shows an embodiment of a vertical power semiconductor device 307 in a section of a vertical cross-section. In the section of Fig. Figure 20 shows only a peripheral region or edge region 320 with an exemplary edge termination and an adjacent active region 310. Typically, another edge region 320 is also provided to the left of the active region 310. For example, the edge region 320 can be arranged around the entire active region. The adjacent active region 310 of the semiconductor body 40 typically contains several transistor structures and / or diode structures, for example, several field-effect transistor cells, as described in [reference to]. Fig. Figure 1 explains. Typically, a first n-type semiconductor region 1, which can form a drift region 1 in the active region 310, reaches the main surface 15 in the peripheral region 320. At least in the active region 310, a pn junction 14 is arranged between the first semiconductor region 1 and the main surface 15. The pn junction 14 of the semiconductor device 307 is formed between the first semiconductor region 1 and a fourth p-type semiconductor region 4. The semiconductor region 4 can, for example, form a body region or an anode region in the active region 310. Typically, the fourth semiconductor region 4 is in ohmic contact with a metallization 90, which can form a source electrode or an anode metallization. The metallization 90 can be arranged on the main surface 15 and form an ohmic contact with the fourth semiconductor region 4 there.

[0088] How Fig. As further illustrated in Figure 20, the pn junction 14 can extend parallel to the main surface 15. Analogously, as with reference to Fig. As explained in section 2, the first semiconductor region 1 of the semiconductor device 307 is also completely or partially cleared during a blocking mode or reverse-bias operation. To ensure a high reverse voltage in reverse-bias operation, an edge termination structure is provided in the peripheral region 320.

[0089] According to one embodiment, the edge termination structure comprises a vertical trench 62 extending from the main surface 15 into the first semiconductor region 1 in the peripheral region 320 and containing a dielectric layer 30 with fixed negative charges arranged vertically both below and above the pn junction 14. Typically, the trench 62 borders the pn junction 14. The concentration of the fixed negative charge carriers can be selected, for example, essentially independently of the vertical distance to the main surface 15. For instance, as shown in Fig. Figure 20 illustrates that the dielectric layer 30 along the side walls of the trench 62 and the trench floor is designed as a substantially uniform layer with a constant negative charge carrier density per area.

[0090] In comparison to lateral edge terminations such as field rings, field plates or edge terminations that work with a lateral variation of a doping concentration (VLD, from English: "variation of lateral doping"), the edge termination structure of the semiconductor device 307, like other edge terminations with a vertical groove, requires significantly less space.

[0091] Typically, the space requirement can be reduced by more than a factor of 2 or even 5 compared to lateral edge terminations with field plates or field rings, or VLD edge terminations, given a specific blocking capability. However, compared to known vertical trenches used as edge terminations, which are filled with an insulator, e.g., silicon oxide, the edge termination structure of the semiconductor device 307 is significantly more robust against positive surface charges, since these can be at least partially compensated by the fixed negative charges if necessary. While positive surface charges can, in principle, also be compensated by an additional p-doped layer in the region of the vertical trench, the doping dose introduced here must be relatively precisely controlled and can only compensate for surface charges to a certain extent, as these vary from wafer to wafer and also across the wafer itself.Another disadvantage is that this p-doped region can inject free charge carriers when connected to the cathode potential. This can negatively affect the robustness when switching off the device.

[0092] According to one embodiment, the vertical groove 62 is completely covered with a dielectric covering 84, e.g., a silicon nitride covering. This prevents external contamination of the groove 63. This enables high long-term stability of the edge termination structure of the semiconductor device 307.

[0093] According to a further embodiment, the charge carrier density per unit area of ​​the fixed negative charges of the dielectric layer 30 decreases stepwise or continuously with increasing vertical distance from the main surface 15. This provides an edge termination structure with a vertically varying charge carrier concentration of the fixed negative charges. This acts similarly to a VLD edge termination folded inwards. Thus, even a relatively wide scattering or some drift of the surface charge during operation of the semiconductor device 307 leads to no or only a slight reduction in the blocking capability. The gradient of the fixed negative charge in the vertical direction is typically adapted to the expected scattering of the surface charge.In addition, unlike edge terminations where dopants were introduced into the semiconductor area of ​​the trench, the injection of free charge carriers from the trench 62 can be excluded, thus increasing the robustness of the edge termination during shutdown processes.

[0094] Typically, the dielectric layer 30 consists of an aluminum-doped silicon oxide or an aluminum-doped silicon oxynitride. The concentration of the fixed negative charges can be precisely adjusted and / or varied over a wide range via the aluminum doping. This is referred to in the Fig. 29 to 32 are explained in detail. However, it is also possible to use several layers with fixed negative charge carriers on top of each other, optionally separated from each other by uncharged dielectric layers.

[0095] In further embodiments, the dielectric layer 30 consists of at least two adjacent layers of different dielectrics, e.g. a silicon oxide layer and a silicon nitride layer, with fixed negative interfacial charges at the respective interfaces between the adjacent layers.

[0096] According to a further embodiment, a cavity 83, e.g. centrally in the horizontal direction, is arranged in the trench 62. This allows mechanical stress due to the semiconductor-dielectric interface 25 to be at least reduced.

[0097] Fig. Figure 21 shows an embodiment of a vertical semiconductor device 407 in a section of a vertical cross-section. Typically, the semiconductor device 407 is a power semiconductor device. For these embodiments, the section corresponds to Fig. 21 shows only one unit cell of a plurality of unit cells in the active region of the semiconductor device 407. The in Fig. The semiconductor device 407, shown as an example in Figure 21, can be operated as a so-called TEDFET (Trench Extended Drain Field-Effect Transistor). The semiconductor device 407 comprises a conventional MOS transistor structure, shown in the left half, with a drift region 1 located between a drain region 3 and a body region 4. The body region 4 is located between the drift region 1 and a source region 6. The MOS transistor structure also includes a gate electrode 11, which is located adjacent to the body region 4 and is separated from both the body region 4 and the drift region 1 by a gate dielectric 81. Within the body region 4, the gate electrode 11 extends from the source region 6 at least as far as the drift region 1, separated by the gate dielectric 81, and serves to control a conducting channel (not shown in Figure 21). Fig. 21) in body region 4 between source region 6 and drift region 1. In the example according to Fig. Figure 21 shows the MOS transistor structure as a vertical trench transistor structure in which the gate electrode 11 is arranged in a trench extending vertically along the semiconductor body 40 in which the MOS transistor structure is integrated. This is, however, only one example. The MOS transistor structure can also be implemented with a planar gate electrode. In addition to the MOS transistor structure, the semiconductor device 407 includes a drift control region 1', which is arranged horizontally adjacent to the drift region 1 and is dielectrically isolated from the drift region 1.

[0098] According to one embodiment, the semiconductor device comprises a dielectric layer 30 with fixed charges of the charge type of the majority charge carriers of the adjacent drift region 1. The dielectric layer 30 with fixed charge carriers also borders the body region 4 and the drift control region 1'. Typically, the dielectric layer 30 forms a so-called drift control region dielectric or accumulation dielectric 30.

[0099] The function of the drift control region 1' is to control a conducting channel in the drift region 1 along the accumulation dielectric 30 when the MOS transistor structure is in an on-state or is driven to conduct. The drift control region 1' therefore serves to reduce the on-resistance R. ON (engl.: “on-resistance”) of the entire transistor component.

[0100] Unlike conventional MOS transistors, the drift region 1 in this semiconductor device (regardless of the type of MOS transistor structure) can be n-doped or p-doped. For example, if the drift region 1 is n-doped in an n-type MOS transistor structure, an accumulation channel forms along the drift control region dielectric 30, controlled by the drift control region 1'. If the drift region 1 is p-doped in an n-type MOS transistor structure, an inversion channel forms along the accumulation dielectric 30 in the drift region 1 when the device is in the on-state. Like a conventional MOS transistor, this device is in the on-state when a voltage (V) is applied. S , V D ) between the source and drain regions 6, 3 or the source and drain connections S, D, and when a suitable electrical potential (V) is applied G) is applied to the gate electrode 11, creating a conducting channel in the body region 4 between the source region 6 and the drift region 1. For an n-type MOS transistor structure, the voltage to be applied between drain D and source S (V) is D- V S ), to switch the component to its on-state, a positive voltage and the gate potential V G is a positive potential in relation to the source potential V SWhen the transistor 407 is in its on-state, charge carriers are required in drift region 1 to create the accumulation or inversion channel along the accumulation dielectric 30 in drift region 1. In a transistor 407 with an n-type MOS transistor structure, p-type charge carriers (holes) are required in drift control region 1' to create this conducting channel. These charge carriers are only needed in drift control region 1' when the device is in its on-state. When the device is in its off-state, the charge carriers are removed from drift control region 1', and—corresponding to drift region 1—a space charge region or depletion region forms in drift control region 1'. In this context, it should be noted that drift control area 1' can be of the same line type as drift area 1 or of a complementary line type.

[0101] The drift control region 1' can be coupled to the drain region 3 via a rectifier element 54, such as a diode. The rectifier element 54 is polarized such that a discharge of the drift control region 1' to the electrical potential V D The drain region 3 is prevented when the device is in its on-state. In an n-type transistor device 407, an anode terminal of the rectifier element 54 is coupled to the drift control region 1', while a cathode terminal is connected to the drain region 3. Another connecting region 3', located between the drift control region 1' and the rectifier element 54, is optional and is of the same conductor type as the drift control region 1, but typically more heavily doped.

[0102] In other embodiments, instead of or in addition to the connection area 3', a further insulating area is provided, so that the drift control area 1' is completely dielectrically isolated from the drift area 1. The rectifier element 54 is logically connected between the drain electrode D and the lower connection area 3' and, in the implementation, can also be located on or near the upper main surface 15, in particular outside an edge termination area. In this case, appropriate electrically conductive connections must be provided (not shown).

[0103] To provide charge carriers in the drift control region 51 when the device is first switched on, the drift control region 1' can be coupled to a terminal 4', which in the case of an n-type device 407 is p-doped, at the gate terminal G. In this case, charge carriers are provided from a gate driver circuit that is coupled to the gate terminal G during operation of the transistor device 407. A diode 55, coupled between the gate terminal G and the connection region 53, serves to prevent the drift control region 51 from discharging towards the gate terminal G.The charge carriers removed from drift control region 1 when the device is off are typically stored in a capacitive structure with an electrode 11' that is separated from drift control region 1' and connection region 4' by a dielectric 81' and contacted with source S, until the device is next switched on, with the capacitive structure being connected between source S and drift control region 1'. Alternatively, and not shown, the charge carriers in drift control region 1' can also be coupled in by other means, e.g., via an additional external contact or via another charging circuit, e.g., from the load circuit. In these cases, diode 55 can be omitted. Alternatively or additionally, diode 56 can be connected between connection region 4' and source electrode S, with the anode of diode 56 being in electrically conductive contact with source electrode S.This additional diode 56 can serve to dissipate thermally generated leakage current from the drift control region 1' in the case of reverse polarity, as soon as the potential in the connection region 4' exceeds the blocking capability of the optional diode 56.

[0104] To achieve the lowest possible on-resistance R ON To enable the semiconductor device to function optimally, the cell grid p must be chosen to be as small as possible. However, this typically leads to problems for a given density of the fixed positive interface charges Q. OX to a corresponding reduction in the blocking capability, as will be shown below.

[0105] Typically, the accumulation dielectric is formed as thermal SiO2. However, this oxidation of the silicon semiconductor body 40 typically leads to a certain density of fixed positive interfacial charges Q. OXin the lower few nanometers of the thermal oxide adjacent to the silicon. For good thermal oxides, the density of solid positive interfacial charges Q can be OX in the range of approximately 1...10·10 10 Elementary charges per cm 2 The concentration of elementary charges in a volume, or the surface charge density, will in the following be simplified as charges per cm³ and charges per cm², respectively.

[0106] With a small grid spacing of the accumulating dielectrics, e.g., in power semiconductor devices with many cells, the reverse voltage of the device is strongly influenced by the oxide charges. The area-specific charge due to the accumulating dielectrics alone, Qeff, is approximately Qeff=QOX⋅4⋅tp, where t represents the vertical extent of the accumulation dielectrics or the depth of the vertical trenches 64 containing the accumulation dielectrics, and p represents the grid (or "pitch") of the cells. The vertical trenches 64 are typically only about 30 nm to about 60 nm wide, but extend to a depth of about 50 µm into the semiconductor body 40. They therefore typically have a high aspect ratio of up to 1000 or more.

[0107] Within each cell there are two accumulation dielectrics, i.e., four interfaces, which is where the factor of 4 in the above formula comes from. Once the value Q eff the so-called breakthrough charge Q BR of about 1.5 10 12 / cm 2 Once this value is reached for silicon, the component can no longer achieve a blocking voltage defined by the vertical extent t without further measures.

[0108] According to one embodiment, the drift region 1 is of n-type and fixed negative charges are incorporated into the dielectric layer 30, which can be operated as an accumulation dielectric. This allows positive charges incorporated during thermal oxidation to be compensated as needed, thus ensuring high blocking capability of the semiconductor device with simultaneously low on-resistance R. ON This is ensured by a small grid of vertical trenches 64.

[0109] Typically, the dielectric layer 30 consists of an aluminum-doped silicon oxide or an aluminum-doped silicon oxynitride, the concentration of which of the fixed negative charges can be precisely and widely adjusted and / or varied via the aluminum doping.

[0110] For example, aluminum, e.g., in the form of Al₂O₃ or AlN, can be deposited onto a thermal oxide by means of one or more atomic layer deposition processes, followed by thermal processes, at least on the side walls of the vertical trenches 64, which typically extend from the main surface 15 to the back surface 16, resulting in solid negative charges. The concentration of the solid negative charges can be very precisely controlled by the number of atomic layer deposition cycles and, if necessary, by additionally covering a defined number of trenches 64 during one or more atomic layer deposition processes if the charge density is too high.

[0111] After atomic layer deposition, the fixed negative charges are located on the surface of the thermal oxide. Subsequent thermal oxidation further moves the fixed negative charges away from the semiconductor material, while maintaining their stability. Typically, thermal oxidation is carried out until the dielectric layer 30 has grown together with the fixed negative charges, i.e., the trench 64 is filled. Accordingly, the charge carrier density per unit area of ​​the fixed negative charges of the dielectric layer 30 will exhibit a highest value in a horizontal plane approximately midway between the third semiconductor region 1' and the first semiconductor region 1. However, thermal oxidation can also be extended to produce a greater oxide thickness at the chip front or main surface 15. In this case, the buried oxide regions typically do not become any thicker.

[0112] Furthermore, the charge carrier density per area of ​​the fixed negative charges of the dielectric layer 30 can be adjusted, for example, by choosing the precursor molecules, i.e., the starting material of the atomic layer deposition processes, so that it decreases stepwise or continuously with increasing distance to the main surface 15.

[0113] Fig. Figures 22-28 show exemplary processes for the fabrication of a semiconductor device 307, as it relates to Fig. 21 explained, according to one or more embodiments in vertical sections. This shows Fig. 22 a semiconductor body 40, typically a silicon semiconductor body 40, extending from a main surface 15 to an opposite surface 16. Oxide bridges 85 are embedded in the semiconductor body 40. The in Fig. The structure shown in Figure 22 can be provided, for example, by generating LOCOS structures 85 on a substrate 1a and subsequent lateral overgrowth using a selective epitaxy step and further optional epitaxy layers to form an epitaxial region 1b. The doping of the epitaxial layers can be appropriately adapted to the semiconductor device to be fabricated.

[0114] Subsequently, 17 deep grooves 65 are etched over a hard mask, completely surrounding the oxide ridges 85. The resulting semiconductor structure 307 is in Fig. 23 shown.

[0115] In the deep trenches 65, a sidewall oxide 18 is produced, e.g., by thermal oxidation and subsequent anisotropic etching at the bottom of the deep trenches, and removed again on the semiconductor mesa that does not border the buried oxide ridges 85, e.g., by means of a carbon hard mask. Now, in addition, retention marks 95 are etched into the remaining hard mask on the semiconductor mesas that lie above the buried oxide ridges 85, and the thin oxide layers on the exposed mesa are removed by wet chemical means. The resulting semiconductor structure 307 is in Fig. 24 shown.

[0116] The in Fig. The 24 dashed-line retaining marks 95 are only local openings in the hard mask and are intended to establish a direct connection between the semiconductor layer 1b via the oxide bridges 85 and a subsequently produced semiconductor filling.

[0117] Starting from the oxide-free semiconductor mesas, the deep trenches 65 are filled laterally by an epitaxial process. The process conditions are typically similar to those for lateral overgrowth. Simultaneously, the hard mask remnants are epitaxially overgrown from the retention markers 95 to create a semiconductor filling 1c. The resulting semiconductor structure 307 is in Fig. 25 shown.

[0118] The protruding semiconductor layer 1c can then be back-polished to the height of the hard mask 17, e.g., using CMP. The resulting semiconductor structure 307 is in Fig. 26 shown. This exposes the hard mask 17, which preferably consists of SiO2 and has a direct connection with the underlying sidewall oxide 18 and the buried oxide struts 85.

[0119] The hard mask 17, the sidewall oxide 18, and the buried oxide bridges 85 can be removed by wet chemical etching, e.g., in RF-containing solutions, especially highly concentrated (approx. 50%) RF solutions. The resulting semiconductor structure 307 is in Fig. 27 shown. The semiconductor regions above the original buried oxide bridges are held sufficiently stable by the Si bridges extending from the holding marks 95.

[0120] Subsequently, a dielectric layer 30 with fixed negative charges can be produced by thermal oxidation and atomic layer deposition processes. The resulting semiconductor structure 307 is in Fig. 27. The generation of the dielectric layer 30 with fixed negative charges is shown with reference to the Fig. 29-35 explains in detail and can include the production of an aluminum oxide or aluminum nitride layer on a thermally produced thin oxide, hereinafter also referred to as pad oxide or start oxide, as well as further thermal oxidation processes. Voids 86 can remain in the area of ​​the original buried oxide ridges 85 to reduce mechanical stresses. The main surface 15 can be flattened via a further CMP step (not shown) so that regions 1b and 1c and the dielectric layers 30 form a continuous surface.

[0121] Subsequently, doping steps can be performed to create further semiconductor regions. Typically, at least one pn junction is formed, which may be adjacent to the trench 62. For example, p-doped body regions, body contact regions, or anode regions and / or n+-doped source regions can be formed from the main surface 15. Of course, these further semiconductor regions can also be formed, at least partially, with fixed negative charges prior to the formation of the trench 62 or the silicon oxide layer 30.

[0122] Subsequently, electrode structures such as gate electrode structures and source electrodes can be created on or near the main surface 15, as well as a drain electrode on the opposite surface 16, to produce, for example, a semiconductor device 307 that can be operated as a TEDFET.

[0123] A particular advantage is that the dielectric layer 30, which acts as an accumulation dielectric, extends with fixed negative charges around the base of the drift control regions 1' in the semiconductor device 307 without a seam, and thus there are no weak points for electrical breakdowns there.

[0124] Fig. Figures 29-34 show manufacturing processes for vertical trenches 62 containing a dielectric with fixed negative charges, according to one or more embodiments in vertical sections. These manufacturing processes can be used for the fabrication of edge termination structures, as exemplified by reference to Fig. Section 20 explains the fabrication of TEDFET structures, as exemplified with reference to Fig. 21 explains, as well as for the production of semiconductor devices with trench electrodes, as exemplified with reference to Fig. 1 explained, can be used. Furthermore, the manufacturing processes can also be used for those related to the Fig. 2 to 10 of the described semiconductor devices are used, whereby the atomic layer deposition processes described below are then not carried out on trench surfaces but typically on the main surface of the semiconductor body.

[0125] First, a semiconductor body 40, typically a silicon semiconductor body 40, is provided, having a main surface 15 and a first semiconductor region 1 of n-type. The first semiconductor region 1 can extend from the main surface 15 to an opposite back surface 16.

[0126] Subsequently, at least one trench 62 extending from the main surface 15 into the first semiconductor region 1 is created. Typically, the at least one trench 62 is created by masked etching. The resulting semiconductor structure 507 is in Fig. Figure 29 shows this. Typically, the trench 62 is a vertical trench. Depending on the semiconductor device being manufactured, a large number of trenches 62 can be produced in parallel, e.g., in the active region of a TEDFET. The trenches 62 can also have a high aspect ratio of up to 1000 or even more. However, it is also possible to produce only one, e.g., a circumferential trench 62 in a peripheral region to create an edge termination structure. In another embodiment, both a trench 62 in the peripheral region and one or more trenches 62 in the active region are etched into the semiconductor body 40.

[0127] Subsequently, an optional thin thermal pad oxide 30a is typically generated at least on the surface of the trench 62 to create defined and good interfacial conditions. The resulting semiconductor structure 507 is in Fig. 30 shown.

[0128] Subsequently, atomic layer deposition is carried out using a metal-organic precursor or metal-organic starting material on the surface of the trench 62 or the pad oxide 30a. This results in the formation of one or more monolayers 30b of organometallic compounds. The resulting semiconductor structure 507 is in Fig. Figure 31 shows. Typically, an organaluminum compound, e.g. TMA (trimethyl-aluminum), is used as a precursor.

[0129] Atomic layer deposition enables the precursor to create a surface coating through a first reaction step, preventing further precursor molecules from adhering to it. In the case of TMA, the precursor reacts by cleaving a ligand (here: a methyl group) and attaching a bond of the central atom (Al atom) to the surface. The cleaving of the ligands can occur, for example, thermally. The two remaining protruding methyl groups sterically prevent further TMA molecules from attaching to the surface. This allows for a defined adjustment of the doping and thus the density of the fixed negative charges.

[0130] After a rinsing step to remove unbound precursor molecules, the remaining ligands can be cleaved off, for example, thermally. Depending on the surrounding medium and temperature, an aluminum oxide layer (in an oxygen-containing environment) or an aluminum nitride layer (with nitrogen purging) can be formed. The temperatures typically range from approximately 700°C to approximately 1250°C, particularly from approximately 800°C to approximately 1100°C. This enables self-limiting incorporation of controlled aluminum doping. The doping dose can be adjusted by the number of atomic layer deposition cycles in the case of TMA in steps of approximately 2 to 3 to 10. 11 / cm 2 be hired.

[0131] Subsequently, the layer thickness can be further increased by additional thermal oxidation, thereby forming a metal-doped (aluminum-doped) silicon oxide layer 30 with fixed negative charges, with temperatures typically ranging from about 700°C to about 1250°C, particularly from about 800°C to about 1100°C. The resulting semiconductor structure 507 is in Fig. 32 shown.

[0132] The dose of the incorporated charge is typically in the range of the breakdown charge of silicon. When using TMA as a precursor, this corresponds to approximately 5 to 25 atomic layer deposition cycles. TMA is particularly well-suited as a precursor when a homogeneous charge distribution across the trench depth is desired, due to its relatively small size. Trenches 62 with a sufficiently wide profile or a sufficiently high aspect ratio (i.e., the ratio of depth to width of the trench 26) are also advantageous for this purpose.

[0133] According to a further embodiment, a vertically decreasing density of the fixed negative charges in the trench 62 is achieved by means of atomic layer deposition with varying doping. To realize this vertically varied doping (VVD), the atomic layer deposition process described above is carried out, for example, in a trench 62 that is as narrow as possible, e.g., in the peripheral region of the semiconductor device. The trench 62 has a high aspect ratio, e.g., greater than approximately 50. In particular, the use of a larger precursor molecule instead of the relatively small TMA can lead to a depletion of the precursor with increasing trench depth due to diffusion limitations. Thus, the amount of aluminum deposited can be varied across the trench depth by means of depletion. Alternative and somewhat more voluminous precursors for aluminum doping are, for example,Materials of the genus Tris(dialkylamino)Aluminum such as TDEAA (Tris(diethylamino)Aluminium) or Tris(diisopropylamino)Aluminum (Al(DIA)3, 2) and Tris(bis(trimethylsilyl)amino)Aluminum (Al(TMSA)3).

[0134] The thermal oxidation can be continued until the trench 62 is at least completely filled. The resulting exemplary semiconductor structure 507 is shown in Fig. Figure 33 shows that, in the case of complete oxidation of the trench 62, the fixed negative charges in the trench 62 are arranged symmetrically, as indicated by the dotted curve s in Figure 33. Fig. Figure 33 illustrates this. The fixed negative charges act uniformly on both interfaces between the oxide and the semiconductor material. This enables very good compensation of positive fixed charges.

[0135] When manufacturing a TEDFET, charge compensation in the low-doped drift region or drift control region is important. In the region of an optional high-doped field-stopping region, i.e., also below the drift control region, the interface charge of the oxide is not critical, since no high electric field is present there in blocking mode.

[0136] Subsequently, the silicon oxide layer 30 with fixed negative charges can be removed by planarizing or etching on the main surface 15. The resulting semiconductor structure 507 is in Fig. 34 shown.

[0137] Trench 62 can now be provided with a passivation layer, e.g. made of a polyimide or benzocyclobutane (BCB), to prevent external contamination with charge carriers.

[0138] As an alternative to completely filling the trench 62 by thermal oxidation, the trench 62 can also be completely or partially filled by a CVD process, whereby any voids remaining in the trench 62 can contribute to reducing mechanical stresses.

[0139] According to another embodiment, starting from the in Fig. Figure 30 illustrates a semiconductor structure 507 in which one or more further atomic layer deposition processes with subsequent thermal oxidation are carried out to generate one or more additional silicon oxide layers 31 with fixed negative charges on the silicon oxide layer 30 with fixed negative charges. An exemplary resulting semiconductor structure 507 is shown in Figure 30. Fig. Figure 35 shows that in this way the charge carrier density per area of ​​the fixed negative charges in the trench 62 can be reduced stepwise with increasing distance from the main surface 15 or trench depth.

[0140] Subsequently, trench 62 can be completely filled, for example by thermal oxidation, and / or layers 30 and 31 can be removed from the main surface.

[0141] Subsequently, as with reference to Fig. 28 explains in detail the doping steps for generating body and source regions, as well as the fabrication of electrode structures, to produce, for example, a TEDFET with a dielectric layer 30 acting as an accumulation oxide with fixed negative charges and / or a vertical edge termination with a dielectric layer 30 with fixed negative charges arranged in the vertical trench 62. For these applications, the charge carrier density per area of ​​the fixed negative charges parallel to the main surface 15 is typically adjusted via atomic layer deposition such that positive fixed charges can be compensated, for example, by thermal oxidation processes. Typically, the charge carrier density per area of ​​the fixed negative charges for these applications is about 10 11 / cm 2 or even slightly less. For example, a good thermal oxide can have a thermal conductivity of approximately 3...7 × 10⁻⁶. 10 / cm 2They exhibit positive charges per interface with the silicon semiconductor, which are almost compensated, completely compensated, or even slightly overcompensated by the corresponding fixed negative charges. For example, the dielectric layer 30 can also have a net negative charge.

[0142] On the other hand, those relating to the Fig. Sections 29 to 35 also described the process for manufacturing semiconductor devices whose dielectrics are protected against degradation due to hot charge carriers during device operation by the incorporation of fixed negative charges. These devices were described in relation to the Fig. Sections 1 to 10 are explained. For these applications, the charge carrier density per unit area of ​​the fixed negative charges is typically greater than 10. 11 / cm 2adjusted to ensure sufficiently good protection against the degradation of the dielectrics, whereby the total charge in conjunction with the dopant charge should not become too high in order not to jeopardize the blocking capability of the component.

[0143] As in Fig. 36 shown relationship between breakdown voltage V br and charge carrier density per area of ​​net charge Q OX The accumulation oxide of two exemplary power TEDFETs with an accumulation oxide grid spacing of approximately 6 µm shows that these devices achieve a maximum breakdown voltage at approximately a negative net charge with a charge density per area and interface between the accumulation oxide and semiconductor of approximately 2·10 10 / cm 2 up to about 4·10 10 / cm 2 , where in this example a donor base dosing of approximately 1·10 14 / cm 3was assumed. The lateral integral of the donor base doping, and thus the surface charge in the semiconductor in reverse bias, is approximately 6 × 10 with these numerical values. 10 / cm 2 , which are two interfaces between the accumulation oxide and the semiconductor. In the reverse bias state, the negative charge of the accumulation oxide compensates for the positive donor charge, resulting in a net reduction, ideally an intrinsic charge, within the reverse bias semiconductor volume. The in Fig. The 36 curves shown were numerically determined for an accumulation oxide with singly charged fixed charges for two different active device thicknesses, considering only the semiconductor volume and neglecting any reduction in blocking capability, e.g., due to a lateral edge termination. The curve with triangles indicates the blocking capability for a thickness of the lightly doped drift zone of 33 µm, while the curve with circles describes the blocking capability at a drift zone thickness of 50 µm. The thicker the drift zone, the higher the maximum achievable blocking capability, but the steeper its decline also becomes with increasing net charge in the semiconductor, taking into account the fixed interfacial charges to the accumulation oxide. In the example of Fig. 36 can, with a drift zone thickness and usual safety margins, achieve the guaranteed blocking capacity of 600V for accumulator oxide charges between approximately -1·10 11 / cm 2 and about +8·10 10 / cm 2 For smaller drift zone thicknesses and / or higher required blocking capacities, the permissible window of the net charge of the accumulation oxide is reduced.

[0144] Fig. Figure 37 shows an embodiment of a vertical semiconductor device 408 in a section of a horizontal cross-section. The vertical semiconductor device 408 is typically a TEDFET. For example, the one in Fig. Figure 37 shows a section of a central horizontal cross-section through an active region of a TEDFET with multiple cells as in Fig. 21 are shown.

[0145] In the exemplary embodiment of Fig. In embodiment 37 with five cells, five drift regions 1 are separated from a common drift control region 1' by accumulation oxides 30, 35 arranged in moat-shaped vertical trenches. In other embodiments, several drift control regions are separated from a common drift region 1 by corresponding accumulation oxides 30, 35. Depending on the specification, the semiconductor device 408 can have fewer or more than five cells.

[0146] According to a further development, only a portion of the accumulation oxides 30, 35 is configured as a dielectric layer 30 with fixed negative charges. In the exemplary embodiment of Fig. 37 This is only the case for the central accumulation oxide 30, which typically has a negative net charge that can be adjusted via atom charge deposition processes. In the following, the accumulation oxides 35 without or with a positive net charge are also referred to as further accumulation oxides 35 or further dielectric layers, respectively.

[0147] Typically, singly charged negative charges with a charge density per area of ​​about 2 10 are used for production via an atomic layer deposition cycle, e.g. with TMA as a precursor. 11 / cm 2 applied. However, to compensate for positive oxide charges, often only a negative charge is applied with a charge density of singly charged charges per area of ​​only about 4...6 10 . 10 / cm 2required. To achieve an averaged compensation for the typically positive dielectric charges of thermal oxides and the fixed negative dielectric charges of aluminum-doped oxides or oxynitrides via atomic layer deposition in the semiconductor device, the additional accumulation oxides 35 are not aluminum-doped. Typically, the additional accumulation oxides 35 are thermal oxides and therefore have a positive net charge. In other words, the vertical device 408 is typically a TEDFET with one or more dielectric layers 30 with a negative net charge as an accumulation oxide and one or more additional dielectric layers 35 with a positive net charge as an accumulation oxide. This allows the average net charge to be very finely adjusted and, for example, compensated.

[0148] Typically, only a portion of the vertical trenches, for example, about every third to fifth vertical trench, preferably about every fourth vertical trench, has a dielectric layer 30 with a net negative charge, while the other vertical trenches each have a dielectric layer 35 with a net positive charge, e.g., a thermal oxide. Experimentally, a mean net surface charge for undoped thermal oxides of about 5 × 10⁻⁶ was determined. 10 Elementary charges per cm 2 The net area charge of aluminum-doped thermal oxides produced by an atomic layer deposition cycle with TMA as a precursor is approximately -2 10 11 Elementary charges per cm 2Thus, a good charge compensation is achieved in this numerical example by a ratio of approximately 1:3 to approximately 1:5 between the total area of ​​the dielectric layer 30 with net negative charge and the total area of ​​the other dielectric layer 35 with net positive charge. Naturally, with changes in the positive and / or negative surface charge density of the oxides, correspondingly different compensation ratios result, i.e., a correspondingly higher or lower proportion of the accumulation oxides with negative oxide charge.

[0149] In other embodiments, a dielectric layer 30 with a net negative charge is arranged in each of the vertical grooves. This allows for higher donor doping levels, e.g., more than 1 × 10⁻⁶. 14 / cm 3 The resulting surface charge in the semiconductor is well compensated in the blocking case.

[0150] It is understood that oxide regions with different net charges can also be used for charge compensation in vertical trenches. This is discussed in relation to the following. Fig. 38 explained.

[0151] Fig. Figure 38 shows an embodiment of a vertical semiconductor device 409 in a section of a horizontal cross-section. The vertical semiconductor device 409 is also typically a TEDFET. In the exemplary embodiment of Fig. Figure 38 shows three cells. The drift regions 1 are separated from a common drift control region 1' by dielectric layers 30 arranged in moat-shaped vertical trenches and acting as accumulation oxides. In other embodiments, several drift control regions are separated from a common drift region 1 by corresponding dielectric layers 30. The dielectric layers 30 consist of sections 38 with a net negative charge, e.g., aluminum-doped oxides or oxynitrides, and sections 39 with a net positive charge, e.g., undoped thermal oxides or cesium-doped oxides or oxynitrides.

[0152] Typically, the area ratio of sections 38 and 39 is in a range of about 3 to about 5 to ensure good charge compensation.

[0153] Typically, the common drift control region 1' is surrounded by a dielectric region 35a arranged in a further circumferential vertical trench. This provides dielectric insulation in the horizontal direction between the common drift control region 1' and adjacent semiconductor regions, thus preventing the flow of charge carriers from the common drift control region 1'. The dielectric region 35a can, for example, be formed from a thermally produced silicon oxide. It is understood that such a dielectric region 35a is also suitable for the [missing information]. Fig. 37 illustrated semiconductor device 408 may be provided.

[0154] As an alternative to a fixed grid of accumulation oxides or accumulation oxide sections with net positive and negative charges, the grid can also vary across the chip area, e.g., to achieve finer compensation of the total charge. For example, a TEDFET can have an alternating grid of 3 and 4 accumulation oxides with a positive charge, each with one accumulation oxide with a negative charge.

[0155] As an alternative to a uniform arrangement of the accumulation oxides or accumulation oxide sections with positive and negative net charge across the chip, i.e., a uniform charge compensation, the density of the accumulation oxides or accumulation oxide sections with negative oxide charge and / or their absolute net charge can be increased, for example, towards the edge termination and / or towards a gate pad, an electrode lead and / or a semiconductor area with a peripheral component, in order to achieve a higher blocking capability, particularly statically, while in the rest of the cell field a positive integral net charge of the accumulation oxides or accumulation oxide sections is achieved, thus increasing the robustness of the component in breakdown.

[0156] Fig. Figure 39 shows an embodiment of a vertical semiconductor device 410 in a section of a horizontal cross-section. The vertical semiconductor device 410 is also typically a TEDFET. In the exemplary embodiment of Fig. Figure 39 shows two cell regions. In each of the two cell regions, several drift regions 1 are separated from a common drift control region 1' by dielectric layers 30, 35 arranged in moat-shaped vertical trenches and functioning as accumulation oxides. In other embodiments, several drift control regions 1' in each of the two cell regions are separated from a common drift region 1 by corresponding dielectric layers 30, 35.

[0157] According to the exemplary embodiment shown, the two cell regions differ in the number and arrangement of the dielectric layer(s) 30 with fixed negative charges. In other embodiments, the number and / or arrangement of the dielectric layers 30 with fixed negative charges in the cell regions are identical.

[0158] Typically, each of the drift control regions 1' is surrounded by a dielectric region 35a arranged in a further circumferential vertical trench to isolate the drift control regions 1' from an adjacent semiconductor region 1''.

[0159] Typically, the dielectric layers 30 exhibit a negative net charge and the dielectric layers 35 a positive net charge. By appropriately defining the net charges and / or the distribution of the dielectric layers 30 and 35, a resulting surface charge in the semiconductor during reverse bias can be effectively compensated.

[0160] Fig. Figure 40 shows an embodiment of a vertical semiconductor device 308 in a top view. The semiconductor device 308 comprises a semiconductor body 40 with a horizontal main surface extending to an outer edge 18. The semiconductor body 40 comprises an active region 510 and a peripheral region 520, both of which extend to the horizontal main surface. Fig. Figure 40 represents a top view of the horizontal main surface. For clarity, metallizations and possible cell structures of the active region 510 are not shown. An n-type semiconductor layer 1 is embedded in the semiconductor body 40 and extends to the horizontal main surface in the peripheral region 520. In the active region 520, a pn junction 14 is located between the n-type semiconductor layer 1 and the horizontal main surface. The pn junction 14 typically extends to the horizontal main surface in a transition region between the active region 510 and the peripheral region 520. Several vertical trenches surround the active region 510 and the pn junction 14 in the peripheral region 520. The vertical trenches extend from the horizontal main surface into the semiconductor body 40.Typically, the vertical trenches extend to a vertical depth greater than the maximum depth of the pn junction 14 in the active region 510. One or more vertical trenches contain a dielectric layer 30 with fixed negative charges. The dielectric layer 30 with fixed negative charges can be located on at least one side wall of the respective vertical trenches or can completely fill them. This allows for a boundary closure with a small horizontal footprint.

[0161] The active area 510 can be a cell array, e.g., an array of TEDFET cells, as with reference to Fig. 21 explains that these could be MOSFET cells or IGBT cells, but also a p-doped anode region 4 of a diode. In the latter case, a vertical section along line s typically corresponds to a structure similar to that in Fig. The semiconductor structure shown in Figure 20 is typically without the dielectric covering 84. Furthermore, depending on the position of line s, the dielectric layer 30 with fixed negative charges and the anode region 4 are spaced apart from each other, since the trench and the active region 510 typically form an acute angle. The dielectric layers 30 and / or 35 may extend at one end into the anode region 4, touch it, or maintain a minimal distance from it. The Fig. The 20 voids shown (83) are also only optional for the semiconductor component 308.

[0162] Typically, the vertical grooves of the semiconductor device 308 are designed as elongated rectangles in horizontal sections or in the top view shown, and in corner areas of the active region 510 are L-shaped or substantially L-shaped, so that at least one section of the vertical grooves forms an acute angle with the active region 510 and / or the nearest outer edge 18.

[0163] Furthermore, additional dielectric layers 35 with a net positive charge are typically arranged in a portion of the vertical trenches. Typically, every second to seventh vertical trench in the peripheral region is at least partially filled with a dielectric layer 30 with a net negative charge, while the other vertical trenches are at least partially filled with another dielectric layer 35 with a net positive charge. Analogously, as with reference to the Fig. As explained in Figures 37 to 39, this enables precise charge compensation even for edge termination structures. Different regions of the peripheral area can be designed with different densities of the dielectric layers 30 with a net negative charge. The corners and / or the L-shaped regions can have a different density, e.g., a lower density of the dielectric layers 30 with a net negative charge, than the straight regions of the peripheral area. Typically, the edge termination structure of the semiconductor device 308 consists of a plurality of vertical grooves completely or partially filled with dielectric, in particular oxide-filled, such that the active region 510 is completely surrounded by the oxide-filled vertical grooves.

[0164] In other embodiments, a dielectric layer 30 with a net negative charge is arranged in each of the vertical grooves of the semiconductor device 308.

[0165] It is understood that for good integral charge compensation, the surface charge density of the fixed negative charges of the dielectric layers 30 with net negative charge is typically adapted both to the donor base doping of the adjacent semiconductor regions and to the surface charge density of the positive charges of the dielectric layers 30, 35 expected according to the fabrication conditions. For example, the surface charge density of the fixed negative charges of the dielectric layers 30 in the peripheral region 520 can be chosen to be larger than for corresponding dielectric layers with net negative charge in the active region 510 if the latter were fabricated under more favorable conditions.

[0166] The production of the items related to the Fig. The semiconductor components 308 and 408 to 410 explained in sections 37 to 40 can be described as follows: Fig. The process is explained in sections 22 to 35, whereby, prior to atomic layer deposition, areas of the vertical trenches and / or a portion of the vertical trenches are completely masked. In this way, dielectric layers 30 or sections 38 of dielectric layers 30 with a net negative charge are obtained, and further dielectric layers 35 or remaining sections 39 of dielectric layers 30 with a net positive charge. This enables a very finely controlled global or integral compensation of the charge of the dielectric layers 30, 35.

[0167] For example, some of the vertical trenches are completely masked before atomic layer deposition, while other, adjacent vertical trenches remain completely open. This can be achieved using a conventional hard mask or by non-conformal carbon deposition on the wafer's front face (main surface) to form a carbon mask. The subsequent atomic layer deposition onto the unmasked vertical trenches typically occurs on a thin starter oxide layer, which is generated chemically or thermally. Afterward, the carbon mask or the conventional hard mask can be removed. In contrast to a conventional hard mask, e.g., made from a deposited oxide, the carbon mask can be easily removed after atomic layer deposition into the open vertical trenches of aluminum or TMA and before thermal oxidation by ashing.Any aluminum that may remain on the wafer front side has no significant effect on the device properties, since the doping levels on the semiconductor surface are sufficiently high to be negligible due to the relatively small absolute areal density of the aluminum doping in the range of approximately 2.5 10. 11 / cm 2 to be significantly affected.

[0168] After ashing of the carbon mask or removal of the hard mask, thermal oxidation typically occurs. Towards the end of this process, the oxidation regions grow towards each other, thus closing the original vertical trench(s). Any remaining buried void and / or seamline in the oxide does not impair the device function. In the horizontal direction, the seamline thickness is sufficiently small, typically less than a few nm, so that no significant reduction in accumulation, i.e., deterioration of the on-resistance, occurs. In the vertical direction, with the high aspect ratios of the vertical trenches, typically greater than 50, the blocking performance is not impaired because avalanche-like ionization cannot occur in the seamline.

[0169] Typically, at least the end of the oxidation process occurs at high temperatures in the range of, for example, 1150°C to 1250°C. This can reduce or even completely prevent wafer warping, as the oxide is sufficiently soft at these high temperatures, allowing the contacting oxide surfaces to fuse together with minimal stress.

[0170] In other embodiments, wet oxidation and / or a sequential sequence of wet and dry oxidation are used for the re-oxidation. Due to their lower viscosity at high temperatures, wet oxides can be readily combined with dry oxides to achieve comparable layer homogeneity and quality.

[0171] According to a further embodiment, additional positive fixed charges are selectively incorporated into the further dielectric layers 35 or remaining sections of dielectric layers 30 with a positive net charge via a further atomic layer deposition. For example, the positive net charge can be adjusted by doping with cesium. This enables even finer charge compensation. Furthermore, areas with increased negative oxide charge, e.g., as Al-doped silicon oxide, areas with increased positive oxide charge, e.g., as Cs-doped silicon oxide, and areas without targeted influence on the net charge by doping, e.g., as undoped thermal oxide, can be integrated into a semiconductor device, e.g., in different vertical trenches or trench sections. Additional appropriate masking is required for fabrication. The oxidation can also be carried out in a single process.

[0172] Spatially relative terms such as "under," "below," "lower," "above," "upper," and the like are used for ease of description to explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the structural element in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and are likewise not intended to be restrictive. Throughout the description, identical terms refer to identical elements.

[0173] As the expressions “with”, “containing”, “comprising”, and the like are used herein, they are open-ended expressions that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles “a”, “an”, and “the” are intended to include both the plural and the singular unless the context clearly indicates otherwise.

Claims

[1] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403), comprising: a semiconductor body (40), comprising: a first semiconductor region (1) comprising majority charge carriers of a first charge type; and a dielectric region (30, 31, 81) comprising a first charged dielectric section (81) and a second charged dielectric section (30), wherein the second charged dielectric section (30) comprises solid charges of the first charge type, the first charged dielectric section (81) comprises a first maximum charge carrier density per area, and the second charged dielectric section (30) comprises a second maximum charge carrier density per area of ​​the solid charges, which is greater than the first maximum charge carrier density per area. wherein the first semiconductor region (1) forms an insulator-semiconductor interface (25) with at least the second charged dielectric section (30), and wherein the dielectric region (30, 33, 81) is arranged between the first semiconductor region (1) and a gate electrode (11) and between the first semiconductor region (1) and a field plate (12). [2] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to claim 1, wherein the semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) is a field-effect power semiconductor device with an n-type drift region formed by the first semiconductor region (1). [3] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to claim 1 or 2, wherein the gate electrode (11) and / or the field plate (10, 12) are arranged in a trench (60, 61, 62) extending into the first semiconductor region (1). [4] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 3, wherein the first semiconductor region (1) extends to a main surface (15) of the semiconductor body (40) and wherein the field plate (10, 12) is arranged on the main surface (15). [5] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 4, wherein the charge carrier density per area is configured such that the dielectric region (30, 31) is shielded from hot majority charge carriers generated in the first semiconductor region (1). [6] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 5, wherein the second charged dielectric section (30) is arranged adjacent to a region with highest electron current in an avalanche mode of the semiconductor transistor. [7] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 6, wherein the semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) is a field-effect transistor which further comprises a channel region (50) and wherein the second charged dielectric section (30) is spaced apart from the channel region (50). [8] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 7, wherein the second charged dielectric section (30) is configured as a stack of layers (8a, 8b, 8c) comprising different dielectric materials. [9] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to claim 8, wherein the stack comprises a layer having a relative dielectric constant of about 7. [10] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 9, wherein the maximum charge carrier density per area of ​​the solid charges is over about 10 11 / cm 2 lies. [11] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 10, wherein the dielectric region (30, 31) comprises a nitride-doped silicon oxide, an aluminum-doped silicon oxide and / or a cesium-doped silicon oxide. [12] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 11, wherein the semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) is a power semiconductor transistor and wherein the dielectric region (30, 31) forms part of an edge termination structure. [13] Semiconductor transistor (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to any one of claims 1 to 12, wherein the second charged dielectric section (30) of the dielectric region (30, 31) is arranged in a lower section of a trench (60, 61, 62) extending into the first semiconductor region (1). [14] Power semiconductor device (100, 200, 201, 207, 250, 300, 400, 401, 402, 403), comprising: a semiconductor body (40), comprising: an active region (210) and a peripheral region (220), both of which define a main surface (15) of the semiconductor body; an n-type semiconductor layer (1) embedded in the semiconductor body (40) and extending to the main surface (15) in the peripheral region; and an edge termination structure arranged on the main surface (15) in the peripheral region (220) and comprising a field plate (10, 12) which is insulated from the semiconductor body (40) by a field-insulating region (30, 31), wherein the field-insulating region (30, 31) comprises a first dielectric section (80) and a negatively charged dielectric section (30), wherein the first dielectric section (80) comprises a first maximum charge carrier density per area of ​​negative charges, the negatively charged dielectric section (30) comprises a maximum charge carrier density per area of ​​negative charges which is greater than the first maximum charge carrier density per area, and the negatively charged dielectric section (30) is arranged at an edge and / or a step of the field plate (10, 12). [15] Power semiconductor device (100, 200, 201, 207, 250, 300, 400, 401, 402, 403) according to claim 14, wherein the charge carrier density per area of ​​the negatively charged dielectric section (30) decreases stepwise or continuously towards the outer edge of the edge termination structure. [16] Power semiconductor device (307, 308), comprising: a semiconductor body (40), comprising: an active region (310, 510) and a peripheral region (320, 520), both of which define a horizontal main surface (15) of the semiconductor body (40); an n-type semiconductor layer (1) embedded in the semiconductor body (40) and extending to the main surface (15) in the peripheral region (320, 520); a pn junction (14) arranged between the n-type semiconductor layer (1) and the main surface (15) in the active region (320, 520); and at least one trench (62) extending in the peripheral region (320, 520) from the main surface (15) into the n-type semiconductor layer (1) and comprising a dielectric layer (30) with fixed negative charges arranged vertically both below and above the pn junction (14), wherein a charge carrier density per area of ​​the fixed negative charges of the dielectric layer (30) decreases stepwise or continuously with increasing distance from the main surface (15). [17] Power semiconductor device (307, 308) according to claim 16, wherein the dielectric layer (30) comprises an aluminum-doped silicon oxide and / or an aluminum-doped oxynitride. [18] Power semiconductor device (307, 308), comprising: a semiconductor body (40), comprising: an active region (310, 510) and a peripheral region (320, 520), both of which define a horizontal main surface (15) of the semiconductor body (40); an n-type semiconductor layer (1) embedded in the semiconductor body (40) and extending to the main surface (15) in the peripheral region (320, 520); a pn junction (14) which is arranged between the n-type semiconductor layer (1) and the main surface (15) in the active region 310, 510; and at least one trench (62) extending in the peripheral region (320, 520) from the main surface (15) into the n-type semiconductor layer (1) and comprising a dielectric layer (30) with fixed negative charges arranged vertically both below and above the pn junction (14), wherein the at least one trench (62) comprises a cavity (83). [19] Power semiconductor device (307, 308) according to one of claims 16 to 18, wherein the pn junction (14) is adjacent to the dielectric layer (30) with fixed negative charges. [20] Power semiconductor device (307, 308) according to one of claims 16 to 19, wherein the dielectric layer (30) with fixed negative charges has a net negative charge, further comprising a further trench extending in the peripheral region (320, 520) from the main surface (15) into the n-type semiconductor layer (1) and comprising a further dielectric layer (35) with a net positive charge, wherein the further dielectric layer (35) is arranged in a vertical direction both below and above the pn junction (14). [21] Power semiconductor device (307, 308) according to claim 20, wherein at least one section of the at least one trench (62) and / or one section of the further trench forms an acute angle with the active area (310, 510). [22] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507), comprising: Providing a semiconductor body (40) comprising a main surface (15) and a first n-type semiconductor region (1); Forming a trench (62) extending from the main surface (15) into the first semiconductor region (1); Forming a dielectric layer (30) with fixed negative charges on a surface of the trench (62), comprising at least one atomic layer deposition using an organaluminum as a precursor. [23] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to claim 22, wherein a monolayer of the organoaluminum is formed by atom layer deposition. [24] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to claim 22 or 23, wherein the atom layer deposition further comprises the removal of ligands of the organaluminum. [25] Method for forming a semiconductor device (307, 308, 407, 408, 40, 410, 507) according to any one of claims 22 to 24, further comprising forming a metal-doped silicon oxide layer. [26] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to any one of claims 22 to 25, wherein trimethyl aluminum is used as a precursor. [27] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to any one of claims 22 to 26, further comprising forming a start oxide layer on the surface of the trench (62) prior to atomic layer deposition. [28] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to any one of claims 22 to 27, wherein the method is carried out such that a charge carrier density per area of ​​the fixed negative charges of the dielectric layer (30) decreases stepwise or continuously with increasing distance to the main surface (15). [29] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to any one of claims 22 to 28, wherein the trench (62) is partially masked prior to atomic layer deposition. [30] Method for forming a semiconductor device (307, 308, 407, 408, 409, 410, 507) according to any one of claims 22 to 29, wherein the dielectric layer (30) is produced such that it has a negative dielectric constant, further comprising: Forming at least one further trench extending from the main surface (15) of the semiconductor body (40) into the semiconductor body (40); and Forming another dielectric layer (35) with a net positive charge on a surface of at least one further trench. [31] Vertical semiconductor transistor (407, 408, 409, 410), comprising: a semiconductor body (40), comprising: a first semiconductor region (1) of the n type; a second semiconductor region (4) that forms a pn junction with the first semiconductor region (1); a third semiconductor region(1'); and a dielectric layer (30) comprising fixed negative charges in at least one section (38), which adjoins the second semiconductor region (4) and is arranged between the first semiconductor region (1) and the third semiconductor region (1'); and an insulated gate electrode (11) adjacent to the first semiconductor region (1) and the second semiconductor region (4), wherein the dielectric layer (30) extends from a main surface (15) of the semiconductor body (40) into the semiconductor body (40) and wherein a charge carrier density per area of ​​the fixed negative charges of the dielectric layer (30) decreases stepwise or continuously with increasing distance from the main surface (15). [32] Vertical semiconductor transistor (407, 408, 409, 410) according to claim 31, wherein the dielectric layer (30) comprises an aluminum-doped silicon oxide or an aluminum-doped oxynitride. [33] Vertical semiconductor transistor (407, 408, 409, 410) according to one of claims 31 and 32, wherein the vertical semiconductor transistor (407) is a TEDFET, and wherein the dielectric layer (30) forms an accumulation oxide. [34] Vertical semiconductor transistor (407, 408, 409, 410) according to any one of claims 31 to 33, wherein the dielectric layer (30) is arranged in a vertical trench (62, 64) extending from a main surface (15) to a rear surface (16) arranged opposite the main surface (15). [35] Vertical semiconductor transistor (407, 408, 409, 410) according to any one of claims 31 to 34, wherein a charge carrier density per area of ​​the fixed negative charges of the dielectric layer (30) in a horizontal plane has a highest value approximately in the middle between the third semiconductor region (1') and the first semiconductor region (1). [36] Vertical semiconductor transistor (407, 408, 409, 410) according to any one of claims 31 to 35, wherein the dielectric layer (30) has a net negative charge in at least one section (38), and wherein the dielectric layer (30) has a net positive charge in at least one further section (39). [37] Vertical semiconductor transistor (407, 408, 409, 410) according to any one of claims 31 to 36, further comprising a further dielectric layer (35) having a net positive charge, wherein the further dielectric layer (35) extends from a main surface (15) of the semiconductor body (40) into the semiconductor body (40).

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