Options for multiple levels of a power MOSFET

Abstract

A semiconductor device comprising: a substrate (213, 413, 1313, 1413, 1513, 1613); a first surface of the semiconductor device located above the substrate (213, 413, 1313, 1413, 1513, 1613), wherein the first surface of the semiconductor device contains at least three pads, of which at least three pads are: a drain pad (1130, 1230, 1330, 1630), a gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532) and a Source-Pad (209, 532, 855, 1131, 1231, 1431, 1631); a multitude of channeled gate structures (1315, 1415, 1605), wherein the many channeled gate structures (1315, 1415, 1605) are configured to control the electrical current flow between the source pad (209, 532, 855, 1131, 1231, 1431, 1631) and the drain pad (1130, 1230, 1330, 1630) when a voltage is applied to the gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532); a first conductive layer (1107, 1207, 1307, 1407, 1507, 1607, 1707), containing: a drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704), wherein the drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704) is connected to the drain pad (1130, 1230, 1330, 1630); a gate distribution trace (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703), wherein the gate distribution trace (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703) is coupled between the gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532) and a plurality of gate electrodes of the plurality of channeled gate structures (1315, 1415, 1605). is, a source contact (202, 402, 1101, 1201, 1301, 1501, 1601, 1701) that is coupled between the source pad (209, 532, 855, 1131, 1231, 1431, 1631) and a multitude of source areas of the multitude of channeled gate structures (1315, 1415, 1605), and a second conductive layer (1108, 1308, 1408, 1508, 1608), wherein at least a part of the second conductive layer is separated from at least a section of the first conductive layer by means of a dielectric layer, wherein the second conductive layer (1108, 1308, 1408, 1508, 1608) contains a drain conductor and at least a section of the drain conductor covers at least a section of the gate distributor trace (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703) and the drain conductor is connected to the drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704).

Description

Technical area

[0001] Examples include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs) and methods of fabricating them. In particular, examples include multi-level power MOSFETs. Background of the invention

[0002] The many different arrangements of metal-oxide-semiconductor field-effect transistor (MOSFET) devices include a gate pad on a semiconductor substrate or die, the dimensions of which are large enough to accommodate leads or other connecting components. Due to this size requirement, the gate pad can occupy a large portion (e.g., 50%, etc.) of a small semiconductor substrate or die. Since no active area is provided beneath the gate pad in many embodiments, the required size of the gate pad can limit the active area of ​​the semiconductor device.

[0003] Fig. 1 illustrates the general structure of one embodiment of a portion of a semiconductor device 100 including a source contact 102, a dielectric layer (insulation layer) 103 for a gate, a gate bus 104, a gate structure 105, a second dielectric layer (insulation layer) 106, and a substrate 113. In certain examples, the gate structure 105 may include a gate pad, a gate distribution track, a gate distribution track, or one or more other gate contacts or gate bus structures, and may be configured to provide a suitable bonding or connection area.

[0004] In this example, the source contact 102 is separated from the gate structure 105 by a gap / space 107, which is configured to maintain a minimum distance and ensure sufficient isolation between the gate structure 105 and the source contact 102, and to isolate the source contact 102 from the gate bus 104 by the second dielectric layer (insulation layer) 106. In various examples, the inactive region of a particular semiconductor device may vary depending on the manufacturing and design parameters used to manufacture and operate the device. In the example of Fig. 1, the edge of the source contact 102 approximately defines the inactive region 111 below the gate bus 104 defining an active region 108 of the semiconductor device 100. The inactive region of a semiconductor device, such as a power FET device, is generally the region that cannot be used to form a functional channel for current conduction.

[0005] The active region 108 of the semiconductor die or substrate may, in one example, include one or more channels forming an active channel array. In certain examples, one or more gate electrodes provided in the active channel array may form a portion of the source region of the semiconductor device 100, a portion of which is laterally offset from the gate structure 105. In certain examples, a lower surface of the substrate 113, which is substantially opposite an upper working surface of the semiconductor device 100, may include a drain region of the semiconductor device 100. In certain embodiments, the inactive region 111 below the gate structure 105 may have a width of more than 55 µm.

[0006] US 2008 / 0 099 926 A1 discloses a semiconductor device comprising a plurality of gate structures. The gate structures are coupled to the gate electrode. The drain electrode is remote from the gate electrode.

[0007] The document JP H04 - 111 360 A discloses a semiconductor device in which the drain electrode is arranged to cover the source electrode.

[0008] The document JP H11 - 74 523 A describes a semiconductor device of the prior art. Summary of the invention,

[0009] This description explains, among other things, a semiconductor device including a first metal layer connected to a source region and a second metal layer connected to a gate structure. A semiconductor device according to the invention is provided in claim 1. At least a portion of the first and second metal layers overlap each other to provide additional active area for the semiconductor device without increasing the size of the semiconductor device. In certain examples, a dielectric between metal layers may provide electrical insulation between the overlapping portions of the first and second metal layers. In other specific examples, pads having gate structures (terminals, leads, etc.) may be provided.) may be provided for connections to the outside and to portions of a gate runner that cover active regions of the semiconductor device, such as active source regions of a power MOSFET. In certain further examples, a second metal layer forming a source bond pad may extend to the boundaries of a semiconductor device to increase heat transfer and current performance. In certain still other examples, tie-down vias connecting a polysilicon gate runner or an insulated polysilicon pad to a metal gate bond pad may improve the cohesion or adhesion of the metal gate bond pad in the semiconductor device.

[0010] The semiconductor device may, in certain examples, comprise a plurality of conductive layers configured to provide a configuration of the external terminals of the semiconductor device according to customer requirements, which also results in an increased active area compared to known semiconductor devices of the same size and shape, for example, known CSP packages (chip scale packaging (CSP) devices) such as power MOSFETs.

[0011] This section is intended to provide an overview of the subject matter of the present invention. It is not intended to be an exclusive or complete explanation of the invention. The detailed description below is intended to provide further explanation of the present invention. Short description of the drawings

[0012] In the drawings, which are not necessarily to scale, like reference numerals designate like semiconductor devices throughout the different views. Like reference numerals with different letter suffixes or indices may designate different embodiments of the same semiconductor devices. The drawings generally illustrate, by way of example but not limitation, various embodiments discussed in the present description. Fig. Figure 1 shows a general example of the structure of a gate runner. Fig. Figure 2 generally shows an example of a portion of a semiconductor device such as a power transistor according to the present invention. Fig. Figure 3 generally shows an example of a method for manufacturing a portion of a semiconductor structure as described in the examples of Fig. 2 and Fig. 3 is shown. Fig. 4A to 4G generally illustrate an example of a method for fabricating a portion of a semiconductor structure. Fig. 5A generally shows a top view of an example semiconductor device. Fig. 5B generally shows a cross-section of an example of a semiconductor device having a trenched gate distribution line provided with a second gate pad having a metal layer using a via between two metal elements. Fig. 6 to 7 generally show examples of structures of segmented second metal layer gate distribution lines. Fig. 8 generally shows an example of a gate distribution line structure including a buried first configuration of a metal gate distribution line. Fig. 9 generally shows an example of a semiconductor device such as a power MOSFET for chip scale packages (CSP). Fig. 10 generally shows a top view of a cross-section of an exemplary semiconductor device, such as a power MOSFET. Fig. Figures 11A to 11C generally show a series of top views of cross sections, such as those of a CSP power MOSFET. Fig. Figures 12A to 12C generally show a series of top views of cross sections, such as those of a CSP power MOSFET. Fig. 13 generally shows an example of a cross-sectional view of a semiconductor device, such as a power MOSFET. Fig. 14 generally shows an example of a second cross-section of a semiconductor device. Fig. 15 generally shows an example of a cross section of a semiconductor device. Fig. 16 generally shows an example of a cross-section of an alternative multi-level semiconductor device. Fig. 17 generally shows a top view of an example of a first conductive layer of a semiconductor device, such as a multi-level power MOSFET. Detailed description of the invention

[0013] The inventors of the present invention have, among other things, discovered a layout of a semiconductor device having first and second metal(ization) structures that at least partially overlap vertically to increase the active area of ​​the semiconductor device without increasing its size. In one example, the design of the semiconductor device may include a first metal connected to a source region and a second metal connected to the gate structure. In certain embodiments, the first and second metals may form portions of the first and second metal structures. In one embodiment, the source region may have a source contact, such as a source pad or source electrode. In other embodiments, the source region may represent a source region on a substrate of the semiconductor device.In one example, the gate structure may include a gate pad, a gate runner, or one or more gate contact or gate bus structures. In one example, at least a portion of a second metal layer may be formed to overlap at least a portion of a first metal layer to increase the active area of ​​the device, such as a power FET, without increasing the size of the substrate or die.

[0014] In certain embodiments, the design of the semiconductor device described here may be configured such that the inactive area of ​​the semiconductor device or of a semiconductor package accommodating one or more semiconductor devices is reduced, with the result that the active area of ​​the substrate or the device is increased without increasing the size of the substrate or the device or its package.In certain embodiments, the device according to the present invention may be configured to reduce the size of the individual semiconductor devices relative to the gate structure, to provide flexibility in the arrangement or sizing of a gate pad on the semiconductor device or a package, to increase the available active area of ​​the semiconductor device by about 5% or more, or to improve the "on" resistance of the device, such as the drain-source resistance (RDS) of a power transistor.

[0015] General shows Fig. 2 shows an example of a portion of a semiconductor device 200, such as a power transistor, comprising a substrate 213, a source contact 202, a gate dielectric layer (insulation layer) 203, a gate bus 204, a gate structure 205, a second gate dielectric layer 206, a source pad 209, an intermetal insulation layer (IMD) 210 (insulation layer (dielectric) between metal(ization) layers) extending between the source contact 202 and a gate structure 205. The gate structure 205 may, in one embodiment, comprise a gate pad, a gate distribution line, one or more other gate contacts, or gate bus structures.

[0016] At least a portion of the gate structure 205 may, in one embodiment, overlap at least a portion of a source region of a semiconductor device 200. In the embodiment according to Fig. 2, the intermetal insulating layer IMD 210 insulates the gate structure 205 from the source contact 202 and allows at least a portion of the gate structure 205 to overlie or overlap at least a portion of the source contact 202, as shown in Fig. 2 as an overlap 212. This allows at least a portion of the source contact 202 to be laterally closer to or even overlap at least a portion of the gate bus 204. As shown in Fig. 1, the area below the gate bus 204 has traditionally been an inactive area. However, the inventors of the present invention have recognized that in certain embodiments, as the width of the gate bus 204 decreases (i.e., while the top width of the gate structure 205 remains the same as that shown in Fig. 1) at least a portion of the active region 208 may laterally approach or vertically overlap (i.e., be located beneath) at least a portion of the gate structure 205, with the result that the inactive region 211 of the semiconductor device 200 decreases in size or that the active region 208 of the semiconductor device 200 increases in size compared to the overall size. In one example, the width or size of the inactive region 211 beneath the gate structure 205 may be reduced by about 25% or more, compared to existing semiconductor devices having an inactive region beneath the gate structure that is greater than about 55%, as shown in the example of Fig. 1. This reduction may result from the overlap of portions of the metal layer of the gate structure 205 with portions of the metal layer or metal of a source structure or source region. Such techniques may enable to reduce or eliminate lateral isolation gaps between metal(ization) portions of the two structures. Some embodiments may even enable to reduce the metal(ization) portions of the gate structures in terms of their width. In one embodiment, the overlapping portion of the source contact 202 and the gate structure 205 may represent double metal layers that allow the active region 208 of the semiconductor device 200 to lie beneath a portion of the gate structure 205, such as a gate pad, a gate distribution line, etc., thereby increasing the active region 208 of the substrate orof the chip without increasing the package or substrate size. In one embodiment, the gate bus 204 may be formed to interface with one or more gate trenches forming part of the active area 208 of the substrate containing the semiconductor device 200. Although the embodiment of the . Fig. 2 is chosen with respect to a power transistor, it is understood that the semiconductor devices embodying the present invention may include, without limitation, power metal oxide semiconductors (MOS), field effect transistors (FETs), planar MOSFETs, double implantation MOS (DMOS), drain-in-the-back DMOS, trench MOSFETs, including charge-locked devices such as shielded gate semiconductor devices, insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and temperature sensing and current sensing MOS devices.In one embodiment, the source contact 202 may comprise a first metal layer material including, but not limited to, aluminum (Al), an alloy of aluminum and silicon (AlSi), an alloy of aluminum, silicon, and copper (AlSiCu), copper (Cu), and one or more other metals or combinations (alloys) thereof, and may include an underlying barrier metal such as titanium (Ti), titanium tungsten (TiW), or titanium nitride (TiN). The gate structure 205 may comprise a second metal layer including, but not limited to, electroless nickel-gold (ENiAu), titanium-nickel-silver (TiNiAg), titanium-nickel-vanadium-silver (TiNiVAg), copper (Cu), solderable metals such as tin (Sn), or one or more other metals or combinations thereof.

[0017] An example of a method 300 for producing a portion (region) of a semiconductor device, as described for the embodiment according to Fig. 2 is shown in Fig. 3 generally shown. In step 301, for example, after a substrate has been doped and trenches and gate buses have been formed, a first metal layer may be formed on the substrate. In step 302, gaps or gaps in the first metal layer may be etched to form a portion of a gate pad or package contact and a source contact. In step 303, a first dielectric layer or insulating layer is formed over the etched first metal layer. In step 304, the first insulating layer is removed except for the regions of the first insulating layer material within the etched gaps or gaps of the first metal layer. In step 305, a second dielectric layer is formed over the etched first metal layer and the insulating layer filling the gaps or gaps of the first metal layer. In step 306, gaps or openings are formed in the second insulating layer orthe second dielectric layer is etched to expose a portion of the first metal layer including the gate pad region or section. In step 307, gaps or openings are etched in the second dielectric layer to expose a portion of the first metal layer including the source contact. In step 308, a second metal layer is formed over the second insulating layer and the exposed portions of the first metal layer. In step 309, the second metal layer is etched to form the gate pad and the source pad. In certain examples, the gate pad may be formed to overlap a portion of the source contact and is insulated from the source contact by a non-etched portion of the second dielectric layer 305.In certain examples, at least a portion of the first metal layer may be thinner than at least a portion of the second metal layer, thereby reducing the extent of separation between the first and second metal layers and consequently increasing the potential active area of ​​the substrate. In another embodiment, the first metal may be thinner than the second metal in the region where the first and second metals overlap.

[0018] In certain embodiments, at 304 and 305, portions of the first insulating layer are not removed and a second dielectric layer is not formed. In such embodiments, contact connections may be created through the etched portions of the first metal layer to contact the second metal layer with the gate bus and the source contact. In certain examples, the contact connections may be covered with an insulating layer to insulate the interior or inner surface of the contact connection from the first metal layer. In some embodiments, tie-down vias may be used to reduce the resistance of the gate pad and to improve the mechanical bond between the second metal layer forming the gate pad and the first insulating layer. After the contact connections have been formed, the second metal layer may beContact holes, the second metal layer may be formed on the first insulating layer and etched to form a gate pad, one or more source connection pads, and one or more optional gate distribution traces.

[0019] The Fig. 4A-4G generally show examples of manufacturing steps for designing a semiconductor device as described herein. Fig. 4A generally illustrates an example of a portion of a semiconductor device 400 including a gate structure 401 (e.g., a gate pad, a gate distribution line, or one or more other gate contacts or a gate bus structure) and a plurality of trenches 440 in a substrate 413, each trench including a gate electrode 433, e.g., a polysilicon electrode. In one example, the gate electrode 433 may be isolated from the substrate 413 by a trench isolation or dielectric 441. In certain embodiments, each of the plurality of trenches 440 may include one or more isolated electrodes. A working surface 442 of the substrate 413 may include a doped source region 443 between successive trenches of the plurality of trenches 440.In one embodiment, the gate structure 401 may include a gate bus 404, for example, a polysilicon gate bus, an insulating layer 403 for isolating the gate bus 404 from the substrate 413, and a dielectric layer or insulating layer 406 for isolating at least a portion of the gate structure 401 from a portion of the source region above the plurality of trenches 404. In another embodiment, a first metal layer 445 may be provided over the substrate 413. The first metal layer 445 may have a gap 444 (for example, an etched gap) formed to form a portion of a gate pad 405 and a portion of a source contact 402.

[0020] Fig. 4B generally shows an example of a first dielectric material (insulating material) 460 formed over the first metal layer 445.

[0021] Fig. 4C generally shows an example of a remaining portion of the first dielectric material (insulating material) 460 after etching the first metal layer 445.

[0022] Fig. 4D generally illustrates an example of a second dielectric material 461 provided over the first metal layer 445 and the remaining portions of the first dielectric material 460. In certain embodiments, the first dielectric material 460 and the second dielectric material 461 are the same insulating material.

[0023] Fig. 4E generally illustrates an example of the remaining areas of the second dielectric material 461 after etching to expose portions of the first metal layer 445, including a portion of the gate pad 405 and a portion of the source contact 402.

[0024] Fig. 4F generally shows one embodiment of a second metal layer 446 overlying the remaining portion of the second dielectric material 461 and the exposed portions of the first metal layer 445.

[0025] Fig. 4G generally shows an example of the remaining portions of the second metal layer 446 after etching to isolate the gate structure 401 from the source pad 409. The combination of the first and second dielectric materials 460 and 461 allows a portion of the source contact 402 to lie beneath a portion of the second metal layer 446 forming part of the gate structure 401. The portion of the source contact 402 that lies beneath the metal portion of the gate structure 401 represents an increase in the active area of ​​the substrate compared to structures with a single metal layer.

[0026] Fig. 5A generally illustrates a top view of one embodiment of a semiconductor substrate 500 having a gate pad 530, a gate distribution line 531, and source pads 532. In one embodiment, a plurality of gate trench electrodes, such as a gate trench electrode 533, may be formed to form a portion of the active area beneath a source contact connected to the source pads 532 and may be formed to connect one or more gate distribution lines 531. Generally, the gate pad 530 may be connected to the active area of ​​the semiconductor substrate or package 500 using one or more gate distribution lines 531 or the gate trench electrodes.

[0027] The gate pad 530 may be subjected to, among other things, external forces transmitted via the bonding medium. In certain examples, these forces may cause the external second metal layer of the gate pad 530 to separate from an underlying inter-metal dielectric (IMD) layer. In certain examples, the gate pad 530 may be connected to a buried gate distribution trace 534 of the semiconductor substrate 500 using one or more tie-down vias, such as a via connection 535. In addition to providing a more robust metallic connection of the metal layer of the gate pad 530 to the underlying structure of the semiconductor substrate or semiconductor package 500, the via connection 535 may reduce the gate resistance of the device 500. In certain other examples, the buried gate distribution trace may be integrated into the substrate of the semiconductor package.In certain embodiments, the buried gate distribution trace may be below a level of the first metal layer. In certain other examples, the buried gate distribution trace may be coplanar with the first metal layer.

[0028] Fig. 5B generally shows an example of a cross-section of a portion of a semiconductor package or substrate 500 having a gate pad 530 connected to a buried gate distribution line, such as a polygate distribution line 534 using a via interconnect 535. In certain embodiments, one or more via interconnects 535 extending through an intermetal insulating layer (IMD) 536 may connect the gate pad 530 to the buried polygate distribution line 534. Because the polygate distribution line 534 extends over an edge of the gate pad 530, the IMD 536 may isolate the buried polygate distribution line 534 from a source pad 532. The vias connecting the buried polygate distribution trace to the gate pad 530 can strengthen the bonding of the metal gate pad to the semiconductor device.In one embodiment, instead of various individual via connections 535, a single thin via connection spanning the length of the buried gate distribution trace 534 may connect the gate pad 530 to the underlying portion of the buried polygate distribution trace 534. In certain embodiments, the bonding or adhesion of the gate pad 530 may be enhanced by connecting the gate pad 530 to isolated polysilicon gate pad structures underlying the gate pad 530. An example of an isolated gate pad is shown in FIG. Fig. 8 shown.

[0029] Fig. 6 generally illustrates an example of a segmented gate distribution trace structure 600 (e.g., a segmented second metal gate distribution trace structure) including a gate distribution trace 605 including selected gate pads 604, 624 (e.g., polysilicon gate bus distribution trace pads) optionally connected to each other using a thinner gate distribution trace 624 (e.g., a polysilicon gate distribution trace thinner than the selected gate bus pads 604, 624 or the gate distribution trace 605). In one embodiment, the gate distribution trace 605 may optionally be connected to selected gate bus pads, for example, to one or more of the selected gate bus pads 604, 624 using one or more contact connections, such as the contact connections 626.In one embodiment, an increased active area of ​​a semiconductor substrate or a semiconductor device having the segmented gate distribution line structure 600 may be achieved by using the thinner gate distribution line 625, or optionally by extending a first metal layer having a source contact (not shown) into the regions 627 partially bonded by adjacent selected gate bus pads 604, 624 and the thinner gate distribution lines 625. In certain further examples, a continuous line of a first metal layer may bridge the gate distribution line 625. The line may extend between the gate bus pads 604, 624, provided the line is electrically insulated from the thin gate distribution line 625.

[0030] An example of a segmented gate distribution trace structure 700 having a plurality of gate bus pads 704, 724 (e.g., polysilicon gate pads) is generally shown in Fig. 7. In one example, one or more of the plurality of gate bus pads 704, 724 may optionally be connected to each other by one or more channel lines 728 that cross the plurality of gate bus pads 704, 724. In one example, the plurality of gate bus pads 704, 724 may at least partially overlap a first metal layer (not shown) that forms part of a source contact. In other examples, one or more of the plurality of gate bus pads 704, 724 may also be further connected to each other in another manner using a second metal layer connecting a gate distribution trace 705 and one or more contact connections, such as contact connections 726. Each connection between the gate distribution trace 705 and the plurality of gate bus pads 704, 724 may form a contact connection through one or more of an intermetal insulating layer, an etched gap, orGap in the first metal layer or an insulating layer adjacent to the pad. An enlarged active area can be achieved by etching the first metal layer surrounding the source contact around the contact connections 726 that connect one or more of the plurality of gate bus pads 704, 724 to the overlapping gate distribution traces 705.

[0031] In one example, a segmented gate distribution line structure 700 formed using a second metal layer may enable a first metal layer having a source contact to intermittently bridge a gate distribution line 705 so as to electrically connect active regions of a semiconductor device separated by a gate distribution line 705.

[0032] An example of an alternative gate distribution track structure having a buried first metal gate distribution track configuration is generally described in Fig. 8. A semiconductor die, or substrate or package 800, in one example may include a first metal layer 845 formed over the semiconductor die 800 and etched to form a gate distribution trace 850 and a source contact region 851. An intermetal insulating layer (IMD), not shown, may be formed such that the first metal layer 845 is insulated from a second metal layer 846 formed above the IMD and etched to form a source pad 855 and a gate pad 853. In one example, gate vias 852 may be formed to connect the gate distribution traces 855 formed from the first metal layer to the gate pad 853 formed from the second metal layer.In addition to the electrical connection, the gate contact connections 852 provide a mechanical connection or adhesion between the gate pad 853 and the underlying components of the semiconductor device. As discussed above, known semiconductor devices include a polysilicon gate structure beneath the gate pad such that virtually the entire area beneath the gate pad is inactive. A semiconductor device employing gate distribution lines 850 with an underlying layer of polysilicon does not require the use of a large polysilicon gate structure, and therefore virtually the entire area beneath the gate pad 853 can be active. Therefore, the semiconductor device according to the present invention can have a significant additional active area compared to known semiconductor devices without thereby increasing the size of the semiconductor device.

[0033] The gate pad 853 may, in certain examples, be connected to a polysilicon gate pad structure 856 beneath the metal gate pad 853 using one or more gate contact interconnects or vias 852 to provide additional adhesion of the second metal layer gate pad 853 to the underlying substrate structure. An isolated polysilicon gate pad structure 856 may include a polysilicon pad 858 and an insulating gap 857 for isolating the polysilicon pad 858 or the contact interconnect 852 from the surrounding source contact region 851. In certain examples, the insulating gap 857 may include an insulating material insulating the first metal layer from the polysilicon pad 858, an intermetal insulating material insulating the first metal layer from the second metal layer, or both types of insulating material.

[0034] The source contact connection 854, in one embodiment, may connect the source contact regions 851 formed from the first metal layer 845 to the source pad 855 formed from the second metal layer 846. Instead of or in addition to the source contact connection 854, in certain examples, large windows may be etched into the IMD, separating the first metal layer forming the source contact region 851 from the second metal layer forming the source pad 855. In one example, the etched windows may be filled with metal, such as the metal forming the second metal layer, to connect the source pad 855 to the source contact region 851.

[0035] The buried nature of the gate distribution traces 850 formed from the first metal layer 845 may, in one example, enable a larger source contact pad 855 formed from the second metal layer 846 compared to a semiconductor device with gate distribution traces formed from the second metal layer as discussed above. In one example, the enlarged source contact pad 855 may provide improved thermal and current conduction, as well as a larger bonding area for a bonding medium, including, but not limited to, solderable bonding material or bonding clips for attaching conductors to devices or packages outside the semiconductor package or substrate.

[0036] In certain embodiments, power semiconductor devices implemented as chip-scale package (CSP) devices (CSP devices), such as power MOSFETs, can benefit from multilayer configurations. According to the Association Connecting Electronics Industries (IPC) J-STD-012 standard, some CSP devices have all of the semiconductor device's connection terminals or package contacts in a common plane. For power devices with a structure with vertically oriented connection nodes, the semiconductor device typically accommodates the routing of one or more of the connection nodes to a common plane, omitting the active area of ​​the semiconductor device.

[0037] Fig. 9 generally illustrates an example of a semiconductor device 900, such as a power MOSFET, configured for chip-scale packaging, including a top view of a cross-section taken approximately at or near the active surface of a substrate of the semiconductor device 900. The semiconductor device 900 includes a metal source contact 901, a gate structure 902, gate distribution lines 903, and a metal drain contact 904.

[0038] The example of Fig. 9 shows exemplary locations of openings 906 through overlying material that allow for electrical connection to the metal source contact 901, the gate structure 902, the gate distribution traces 903, and the metal drain contact 904. The openings 906 provide routing areas so that contact pads for the source, drain, and gate of the semiconductor device 900 can all be arranged in a common overlapping area of ​​the semiconductor device 900. Note, however, that a significant area of ​​the substrate area is reserved for routing a connection for the metal drain contact 904.

[0039] Fig. 10 generally shows a top cross-sectional view of an exemplary semiconductor device 1000, such as a CSP power MOSFET, including a metal source contact 1001, gate distribution traces 1003, and a metal drain contact 1004. The top cross-sectional view of the semiconductor device 1000 includes outlines of the external terminal contacts of the semiconductor device, such as solder ball locations 1006 covering the metal source contact 1001, the gate distribution traces 1003, and the metal drain contact 1004.

[0040] Fig. 10 further shows an example of contact connection locations for supplying conductive material for connecting solder balls to the drain metal contact 1004, the gate distribution lines 1003, or the source metal contact 1001. In one example, the semiconductor device 1000 may include drain contact connections 1010 configured to connect the drain metal contact 1004 to a drain solder ball, source connection contacts 1011 configured to connect the source metal contact 1001 to the solder balls, or gate connection contacts 1012 configured to connect the gate distribution lines 1003 to a solder ball for the gate. In one example, multiple drain-source or gate contact connections 1010, 1011, and 1012 may extend through a dielectric material separating the solder ball from the metal source contact 1001, the gate distribution traces 1003, or the metal drain contact 1004.In one example, vias may include a series of individual openings for electrical connection between two or more layers in a semiconductor device. In certain examples, the contact connections may include a slot-shaped opening, such as an elongated opening, a segmented slot-shaped opening, or a large opening for electrical connection between two or more layers in a semiconductor device. In certain examples, instead of solder balls, an overlying conductive layer may include pads, such as a source pad, a gate pad, or a drain pad.

[0041] In one example, compared to the layout of the semiconductor device 900, the Fig. 9 the layout of the semiconductor device 1000 of the Fig. 10 may have an additional active region in which a gate structure is typically arranged. In some examples, the layout of the semiconductor device 1000 may be Fig. 10 about 14% more active area compared to a semiconductor device of the same size, which uses the layout of the Fig. 9 used.

[0042] The Fig. 11A through 11C generally illustrate a series of top cross-sectional views for an exemplary semiconductor device 1100, such as a CSP package MOSFET. Fig. 11A generally shows a top cross-sectional view for an example of a first conductive layer 1107, or near the surface of a substrate of the semiconductor device 1100. Fig. 11B generally shows a top cross-sectional view of an example of a second conductive layer 1108 of the semiconductor device 1100 overlying the first conductive layer 1107. Fig. 11C generally shows an example of a third conductive layer 1109 at or near an outer surface of the semiconductor device 1100.

[0043] Referring to Fig. 11A, in one example, a first conductive layer 1107 may include a metal drain contact 1104, gate distribution traces 1103, and a metal source contact 1101. Dielectric material may cover the first conductive layer 1107 and may underlie the second conductive layer 1108. In one example, one or more vias may be used to connect portions of the first conductive layer 1107 to the second conductive layer 1108. Fig. 11A illustrates exemplary contact connection locations that may extend through a dielectric material provided between the first conductive layer 1107 and the second conductive layer 1108. The one or more contact connection locations include, for example, locations for one or more drain contact connections 1110, one or more source contact connections 1111, or one or more gate contact connections 1112.

[0044] In certain examples relating to Fig. 11B, the second conductive layer 1108 of the semiconductor device 1100 may include at least a drain conductor 1120 (e.g., a drain interposer), a source conductor 1121 (e.g., a source interposer), or a gate conductor 1122 (e.g., a gate interposer). In one example, the second conductive layer 1108 may overlie the first conductive layer 1107, and portions of the second conductive layer 1108 may be connected to the first conductive layer 1107 using one or more contact connections underlying the second conductive layer 1108 and extending through the dielectric material provided between the first conductive layer 1107 and the second conductive layer 1108.The one or more contact connections may include one or more drain contact connections 1110 configured to connect the drain conductor 1120 to the drain metal contact 1104, one or more source contact connections 1111 for connecting the source conductor 1121 to the source metal contact 1101, or one or more gate contact connections 1121 for connecting the gate conductor 1122 to one or more gate distribution traces 1103.

[0045] If one refers to Fig. 11C, in certain examples, a third conductive layer 1109 of the semiconductor device 1100 may include pads, such as at least one drain pad 1130, a source pad 1131, or a gate pad 1132, configured to connect the semiconductor device 1100 to other semiconductor devices or devices. In one example, one or more of the drain, source, or gate pads 1130, 1131, and 1132 may include solder balls connected to one or more conductors of the second conductive layer 1108 using one or more contact connections 1139 extending through the dielectric material and disposed between the first conductive layer 1108 and the third conductive layer 1109.

[0046] The semiconductor device 1100, which is used in the Fig. 11A to 11C shows an example of an external connection pattern that can be obtained using power MOSFETs with multiple conductive layers. Other external connection patterns or arrangements are possible without departing from the scope of the present invention.

[0047] The Fig. 12A through 12C generally illustrate a series of top cross-sectional views of an exemplary device 1200, such as a CSP power MOSFET. Fig. 12A generally shows a top-down cross-sectional view of an example of a first conductive layer 1207 at or near the surface of a substrate of a semiconductor device 1200. Fig. 12B generally shows a top-down cross-sectional view of an example of a second conductive layer 1208 of the semiconductor device 1200 overlying the first conductive layer 1207. Fig. 12C generally shows an example of a cross-sectional view of a third conductive layer 1209 at or near an outer surface of the semiconductor device 1200.

[0048] It will now Fig. 12A. In one example, the first conductive layer 1207 may include a metal drain contact 1204, a gate connection trace 1203, and a metal source contact 1201. The metal source contact 1201 may extend to and from an active region of the semiconductor device 1200 via trenched gate structures, not shown. Dielectric material may overlie the first conductive layer 1207 and may underlie a second conductive layer 1208 of the semiconductor device 1200. In one example, contact connections, such as drain contact connections 1210, as shown in Fig. 12B, source contact interconnections 1211 or gate contact interconnections 1212 may be used to connect portions of the first conductive layer 1207 to the second conductive layer 1208. In one example, the metal drain contact 1204 may include a metal band (metal strip) along the perimeter of the semiconductor device 1200, and in certain examples, it may be connected to a lower portion of the substrate of the semiconductor device 1200 using one or more drain-to-substrate contact interconnections, not shown. In one example, the metal drain contact 1204 may comprise a trace of metal within the interior of the semiconductor device 1200, for example, like the gate distribution traces that divide the source region into different regions, or a combination of perimeter and inner drain metal contact.In one example, the metal drain contact 1204 may have a substantially uniform width around the perimeter of the semiconductor device 1200. In some examples, the layout of the . Fig. 12A about 37% more active area compared to a semiconductor device with the layout of the Fig. 9 and the same size. In a particular example, the gate interconnect line 1203 may be connected to trenched gate structures in the semiconductor device 1200.

[0049] With reference to Fig. 12C, in certain examples, the third conductive layer 1209 may include one or more pads, such as drain pads 1230, source pads 1231, or gate pads 1232, to connect the semiconductor device to other semiconductor devices. In one example, one or more pads may include solder balls connected to one or more of the drain conductors 1220, the source conductor 1221, or the gate conductor 1222 of the second conductive layer 1208 using one or more contact connections 1239 extending through the dielectric material disposed between the second conductive layer and the third conductive layer 1209. The semiconductor device 1200 shown in the Fig. 12A to 12C show an example of an external connection pattern that can be obtained for a power MOSFET with multiple conductive layers. In other examples, other external connection patterns are possible without departing from the scope of the present invention.

[0050] Fig. 13 generally illustrates an example of a cross-sectional view of a semiconductor device 1300, such as a power MOSFET, extending from a substrate 1313 through overlying material including first, second, and third conductive layers 1307, 1308, and 1309. In one example, the first conductive layer 1307 may include a metal drain contact 1304, a gate distribution trace 1303, and a source metal contact 1301. In one example, the gate distribution traces 1303 may include polycrystalline silicon, a metallic interconnect (e.g., a metallic interconnect formed using a metal gate process), a metallic interconnect and polycrystalline silicon (e.g., a metallic material overlying a polycrystalline material), or metal, such as, but not limited to, Al, AlSi, AlSiCu.In one example, the gate distribution lines 1303 may include polycrystalline silicon converted to silicon silicide, resulting in low resistance gate distribution lines to reduce the size of the gate distribution lines 1303 or increase the performance of the semiconductor device 1300.

[0051] In one example, the metal drain contact 1304 may be in electrical communication with a drain-to-substrate contact connection 1314 extending into the substrate 1313, and a gate distribution trace 1303 may be in electrical communication with a plurality of channeled gate structures 1315. In one example, a drain-to-substrate contact connection may extend into an epitaxial layer 1316 of the substrate 1313. A plurality of trenched gate structures 1315 may underlie the metal source contact 1301 and, in certain examples, may control the flow of electrical current between the metal source contact 1301 and the metal drain contact 1303 when a voltage is applied to the gate distribution trace 1303.

[0052] In one example, the second conductive layer 1308 may be separated from the first conductive layer 1307 using a first dielectric layer 1317 and may include a drain conductor 1320 connected to the drain metal contact 1304, for example, using one or more drain contact interconnects 1310 in the first conductive layer 1317. In one example, the drain contact interconnect 1310 may connect the drain conductor 1320 to the drain metal contact 1304. In certain examples, the drain conductor 1320 may overlie the gate distribution lines 1303 or the source metal contact 1301 and may be used as a drain pad for connecting the semiconductor device 1300 to any other electronic semiconductor devices.

[0053] In one example, the third conductive layer 1309 may include a drain pad 1330. In certain examples, the drain pad 1330 may include a drain solder ball. In one example, the second conductive layer 1308 may be separated from the third conductive layer 1309 using a second dielectric layer 1318, and the drain pad 1330 may be connected to the drain conductor 1320 using one or more drain contact connections 1340 that extend through the second dielectric layer 1318. In one example, the drain conductor may provide a medium that allows the arrangement of the drain pad 1330 to be customized regardless of the location of the underlying metal drain contact 1303. In certain examples, the drain pad 1330 may have a flat top surface.

[0054] Fig. 14 generally shows an example of a second cross-section of a semiconductor device 1400 extending from a substrate 1430 through overlying materials including first, second, and third conductive layers 1407, 1408, and 1409. In one example, the substrate 1413 may include an epitaxial layer 1416.

[0055] In one example, the first conductive layer 1407 may include a source metal contact 1401 and may overlie a plurality of trenched gate structures 1415. The second conductive layer 1408 may include a source conductor 1421 connected to the source metal contact 1401 and may be separated from the first conductive layer 1407 using a first dielectric layer (insulating layer) 1417. In certain examples, the source conductor 1421 may be connected to the source metal contact 1401 using source contact connections 1411 in the first dielectric layer 1417. In one example, the source conductor 1421 may be used as a source pad 1431 for connecting the device 1400 to other electronic components and may overlie at least one drain metal contact or a gate runner.

[0056] In one example, the third conductive layer 1409 may include the source pad 1431. In certain examples, the source pad 1431 may include a source solder ball. In one example, the second conductive layer 1408 may be separated from the third conductive layer 1409 using a second dielectric layer 1418, and the source pad 1431 may be connected to the source conductor 1421 using one or more source contact connections 1441 extending through the second dielectric layer 1418. In one example, the source conductor 1431 may form a medium that enables the customization of the source pad 1431, independent of the underlying source metal contact 1401. In certain examples, the source pad 1431 may have a planar top surface.

[0057] Fig. 15 generally shows an example of a cross-section of device 1500 extending from a substrate 1513 through overlying material including first, second, and third conductive layers 1507, 1508, and 1509. In one example, substrate 1513 may include an epitaxial layer, and at least one of substrate 1513 and the epitaxial layer may include a channel for supporting a gate distribution trace 1503.

[0058] In one example, the first conductive layer 1507 may include a metal drain contact 1504, a gate distribution trace 1503, and a metal source contact 1501. In one example, the first conductive layer 1507 may be separated from the second conductive layer 1508 by a first dielectric layer 1517.

[0059] In one example, the second conductive layer 1508 may include a gate conductor 1522 connected to the gate distribution trace 1503 using one or more gate contact interconnects 1512 extending through the first dielectric layer 1517. In certain examples, the gate conductor 1522 may overlie at least one of the metal source contact 1501 and the metal drain contact 1504. In one example, the gate conductor 1522 may be used as a gate pad for connecting the device to other electronic components. In one example, the second conductive layer 1508 may be separated from the third conductive layer 1509 by a second dielectric layer 1518.

[0060] In one example, the third conductive layer 1509 may include a gate pad 1532 connected to the gate conductor 1522 using one or more gate contact connections 1532 extending through the second dielectric layer 1518. In certain examples, the gate pad 1532 may include a gate solder ball. In one example, the gate conductor 1522 may provide a medium that enables customization of the gate pad 1532 independent of the location of the underlying gate distribution trace 1503. In certain examples, the gate pad 1532 may have a planar top surface 1552.

[0061] Fig. 16 generally shows an example of a cross-section of an alternative multilayer device 1600 including a substrate 1613, a first conductive layer 1607, a first dielectric layer 1617, a second conductive layer 1608, a second dielectric layer 1618, and a third conductive layer 1609.

[0062] In one example, the first conductive layer 1607 may include a metal source contact 1601. The metal source contact 1601 may cover a plurality of trenched gate structures 1605 to form an active area of ​​the semiconductor device 1600. The second conductive layer 1608, separated from the first conductive layer 1607 by a first dielectric layer 1617, may include a drain conductor 1620 and a gate conductor 1622. In one example, the drain conductor may be connected to the substrate 1613 using a drain-to-substrate contact connection 1614 that extends through the first dielectric layer 1617. In one example, the drain conductor 1620 may cover the metal source contact 1601. In one example, the gate conductor maythe gate conductor line 1622 may be connected to a gate distribution conductor line using a gate contact connection (not shown) extending through the first dielectric layer 1617.

[0063] In one example, where the third conductive layer 1609 is separated from the second conductive layer 1608 by a second dielectric layer 1618, the second dielectric layer 1618 may include a drain pad 1630, a gate pad (not shown), and a source pad 1631. In one example, the source pad 1631 may be connected to the metal source contact 1601 using one or more source contact interconnections 1641 extending through the dielectric material, such as the first and second dielectric layers 1617 and 1618, and provided between the first conductive layer 1607 and the third conductive layer 1609. In one example, the drain pad 1630 may be connected to the drain conductor 1620 using one or more drain contact interconnections 1640 extending through the second dielectric layer 1618.In one example, the gate pad (not shown) may be connected to the gate conductor 1622 using one or more contact connections through the second dielectric layer 1618. In certain examples, one or more of the drain pad 1630, the gate pad (not shown), or the source pad 1631 may each include a planar top surface, such as the planar top surface 1650 of the drain pad or the planar top surface 1651 of the source pad. In one example, the planar top surfaces may be coplanar to form a CSP package. In certain examples, each of the pads may include bondable material, such as aluminum, gold, or other metals used in connection with leads with bond wires.In one example, each of the pads may include solderable material, such as solderable material including copper, silver, tin, chromium, or other underlying barrier metal or a combination of metals to form a metallic surface.

[0064] Fig. 17 generally illustrates an example of a cross-sectional view of a first conductive layer 1707 of a device 1700, such as a multi-level power MOSFET device. In one example, the first conductive layer 1707 may include a metal drain contact 1704, at least a portion of a gate distribution trace 1703 (e.g., a conductive portion of the gate distribution trace 1703), and a metal source contact 1701. In one example, the cross-sectional view of the device 1700 includes exemplary locations of drain contact connections 1710 and gate contact connections 1712 configured to connect the drain metal contact 1704 and the gate distribution trace 1703 to the overlying conductive layers.

[0065] In the example of the cross-sectional view of Fig.17, the metal drain contact 1704, the metal source contact 1701, and the conductive components of the gate distribution trace 1703 are isolated from each other. In one example, the metal drain contact 1704 and the conductive portion of the gate distribution trace 1703 may extend over a portion of the perimeter of the device 1700. In one example, a portion of the metal drain contact 1703 may bisect the metal source contact 1701 near the center of the device 1700.

[0066] In certain examples, the metal drain contact 1704 may vary in width across its length across the device 1700. In one example, the width of the metal drain contact 1704 may taper along its length. In one example, the metal drain contact 1704 may increase in width from the drain contact connections 1710 that connect the metal drain contact 1704 to the drain pads. In one example, the metal drain contact 1704 may gradually change its width along its length, which may reduce the resistance of the path of the metal drain contact 1704 and increase the performance of the device 1700.

[0067] It should be understood that other layouts for the first conductive layer 1707 are possible without departing from the scope of the present invention. Such layouts may include gate distribution lines that differ in width from one another, gate distribution lines whose widths vary across a longitudinal portion of the gate distribution line, or one or more other layouts.

[0068] In certain examples, a multi-level device may include sensor components such as temperature sensors, current sensors, diodes, or resistive components. In one example, the terminals of a sensor component may take advantage of the multi-level nature of the present invention in that the sensor and sensor terminals maximize the active area of ​​the component. For example, a sensor component integrated into the power MOSFET may include one or more contact connections for connecting the component to bondable terminals on the exterior of the integrated device. In semiconductor devices or parts that incorporate terminal pads into the substrate surface, the area beneath the terminal pads may be inactive and of considerable size.The one or more contact connections extending between conductive layers of the integrated multilevel device can maximize the active area at the surface of the device substrate.

[0069] It should be understood that semiconductor devices employing the present invention may include, but are not limited to, power metal-oxide-semiconductor (MOS) field-effect transistors (FETs), planar MOSFETs, double-implantation metal-oxide-semiconductor (DMOS), drain-in-the-back DMOS, trench MOSFETs, including charge-bound devices such as shielded gate devices, insulated gate bipolar transistors (IGBTs), lateral diffused metal oxide semiconductor (LDMOS), MOS-gated thyristors (MCTs), and temperature and current sensing MOS devices. In one example, the source metal contact may be made of, but is not limited to, aluminum (Al), aluminum-silicon (AlSi), aluminum-silicon-copper (AlSiCu), copper (Cu), one or more other metals, or combinations or alloys thereof.Barrier metal including, but not limited to, tungsten (W), platinum (P), titanium (Ti), titanium tungsten (TiW), or titanium nitride (TiN). In certain examples, the gate structures and source structures may include a metal layer of, but not limited to, aluminum (Al), aluminum-silicon-copper (AlSiCu), electroless nickel-gold (ENiAu), titanium-nickel-silver (TiNiAg), titanium-nickel-vanadium-silver (TiNiVAg), copper (Cu), solderable metals such as tin (Sn), or one or more other metals or combinations or alloys thereof. Additional comments

[0070] A semiconductor device according to Example 1 may include a substrate, a first device surface above the substrate, and a first device surface having at least three pads. The at least three pads include a drain pad, a gate pad, and a source pad. The semiconductor device may also include a plurality of trenched gate structures connected to the gate pad, wherein the plurality of trenched gate structures are configured to control the electrical current between the source pad and the drain pad when a voltage is applied to the gate pad and a first conductive layer.The first conductive layer may include a drain contact, the drain contact being connected to the drain pad, a gate distribution trace for the gate, the gate distribution trace being connected to the gate pad, and a source contact coupled between the source pad and the plurality of trenched gate structures. The semiconductor device may further include a second conductive layer, at least a portion of the second conductive layer being separated from at least a portion of the first conductive layer using a dielectric layer, the second conductive layer including a drain conductor, at least a portion of the drain conductor covering at least a portion of the gate distribution trace, and the drain conductor being connected to the drain contact.

[0071] In Example 2, a portion of the drain conductor according to Example 1 may optionally cover at least a portion of the source contact.

[0072] In Example 3, the drain conductor according to Examples 1 and 2 optionally includes the drain pad.

[0073] In Example 4, the semiconductor device according to one or more of Examples 1 to 3 optionally includes a drain contact connection connecting the drain contact to the drain pad.

[0074] In Example 5, the semiconductor device according to one or more of Examples 1 to 4 optionally includes a gate contact connection configured to connect the distribution trace for the gate to the gate pad.

[0075] In Example 6, the distribution conductor track for the gate according to one or more of Examples 1 to 5 optionally contains polycrystalline silicon.

[0076] In Example 7, the distribution conductor for the gate according to one or more of Examples 1 to 6 optionally includes a first metal overlying the polycrystalline silicon, wherein the first conductive layer includes the first metal.

[0077] In Example 8, the polycrystalline silicon (polysilicon) according to one or more of Examples 1 to 7 optionally contains polycrystalline silicon converted into silicon silicide.

[0078] In Example 9, the substrate according to one or more of Examples 1 to 8 optionally includes a channel configured to carry the distribution trace for the gate.

[0079] In Example 10, the substrate according to one or more of Examples 1 to 9 optionally contains an epitaxial layer, wherein the epitaxial layer has the channel.

[0080] In Example 11, the second conductive layer according to one or more of Examples 1 to 10 optionally includes a gate conductor connected to the distribution trace of the gate.

[0081] In Example 12, the gate conductor according to one or more of Examples 1 to 11 optionally contains the gate pad.

[0082] In Example 13, at least a portion of the gate conductor according to one or more of Examples 1 to 12 overlies at least a portion of the source contact.

[0083] In Example 14, the second conductive layer according to one or more of Examples 1 to 13 optionally includes a source conductor connected to the source contact.

[0084] In Example 15, the source conductor according to one or more of Examples 1 to 14 optionally includes the source pad.

[0085] In Example 16, the semiconductor device according to one or more of Examples 1 to 15 optionally includes a third conductive layer, wherein at least a portion of the third conductive layer separates and overlies at least a portion of the second conductive layer using a dielectric layer.

[0086] In Example 17, the third conductive layer according to one or more of Examples 1 to 16 optionally contains at least three pads or connection contacts.

[0087] In Example 18, the at least three pads according to one or more of Examples 1 to 17 optionally each include a top surface, which are substantially coplanar with each other.

[0088] In Example 19, at least the three pads according to one or more of Examples 1 to 18 contain solderable material.

[0089] In Example 20, the drain contact of any one or more of Examples 1 to 19 optionally has a substantially uniform width and extends around the perimeter of the semiconductor device.

[0090] In Example 21, the drain contact according to one or more of Examples 1 to 20 optionally has a decreasing width and extends parallel to the plurality of trench gate structures.

[0091] In Example 22, the drain contact according to one or more of Examples 1 to 21 optionally has a substantially constant width and extends parallel to the plurality of trench gate structures.

[0092] In Example 23, the drain contact according to one or more of Examples 1 to 22 optionally has a tapered width and extends perpendicular to the plurality of trench gate structures.

[0093] In Example 24, the drain contact of any one or more of Examples 1 to 23 optionally has a substantially uniform width and extends perpendicular to the plurality of trench gate structures.

[0094] In Example 25, the distribution conductor track for the gate according to one or more of Examples 1 to 24 optionally contains a metallic connection.

[0095] Example 26 may include, or may optionally be combined with, any portion or combination of any of the portions of any one or more of Examples 1 to 25 to yield an article including means for performing one or more of the functions of Examples 1 to 25, or a machine-readable medium including instructions that, when executed by the machine, cause the machine to perform one or more of the functions of Examples 1 to 25.

[0096] The foregoing description contains references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of example, particular embodiments in which the invention may be practiced. These embodiments are referred to herein as "examples." Such examples may include additional elements or components to those shown or described. Moreover, the inventors of the present invention also contemplate examples that employ any combination or permutation of these shown or described elements (or one or more aspects thereof), either with reference to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) as shown or described herein.

[0097] In this description, the terms "ein" or "eine" are used, as is customary in patent publications, to include one or more than one, regardless of other instances or uses of "at least one" or "one or more." In this description, the term "or" is applied to refer to a "non-exclusive or," such that "A or B" includes "A but not B," "B but not A," and "A and B," unless expressly stated otherwise. In the appended claims, the terms "haltigen" and "in dem" are used as the plain English equivalents of the corresponding terms "umfassend" and "bei der or bei dem." Also, in the following claims, the terms "haltigen" and "umfassend" are used openly or without end, i.e.A system, apparatus, device, article, or method comprising these elements in addition to those listed after such a term in a claim shall nevertheless be considered to fall within the scope of the claim. Furthermore, in the subsequent claims, the terms "first," "second," and "third," etc., are used as identifiers or designators without any intention of numerically defining their subject matter.

[0098] The above description is intended to be illustrative and explanatory. The scope of the invention should therefore be determined based on the appended claims.

Claims

[1] A semiconductor device comprising: a substrate (213, 413, 1313, 1413, 1513, 1613); a first surface of the semiconductor device overlying the substrate (213, 413, 1313, 1413, 1513, 1613), the first surface of the semiconductor device including at least three pads, of which the at least three pads include: a drain pad (1130, 1230, 1330, 1630), a gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532) and a source pad (209, 532, 855, 1131, 1231, 1431, 1631); a plurality of channeled gate structures (1315, 1415, 1605), the plurality of channeled gate structures (1315, 1415, 1605) configured to control the flow of electrical current between the source pad (209, 532, 855, 1131, 1231, 1431, 1631) and the drain pad (1130, 1230, 1330, 1630) when a voltage is applied to the gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532); a first conductive layer (1107, 1207, 1307, 1407, 1507, 1607, 1707) comprising: a drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704), wherein the drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704) is connected to the drain pad (1130, 1230, 1330, 1630); a gate distribution track (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703), wherein the gate distribution track (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703) is connected between the gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532) and a plurality of gate electrodes of the plurality of channeled gate structures (1315, 1415, 1605) is coupled, and a source contact (202, 402, 1101, 1201, 1301, 1501, 1601, 1701) coupled between the source pad (209, 532, 855, 1131, 1231, 1431, 1631) and a plurality of source regions of the plurality of channeled gate structures (1315, 1415, 1605), and a second conductive layer (1108, 1308, 1408, 1508, 1608), wherein at least a portion of the second conductive layer is separated from at least a portion of the first conductive layer using a dielectric layer, wherein the second conductive layer (1108, 1308, 1408, 1508, 1608) includes a drain conductor and at least a portion of the drain conductor covers at least a portion of the gate distribution trace (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703), and the drain conductor is connected to the drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704). [2] The semiconductor device of claim 1, wherein a portion of the drain conductor covers at least a portion of the source contact (202, 402, 1101, 1201, 1301, 1501, 1601, 1701). [3] The semiconductor device of claim 1, wherein the drain conductor includes the drain pad (1130, 1230, 1330, 1630). [4] The semiconductor device of claim 3, including a drain (via) contact connection connecting the drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704) to the drain pad (1130, 1230, 1330, 1630). [5] The semiconductor device of claim 1, including a drain (via) contact connection configured to connect the gate distribution trace (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703) to the gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532). [6] The semiconductor device according to claim 1, wherein the gate distribution line (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703) comprises polycrystalline silicon. [7] The semiconductor device according to claim 6, wherein the gate distribution line (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703) contains a first metal covering the polycrystalline silicon, and wherein the first conductive layer (1107, 1207, 1307, 1407, 1507, 1607, 1707) contains the first metal. [8] The semiconductor device of claim 6, wherein the polycrystalline silicon contains polycrystalline silicon silicide. [9] The semiconductor device of claim 1, wherein the substrate (213, 413, 1313, 1413, 1513, 1613) includes a channel configured to support the gate distribution trace (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703). [10] The semiconductor device of claim 9, wherein the substrate (213, 413, 1313, 1413, 1513, 1613) includes an epitaxial layer, and wherein the epitaxial layer includes the channel. [11] The semiconductor device according to claim 1, wherein the second conductive layer (1108, 1308, 1408, 1508, 1608) includes a gate conductor connected to the gate distribution line (531, 534, 605, 625, 705, 850, 903, 1003, 1103, 1303, 1503, 1703). [12] The semiconductor device of claim 11, wherein the gate conductor includes the gate pad (405, 530, 604, 624, 704, 724, 853, 1132, 1232, 1532). [13] The semiconductor device of claim 11, wherein at least a portion of the gate conductor covers at least a portion of the source contact (202, 402, 1101, 1201, 1301, 1501, 1601, 1701). [14] The semiconductor device of claim 1, wherein the second conductive layer (1108, 1308, 1408, 1508, 1608) includes a source conductor connected to the source contact (202, 402, 1101, 1201, 1301, 1501, 1601, 1701). [15] The semiconductor device of claim 14, wherein the source conductor includes the source pad (209, 532, 855, 1131, 1231, 1431, 1631). [16] The semiconductor device of claim 1, including a third conductive layer, wherein at least a portion of the third conductive layer separates and covers at least a portion of the second conductive layer using a dielectric layer. [17] The semiconductor device of claim 16, wherein the third conductive layer includes the at least three pads. [18] The semiconductor device of claim 1, wherein the at least three pads each have a top surface that is substantially coplanar with each other. [19] The semiconductor device of claim 1, wherein the at least three pads comprise a solderable material. [20] The semiconductor device of claim 1, wherein the drain contact (904, 1004, 1104, 1204, 1304, 1504, 1704) has a substantially constant width and extends around the perimeter of the semiconductor device.

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