semiconductor device

Abstract

Semiconductor device comprising: a substrate (1) having a recess (84) partially defined by a side wall (85), the substrate (1) having a top surface (81); a device insulation layer (3) provided in the recess (84), the device insulation layer (3) having a top surface (83) lower than a top surface (81) of the substrate (1); a memory element (CP) arranged on the substrate (1); one or more first contacts (72) electrically connected to the memory element (CP); and an insulation structure (21a) arranged on a corresponding device isolation region and between the adjacent first contacts (72), the insulation structure (21a) being in direct contact with the adjacent first contacts (72), wherein at least one of the first contacts (72) is in contact with the top side (81) of the substrate (1) and is formed adjacent to the side wall (85) of the recess (84).

Description

background

[0001] Embodiments of the inventive idea relate to a semiconductor device and a method for manufacturing the same.

[0002] Small, multifunctional and / or low-cost semiconductor devices are in high demand in the electronics industry for the production of popular electronic devices such as smartphones. Higher integration of semiconductor devices is desired to meet consumer demand for high-performance and low-cost electronic devices. In the case of semiconductor memory devices, increased integration is particularly desired because their integration is an important factor in determining product prices. However, the very expensive process equipment required to increase the pattern fineness sets a practical limit for high integration of semiconductor memory devices. To overcome this hurdle, numerous studies have been conducted to develop new technologies for increasing the integration density of semiconductor memory devices.

[0003] US 2011 / 0 195 551 A1 discloses: A semiconductor device having a bit line connection with an increased width and a reduced level on a bit line contact, as well as methods for fabricating such devices. These methods include forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a hole in the first conductive layer configured to expose the drain region. A second conductive pattern is formed in the hole of the first conductive layer to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern.A third conductive layer and a bit line cap layer are formed on the first conductive pattern and the second conductive pattern, and are patterned to form a third conductive pattern and a bit line cap pattern. The second conductive pattern, the third conductive pattern, and the bit line cap pattern, sequentially stacked on the drain region, form first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line cap pattern, sequentially stacked on the isolation region, form second bit line structures.

[0004] US 2008 / 0 182 399 A1 discloses: Methods for forming pad structures, in which a first contact region and second contact regions are formed in an active region of a substrate. An insulating interlayer is formed on the substrate. The insulating interlayer has a first opening exposing the first contact region and the second contact regions. First conductive pads are formed in the first opening. Each first conductive pad is in electrical contact with a respective one of the second contact regions. Spacers are formed, each spacer being located on a sidewall of a respective one of the first conductive pads. Finally, a second conductive pad is formed between the first conductive pads and is in electrical contact with the first contact region to complete the pad structure.

[0005] US 2005 / 0 173 750 A1 discloses: A method comprising forming a buried bit line in a substrate; forming an insulating layer in the substrate to define an active region, the insulating layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line extending across the active region at a right angle to the bit line and electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line may be integrally formed.

[0006] US 2011 / 0 147 889 A1 discloses: A semiconductor device including an insulating film over a silicon substrate, the insulating film having an opening and a contact plug in the opening, the contact plug having a first top surface that is lower than a top surface of the insulating film.

[0007] US 2004 / 0 058 499 A1 discloses: A semiconductor device having an element isolating region provided with a trench and an insulating film embedded in the trench, and a method of manufacturing the same.

[0008] US 2009 / 0 267 152 A1 discloses: A device is disclosed having a conductive gate structure overlying a semiconductor layer having a main surface. An insulating material is embedded in a trench region below the main surface of the semiconductor layer. An epitaxial layer is formed over a portion of the main surface and on an active region forming a sidewall of the trench. Summary

[0009] The invention is defined in the appended claims.

[0010] Embodiments of the inventive idea provide a semiconductor device with reduced contact resistance and improved reliability.

[0011] Further embodiments of the inventive idea provide a method for manufacturing a highly integrated semiconductor device which prevents the occurrence of a mask alignment or a contact pad bridge.

[0012] According to exemplary embodiments of the inventive concept, a semiconductor device includes a substrate, a device insulation layer provided in the substrate to have a top surface lower than that of the substrate, a memory element disposed on the substrate, and a first contact electrically connected to the memory element to be connected to top and side surfaces of the substrate. The device further includes an insulation structure provided between adjacent ones of the first contacts.

[0013] In exemplary embodiments, an entire side surface of the first contact may be in contact with a silicon nitride layer.

[0014] In exemplary embodiments, the number of first contacts may be two or more.

[0015] In exemplary embodiments, a top surface of the isolation structure may be substantially coplanar with a top surface of the first contact.

[0016] In exemplary embodiments, a bottom surface of the isolation structure may be deeper than the top surface of the substrate.

[0017] In exemplary embodiments, the device may include a wordline capping structure adjacent to the first contact and a wordline extending along a first direction beneath the wordline capping structure.

[0018] In exemplary embodiments, the word line may be provided in the substrate.

[0019] In exemplary embodiments, a top surface of the wordline capping structure may be substantially coplanar with that of the first contact.

[0020] In exemplary embodiments, the isolation structure has a beam shape extending along a second direction that crosses the first direction.

[0021] In exemplary embodiments, a bottom surface of the isolation structure may be higher than a bottom surface of the wordline capping structure.

[0022] In exemplary embodiments, the insulation layer divides a top surface of the wordline capping structure into a plurality of regions.

[0023] In exemplary embodiments, the device may further include a second contact provided on one side of the first contact and a spacer interposed between the first and second contacts. The spacer may also be referred to as a partition.

[0024] In exemplary embodiments, a bottom surface of the second contact may be deeper than a top surface of the device insulation layer.

[0025] In exemplary embodiments, the device may further comprise a conductive trace extending along the first direction on the second contact. The conductive trace may have the same width as the isolation structure and may intersect the isolation structure in a plan view.

[0026] In exemplary embodiments, the device may further comprise a first doped region provided in the substrate and connected to the first contact, and a second doped region provided in the substrate and connected to the second contact. The second doped region has a depth greater than that of the first doped region.

[0027] According to exemplary embodiments of the inventive concept, a semiconductor device has a plurality of word lines provided in a substrate with a gate insulation layer interposed therebetween to extend along a first direction, word line capping structures respectively arranged on the word lines to protrude upward from a top surface of the substrate, storage node pads arranged between the word line capping structures to be in contact with the substrate, and insulation structures arranged between the storage node pads and between the word line capping structures.

[0028] In exemplary embodiments, the storage node pads, the isolation structures, and the wordline capping structures may have top surfaces that are substantially coplanar with each other.

[0029] In exemplary embodiments, the semiconductor device may further include a device isolation layer in the substrate to define an active region. A top surface of the device isolation layer is deeper than a top surface of the substrate and higher than a bottom surface of the isolation structures.

[0030] In exemplary embodiments, a sidewall of the substrate may be exposed through the device isolation layer, and the storage node pad may extend to cover a portion of a sidewall of the recess formed in the substrate and a top surface of the device isolation layer.

[0031] In exemplary embodiments, the semiconductor device may further include a bit line node contact connected to the substrate between the word lines and spatially separated from the isolation structure, and a bottom surface of the bit line node contact may be deeper than the top surface of the device isolation layer.

[0032] In exemplary embodiments, the semiconductor device may further include an isolation spacer interposed between the bit line node contact and the storage node pad.

[0033] In exemplary embodiments, the semiconductor device may further include a bit line disposed on the bit line node contact. The bit line may overlap with the isolation structures in a top view.

[0034] In exemplary embodiments, the semiconductor device may further include a storage node contact in contact with the storage node pad and a storage element electrically connected to the storage node contact.

[0035] In exemplary embodiments, the substrate may include a cell matrix region, a cell edge region, and a peripheral circuit region, and the memory device may further include a dummy bit line node contact and a dummy isolation structure disposed adjacent to each other in the cell edge region.

[0036] In exemplary embodiments, the dummy isolation structure may have a “U”-shaped structure.

[0037] In exemplary embodiments, a dummy isolation structure may overlap with two adjacent ones of the bit lines.

[0038] In exemplary embodiments, the dummy isolation structure may be arranged closer to an outer region of the cell edge region compared to the dummy bit line node contact. Brief description of the drawings

[0039] Exemplary embodiments will be described in more detail in the following description taken in conjunction with the accompanying drawings. The accompanying drawings are non-limiting exemplary embodiments as described herein. The Fig. 1A is a plan view of a semiconductor device according to exemplary embodiments of the inventive concept. The Fig. 1B is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept, taken along lines A-A', B-B', and CC' of the Fig. 1A is recorded. The Fig. 1C is a cross-sectional view of a semiconductor device according to another embodiment of the inventive concept, taken along lines A-A', B-B', and CC' of the Fig. 1A is recorded. The Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A and Fig. 6A are plan views sequentially illustrating a method of manufacturing the memory device of Fig. 1A illustrate. The Fig. 2B, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F, Fig. 4B, Fig. 4C, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 5E, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E, Fig. 6F, Fig. 6G and Fig. 6H are cross-sectional views sequentially illustrating the method of forming the semiconductor device of Fig. 1A illustrate. The Fig. 5F is a perspective view of a semiconductor device according to an embodiment of the inventive concept. The Fig. 7 is a schematic block diagram of an electronic device including the semiconductor device constructed according to exemplary embodiments of the inventive concept. The Fig. 8 is a schematic block diagram of a memory system including the memory device constructed according to exemplary embodiments of the inventive concept.

[0040] It should be noted that these figures are intended to illustrate general characteristics of methods, structures, and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not to scale and do not reflect the precise structure or performance characteristics of any given embodiment and should not be construed as defining and / or limiting the scope of values or characteristics encompassed by example embodiments. For example, the relative thickness and position of molecules, layers, regions, and / or structural elements may be reduced in size or exaggerated for clarity.

[0041] The use of similar or identical reference numerals in the different drawings is intended to indicate the presence of a similar or identical element or feature. Detailed description

[0042] Exemplary embodiments of the inventive concept will now be described in more detail with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the specific embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0043] It is understood that when an element is described as being "connected to" or "coupled to" another element, it is directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is described as being "directly connected to" or "directly coupled to" another element, no intervening elements are present. Like reference numerals indicate like elements throughout. As used herein, the terms "and / or" include any combination of one or more of the associated listed items. Other words used to describe relationships between elements or layers should be interpreted in a similar manner (e.g., "between" versus "directly connected," "adjacent" versus "directly adjacent," "on" versus "directly upon").

[0044] It should be understood that although the terms "first," "second," etc., are used herein to describe different elements, components, regions, layers, and / or subregions, these elements, components, regions, layers, and / or subregions are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or subregion from another element, component, region, layer, or subregion. Therefore, a first element, component, region, layer, or subregion discussed further below could be referred to as a second element, component, region, layer, or subregion without departing from the teachings of the inventive concept.

[0045] Spatially related terms such as "beneath," "under," "lower," "above," "above," "above," "upper," and the like may be used herein for ease of description to describe an element or the relationship of a feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relevant terms are intended to encompass different orientations of the device in operation in addition to the orientation as described in the figures. For example, if the device is rotated in the figures, elements described as "below" or "deeper" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" can delineate both an upward and downward orientation.The device may be oriented differently (rotated by 90° or in a different orientation) and the spatially relevant terms used here may be interpreted accordingly.

[0046] The technical language used herein is intended only to describe particular embodiments and is not intended to limit the inventive concept. As used herein, the singular forms "a" and "an" are intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, it is to be understood that the terms "he / she / it comprises" and / or "comprising", when used in this specification, indicate the presence of certain features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0047] Example embodiments of the inventive concept are described herein with reference to schematic views, perspective, and cross-sectional illustrations, which are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. Therefore, deviations from the shape of the illustrations are to be expected as a result, for example, of manufacturing techniques and / or tolerances. Consequently, example embodiments of the inventive concept should not be construed as limiting the particular shapes of the regions illustrated herein, but should be understood to include variations in shape resulting, for example, from manufacturing processes.An implanted region illustrated as a rectangle may have rounded or curved characteristics and / or a gradient of implant concentration at its edge regions, rather than a binary transition from an implanted to a non-implanted region. Likewise, a recessed region formed by implantation may develop at some implantation in the region between the recessed region and the surface through which the implantation takes place. Consequently, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one skilled in the art to which exemplary embodiments of the inventive concept refer. Furthermore, it is understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant art and are not interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] The Fig. 1A is a plan view of a semiconductor device according to an exemplary embodiment of the inventive concept and the Fig. 1B is a cross-sectional view of a semiconductor device according to an embodiment of the inventive concept, taken along lines A-A', BB' and CC' of the Fig. 1A are recorded.

[0050] Regarding the Fig. 1A and Fig. 1B, a substrate 1 may include a cell array region CAR and a peripheral circuit region PCR. The cell array region CAR may include a cell edge region ER in which dummy structures may be arranged. A device insulation layer 3 may be provided in a recess or trench 84 formed in the substrate 1 to define at least one active region AR. In a plan view, the active region AR may be shaped like a bar extending along a first direction D1, and in exemplary embodiments, the at least one active region AR may include a plurality of active regions that may be spatially spaced from each other and parallel to each other. A plurality of word lines WL may be provided on the substrate 1 to intersect the active region AR and the device insulation layer 3.The word lines WL may extend, for example, along a second direction D2. The word lines WL may be formed of a conductive material such as doped polysilicon, metal silicide, and / or a metal. The second direction D2 may not be parallel to the first direction D1. The word lines DL may be provided in a recessed region R. Top surfaces of the word lines WL may be deeper than a top surface of the substrate 1. Hereinafter, each of the word lines WL may be referred to as a cell gate structure. A gate insulation layer 7 may be interposed between the word lines WL and the substrate 1. A first doped region 11 may be provided in the substrate 1 on one side of the word line WL, and a second doped region 13 may be provided in the substrate 1 on another side of the word line WL.The second doped region 13 may be interposed between two adjacent word lines WL. The second doped region 13 may have a bottom surface positioned at a lower level than that of the first doped region 11. In some embodiments, the bottom surface of the second doped region 13 may be positioned at substantially the same level as that of the first doped region 11.

[0051] A first wordline capping structure 14 may be provided on the wordlines WL. The first wordline capping structure 14 may protrude from the top surface of the substrate 1. A top surface of the first wordline capping structure 14 may, for example, be higher than that of the substrate 1. The first wordline capping structure 14 may, for example, comprise silicon nitride, silicon oxynitride, silicon oxide, or combinations thereof. Storage node pads 25a may contact the first doped region 11 between adjacent ones of the wordline capping structures 14. Additionally, isolation structures 21a may be provided between adjacent storage node pads 25a and overlie the device isolation layer 3. The isolation structure 21a may be made of the same material as the wordline capping structures 14.The isolation structure 21a, the storage node pads 25a and the first word line capping layer structure 14 may have top surfaces that are substantially coplanar to each other according to an embodiment of the inventive concept.

[0052] The storage node pads 25a may be spatially separated from each other by the isolation structure 21a. In a plan view, the storage node pads 25a may have a rectangular structure, but may also have a curved region adjacent to a bit line node contact DC. According to exemplary embodiments of the inventive concept, each of the storage node pads 25a may have a bottom surface larger than that of the conventional storage node pad (e.g., a cylindrical storage node pad). The area of the storage node pad 25a in contact with the active region AR may be increased, for example, by 1.37 times compared to the conventional or cylindrical storage node pad. Accordingly, it is possible to reduce a contact resistance between the storage node pad 25a and the first doped region 11.

[0053] A top surface of the device insulation layer 3 may be deeper than that of the substrate 1 and higher than a bottom surface of the insulation structure 21a. A height difference between the top surfaces of the device insulation layer 3 and the substrate 1 may be less than approximately 80 Å.

[0054] In some embodiments, the storage node pads 25a may extend to cover a portion of a sidewall of the recess 84 formed in the substrate 1 and the top surface of the device isolation layer 3. As in the sectional view BB' of the Fig. As shown in Fig. 1B, the storage node pad 25a may be formed to cover both sides of a protruding portion of the substrate 1. This increases a contact area between the storage node pad 25a and the substrate 1.

[0055] In the present embodiment, since the word lines WL are provided in the recessed region R, a cell transistor can have a recessed channel region. This can reduce short-channel effects and reduce leakage current in a highly integrated semiconductor device.

[0056] In the cell array region CAR, a first insulation layer 27 may be provided on the substrate 1. A bit line BL may be provided on the first insulation layer 27 to extend along a third direction D3 intersecting both the first and second directions D1 and D2. The bit line BL may overlap with the insulation structures 21a in a sectional view. The bit line BL may be a layer comprising metal. A width of the bit line BL may be substantially equal to a width of the insulation structure 21a. In addition, the bit line BL and the insulation structure 21a may vertically overlap. Sidewalls of the bit line BL and the insulation structure 21a may be aligned with each other.

[0057] The bit line BL may be electrically connected to the second doped region 13 via the bit line node contact DC. The bit line node contact DC may comprise, for example, metal, silicide, doped polysilicon, metal nitride, a metal, and combinations thereof. An upper width of the bit line node contact DC may be substantially equal to the width of the bit line BL. The bit line node contact DC may be provided in a bit line node hole 37 formed by etching the first insulation layer 27, a portion of the first word line capping layer structure 14, and a portion of the substrate 1. A bottom surface of the bit line node hole 37 or a bottom surface of the bit line node contact DC may be deeper than the top surface of the device insulation layer 3.

[0058] A sidewall of the bit line node hole 37 may be covered with a first spacer 39. In exemplary embodiments, the first spacer 39 may have a thickness ranging from approximately 30 Å to approximately 300 Å. The first spacer 39 with this thickness allows the storage node pad 25 to be effectively electrically separated from the bit line node contact DC. Sidewalls of the bit line BL and the bit line node contact DC may be covered with a second spacer 47a. A sidewall of the first spacer 39 may be covered with a third spacer 47b. The first, second, and third spacers 39, 47a, and 47b may be formed from at least one layer selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. The side wall of the second spacer 47a may be spatially separated from the side wall of the third spacer 47b.

[0059] According to exemplary embodiments of the inventive concept, as described in the Fig. 1A and Fig. 1B, the first wordline capping layer structure 14, the isolation structure 21a, and the first spacer 39 may be provided on sidewalls of the storage node pad 25a. Therefore, if the first wordline capping layer structure 14, the isolation structure 21a, and the first spacer 39 are formed from the same material (e.g., a silicon nitride layer), the sidewalls of the storage node pads 25a may be covered with the same material.

[0060] With regard to the Fig. 1A, a dummy bit node contact BCD may be provided in the cell edge region ER. The dummy bit node contact BDC may have the same shape as the bit node contact BDC, but may be provided for a different purpose from that of the bit node contact DC. Additionally, a dummy isolation structure 21c may be provided in the cell edge region ER. The dummy isolation structure 21c may be arranged at the edge region of the cell edge region ER (e.g., outside the dummy bit node contact DDC). For example, the dummy isolation structure 21c may be arranged closer to an edge region of the cell edge region ER than to the dummy bit node contact DDC. The dummy isolation structure 21c may be formed of the same material as the isolation structure 21a. The dummy insulation structure 21c may be shaped like the letter “U”.The dummy isolation structure 21c may overlap adjacent bit lines. The dummy isolation structure 21c may connect adjacent dummy bit line node contacts DDC.

[0061] Regarding the Fig. 1B, the second insulation structure 50 may be provided on the first insulation layer 27. The second insulation layer 50 may extend between the first spacer 47a and the third spacer 47b and cover sidewalls of the second spacer 47a and the third spacer 47b. A storage node contact BC may be connected to the storage node pads 25a through the first and second insulation layers 27 and 50. The storage node contact BC may comprise at least one material selected from the group consisting of a metal silicide layer, a polysilicon layer, a metal nitride layer, and a metal layer. A bottom electrode pad BEP may be provided on the second insulation layer 50. The bottom electrode pad BEP may penetrate at least a portion of the second insulation layer 50 and thus be connected to the storage node contact BC.In some embodiments, some or all of the storage node pads 25a, the storage node contact BC, and the lower electrode pad BEP may optionally be referred to as a contact. In this case, the contact may be considered as an upper region, e.g., the storage node contact BC, and a lower region, e.g., the storage node contact 25a, and the upper region may be adjacent to the lower region.

[0062] In the peripheral circuit region PCR, a peripheral circuit gate electrode 68 may be provided on the substrate 1. The peripheral circuit gate electrode 68 may include a first gate layer 33 and a second gate layer 43 stacked in sequence. The first gate layer 33 may be a polysilicon layer, while the second gate layer 43 may be a metal-containing layer. The second gate layer 43 may be made of the same material as the bit line BL. In other words, gate electrodes in the peripheral circuit region may be made of the same material as the bit line BL in the cell array region, and thus, there is no need to perform an additional plating process for the gate electrode. This simplifies the manufacturing process and reduces an interlayer thickness. A sidewall of the peripheral circuit gate electrode 68 may be covered with a fourth spacer 47c.Top surfaces of the bit line BL and the peripheral circuit gate electrode 68 may be covered with a second word line capping layer structure 45. The second to fourth spacers 47a, 47b, and 47c may be formed of the same material.

[0063] A doped peripheral circuit region 69 may be provided in the substrate 1 on both sides of the peripheral circuit gate electrode 68. The substrate 1 of the peripheral circuit region PCR may be covered with the second insulation layer 50. The bit line BL may be electrically connected to the doped peripheral circuit region 69 through a first peripheral contact 72 penetrating the second word line capping structure 45, a peripheral wire 70 deposited on the second insulation layer 50, and a second peripheral contact 77 penetrating the second insulation layer 50. The first peripheral contact 72, the second peripheral contact 74, and the peripheral wire 70 may be connected to each other to form a single interconnect structure. The first peripheral contact 72, the second peripheral contact 74 and the peripheral wire 70 may be formed of the same material as the lower electrode pad BEP.

[0064] In the cell array region CAR, the third insulating layer 51 may be provided on the second insulating layer 50. The third insulating layer 51 may be formed of the same material as the first and second insulating layers 27 and 50. An etching stop layer 52 may be provided on the third insulating layer 51 and have an opening to expose the lower electrode pad BEP. A memory element may be provided on the lower electrode pad BEP. In the present embodiment, the memory element may be a capacitor CP, and the semiconductor device may be a DRAM device. A lower electrode 60 may be provided, for example, on the third insulating layer 51 in the cell array region CAR. The lower electrode 60 may be electrically connected to the lower electrode pad BEP through the etching stop layer 52. The lower electrode pad BEP may be shaped, for example, like a plug or a pillar.At least one support layer may be provided to support a sidewall of the lower electrode 60. The at least one support layer may, for example, comprise first and second support structures 40 and 41 that are vertically spatially separated from one another, as well as in the . Fig. 1B. The support structures 40 and 41 may be arranged to support sidewalls of at least two adjacent lower electrodes 60. In a plan view, a shape of each of the support structures 40 and 41 may be modified. The support structures 40 and 41 make it possible to substantially prevent the lower electrodes 60 from tilting.

[0065] A dielectric 58 may be provided to uniformly cover exposed areas of the bottom electrode 60 and the support structures 40 and 41. The dielectric 58 may be a high-k dielectric layer (e.g., metal oxide). The dielectric 58 may be uniformly covered with a top electrode layer 56. The bottom electrode 60, the dielectric 58, and the top electrode layer 56 may form the capacitor CP, which serves as the storage element. The top electrode layer 56 may, for example, comprise a titanium nitride layer. The top electrode layer 56 may be covered with a plate electrode layer 62. The plate electrode layer 62 may, for example, comprise tungsten. In several embodiments, the plate electrode layer 62 may fill spaces between the bottom electrodes 60, between the support structures 40 and 41, and between the bottom electrodes 60 and the support structures 40 and 41 adjacent thereto.

[0066] In the semiconductor device according to the exemplary embodiment, the storage node pads 25, which are arranged adjacent to each other between the word lines WL, may be separated from each other by an isolation structure 21a. Consequently, it is possible to increase contact areas between the storage node pads 25a and the first doped region 11. Additionally, the storage node pads 25a may extend to cover a side surface of the first doped region 11 to increase the contact area and reduce contact resistance between the storage node pad 25a and the first doped region 11.

[0067] In some embodiments, a semiconductor device may include a substrate 1 having a recess (or trench) 84 partially defined by a sidewall 85 ( Fig. 1B). Those skilled in the art will understand how the recess is formed using techniques such as shallow trench isolation. The substrate 1 has a top surface 81. The semiconductor device may include a device isolation layer 3 formed in the recess 84. The device isolation layer 3 may have a top surface 83 deeper than the top surface 81 of the substrate 1. A memory element, e.g., CT, may be disposed over the substrate 1. One or more storage node pads 25a are electrically connected to the memory element. At least one of the storage node pads 25a may be in contact with the top surface 81 of the substrate 1 and may be formed adjacent to the sidewall 85 of the recess 84. In some embodiments, the storage node pads 25a may extend to cover a portion of the sidewall 85.

[0068] The Fig. 1C is a cross-sectional view of a semiconductor device according to further exemplary embodiments of the inventive concept, taken along lines A-A', BB' and CC' of the Fig. 1A are recorded.

[0069] Regarding the Fig. 1C, a semiconductor device according to the present embodiment may differ in a structure of the bit line node contact DC from that shown in relation to the Fig. 1B. The bit line node contact DC may fill the bit line node hole 37. A width of the bit line node contact DC may be larger than that of the bit line BL. The first spacer 37 may, for example, be interposed only between the bit line node contact DC and the first insulation layer 27. In other words, the third spacer 47b may be Fig. 1B may be omitted in the semiconductor device according to the present embodiment. The second spacer 47a may cover side surfaces of the bit line BL and a portion of the top surface of the bit line node contact DC. Apart from the characteristics discussed above, the semiconductor device according to the present embodiment may be configured to have the same characteristics as those previously discussed with respect to the Fig. 1B described embodiment.

[0070] The Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A and Fig. 6A are sectional views sequentially showing a method of forming the semiconductor device of the Fig. 1A. The Fig. 2B, 3B to 3D, 4B, 4C, 5B to 5E and 6B to 6H are cross-sectional views taken along lines A-A', BB' and CC' of the corresponding Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A and Fig. 6A and show the method of manufacturing the semiconductor device of the Fig. 1A.

[0071] Regarding the Fig. 2A and Fig. 2B, the substrate 1 may be prepared with the cell array region CAR and the peripheral circuit region PCR. The cell array region CAR may include the cell edge region ER. The device isolation layer 3 may be formed in the substrate 1 to define the active region AR. The device isolation layer 3 may be formed using a shallow trench isolation (STI) technique. The device isolation layer 3 may be formed from at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. An ion implantation process using an ion structure (not shown) may be performed on the active region AR of the cell array region CAR to form the first doped region 11 and the second doped region 13.In certain embodiments, the ion implantation process may be performed several times and the second doped region 13 may be formed to form a bottom deeper than that of the first doped region 11.

[0072] A plurality of first mask patterns 15 may be formed on the substrate 1. Each of the first mask patterns 15 may be shaped like a line pattern extending along the second direction D2. The first mask pattern 15 may comprise, for example, silicon oxide. Furthermore, the first mask pattern 15 may be formed to intersect the active region AR and the device isolation layer 3.

[0073] The substrate 1 and the device insulation layer 3 may be patterned using the first mask pattern 15 as an etching mask to form the first hole 6 in the cell array region CAR. The first hole 6 may have a bottom surface positioned at a level higher than a bottom surface of the device insulation layer 3. The gate insulation layer 7 may be formed on a portion of the substrate 1 exposed by the first hole 6. The gate insulation layer 7 may be formed of, for example, a thermal oxide. A conductive layer may be inserted into the first hole 6 provided with the gate insulation layer 7 and then recessed to form the word line WL.

[0074] The first wordline capping layer structure 14 may be formed in the first hole 6 to cover the wordline WL. The first wordline capping layer structure 14 may be formed, for example, from silicon nitride and / or silicon oxynitride. The first wordline capping layer structure 14 may be formed by depositing an insulating capping layer on the wordline WL to fill the first hole 6 and then exposing a top surface of the first mask structure 15 by performing a polishing process. As a result of the polishing process, the first wordline capping layer structure 14 may have a top surface that is substantially coplanar with the top surface of the first mask structure 15. Additionally, the first wordline capping layer structure 14 may have a side surface that is aligned with the first mask structure 15 in a self-aligned manner. The top surface of the first wordline capping layer structure 14 may be higher than that of the substrate 1.In other words, the first word line capping layer structure 14 may protrude above a plane of the top surface of the substrate 1.

[0075] Regarding the Fig. 3A and Fig. 3B, after forming the first wordline capping layer structure 14, second mask patterns 17 may be formed on the substrate 1. The second mask patterns 17 may include a plurality of line-shaped patterns extending along the third direction D3, intersecting both of the first and second directions D1 and D2. Line-shaped openings 19 may be formed between the second mask patterns 17 to expose the first mask pattern 15 and the first wordline capping layer structure 14. The openings 19 may be connected to each other in the cell edge region ER. The second mask patterns 17 with the opening 19 may be formed using a double-pattern technology. A plurality of line-shaped photoresist patterns may be formed to have a minimum width, for example, using an ArF or KrF photolithographic process.Thereafter, a first layer may be uniformly formed to cover sides and surfaces of the photoresist pattern. Subsequently, a second layer may be formed on the first layer to fill spaces between the photoresist patterns and to have a top surface coplanar with the uppermost surface of the first layer. Next, the first layer between the second layer and the photoresist pattern may be removed. An underlying layer may then be etched using the second layer and the photoresist pattern as an etch mask to form the mask patterns 17.

[0076] Alternatively, a plurality of line-shaped photoresist structures may be formed using an ArF or KrF photolithographic process to have a minimum width. Thereafter, a first layer may be uniformly formed to cover sides and surfaces of the photoresist structure and anisotropically etched to form spacers covering both sidewalls of the photoresist structure. Afterward, the photoresist structures may be removed, and an underlying layer may be etched using the spacers as an etching mask to form the mask structures 17.

[0077] The use of the dual-structure technology can overcome the limitations of the ArF or KrF photolithographic process without using a costly EUV process. That is, the second mask structures 17 can be formed to have a line shape defining the opening 19 and having a width smaller than the minimum width using the ArF or KrF lithographic process.

[0078] In a conventional lithographic process, the process should be performed twice to form the conventional storage node pad having a cylindrical shape because the space between adjacent storage node pads is too small. This increases the risk of alignment error. In contrast, according to exemplary embodiments of the inventive concept, it is only necessary to perform the lithographic process once. Consequently, the risk of alignment error can be reduced.

[0079] Regarding the Fig. 3A and Fig. 3C, the first mask pattern 15 and the first wordline cap layer pattern 14 may be etched using the second mask patterns 17 as an etch mask to form the second holes 19a and 19b. The second holes 19a and 19b may include a first recessed portion 19a exposing a portion of the device isolation layer 3 and a second recessed portion 19b exposing a portion of the active region AR of the substrate 1. Upper portions of the device isolation layer 3 and the substrate 1 exposed by the second holes 19a and 19b may be overetched. In exemplary embodiments, the etching process may be controlled such that an etch depth in the device isolation layer 3 is greater than in the active region AR of the substrate 1.Consequently, a first height difference H1 between a bottom surface of the first recessed region 19a and the top surface of the substrate 1 may be greater than a second height difference H2 between a bottom surface of the second recessed region 19b and the top surface of the substrate 1. In exemplary embodiments, the second height difference H2 may be in a range from about 10 Å to about 350 Å. Although not shown in the . Fig. 3C, the second hole 19a, 19b may be formed in the first word line capping layer structure 14, but it may not expose the top surface of the word line WL.

[0080] Regarding the Fig. 3A and Fig. 3D, the second mask pattern 17 may be optionally removed. An insulating isolation layer may be formed on the first mask pattern 15 to fill the second hole 19a and 19b. The isolation layer may comprise silicon nitride and / or silicon oxynitride. A polishing process may be performed on the isolation layer to expose the top surface of the first mask pattern 15 and to form isolation patterns 21a and 21b in the second hole 19a and 19b. The isolation patterns 21a and 21b may comprise the first isolation pattern 21a provided in the first recessed region 19a and the second isolation pattern 21b provided in the second recessed region 19b. The first isolation pattern 21a may be in contact with the device isolation layer 3, and the second isolation pattern 21b may be in contact with the second doped region 19 of the substrate 1.The dummy isolation structure 21c may be formed on the cell edge region ER. The dummy isolation structure 21c may be formed to have a "U"-shaped structure in a plan view and to connect adjacent ones of the isolation structures 21a and 21b to each other. The bottom surface of the first isolation structure 21a may be deeper than that of the second isolation structure 21b. When the bottom surfaces of the first and second isolation structures 21a and 21b are each deeper than the top surfaces of the device isolation layer 3 and the substrate 1, the first and second isolation structures 21a and 21b can be positioned more firmly. This allows the storage node pads formed in subsequent steps to be electrically isolated from each other.

[0081] Although it is not in the Fig. As shown in Figure 3D, the isolation structures 21a and 21b may be formed in the second holes 19a, 19b in the first wordline capping layer structure 14. The isolation structures 21a and 21b may be aligned with the first mask structures 15 in a self-aligned manner. Furthermore, the first wordline capping layer structure 14, the first mask structures 15, and the isolation structures 21a and 21b may have top surfaces that are substantially coplanar with each other.

[0082] Regarding the Fig. 3E, a third mask pattern 23 may be formed on the substrate 1 to cover the peripheral circuit region PCR, exposing the cell array region CAR. The first mask pattern 15 may be removed using the third mask pattern 23 as an etching mask to expose sidewalls of the first word line capping pattern 14 and the isolation patterns 21a and 21b, and to expose the device isolation layer 3 and the substrate 1. When both the first mask pattern 15 and the device isolation layer 3 are formed of the same material (e.g., silicon oxide), an upper portion of the device isolation layer 3 may be partially etched during the removal of the first mask pattern 15. The first mask pattern 15 may be removed using a wet etching process.As a result of partially etching the upper portion of the device insulation layer 3, the device insulation layer 3 may have a top surface that is deeper than the top surface of the substrate 1. This third height difference H3 between top surfaces of the device insulation layer 3 and the substrate 1 may be less than approximately 80 Å. Since the first mask pattern 15 is removed using a wet etching process, the removal process can be performed without the risk of producing etching byproducts by a dry etching process. Accordingly, unlike a dry etching process, it appears unnecessary to perform an over-etching process to remove etching byproducts. Consequently, the top portion of the device insulation layer 3 may not be excessively removed.Consequently, the surface area of the device isolation layer 3 and a bottom surface of the storage node pad formed thereon cannot be excessively reduced. Consequently, a gate-induced drain leakage current (GIDL) effect can be reduced. In exemplary embodiments, the third height difference A3 can be smaller than the first height difference H1. In this case, the remaining area of the device isolation layer 3 can be in contact with the bottom surface and the lower sidewall of the first isolation structure 21a. Consequently, the first isolation structure 21a can be supported by the device isolation layer 3 and can be prevented from falling, allowing the storage node pads to be electrically isolated from each other.

[0083] Alternatively, in other embodiments, as shown for example in the Fig. 3F, the device isolation layer 3 may be formed to have a top surface that is substantially coplanar with the top surface of the substrate 1. The first mask pattern 15 and the device isolation layer 3 may, for example, be formed from a different material, and the upper portion of the device isolation layer 3 may not be formed during the reception of the first mask pattern 15 as in the Fig. 3E illustrated embodiment.

[0084] Regarding the Fig. 4A and Fig. 4B, the third mask pattern 23 may be removed to expose the first mask pattern 15 on the peripheral circuitry region PCR. A conductive layer may be applied to the substrate 1 and then polished to expose the top surfaces of the first wordline capping pattern 14 and the isolation patterns 21a and 21b, and to form a first storage node pad 25 in contact with the substrate 1 between the first wordline capping pattern 14 and the isolation patterns 21a and 21b. The conductive layer may be, for example, a doped polysilicon layer. The first storage node pad 25 may be formed to connect the first doped region 11 to the second doped region 13.Since the first storage node pad 25 is formed in a self-aligned manner with respect to the first word line capping layer structure 14 and the isolation structures 21a and 21b, an alignment error between the second doped region 13 and the first storage node pad 25 can be reduced. To prevent a void from forming in the first storage node pad 25, a deposition step and an etching step may be repeatedly performed during the formation of the conductive layer. After forming the first storage node pad 25, the first isolation layer 27 may be formed on the substrate 1.

[0085] Regarding the Fig. 4C, the first insulation layer 27 and the first mask pattern 15 may be removed from the peripheral circuitry region PCR to expose the substrate 1. A peripheral gate insulation layer 31 and the first gate layer 33 may be formed on the substrate 1 of the peripheral circuitry region PCR by performing deposition and polishing processes. The first gate layer 33 may be formed, for example, from a doped polysilicon layer. The surface of the first gate layer 33 on the peripheral circuitry region PCR may be substantially coplanar with the top surface of the first insulation layer 27 on the cell array region CAR.

[0086] Regarding the Fig. 5A and Fig. 5B, a fourth mask pattern 35 may be formed on the substrate 1 to include a second opening 24 provided on the second doped region 13. The second opening 24 may be formed to expose the first insulation layer 27. A width of the second opening 24 may be larger than that of the second insulation pattern 21b.

[0087] Regarding the Fig. 5A and Fig. 5C, portions of the first insulation layer 27, the first storage node pad 25, and the second insulation structure 21b may be removed using the fourth mask pattern 35 as an etch mask to form the bit line node hole 37 and the storage node pad 25a. In exemplary embodiments, the storage node pad 25a may be electrically connected exclusively to the first doped region 11. A width of the bit line node hole 37 may be larger than a space between adjacent word line capping layer structures 14. Consequently, a sidewall of the word line capping layer structure 14 may be partially removed during the formation of the bit line node hole 37. However, the bit line node hole 37 may be formed such that it does not expose any portion of the word line WL.A fourth height difference H4 between a bottom surface of the bit line node hole 37 and a top surface of the first word line capping layer structure 14 may be greater than the second height difference H2. In exemplary embodiments, the fourth height difference H4 may be in a range from approximately 30 Å to approximately 600 Å. Accordingly, the second isolation structure 21b may not remain on a bottom surface of the bit line node hole 37.

[0088] Regarding the Fig. 5A and Fig. 5D, the fourth mask pattern 35 may be removed. The first spacer 39 may be formed to cover a sidewall of the bit line node hole 37. The first spacer 39 may have a thickness T1 of approximately 30 to 300 Å.

[0089] Regarding the Fig. 5A and Fig. 5E, the conductive layer may be applied to fill the bit line node hole 37. The conductive layer may be polished to expose the top surface of the first insulation layer 27 and to form the bit line node contact DC in the bit line node hole 37. In exemplary embodiments, the dummy bit line node contact DDC may be formed on the cell edge region ER to have substantially the same shape as the bit line node contact DC.

[0090] The Fig. 5F is a perspective view of the semiconductor device of the Fig. 5E, which runs along lines AA' of the Fig. 5A and on a plane of the top side of the first word line capping layer structure 14. With respect to the Fig. 5F, the first wordline capping layer structure 14, the first isolation structure 21a, and the first spacer 39 may be provided adjacent to the storage node pad 25a. If the first wordline capping layer structure 14, the isolation structure 21a, and the first spacer 39 are formed from the same material (e.g., a silicon nitride layer), substantially the entire side surface of the storage node pad may be surrounded by the silicon nitride layer.

[0091] Regarding the Fig. 6A and Fig. 6B, the second gate layer 43 and the second word line capping layer structure 45 may be formed substantially on the entire area of the structure provided with the bit line node contact DC.

[0092] Regarding the Fig. 6A and Fig. 6C, the second wordline capping layer structure 45 and the second gate layer 43 on the cell array region CAR may be substantially patterned to form the bitline BL and to expose the top surface of the bitline node contact DC. In exemplary embodiments, the bitline BL may be formed such that a width W2 thereof is substantially equal to the width W1 of the first isolation structure 21a. In a top view, the bitline BL may cover the first isolation structure 21a, and thus, the bitline BL and the first isolation structure 21a may have sidewalls that are vertically aligned with each other. The second wordline capping layer structure 45 and the second gate layer 43 may be etched in the peripheral circuitry region PCR, and in this case, the top surface of the first gate layer 33 may be exposed.

[0093] Regarding the Fig. 6A and Fig. 6D, the first gate layer 33 may be etched from the peripheral circuit region PCR to form the peripheral circuit gate electrode 68. If the first gate layer 33 and the first bit line node contact DC are formed from the same material (e.g., a polysilicon layer), the bit line node contact DC may also be etched during etching of the first gate layer 33. In exemplary embodiments, the bit line node contact DC may be formed such that a lower portion thereof is wider than an upper portion thereof.

[0094] Regarding the Fig. 6A and Fig. 6E, the doped peripheral circuit region 69 may be formed in the peripheral circuit region PCR of the substrate 1. A spacer layer may be uniformly formed on the resulting structure. Next, a spacer layer is anisotropically etched to simultaneously form the second, third, and fourth spacers 47a, 47b, and 47c. The second spacer 47a may be formed to form side surfaces of the bit line BL and the bit line node contact DC, the third spacer 47b may be formed to cover a side surface or side wall of the first spacer 39, and the fourth spacer 47c may be formed to cover a side surface or side edge of the peripheral circuit gate electrode 68.

[0095] Regarding the Fig. 6F, the second insulation layer 50 may be formed on the resulting structure and then polished to expose a second word line capping layer structure 46. In the cell array region CAR, the second insulation layer 50 and the first insulation layer 27 may be patterned to form a storage node hole 53 contacting the storage node pad 25a as shown in FIG. Fig. 6G. Thereafter, a storage node contact BC can be formed by filling the storage node hole 53 with a conductive layer. Since the storage node pad 25a is formed to have an enlarged area, it is possible to reduce the alignment error during the formation of the storage node hole, thereby increasing the alignment error limitation.

[0096] With reference again to the Fig. 6G, the second wordline capping layer structure 45 may be etched into the peripheral circuitry region PCR to expose a portion of the bitline BL, and the second insulation layer 50 may be etched to expose the doped peripheral circuitry region 69. In exemplary embodiments, an upper portion of the storage node contact BC may be partially removed during this etching process.

[0097] Regarding the Fig. 6H, a conductive layer may be applied and patterned to form the lower electrode pad BEP, the first and second peripheral contacts 72 and 74, and the peripheral wire 70.

[0098] With reference to the Fig. 1A and Fig. 1B, the third insulating layer 51 may be formed on the cell array region CAR to fill a space between the lower electrode pad BEP. The etch stop layer 52 may be formed on the third insulating layer 51. Mold layers (not shown) and support layers 40 and 41 may alternatively be formed on the etch stop layer 52. The lower electrode 60 may be connected to the lower electrode pad BEP through the support layers 40 and 41, the mold layers, and the etch stop layer 52. After that, the mold layers may be removed. Here, the support layers 40 and 41 may not be removed. The dielectric 58, the upper electrode layer 56, and the plate electrode 62 may be formed on the cell array region CAR.

[0099] The semiconductor memory devices described above can be packaged using a variety of different packaging techniques. The semiconductor memory devices according to the aforementioned embodiments may be manufactured, for example, using any of a package-on-package (POP) technique, a ball grid array (BGA) technique, a chip-scale package (CSP) technique, a plastic-leaded chip carrier (PLCC) technique, a plastic dual in-line package (PDIP) technique, a die-in-waffle package technique, a die-in-wafer form technique, a chip-on-board (COB) technique, a ceramic dual in-line package (CERDIP) technique, a plastic quad flat package (PQFP) technique, a thin quad flat package (TQFP) technique, a small outline package (SOIC) technique, a Shrink Small Outline Package (SSOP) technology, a Thin Small Outline Package (TSOP) technology, a Thin Quad Flat Package (TQFP) technology, a System-In-Package (SIP) technology,a multi-chip package (MCP) technology, a wafer-level fabricated package (WFP) technology and / or a wafer-level processed stack package (WSP) technology.

[0100] The package in which the semiconductor memory device according to any of the above embodiments is mounted may further include at least one semiconductor device (e.g., a control device and / or a logic device) that controls the semiconductor memory device.

[0101] The Fig. 7 is a block diagram schematically illustrating electronic devices including a semiconductor device according to exemplary embodiments of the inventive concept.

[0102] Regarding the Fig. 7, an electronic device 1300 including a semiconductor device according to exemplary embodiments of the inventive concept can be used in one of a personal digital assistant (PDA), a laptop computer, a mobile computer, a web tablet, a cordless phone, a mobile phone, a digital music player, a wired or wireless electronic device, or a complex electronic device comprising at least two thereof. The electronic device 1300 can include a control unit 1310, an input / output device 1320 such as a keypad, a keyboard, a display, a memory 1330, and a wireless interface 1340, which are combined with each other via a bus 1350. The control unit 1310 can include, for example, at least one microprocessor, a digital signal processor, a microcontroller, or the like.The memory 1330 may be configured to store an instruction code to be used by the control unit 1310 or user data. The memory 1330 may comprise a semiconductor device with a vertical-channel transistor according to exemplary embodiments of the inventive concept. The electronic device 1300 may use a wireless interface 1340 configured to transmit or receive data to or from a wireless communication network using an RF signal. The wireless interface 1340 may, for example, comprise an antenna, a wireless transceiver, etc. The electronic device 1300 may be implemented in a communication interface protocol of a communication system such as CDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000, Wi-Fi, Multi-Wi-Fi, Bluetooth, DECT, Wireless USB, Flash OFDM, IEEE802.20, GPRS, iBurst, WiBro, WiMAX, WiMAX-Advanced, UMTS-TDD, HSPA, EVDO, LTE-Advanced, MMDS, etc.

[0103] The Fig. 8 is a block diagram schematically illustrating memory systems including a semiconductor device according to exemplary embodiments of the inventive concept.

[0104] Regarding the Fig.8, a memory system including a semiconductor device according to exemplary embodiments of the inventive concept will be described. The memory system 1400 may include a memory device 1410 for storing large amounts of data and a memory controller 1420. The memory controller 1420 controls the memory device 1410 to read data stored in the memory device 1410 or write data to the memory device 1410 in response to a read / write request from a host 1430. The memory controller 1420 may include an address mapping table for mapping an address received from the host 1430 (e.g., a mobile device or a computer system) into a physical address of the memory device 1410. The memory device 1410 may include a semiconductor device with a vertical-channel transistor according to exemplary embodiments of the inventive concept.

[0105] According to exemplary embodiments of the inventive concept, the semiconductor device may comprise storage node pads that are adjacent to each other between word lines but spatially separated from each other by an isolation structure. Accordingly, the storage node pads may be connected to an active region of a substrate with an increased contact area, and consequently, it is possible to reduce contact resistance between the storage node pad and the substrate.

[0106] According to exemplary embodiments of the inventive concept, a method for manufacturing a semiconductor device may include forming the storage node pads in a self-aligned manner using the isolation structure. Accordingly, it is possible to prevent a bridging problem caused by a mask alignment error. This makes it possible to improve the reliability of the semiconductor device.

[0107] Furthermore, the isolation structure can be formed using a double-structure technique, and thus, photolithography can be performed using an ArF and / or KrF beam rather than an EUV beam. This makes it possible to reduce the manufacturing cost of the semiconductor device.

Claims

[1] A semiconductor device comprising: a substrate (1) having a recess (84) partially defined by a side wall (85), the substrate (1) having a top surface (81); a device insulation layer (3) provided in the recess (84), the device insulation layer (3) having a top surface (83) lower than a top surface (81) of the substrate (1); a memory element (CP) arranged on the substrate (1); one or more first contacts (72) electrically connected to the memory element (CP); and an insulation structure (21a) arranged on a corresponding device insulation region and between the adjacent first contacts (72), the insulation structure (21a) being in direct contact with the adjacent first contacts (72), wherein at least one of the first contacts (72) is in contact with the upper side (81) of the substrate (1) and is formed adjacent to the side wall (85) of the recess (84). [2] The device of claim 1, further comprising an interlayer insulation layer, wherein an entire side surface of at least one of the first contacts (72) is substantially in contact with an insulation layer having an etch selectivity with respect to the interlayer insulation layer. [3] The device of claim 2, wherein the insulating layer comprises nitride. [4] The device of claim 1, wherein at least one of the first contacts (72) comprises a contact pad, and wherein a top surface of the insulation structure (21a) is substantially coplanar with a top surface of the contact pad. [5] The device according to claim 1, wherein a bottom surface of the insulation structure (21a) is deeper than the top surface (81) of the substrate (1). [6] The device of claim 1, further comprising: a wordline cap layer structure (14) adjacent to at least one of the first contacts (72); and a word line (WL) extending along a first direction (D1) under the word line capping structure (14). [7] A device according to claim 6, wherein the word line (WL) is provided in the substrate (1). [8] The device of claim 6, wherein at least one of the first contacts (72) comprises a contact pad, and wherein a top surface of the wordline capping structure (14) is substantially coplanar with that of the contact pad. [9] The device according to claim 6, wherein the isolation structure (21a) has a beam shape extending along a second direction (D2) crossing the first direction (D1). [10] The device of claim 9, wherein a bottom surface of the isolation structure (21a) is higher than a bottom surface of the word line capping layer structure (14). [11] The device according to claim 9, wherein the isolation structure (21a) divides a top surface of the word line capping layer structure (14) into a plurality of regions. [12] The device of claim 1, further comprising a second contact (74) provided on one side of the first contact (72); and a spacer (39) interposed between the first and second contacts (72; 74). [13] The device of claim 12, wherein a bottom surface of the second contact (74) is deeper than a top surface (83) of the device insulation layer (3). [14] The device of claim 12, further comprising a conductor track extending along a first direction (D1) on the second contact (74), wherein the conductor track has substantially the same width as the insulation structure (21a) and overlaps with the insulation structure (21a) in a plan view. [15] The device of claim 12, further comprising a first doped region (11) provided in the substrate (1) and connected to the first contact (72); and a second doped region (13) provided in the substrate (1) and connected to the second contact (74), wherein the second doped region (13) has a depth which is greater than that of the first doped region (11). [16] A semiconductor device comprising: a substrate (1) having a cell matrix region (CAR), a cell edge region (ER) and a peripheral circuit region (PCR); a plurality of word lines (WL) provided in the substrate (1) with a gate insulation layer (7) interposed therebetween, the word lines (WL) extending along a first direction (D1); word line capping layer structures (14) each arranged on the word lines (WL), the word line capping layer structures (14) projecting upwards from a top side (81) of the substrate (1); storage node pads (25a) arranged between the word line capping structures (14) to be in contact with the substrate (1); Isolation structures (21a, 21b) arranged between adjacent storage node pads (25a) and between the word line capping layer structures (14); and a dummy bit line node contact (DDC) and a dummy insulation structure (21c) arranged adjacent to each other in the cell edge region (ER), wherein the isolation structures (21a, 21b) are in direct contact with the adjacent storage node pads (25a). [17] The device of claim 16, further comprising: a bit line node contact (DC) provided in the cell matrix area (CAR), wherein the bit line node contact (DC) is connected to the substrate (1) between the word lines (WL) and is spatially separated from the insulation structure (21a); and a plurality of bit lines (BL) provided substantially parallel to each other on the bit line node contact (DC), wherein a dummy isolation structure (21c) overlaps together with at least two adjacent bit lines (BL). [18] The device of claim 16, wherein the dummy isolation structure (21c) is arranged closer to an outer region of the cell edge region (ER) than to the dummy bit line node contact (DDC). [19] The device according to claim 16, further comprising a device insulation layer (3) provided in the substrate (1), the device insulation layer (3) having a top surface (83) lower than the top surface (81) of the substrate (1). [20] The device of claim 16, further comprising a device insulation layer (3) provided in the substrate (1), wherein the device insulation layer (3) has a top surface (83) that is substantially planar to the top surface of the substrate (1). [21] A semiconductor device comprising: a device isolation layer (3) formed in a semiconductor substrate (1), the device isolation layer (3) defining an active region (AR) having a first crossing region and a second crossing region; a plurality of word lines (WL) buried in the semiconductor substrate (1), the plurality of word lines (WL) each having a word line cap layer formed thereon and extending above the active region (AR); a plurality of bit lines (BL) extending across the plurality of word lines (WL); a first contact (72) connecting the first crossing region and a corresponding one of the plurality of bit lines (BL); a second contact (74) electrically coupled to the second crossing region, an insulation structure (21a) arranged on the device insulation layer and between the adjacent second contacts, the insulation structure (21a) being in direct contact with the adjacent second contacts, wherein a lower portion of the second contact (74) is disposed in a space defined by opposite sidewalls of adjacent ones of the word line capping layers and opposite sidewalls of adjacent partition walls extending between the adjacent ones of the word line capping layers, wherein the device insulation layer (3) has a top surface (83) lower than that of the substrate (1), wherein the second contact (74) has an upper region and a lower region, and wherein the upper region is adjacent to the lower region. [22] The device of claim 21, further comprising a storage node electrically coupled to the second contact (74).

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