Methods for structuring vias in a chip and chip structure with vias

Abstract

Method for structuring vias in a chip, wherein the method comprises the following: Forming (530) a photoresist layer (340) containing a recess (350) on a structured hard mask layer (310) containing a plurality of openings, and in contact with an etch stop layer (320) on a substrate (330), wherein the recess (350) overlaps with two or more of the openings, the substrate (330) being a semiconductor substrate; Etching (540) of an area of ​​the etch stop layer (320) overlapping with the recess (350) of the photoresist layer (340) through the two or more openings to obtain a plurality of vias (360) extending partially through the substrate (330); further etching (550) of the majority of vias (360) through the entire depth of the substrate to obtain corresponding through-substrate vias (370), wherein the obtained through-substrate vias (370) comprise: - a first via (1A, 1B, 1C, 1D) that is positioned inside a first metal body in the substrate; - a second via (1A, 1B, 1C, 1D) positioned within a second metal body in the substrate, wherein top views of the first vias and the second vias have a trapezoidal geometry, a rectangular geometry or a combined trapezoidal and rectangular geometry, wherein a first via-to-via space between the first via and the second via is essentially equal to a first metal-body-to-metal space between the first metal body and the second metal body, and wherein a first metal-body-to-metal pitch between the first metal body and the second metal body is less than or equal to about 100 nm.

Description

Technical area

[0001] The present invention relates generally to a system and method for manufacturing a semiconductor chip and, in particular embodiments, to a patterning approach to reduce minimum via-to-via spacing. background

[0002] Multi-patterning is a class of integrated circuit (IC) manufacturing technologies developed for lithography to improve feature density (e.g., linear density). The simplest case of multi-patterning is double-patterning, in which a conventional lithographic process is enhanced to produce twice the expected number of features. Double exposure is an example of double patterning. Double exposure is a sequence of two separate exposures of the same photoresist layer. The double-exposure technique allows for the manufacturability of minimal-pitch features in a layout that may contain a range of features. For example, double exposure can be used to pattern parallel or adjacent trenches in the same layer.One approach to patterning trenches involves a sequence of two separate exposure and etching steps (2P2E) of independent structures using litho-etch-litho-etch steps into the same layer. Once the sequence is complete, the structure is a composite of the previously etched substructures. By interleaving the substructures, the structure density can be increased, with the half-pitch being inversely proportional to the number of substructures used. For example, a structure with a trench, ridge, or line pitch of 100 nanometers (nm) can theoretically be created by interleaving structures with a trench pitch of 200 nm.

[0003] US 2003 / 0 111 732 A1 discloses a chip structure comprising a first via within a first metal body and a second via within a second metal body, wherein top views of the first via and the second via have a rectangular geometry. A via-to-via space between the first via and the second via is substantially equal to a metal body-to-metal body space between the first metal body and the second metal body.

[0004] Further prior art relating to the subject matter of the invention can be found, for example, in US 2012 / 0 322 224 A1 and US 6 221 759 B1.

[0005] The present invention is defined by the independent claims. Specific embodiments are defined by the dependent claims. Short description of the drawings

[0006] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions, which should be seen in conjunction with the accompanying drawings, in which: Fig. 1A -1H are top views and corresponding cross-sectional views of conventional patterning steps for vias in trenches for a chip structure, Fig. 2 is a plan view of a conventional structure of vias in trenches for a chip structure, Fig. 3A-3I are top views and cross-sectional views of patterning steps for vias in trenches for a chip structure according to an embodiment, Fig. 4 is a plan view of a structure of vias in trenches for a chip structure according to an embodiment, and Fig. 5 is a process flow of a method for patterning vias in trenches for a chip structure according to parts of an embodiment of the invention. Detailed description of illustrative embodiments

[0007] The making and using of the present preferred embodiments will be described in detail below.

[0008] Vias, for example, can be patterned within a structured layout of parallel trenches to add electrical interconnects for ICs or semiconductor chips. The minimum trench pitch can be achieved using a double patterning technique, such as a 2P2E sequence. The pitch is the distance separating two centers (or edges on the same side) of two or more repeated features (e.g., trench / via center to trench / via center). The minimum via-to-via pitch in post-development inspection (ADI) is larger than that of trench ADI due to lithographic limitations (e.g., optical resolution). Spacing is the smallest measured distance between two features, e.g., between the facing edges of two separate vias or trenches.The pitch between two vias or trenches can be larger than the spacing between the same two vias or trenches. For example, even for a trench pitch of less than 100 nm, the minimum achievable via-to-via pitch is approximately 100 nm. Furthermore, multiple patterning steps may be required to achieve a via-to-via spacing equivalent to that of trenches. For example, a sequence of three separate exposure and etch steps (3P3E) is required to pattern vias with a via-to-via spacing (e.g., of less than 100 nm) equivalent to that of trenches obtained using 2P2E.

[0009] Described here are embodiments of a patterning approach to reduce via-to-via spacing in chip or IC manufacturing. A plurality of vias may be patterned within a layout of parallel trenches. The patterning approach uses a combination or overlay of a hard mask layer (to pattern the trenches) and a photomask to pattern the vias with a reduced via-to-via spacing equivalent to the trench spacing, such as below the limit of optical resolution (e.g., a pitch of less than 100 nm). The exposure resulting from the overlap between the hard mask trench spacing and the photomask enables the via-to-via spacing to be matched to the hard mask trench spacing. As a result, a via-to-via pitch may be matched to a trench pitch of less than 100 nm.The patterning approach reduces via-to-via spacing, essentially using a single mask patterning step, and therefore reduces costs compared to traditional double (or multiple) patterning approaches. Therefore, a via-to-via pitch of less than 100 nm can be achieved without double or multiple patterning steps. Furthermore, the steps of the patterning approach presented here can be combined with conventional or other double (or multiple) patterning steps to obtain a layout of vias in trenches with a different via-to-via pitch, for example, where both have a spacing of less than 100 nm or more than 100 nm.

[0010] Fig. 1A-1H show top views and corresponding cross-sectional views of conventional patterning steps for vias in trenches for a chip structure. The cross-sectional views for each step are shown in their respective top views. Fig. Figure 1A shows a top view of a first step for patterning a hard mask having trenches. Fig. 1B shows a cross-sectional view of the same step. A hard mask layer 110 is patterned over a second layer 120. The hard mask layer 110 can be patterned using conventional lithographic processes (e.g., exposure and etching). The hard mask layer 110 is a hard mask comprising a plurality of equally spaced ridges, called lines in the art (e.g., mesas) and gaps between the ridges (e.g., trenches) with a specific pitch. The hard mask layer 110 is used to pattern ridges and, in particular, lines (e.g., by photoexposure) in the layer or layers below the hard mask. For example, the hard mask layer 110 can be patterned (or formed) from a layer of titanium nitride (TiN) or any other suitable dielectric. The second layer 120 can be a uniform (non-patterned) layer formed from any suitable dielectric (e.g.,Ceramic). The second layer 120 is deposited on a substrate 130 and serves as an etch stop layer (ESL) between the hard mask layer 110 and the substrate 130. The substrate 130 may be a semiconductor substrate containing an elemental semiconductor including silicon and / or germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAs; or one or more combinations thereof. The alloy semiconductor substrate may include a gradient SiGe feature in which the Si and Ge composition changes from one ratio at one location to a different ratio at another location of the gradient SiGe feature. The alloy SiGe may be formed over a silicon substrate.The SiGe substrate may be strained. Furthermore, the substrate 130 may be a semiconductor-on-insulator (SOI). In some examples, the substrate 130 may include a doped epi layer. In other examples, the silicon substrate may include a multilayer compound semiconductor structure. Alternatively, the first substrate may include a non-semiconductor material, such as a glass, molten glass, or calcium fluoride. In the present example, the substrate 130 includes a silicon wafer. In another example, the substrate 130 may also include a dielectric layer (e.g., a low-k layer), a conductive layer (e.g., a gate electrode or a metal line), or one or more combinations thereof.

[0011] Fig. Figure 1C shows a top view of a second step for patterning a layout of vias using photomask exposure. Fig. 1D shows a cross-sectional view of the same step. In this step, a photomask 140 (e.g., a mask formed from a photoresist) may be patterned on the hard mask layer 110 and the second layer 120 below the trenches of the hard mask layer 110, and may include a plurality of recesses 150. The photomask 140, including the recesses 150, may be patterned using photoresist deposition, exposure (e.g., ultraviolet (UV) exposure), and one or more etching procedures. The resulting patterned photomask 140 may include two recesses 150 (shaped, for example, as holes), each overlapping with two adjacent trenches in the hard mask layer 110 and the second layer 120 below the trenches. The recesses 150 have a separation that determines the via-to-via spacing.The minimum achievable separation is limited by the photolithographic process, such as the optical resolution (e.g., UV optical resolution), the photoresist, etc. Each recess 150 may overlap with a portion of the second layer 120 (in a trench). The edges of the recess 150 may also overlap with one or two lands adjacent to the trench of the hard mask layer 110.

[0012] Fig. Figure 1E shows a top view of a third step for etching vias through the second layer 120 and partially through the substrate 130. Fig. 1F shows a cross-sectional view of the same step. An extremely low-k etch, known in the art as an extreme low-k (ELK) etch, or any other suitable controlled etch process may be used to etch through the entire photomask 140 layer, and simultaneously through exposed portions of the second layer 120 and partially through the substrate 130 below. The exposed portions of the second layer 120 correspond to the recesses 150 of the photomask 140. The remaining portions of the hard mask layer 110 and the second layer 120 that were covered by the photomask 140 are protected from this etch process and therefore do not undergo etching while the photomask 140 is etched. The resulting etched regions of the second layer 120 and partially the substrate 130 thereunder form partial vias 160 that do not extend through the entire depth of the substrate 130.Two partial vias 160 are obtained where the two recesses 150 have been patterned in the photomask 140. Therefore, the separation between the partial vias 160 is equal to the separation of the recesses 150 defined by the photolithographic process.

[0013] Fig. Figure 1G shows a top view of a fourth step of etching vias and trenches through the substrate 130. The Fig. Figure 1H shows a cross-sectional view of the same step. Any suitable controlled etching process (e.g., a chemical etch) can be used to complete the etching of the partial vias 160 through the entire depth of the substrate 130, thus obtaining the through-substrate vias 170. Concurrently, the trenches in the hard mask layer 110 are etched to extend through the second layer 120 and partially through the substrate 130 to achieve in-substrate trenches 180.

[0014] Fig. Figure 2 shows a conventional structure of vias in trenches that can be obtained for a chip structure using conventional patterning steps for vias in trenches, such as in the Fig. 1A-1H. The minimum trench pitch can be reduced to less than about 100 nm using dual patterning (e.g., 2P2E), for example, with UV lithography and ELK etching. However, the minimum via-to-via pitch remains limited to about 100 nm or larger, for example, due to optical resolution. Additional multiple patterning steps (e.g., 3P3E) can help reduce via-to-via spacing, but also increase manufacturing costs and complexity.

[0015] Fig. 3A to 3I show top and cross-sectional views of patterning steps for vias in trenches for a chip structure according to one embodiment. The cross-sectional views for the steps are shown under their respective top views. A final step is shown only in a cross-sectional view. The patterning method according to this embodiment allows a reduction of the via-to-via spacing to match the trench spacing using single mask patterning for vias. As such, the via-to-via spacing can be matched to the trench spacing without using multiple via patterning steps. For example, the via-to-via pitch can be reduced using the single mask patterning method or steps to match a trench pitch of less than 100 nm without using 3P3E steps.

[0016] Fig. Figure 3A shows a top view of a first step for patterning a hard mask of trenches. Fig. Figure 3B shows a cross-sectional view of the same step. This step is similar to the first step in the Fig. 1A and Fig. 1B. The step includes patterning a hard mask layer 310 (using, for example, exposure, etching, and other suitable lithographic processes) over a second layer 320. The hard mask layer 310 includes a plurality of equally spaced ridges (e.g., mesas) with a specific pitch over a uniform second layer 320. The recesses between the ridges form trenches in the hard mask layer 310. The hard mask layer 310 and the second layer 320 may be any suitable dielectric, as described above, that serves as an ESL. The trench pitch may be less than 100 nm, for example, using a double patterning approach to interleave two trench structures of the same pitch (e.g., less than 200 nm) on the same hard mask layer 310.

[0017] Fig. Figure 3C shows a top view of a second step for patterning a layout of vias using photomask exposure. Fig. 3D shows a cross-sectional view of the same step. In this step, a photomask 340 (e.g., a mask formed from a photoresist) may be patterned on the hard mask layer 310 and the second layer 320 below it, using photoresist deposition, exposure (e.g., UV exposure), and one or more etching processes to pattern one or more elongated recesses 350 in the photomask 350. The resulting patterned photomask 340 includes an elongated recess 350 (e.g., a slot or any other shape) that overlaps with at least two adjacent trenches in the hard mask layer 310 and the second layer 320 below the trenches. The elongated recess 350 may have any suitable geometry, such as a slot or an elliptical recess extending across two adjacent trenches (as shown) or across more than two adjacent trenches.The geometry of the elongated recess 350 determines the exposure pattern of the spot (for forming the vias) in the second layer 320 and subsequently the shape of the resulting vias in the trenches, as described below. The overlap between the elongated recess 350 and the trenches is used to expose areas or spots in the underlying second layer 320 across two (or more) consecutive trenches in the hard mask layer 310 with a separation between the spots corresponding to the trench pitch. As such, the separation between adjacent exposed spots of the second layer 320 is no longer limited by the photolithographic process (e.g., the optical resolution and other factors), but only by the minimum achievable trench pitch (achieved, for example, by using 2P2E). The exposed spots are converted into vias in subsequent steps, as described below.

[0018] Fig. 3E shows a top view of a third step for etching vias through the second layer 320 and a portion of the substrate 330. Fig. Figure 3F shows a cross-sectional view of the same step. This step is similar to the third step in the Fig. 1E and Fig. 1F. The step includes using an ELK etch or any other suitable controlled etching process to etch through the entire layer of the photomask 340 and simultaneously exposed areas or spots of the second layer 320 and partially through the substrate 330 beneath the exposed spots. Therefore, the two (or more) exposed spots of the second layer 320 are converted into two partial vias 360 separated by a via-to-via spacing equal to the trench pitch via two adjacent trenches of the hard mask layer 310. As such, a single mask patterning process is used instead of the double (or multiple) patterning process to obtain a via-to-via spacing equal to the trench spacing, thereby reducing the overall manufacturing cost, overall manufacturing complexity, and potentially the manufacturing time.However, the double or multiple patterning process can still be used to reduce the trench pitch.

[0019] Fig. 3G shows a top view of a fourth step for etching vias and trenches through the substrate 330. Fig. Figure 3H shows a cross-sectional view of the same step. This step is similar to the fourth step in the Fig. 1G and Fig. 1H. This step includes using any suitable controlled etching process (e.g., a chemical etch) to complete the etching of the partial vias 360 through the entire depth of the substrate 130, thus obtaining the through-substrate vias. Simultaneously, the trenches in the hard mask layer 310 are etched to extend through the second layer 320 and partially through the substrate 330 to achieve in-substrate trenches 380. Fig. 3I shows a cross-sectional view of a final step for filling the through-substrate vias 370 and the in-substrate trenches 380 with a conductor or metal 375, such as copper, gold, or aluminum, using any suitable processes (e.g., including sputtering, deposition, and / or etching) to obtain conductive structures or interconnects (e.g., vias within metal lines or fins). The hard mask layer 310 and the second layer 320 are also removed, e.g., by etching.

[0020] Fig. 4 is a top view of a via-in-trench structure for a chip structure according to one embodiment. Fig. 4 shows a structure of vias in metal lines that can be obtained using a combination of the patterning method according to an embodiment or steps described in the Fig. 3A-3I, and conventional structuring steps, such as in the Fig. 1A-1H. The structure includes a plurality of metal lines having variable metal pitches or variable metal separation, including a minimum pitch or spacing. The structure also includes a plurality of vias in metal lines with different via-to-via separation corresponding to the different metal separations. At least some of the vias are obtained using the single mask patterning approach described above, for example, to conform to a minimum pitch of less than 100 nm. This approach can be used to conform to a minimum metal line or minimum metal-to-metal spacing down to about 32 nm, which may be achievable with extreme UV (EUV) lithography or multiple patterning approaches.Other vias separated by longer via-to-via spacing are obtained using conventional patterning processes, such as the steps in the . Fig. 1A-1H.

[0021] Furthermore, vias with different shapes or geometries can be obtained using the single patterning approach. Examples of possible geometries include trapezoidal via recesses (referred to as 1A), rectangular via recesses (referred to as 1B and 1C), and a combination of both (referred to as 1D). Furthermore, different via pattern types can be combined for a chip structure. A first type of via (Type 1 vias) can be created by dividing a larger via (elongated recess) into two or more vias using trench hard masks, as described above. The Type 1 vias can include trapezoidal vias (1A), rectangular vias (1B and 1C), and / or polygonal vias (1D). The rectangular via 1C has at least one side width equal to the metal line width. At least one space between the Type 1 vias is approximately equal to the metal-to-metal spacing (trench spacing).A second type of via (Type 2 vias) can also be created using traditional or conventional approaches. Type 2 vias can have a rounder shape (compared to Type 1 vias, for example). Type 2 vias can have vias with a pitch of 100 nm (referred to as 2A) and vias with a pitch of more than 100 nm (referred to as 2B).

[0022] The trapezoidal vias (1A) correspond to exposed areas or spots resulting from an overlap of trenches with edge regions of the elongated recesses in the photomask that extend over several trenches (e.g., the elongated recess 350). The rectangular vias (1B and 1C) correspond to exposed areas or spots resulting from an overlap of trenches with central regions of the elongated recesses. For example, three adjacent vias are obtained in the three adjacent trenches, having a 1A-1B-1A sequence of shapes (as in Fig. 4) when an elongated recess extending across three trenches is used. The 1C geometry can also be obtained by overlapping a trench with an edge region of the elongated recess. The other conventionally structured vias 2A and 2B can have a typical hole-like geometry.

[0023] Fig. 5 shows a process flow of a method 500 for patterning vias in trenches for a chip structure according to parts of an embodiment of the invention. The steps of the method 500 may be similar to the top and cross-sectional views of the steps in the Fig. 3A to 3I. In step 510, a uniform dielectric layer is formed on a substrate. The formed layer serves as an etch stop layer (ESL) in subsequent steps. In step 520, a patterned hard mask layer is formed on the ESL. The hard mask layer includes a plurality of openings by patterning (as in Fig. 3B). At step 530, a photoresist (photomask) layer is formed on the hardmask layer. The photoresist layer includes a recess that overlaps two or more openings of the hardmask (as shown in Fig. 3D). At step 540, the photomask layer and a portion of the ESL that overlaps the photomask recess are etched to obtain a plurality of vias that extend partially through the substrate (as shown in Fig. 3F). The partial vias are etched into the ESL through the openings of the hard mask. At step 550, the partial vias are etched into the substrate to obtain through-substrate vias. The remaining openings in the photomask are also etched to obtain in-substrate trenches (as shown in Fig. 3H). At step 560, the through-substrate vias and the in-substrate trenches are filled with a metal or conductor (as shown in Fig. 3I shown).

Claims

[1] A method for patterning vias in a chip, the method comprising: Forming (530) a photoresist layer (340) containing a recess (350) on a patterned hard mask layer (310) containing a plurality of openings, and in contact with an etch stop layer (320) on a substrate (330), wherein the recess (350) overlaps with two or more of the openings, wherein the substrate (330) is a semiconductor substrate; Etching (540) a portion of the etch stop layer (320) overlapping the recess (350) of the photoresist layer (340) through the two or more openings to obtain a plurality of vias (360) extending partially through the substrate (330); further etching (550) the plurality of vias (360) through the entire depth of the substrate to obtain corresponding through-substrate vias (370), the obtained through-substrate vias (370) comprising: - a first via (1A, 1B, 1C, 1D) positioned within a first metal body in the substrate; - a second via (1A, 1B, 1C, 1D) positioned within a second metal body in the substrate, wherein top views of the first via and the second via have a trapezoidal geometry, a rectangular geometry or a combined trapezoidal and rectangular geometry, wherein a first via-to-via space between the first via and the second via is substantially equal to a first metal body-to-metal body space between the first metal body and the second metal body, and wherein a first metal body-to-metal body pitch between the first metal body and the second metal body is less than or equal to about 100 nm. [2] The method of claim 1, wherein the patterned hard mask layer (310) further includes a trench and further etching (550) the plurality of vias (360) through the entire depth of the substrate further comprises: Etching the trench to obtain an in-substrate trench (380), and wherein the method further comprises: Filling the through-substrate vias and the in-substrate trench with a conductor. [3] A method according to claim 1 or 2, further comprising: Forming a plurality of second recesses in the photoresist layer (340), each overlapping with another opening of the plurality of openings in the patterned hard mask layer (310), and Etching a second region of the etch stop layer (320) and the substrate that overlaps one of the second recesses in the photoresist layer (340) through the corresponding other opening to obtain corresponding second through-substrate vias. [4] The method of claim 3, further comprising spacing the second recesses with a via-to-via distance that exceeds a pitch of the openings in the patterned hard mask layer. [5] The method of claim 3, further comprising: Spacing the openings with a pitch less than or equal to 100 nm, and Spacing the second recesses with a via-to-via distance greater than 100 nm. [6] The method of claim 1, further comprising patterning the plurality of openings in the hard mask layer (310) using at least two separate exposure and etching steps (2P2E) with ultraviolet (UV) or extreme UV (EUV) photolithography to minimize a pitch of the openings. [7] The method of claim 1, further comprising aligning an edge region of the recess (350) to overlap with an opening of the hard mask to pattern a via with a trapezoidal recess geometry or a combined rectangular and trapezoidal recess geometry. [8] The method of claim 1, further comprising aligning a central region of the recess (350) to overlap with an opening of the hard mask to pattern a via with a rectangular recess geometry. [9] Chip structure comprising: a first via (1A, 1B, 1C, 1D) positioned within a first metal body in a substrate; a second via (1A, 1B, 1C, 1D) positioned within a second metal body in the substrate, wherein top views of the first via and the second via have a trapezoidal geometry, a rectangular geometry, or a combined trapezoidal and rectangular geometry, and wherein a first via-to-via space between the first via and the second via is substantially equal to a first metal body-to-metal body space between the first metal body and the second metal body, and wherein a first metal body-to-metal body pitch between the first metal body and the second metal body is less than or equal to 100 nm; wherein the first and second vias are through-substrate vias, wherein the substrate (330) is a semiconductor substrate. [10] Chip structure according to claim 9, further comprising: - a third via (2A) positioned within a third metal body in the substrate; - a fourth via (2A) positioned within a fourth metal body in the substrate, wherein top views of the third via and the fourth via have a round geometry, and wherein a via-to-via pitch between the third via and the fourth via is greater than or equal to 100 nm, where the third and fourth vias are through-substrate vias. [11] Chip structure according to claim 9 or 10, further comprising: - a fifth via (1B) within a fifth metal body in the substrate; and - a sixth via (1C) within a sixth metal body in the substrate, wherein top views of the fifth via and the sixth via have a trapezoidal geometry, a rectangular geometry or a polygonal geometry, wherein a third via-to-via space between the fifth via and the sixth via is substantially equal to a third metal body-to-metal body space between the fifth metal body and the sixth metal body, wherein a second metal body-to-metal body pitch between the fifth metal body and the sixth metal body is greater than 100 nm. [12] Chip structure according to one of the preceding claims 9 to 11, wherein the first metal body and the second metal body are metal lines in the substrate. [13] Chip structure according to one of the preceding claims 9 to 12, wherein the first via and the second via are repeated along the first metal body and the second metal body. [14] The chip structure of any one of the preceding claims 9 to 13, wherein a second via-to-via space between the third via and the first via, the second via, or the fourth via is larger than the first metal body-to-metal body space. [15] Chip structure according to one of the preceding claims 9 to 14, further comprising: a seventh via (2B) within a seventh metal body in the substrate and an eighth via (2B) within an eighth metal body in the substrate, wherein top views of the seventh via and the eighth via have a round geometry, and wherein a fourth via-to-via space between the seventh via and the eighth via is larger than a fourth metal body-to-metal body space between the seventh metal body and the eighth metal body. [16] The chip structure of claim 15, wherein a third metal body-to-metal body pitch between the seventh metal body and the eighth metal body is less than or equal to 100 nm. [17] Chip structure according to one of the preceding claims 9 to 16, wherein the first metal body-to-metal body pitch is under a resolution limitation of ultraviolet (UV) light or extreme ultraviolet (EUV) light, and is photoexposed with double or multiple patterning steps.

Images