Enclosed vertical power device subject to pressure loading, and method for manufacturing an enclosed vertical power device

Abstract

Composite device (200) comprising the following: a carrier (260); a bonding layer (250) formed on the support (260), wherein the bonding layer (250) has a first thickness; and a chip (210) formed on the interconnect layer (250), wherein the chip (210) has a second thickness, where the second thickness is less than the first thickness; and the chip (210) is subjected to pressure over its entire second thickness.

Description

[0001] The present invention relates generally to the encapsulation of semiconductor chips and in particular to the encapsulation of vertical power semiconductor power chips.

[0002] Encapsulation and assembly represent the final stage in the manufacturing of a single or multiple chips. They provide mechanical and electrical connections between the chip and a chip substrate, as well as a protective shield against mechanical, chemical, or radiation-induced damage.

[0003] Defects induced by thermomechanical stress, such as delamination, crack formation or solder joint failure, typically lead to potential reliability problems regarding the lifetime of a component.

[0004] DE 10 2012 102 124 A1 discloses a semiconductor device comprising a vertical power semiconductor chip with a semiconductor layer. A first terminal is located on a first side of the semiconductor layer, and a second terminal is located on a second side of the semiconductor layer, the second side being oriented along a first direction opposite the first side. A drift zone is located within the semiconductor layer between the first terminal and the second terminal. The drift zone exhibits a compressive stress of at least 100 MPa in a central portion along a second direction perpendicular to the first direction. The central portion extends from 40% to 60% of the total extent of the drift zone along the first direction and also reaches a depth of at least 10 µm in the semiconductor layer with respect to the first side and / or the second side of the semiconductor layer.

[0005] A composite device according to claim 1, an enclosed power component according to claim 11, and a method for manufacturing a semiconductor device according to claim 18 are provided. Further embodiments are specified in the dependent claims.

[0006] According to one embodiment of the invention, an assembled device has a carrier, a connecting layer arranged on the carrier, wherein the connecting layer has a first height and a chip formed on the connecting layer, wherein the chip has a second height, the second height being smaller than the first height.

[0007] In one embodiment, the second height can be 40 µm or less, and the first height can be 40 µm or more. In yet another embodiment, the interconnect layer can comprise a conductive adhesive paste. In yet another embodiment, the interconnect layer can comprise a conductive adhesive film. In yet another embodiment, the interconnect layer can comprise a soft solder. In yet another embodiment, the second height can be 5 µm or less, and the first height can be 5 µm or more. In yet another embodiment, the interconnect layer can comprise a diffusion solder layer. In yet another embodiment, the interconnect layer can be a backside metallization layer (BSM). In yet another embodiment, the chip can be a vertical power semiconductor device subjected to compressive stress. In yet another embodiment, the chip can comprise silicon carbide (SiC).

[0008] According to one embodiment of the invention, an enclosed power device comprises a connection frame, a bonding layer arranged on a support, and a vertical power semiconductor chip arranged on the bonding layer, wherein the vertical power semiconductor chip is subjected to compressive stress over its entire height. The enclosed power device further comprises intermediate connections that link chip contact points to leads of the connection frame, and an encapsulation that encapsulates the vertical power semiconductor chip.

[0009] In one embodiment, the compressive stress can be 100 MPa or more. In another embodiment, the vertical power semiconductor chip can be 40 µm or less thick. In yet another embodiment, the interconnect layer can comprise a soft solder layer, a conductive adhesive film, or a conductive adhesive paste, and the interconnect layer can have a thickness of 40 µm or more. In yet another embodiment, the vertical power semiconductor chip can be 10 µm or less thick. In yet another embodiment, the interconnect layer can comprise a diffusion solder layer, and the diffusion solder layer can have a thickness of 10 µm or less. In yet another embodiment, the coefficient of thermal expansion (CTE) of the connection frame can be more than 15 ppm / K, and the CTE of a substrate of the power semiconductor chip can be between 2 ppm / K and 7 ppm / K.

[0010] According to one embodiment of the invention, a method for manufacturing a semiconductor device comprises placing a vertical semiconductor device with a lower main surface on a connection frame and connecting the semiconductor device to the connection frame by means of a bonding layer, whereby a compressive stress is formed over the entire height of the semiconductor device, wherein the bonding layer is thicker than the semiconductor device.

[0011] In one embodiment, the method further includes thinning the semiconductor device before placing it on the mounting frame. In yet another embodiment, the vertical semiconductor device can be a vertical power semiconductor device with a height of 40 µm or less.

[0012] For a better understanding of the present invention and its advantages, the following descriptions follow in conjunction with the accompanying drawings, wherein: Fig. Figure 1 shows a cross-sectional view of a chip / carrier arrangement, wherein Fig. 1a shows the arrangement at the very beginning of the bonding of the microchip to the substrate, while Fig. 1b shows the bonded arrangement after cooling; Fig. 2 shows a cross-sectional view of an embodiment of an enclosed vertical power semiconductor device which has a compressive stress over the entire height of the vertical power semiconductor chip; Fig. 3 simulation data regarding the formation of a stress pattern in a silicon / copper bilayer; Fig. 4 A diagram of test data shows the variation in stress on the lower surface of a silicon chip at a silicon chip / copper connection frame interface; Fig. 5 A diagram of experimental data shows the variation in stress on the upper surface of a silicon chip at a silicon chip / copper connection frame interface; and Fig. Figure 6 shows an embodiment of a method for encapsulating a vertical power chip.

[0013] The manufacture and application of the currently preferred embodiments are explained in detail below.

[0014] The present invention is described with reference to embodiments in a specific context, namely in relation to enclosed vertical power semiconductor chips. However, the invention can also be used for other enclosed semiconductor devices or enclosed components.

[0015] Stresses within an enclosed component can arise as a result of high-temperature processing at interfaces with adjacent component architectural elements. A typical example of processing-related compressive stress is in Fig. 1 shown. Fig. Figure 1 shows the transition from the beginning to the end of a process for connecting a microchip to a substrate. Fig. Figure 1a shows an arrangement 100 at the time of the first physical contact between a microchip (chip) 110 and a carrier 130, wherein the carrier 130 is covered with a bonding layer 120 or wherein the back side of the microchip 110 is covered with the bonding layer 120. At this initial stage of bonding, the contact interface is essentially stress-free, except for stresses that may arise from the application of the bonding layer 120.

[0016] After the bonding of the microchip 110 to the carrier 130, which generally takes place at temperatures between 200 °C and 400 °C, and subsequent cooling to room temperature, a significant degree of additional stress is introduced. The state of a bonded microchip 110 / carrier 130 assembly is described in Fig. Figure 1b illustrates this. During cooling from the bonding temperature to room temperature, the various parts of the component architecture contract to different degrees because their coefficients of thermal expansion (CTE) differ. As a result, a shape distortion of the assembly 150 occurs, leading to a slight deflection of the assembly 150. In general, this deflection can be upward or downward. In the example shown in Fig. In Figure 1b, the downward deflection is exaggerated. This type of shape distortion can be observed, for example, when a metal substrate with a relatively high coefficient of thermal expansion (CTE) is applied to a semiconductor microchip.

[0017] Some embodiments of the present invention provide compressive stress for vertical power semiconductor devices, wherein the vertical power semiconductor chip has a height of 40 µm or less. Some embodiments of the present invention provide compressive stress for vertical power devices, wherein the height of the interconnect layer is equal to or greater than the height of the vertical power semiconductor chip.

[0018] Fig. Figure 2 shows a cross-sectional view of an embodiment of an enclosed electrical component 200, which features a thermomechanical load configured to improve the performance of the electrical device. The enclosed component 200 comprises a semiconductor chip 210, a carrier 260, and an interconnect layer 250 that connects the chip 210 to the carrier 260. The semiconductor chip 210 comprises a semiconductor substrate 220, a terminal layer 230 arranged above a first (upper) main surface 222 of the semiconductor substrate 220, and a backside metallization (RSM) layer 240 arranged below a second (lower) main surface 224 of the substrate 220.

[0019] The semiconductor substrate 220 can comprise a single semiconductor material, such as silicon or germanium, or a semiconductor composite material. In some embodiments, the semiconductor composite material is silicon carbide (SiC). In other embodiments, the semiconductor composite material is SiGe, GaN, GaASs, GaP, InP, or InAs, or a combination thereof.

[0020] The semiconductor materials can exhibit relatively low CTE values ​​in the range of approximately 2 ppm / K to approximately 7 ppm / K. For example, the CTE of Si and GaN is approximately 2.3 ppm / K and approximately 3.2 ppm / K, respectively. The semiconductor substrate 220 can comprise a sheet of semiconductor substrate material. Alternatively, the substrate 220 can also comprise an epitaxial semiconductor layer arranged over a semiconductor substrate material. The bulk and / or epitaxial semiconductor can include regions containing dopants to enhance electrical conductivity. In some embodiments, the semiconductor substrate 220 can comprise inorganic or organic materials that are not semiconductors.

[0021] The semiconductor chip 210 can be a vertical power semiconductor device. In a vertical power semiconductor device, the current flows parallel to a vertical direction, e.g., in the direction of height (here also referred to as thickness) D. sub. In the in Fig. In the embodiment shown in 2, the current flows in the direction 225 or orthogonally to the main surfaces 222 / 224 of the chip 210.

[0022] The semiconductor chip 210 can include the following types of components: power MOSFETs (metal-oxide-semiconductor field-effect transistors), JFETs (junction field-effect transistors), IGBTs (insulated-gate bipolar transistors), bipolar power transistors, or power diodes. In one embodiment, the semiconductor chip 210 includes a plurality of power devices or a combination of different devices. Alternatively, the semiconductor chip 210 can include an integrated circuit that incorporates further elements, such as control devices, electro-optical or electromechanical circuits, or passive elements. In other embodiments, the semiconductor substrate includes a vertical non-power transistor.

[0023] In one embodiment, the semiconductor chip 210 is subjected to a pressure load equal to or greater than 100 MPa in a direction orthogonal to the main surfaces 222 / 224 of the substrate 220, e.g., in a direction parallel to the current flow through the vertical power component. Alternatively, the pressure load is equal to or greater than 200 MPa or equal to or greater than 500 MPa. A load of this magnitude and type leads to a significant improvement in the electrical performance of the power component(s) 210. The performance increase can result from an increase in electron mobility due to a load-induced reduction in the effective electron mass and a reduction in electron scattering in the critical regions of the component. The achieved performance increase can be reflected in a higher component speed and lower power consumption.

[0024] In some embodiments, the semiconductor chip 210 is a thin chip. The thickness values ​​(height) D sub The thickness values ​​of the semiconductor chip 210 can represent an important parameter with regard to the performance increase of the component. sub The thickness of the semiconductor chip 210 can be small compared to semiconductor substrate thicknesses typically found in conventional component architectures. In many embodiments, the thickness D sub The thickness of the semiconductor chip 210 is equal to or less than approximately 40 µm. Alternatively, the semiconductor chip 210 is 30 µm thick or thinner, or 20 µm thick or thinner. In some embodiments, the semiconductor chip 210 is between 20 µm and 40 µm thick.

[0025] In some embodiments, the semiconductor chip 210 is an ultrathin chip. The thickness values ​​D subThe thickness of the semiconductor chip 210 can be only a few µm. For example, the semiconductor chip 210 can be 10 µm thick or thinner, or 5 µm thick or thinner. In some embodiments, the thickness D sub between 2 µm and 4 µm or 5 µm.

[0026] The semiconductor chip 210 can have a terminal or passivation layer 230 formed on the first (upper) major surface 222 of the semiconductor substrate 220. The passivation layer 230 can have or define electrically conductive contacts and insulating elements (not shown) that isolate the contacts from each other. The contacts can have a highly conductive metal, such as copper or aluminum, and may have a gold plating. The contacts are part of interconnect paths that enable load current flow and signal transmission. In some embodiments, the semiconductor substrate 220 has a power transistor with the source contact (alternatively, the drain contact) and gate contact on the upper surface 222 of the substrate 220.

[0027] In some embodiments, the semiconductor chip 210 has a backside metallization (RSM) layer 240 arranged on the back side 224 of the semiconductor substrate 220. The RSM layer (stack) 240 can have one or more layers of metal or metal alloys. For example, the RSM layer 240 can have Cu / W / Ti, Au / Cu / Cr, Al / Ti, Al / TiW, Al / Ti / NiV, or Al / Ti(W) / Cu / Sn / Ag. The thickness or height of the RSM layer (stack) 240 can be in a range between about 50 µm and about 100 µm. Alternatively, the thickness of the RSM layer 240 can be in a range between about 50 µm and about 200 µm or about 50 µm to about 300 µm. The RMS layer 240 can serve as a contact with low specific resistance. In some embodiments, the RSM layer 240 is in electrical contact with either a source or a drain region of a power MOSFET.Due to its high thermal conductivity, the RSM layer 240 can dissipate heat from devices that are in operation.

[0028] The semiconductor chip 210 is mounted on an electrically conductive substrate 260. In some embodiments, the coefficient of thermal expansion (CTE) of the selected material of the substrate 260 is significantly higher than that of the semiconductor substrate 220. In some embodiments, the CTE of the substrate 260 can be 3 or 4 times greater than that of the semiconductor chip 210. In other embodiments, the CTE of the substrate is 7 times greater, and in some cases, it is 10 times greater than the CTE of the semiconductor material of the chip 210.

[0029] The chip 210 can be mounted on a central section 262 (“paddle”) of a carrier 260, e.g., a metallic mounting frame. The carrier 260 can be a continuous plate or track made of a metal / alloy with a CTE of 15 ppm / K or more. The mounting frame can, for example, be made of copper (CTE: ~17 ppm / K), brass (CTE: ~20 ppm / K), or aluminum (CTE: ~23 ppm / K). Alternatively, the carrier 260 can be a metal-coated ceramic plate. In one embodiment, the ceramic plate can be made of a ceramic material having a CTE of 10 ppm / K or more. It can, for example, be made of zirconium dioxide (CTE: ~10.5 ppm / K) or magnesium oxide (CTE: ~13.5 ppm / K). The height (also referred to herein as thickness) D carr The thickness of the metal or metal-coated ceramic substrate 260 can vary between approximately 50 µm and approximately 2000 µm. For example, the thickness D carrThe thickness D can be approximately 100 µm to 300 µm or approximately 200 µm to approximately 500 µm. Alternatively, the thickness D can be... carr be equal to or greater than approximately 500 µm.

[0030] In some embodiments, the bonding layer 250 comprises a soft solder material, such as a Sn-Pb alloy with a varying Sn / Pb ratio (e.g., eutectic Sn63Pb37 with a melting point of 183 °C), an alloy of Bi or Cd with Sn or Pb, or an alloy of In with Pb and / or Sn and / or Ag. The melting points of soft solder materials are below 200 °C; for some solder alloys containing In or Bi, the melting point may be as low as approximately 120 °C. The height (hereafter also referred to as thickness) D Con The thickness of the soft solder material 250 can vary between approximately 50 µm and approximately 1,000 µm. For example, the thickness D Con approximately 50 µm to 100 µm or approximately 50 µm to approximately 200 µm. Alternatively, the thickness D can be... Conbe equal to or greater than 200 µm.

[0031] In some embodiments, the interconnect layer 250 can comprise an electrically conductive organic adhesive film or paste. Such films / pastes have a base polymer, such as polyimide, epoxy, epoxy / urethane, or polyester resins, a high loading (between 70 vol.% and 85 vol.%) with metallic nanoparticles, and a crosslinking compound. The nanoparticles can, for example, be Ag, Cu, Au, or Ag-plated or Au-plated Ni. The thickness D Con The thickness of the film or paste material 250 can vary between approximately 50 µm and approximately 2,000 µm. For example, the thickness D Con approximately 50 µm to 100 µm or approximately 50 µm to approximately 200 µm. Alternatively, the thickness D can be... Con be equal to or greater than 200 µm.

[0032] In some embodiments, the bonding layer 250 may comprise a rigid layer of a diffusion solder material, such as AuSn, CuSn, AgSn, or SnSb. Diffusion solder materials contain tin or silver, but generally no lead. Diffusion solder materials melt at temperatures of about 210 °C or higher, meaning that their melting points are about 20 °C higher than those of soft solder materials. The thickness D Con The thickness of the diffusion seal material can vary between approximately 1 µm and approximately 20 µm. Alternatively, the thickness D can be Con the diffusion plug material should be equal to or smaller than approximately 10 µm or approximately 5 µm, e.g. between approximately 2 µm and approximately 3 µm or approximately 3 µm and approximately 5 µm.

[0033] In some embodiments, the thin power semiconductor chip 210 is attached to the support 260 with a soft solder, an adhesive film, or an adhesive paste 250. In many embodiments, the ultra-thin power semiconductor chip 210 is attached to the support 260 with a diffusion-bonded interconnect layer 250. The thickness or height of the support D carr It can vary between approximately 10 µm and approximately 1,000 µm. For example, the thickness D can carr approximately 100 µm to 300 µm or approximately 200 µm, for example approximately 500 µm. Alternatively, the thickness D can be carr be equal to or greater than 500 µm.

[0034] The assembled component 200 further comprises connecting elements 270, 272, which provide electrical connections between contact points in the terminal layer 230 and peripheral terminal frame areas 264, 266. The connecting elements 270, 272 can be bond wire or prefabricated (e.g., stamped) metal parts, so-called clips. Clips and bond wire with larger diameters, generally in the range of 100 µm to 500 µm, can be used for connections in the load path of the electrical system. Au wires with diameters of 12 µm to 50 µm can be used for signal connections.

[0035] The electrical component 200 has an encapsulation 280 that fully or partially encloses the semiconductor chip 210 and the carrier 260 and, for example, connects the bond wires 270 and 272. The encapsulation 280 can be a molding compound containing epoxy, polyimide, polyacrylate, polyurethane, polysulfone, or polyetherimide resins. Alternatively, the encapsulation 280 can be, for example, a laminate or a glop-top coating.

[0036] The following paragraphs describe various embodiments of the enclosed component 200, which is subjected to pressure stress in the semiconductor substrate 220. In general, the magnitude of the stress emanating from a particular component interface also increases with increasing difference in the coefficients of thermal expansion (CTE) of the materials forming the interface and with increasing temperature of the deposition / application processes that lead to the formation of the interface.

[0037] With regard to the specific architectural structure of the enclosed component 200, most, if not all, materials in layers beneath the semiconductor substrate 220 can exhibit CTE values ​​that are higher, often significantly higher, than the CTE of the material(s) used for the semiconductor substrate 220. This applies to metals such as Ti (CTE between approximately 8.5 and approximately 9.5 ppm / K) and Ni, Au, Cu, or Al (with CTE between approximately 13 ppm / K and approximately 23 ppm / K), which can be selected as materials for the backside metallization (RSM) layer 240.

[0038] Solder materials suitable for the 250 bonding layer generally have CTE values ​​of approximately 15 ppm / K or higher. Eutectic Au80Sn20, for example, has a CTE of approximately 16 ppm / K, and eutectic Sn63Pb37 has a CTE of approximately 25 ppm / K.

[0039] The CTE of a 250 compound layer containing an organic conductive adhesive can be close to or above approximately 20 ppm / K. The average CTE of such an adhesive film or paste depends primarily on the CTE of the material forming metallic nanoparticles (e.g., Ag with a CTE of approximately 18 ppm / K) and the CTE of the base resin compound (which can be ≥ approximately 25 ppm / K for polyimides or ≥ approximately 50 ppm / K for epoxy resins).

[0040] The CTE of conventional metallic substrates 260 is equal to or greater than approximately 17 ppm / K, as already mentioned. Alternatively, ceramic substrate materials are available that exhibit CTE values ​​above approximately 10 ppm / K.

[0041] During a cooling phase after material deposition, all of the above-mentioned materials can contract more than the proposed materials of the semiconductor substrate 220. As a result, all corresponding layers under the semiconductor substrate 220 can contribute to the pressure load that propagates into the semiconductor substrate 220.

[0042] The effect of absolute thickness values ​​and thickness ratios between individual elements of the architecture of component 200 is examined with reference to the Fig. Figures 3 to 5 are easier to understand. These figures show stress data in bilayers produced by bonding a silicon layer to a copper layer at 300 °C. Since the CTE of silicon is lower than that of copper, the silicon / copper bilayer assemblies described can be considered simplified test cases for electrical component assemblies (e.g., Assembly 200) that have a semiconductor substrate over a stack of layers of materials with a CTE higher than that of the semiconductor substrate.

[0043] Fig. Figure 3 shows a graph of finite element simulation data and an analytical calculation regarding the stress variation in a bilayer consisting of a 170 nm thick silicon layer bonded to a 250 nm thick copper substrate. The finite element simulations show data for separate values ​​of the distance from the silicon / copper interface. The analytical calculation program provides data regarding the continuous variation of this distance.

[0044] The two simulation methods used yielded identical results. They predicted that compressive stress (indicated by negative stress values) is present across the entire thickness of the copper substrate. In the silicon layer, the compressive stress decreases continuously and eventually becomes tensile stress with increasing distance from the silicon / copper interface. For the given silicon and copper thickness values, silicon regions adjacent to the copper interface are evidently compressed, while silicon regions further away from the copper are expanded. The simulations predict a compressive stress of 200 MPa or more for silicon thicknesses of 40 µm or less.

[0045] In some embodiments, the combination of semiconductor CTE value(s), compound layer CTE value(s), backside metallization layer CTE value(s), and / or substrate CTE value(s) results in compressive stress across the entire thickness (height) of the semiconductor substrate (or chip). In some embodiments, the combination of these CTE values ​​results in no tensile stress, and in particular, tensile stress on the top surface of the semiconductor substrate (or chip). In many embodiments, the semiconductor substrate is compressed when the ratio between compound layer thickness and semiconductor substrate (or chip) thickness is 1.5:1, 2:1, or 2.5:1. In many embodiments, the semiconductor substrate is compressed when the ratio between backside metallization layer thickness and semiconductor substrate (or chip) thickness is 1.5:1, 2:1, or 2.5:1.

[0046] The Fig. 4 and Fig. Figure 5 shows experimental data of a silicon chip / copper connector frame interface formed at 300 °C. Fig. Figure 4 shows the load on the lower surface, and Fig. Figure 5 shows the stress on the upper surface. The silicon thickness was varied between 10 µm and 725 µm, and the copper thickness of the connection frame was varied between 50 µm and 1,000 µm.

[0047] In accordance with the simulation data from Fig. 3 confirm the experimental data from the Fig. 4 and Fig. 5. For a copper thickness range of 250 µm to 1,000 µm, a moderate reduction in compressive stress in the silicon substrate was observed, eventually reversing into tensile stress with increasing distance from the silicon / copper interface. It was found that the compressive stress increased with increasing copper layer thickness compared to silicon layer thickness. For a copper thickness range of 250 µm to 1,000 µm, compressive stress values ​​of -300 MPa or more were measured across the entire silicon thickness when the silicon thickness was 40 µm or less. A value of -300 MPa exceeds the value of -100 MPa, the minimum stress required to achieve a significant performance increase in an electrical device, by a factor of 3.

[0048] The formation of compressive stress becomes more difficult in thicker silicon layers, which are harder to deform under the mechanical forces originating from the silicon / copper interface. For example, when a silicon thickness of 380 µm was combined with a copper thickness of 1,000 µm, the resulting compressive stress in the silicon was rather low (only about 40 MPa). In some embodiments, the silicon thickness should not exceed 40 µm or 50 µm because tensile stress and / or lower loads may not lead to the desired improvement in electrical performance.

[0049] Fig. Figure 6 shows an embodiment of a method for manufacturing an enclosed component 600, which has a vertical power semiconductor device subjected to pressure.

[0050] In step 605, one or more vertical devices are fabricated in or on the semiconductor substrate (e.g., the wafer). The vertical devices may contain integrated circuits (ICs). Step 605 represents a sequence of conventional processing steps, including lithography, dry or wet setting, thin-film deposition, implantation, chemical-mechanical polishing (CMP), and metrological steps.

[0051] In step 610, the semiconductor substrate is thinned if necessary. The substrate is thinned, for example, by grinding or lapping. Lapping machines use a liquid called a "lapping mixture" containing abrasive materials that act on the surface exposed to the mixture. Grinding wheels can be used in grinding machines. Alternatively, chemical-mechanical polishing (CMP), which is based on a combination of chemical attack and mechanical abrasion, can be used. The semiconductor substrate is thinned, for example, to 40 µm, 30 µm, 20 µm, or 10 µm.

[0052] In step 615, a final (or passivation) layer, which has electrically isolated contact points, is formed on the upper surface of the semiconductor substrate. Similar methods can be used as in step 605.

[0053] In step 620, the semiconductor substrate is temporarily bonded to a support wafer. The semiconductor substrate can be bonded to the support wafer with its top surface facing down. A backside metallization (RSM) layer is applied to the back side of the semiconductor substrate. The RSM layer can have one or more metal or metal alloy layers. Material options and thickness ranges have already been described. The RSM layer can be sputtered onto the semiconductor substrate.

[0054] Sputtering involves bombarding atoms from a negatively biased target (using biases of -300 V or more) due to the action of high-energy positively charged ions created in a low-pressure atmosphere under the influence of an electric field. Magnetron systems are commonly used to generate direct current or radio frequency fields, both of which can be used to sputter conductive materials. The sputtering gas typically contains a noble gas, such as argon. The material ejected from the target is deposited as a thin film onto the substrate, for example, a wafer of silicon or an alternative semiconductor material. The substrate is generally maintained at a temperature between approximately 200 °C and 400 °C to improve film density and adhesion to the substrate.

[0055] In general, the stress induced in a deposited film can have two components: thermal stress and intrinsic stress (residual stresses). Thermal stress plays a role when deposition occurs at an elevated temperature and the coefficients of thermal expansion (CTE) of the deposited film material and the substrate material differ. Intrinsic stress refers to the microstructure of the deposited film. Intrinsic stress can be either compressive or tensile. Intrinsic stress can contribute significantly to the overall stress in a sputtered film when the deposition temperature is below one-fifth of the melting point (Fp) of the sputtered material. This condition can occur in practice, particularly when copper (Fp 1083 °C) or aluminum (Fp 660 °C) layers are part of a resurfaced surface finish (RSM) stack.

[0056] The development of intrinsic compressive stress is generally attributed to a mechanism known as "atom peening," where bombardment with a high-energy species causes a denser packing of atoms in the deposited layer. Intrinsic compressive stress in sputtered films can be facilitated by increasing the energy and / or flux of the metal and noble gas ions arriving at the substrate. This can be achieved, for example, by applying a negative preload to the substrate or by working in a very low pressure range (e.g., by applying an Ar pressure of only a few mT).

[0057] In step 625, the processed semiconductor substrate is divided into individual chips. The semiconductor substrate can be cut, for example, with a saw or a laser.

[0058] In step 630, a bonding layer material (e.g., a conductive layer material) is formed over defined areas on the upper surface of a substrate. As previously explained, the bonding layer can consist of a solder material or a conductive organic adhesive. Diffusion solder materials, such as AuSn, CuSn, CuSn, or AgIn, can be applied as a coating over the entire substrate surface using electroplating, vapor deposition, or evaporative sputtering processes. The subsequent partial removal of solder material from substrate areas that are to be solder-free can be achieved by laser ablation using high-energy lasers (Nd:YAG or excimer lasers) or by conventional lithography followed by dry or wet plating.

[0059] Alternatively, solder paste can be selectively applied using methods such as edge masking, spraying, speckling, or stencil printing. Drying in an oven or with hot air can remove any remaining solvent from the paste. The solder paste can then be baked / cured for several minutes at temperatures between approximately 100 °C and 250 °C.

[0060] The mechanical properties of diffusion-resistant and soft solder materials can vary considerably depending on the type and weight fraction(s) of metals contained within each group. On average, diffusion-resistant solder materials are more rigid than soft solder materials. For example, the modulus of elasticity of Au80Sn20 is 68 GPa, while the modulus of elasticity of Sn63Pb37 is only 41 GPa.

[0061] Alternatively, electrically conductive adhesive materials used as a bonding layer can be applied in the form of so-called preforms, i.e., prefabricated sections of adhesive film. The thickness of preforms can vary between 5 µm and 50 µm. Some preforms contain a UV-sensitive component. Such materials can be UV-cured after application. Depending on the thickness of the preform, the curing time can vary between approximately 1 s and approximately 20 s. Preforms that are not sensitive to UV light can be heat-cured at temperatures between approximately 130 °C and approximately 160 °C. Curing times for this process can vary between approximately 20 s and approximately 60 s.

[0062] In step 635, one or more chips are bonded to the substrate. A first chip is picked up using a conventional pick-and-place machine and placed over a predefined position on the substrate, with the RSM-coated side of the chip facing the substrate. The chip is precisely aligned and then bonded to the preheated substrate. In large-scale production, the picking, placement, and chip-to-substrate bonding process is generally repeated for a large number of chips.

[0063] The temperature during bonding depends on the type of bonding material applied to the substrate. For attaching chips to substrates coated with diffusion solder, thermocompression bonding can be used at temperatures between approximately 300 °C and 400 °C. Examples of processing conditions for Au75Sn25 solder bonding include: solder thickness 1200 nm, bonding temperature 360 ​​°C, bonding time 350 ms, and bonding force 3.3 N / mm². 2 Bonding soft retardation of 150 ms, using a bonding tunnel with a forming gas (85% N2 + 15% H2) atmosphere. Bonding with soft solder materials can be carried out at temperatures in the range of approximately 200 °C to approximately 240 °C, again under a reducing atmosphere.

[0064] Bonding of electrically conductive adhesive films or pastes can be performed at temperatures between approximately 180 °C and 250 °C. The bonding pressure can vary from approximately 1 MPa to approximately 5 MPa. The bonding time can vary between approximately 1 and 2 minutes. The bonding temperature can potentially be increased to 20 °C below the temperature at which the adhesive begins to degrade. This can improve the stiffness of the adhesive layer and enhance its effectiveness as a stress buffer to mitigate stresses entering the semiconductor substrate from the microchip / support connection.

[0065] In the next step, bonding elements are attached to the component contact points and carrier contact points (e.g., connection frame contact points). Bond wires used as connections can be applied using methods such as ultrasonic, thermal compression, or combined thermal compression and ultrasonic bonding. Ultrasonic bonding uses ultrasonic energy with a frequency range of approximately 20 kHz to 60 kHz at room temperature. The duration of ultrasonic bonding is approximately 20 ms. Combined thermal compression and ultrasonic bonding uses a combination of heat, ultrasonic energy, and pressure. Combined thermal compression and ultrasonic bonding can be performed at lower temperatures and pressures than thermal compression bonding. Temperatures in the range of approximately 125 °C to 150 °C and bonding loads between 0.5 g and 2.5 g per bonding wire are sufficient.

[0066] In step 645, the carrier and the attached component(s) and fasteners are fully or partially encapsulated. The encapsulation material can be a molding compound, a laminate, or a glob-top coating. Encapsulation processes such as compression molding, injection molding, injection casting, power or liquid molding, dispensing, or laminating can be used for encapsulation with a dielectric material.

[0067] In step 650, the encapsulated carrier and the component(s) are separated into individual encapsulated components (individual encapsulated components can contain more than one component). For example, individual connection frame units can be punched out of a connection frame track, or a larger carrier plate can be cut into smaller units by sawing or laser cutting.

Claims

[1] Composite device (200) comprising the following: a carrier (260); a bonding layer (250) formed on the support (260), wherein the bonding layer (250) has a first thickness; and a chip (210) formed on the interconnect layer (250), wherein the chip (210) has a second thickness, where the second thickness is less than the first thickness; and the chip (210) is subjected to pressure over its entire second thickness. [2] Composite device (200) according to claim 1, wherein the second thickness is 40 µm or less and wherein the first thickness is 40 µm or more. [3] Composite device (200) according to claim 2, wherein the connecting layer (250) comprises a conductive adhesive paste. [4] Composite device (200) according to claim 2, wherein the connecting layer (250) comprises a conductive adhesive film. [5] Composite device (200) according to claim 2, wherein the connecting layer (250) comprises a soft solder. [6] Composite device (200) according to claim 1, wherein the second thickness is 5 µm or less and wherein the first thickness is 5 µm or more. [7] Composite device (200) according to claim 6, wherein the connecting layer (250) has a diffusion bond layer. [8] Composite device (200) according to any one of claims 1 to 7, wherein the connecting layer (250) is a backside metallization layer. [9] Composite device (200) according to any one of claims 1 to 8, wherein the chip (210) is a vertical power semiconductor device. [10] Composite device (200) according to any one of claims 1 to 9, wherein the chip (210) comprises silicon carbide. [11] Enclosed power component (200) comprising the following: a connection frame; a bonding layer (250) formed on a support (260); a vertical power semiconductor chip (210) formed on the interconnect layer (250), which has a thickness, wherein the vertical power semiconductor chip (210) is subject to pressure over its entire thickness; Intermediate connections (270, 272) that connect the chip contact points to the leads of the connection frame; and an encapsulation (280) that encapsulates the vertical power semiconductor chip (210). [12] Enclosed power component (200) according to claim 11, wherein the pressure load is 100 MPa or more. [13] Enclosed power component (200) according to claim 11 or 12, wherein the vertical power semiconductor chip (210) has a diameter of 40 µm or less. [14] Enclosed power component (200) according to claim 13, wherein the interconnect layer (250) comprises a soft solder layer, a conductive adhesive film or a conductive adhesive paste and wherein the interconnect layer (250) has a thickness of 40 µm or more. [15] Enclosed power component (200) according to any one of claims 11 to 14, wherein the vertical power semiconductor chip (210) has a diameter of 10 µm or less. [16] Enclosed power component (200) according to claim 15, wherein the interconnect layer (250) has a diffusion solder layer and wherein the diffusion solder layer has a thickness of 10 µm or less. [17] Enclosed power component (200) according to any one of claims 11 to 16, wherein a coefficient of thermal expansion of the connection frame is more than 15 ppm / K and wherein a coefficient of thermal expansion of a substrate (220) of the power semiconductor chip (210) is between 2 ppm / K and 7 ppm / K. [18] Method for manufacturing a semiconductor device (210), wherein the method comprises: placing a vertical semiconductor device (210) with a lower main surface on a terminal frame; and connecting the semiconductor device (210) to the connection frame by means of a connecting layer (250), thereby creating a pressure load over the entire thickness of the semiconductor device, wherein the connecting layer (250) is thicker than the semiconductor device (210). [19] The method of claim 18, further comprising thinning the semiconductor device (210) prior to placing the semiconductor device (210) on the connection frame. [20] Method according to claim 18 or 19, wherein the vertical semiconductor device (210) is a vertical power semiconductor device (210) having a thickness of 40 µm or less.

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