Cache control to reduce transaction rollback

Abstract

A microprocessor system (100) comprising: a cache (104-110) comprising: a plurality of cache lines, each characterized by a replacement priority level selected from a plurality of replacement priority levels, wherein the replacement priority level indicates a probability of replacing a cache line causing a rollback of a transaction, each cache line having priority bits (124) indicative of the replacement priority level identifying the cache line, wherein replacing the cache line having a higher replacement priority level has a lower probability of triggering a rollback of a transaction than replacing a cache line having a lower replacement priority level; and a cache controller (128) configured to (1) select a least recently used cache line from the plurality of cache lines having a highest available replacement priority level, and (2) replace the least recently used cache line having the highest available replacement priority level according to a replacement scheme.

Description

BACKGROUND

[0001] Microprocessors can use transaction-based processing, where operations (e.g., arithmetic, logical, memory-related, branching, floating-point-related, etc.) are organized into indivisible sets called transactions. Each transaction succeeds or fails when processed by the microprocessor as a whole. In other words, the microprocessor ensures that either all operations in a transaction complete without errors, or none of them complete. If some of the operations complete but errors occur when the other operations are picked up, the microprocessor "rolls back" all operations of the transaction (including the previous operations).all successful ones), erasing all traces of the transaction and returning the system to a consistent, known state from which the microprocessor started the transaction. When all operations of a transaction are successfully completed, the transaction is committed by the microprocessor, all changes are marked as permanent, and the known state is updated.

[0002] Transaction processing protects against hardware and software errors that leave a transaction partially completed, which can lead to an unknown, inconsistent state. For example, if an agent (e.g., a processing core, a direct memory access (DMA) snooping memory controller, an instruction loader, etc.) that is not involved in the transaction attempts to access or modify data involved in a transaction, the transaction system guarantees that all operations in any uncommitted transactions are rolled back and a consistent state is restored. By tracking a known and consistent state of the microprocessor, rolling back such a state if the state is uncommitted, the transaction system ensures that the transaction cannot be committed.If the memory can be committed, the integrity of the data in the microprocessor can be protected against corruption and operational instability of the microprocessor. US 2010 / 0318741 A1 discloses a multi-processor system with a local memory shared by the various processors. US 6 961 821 B2 discloses a system memory with multiple nodes, wherein a cache memory is replaced depending on a rank.

[0003] Although transaction rollback protects against data corruption, there are performance penalties associated with rollbacks. These penalties are paid for, for example, by additional processing during recovery from a rollback relative to a fully committed transaction. In particular, performance penalties can be significant for large and long-running transactions. One objective of the invention is to reduce the probability of a rollback occurring. SUMMARY

[0004] This object is achieved by the features of the independent claims. Preferred embodiments are described in the dependent claims. Various embodiments are known relating to controlling a cache of a microprocessor system in order to reduce the possibility of a rollback. In one embodiment, a microprocessor system according to claim 1 comprises, among other things, a plurality of cache lines, each characterized by a replacement priority level selected from a plurality of priority levels, and a cache controller. The cache controller is configured to (1) select a least recently used cache line of the plurality of cache lines with the highest available replacement priority level and (2) replace the least recently used cache line having the highest available replacement priority level according to a replacement scheme. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1 shows an embodiment of a microprocessor of a computing device of the present disclosure. Fig. Figure 2 shows an example list of replacement priority levels used to mark the cache lines in the cache. Fig. Figure 3 schematically shows a tree LRU cache line replacement scheme used for a cache. Fig. 4 shows an embodiment of a method for controlling a cache to reduce transaction rollback. DETAILED DESCRIPTION

[0005] This discussion describes novel systems and methods for controlling a microprocessor cache in a manner that reduces the probability of a transaction rollback. In particular, this discussion relates to a multi-level cache line replacement scheme.

[0006] In one example, cache lines are prioritized for replacement based on the probability of their replacement causing a transaction rollback. Specifically, each cache line in a cache is assigned a replacement priority level selected from a plurality of replacement priority levels. For example, in an inclusive cache, a cache line duplicated in a lower-level cache is assigned a lower replacement priority level compared to a cache line that is invalid. This is because if the cache line duplicated in a lower-level cache is replaced, the corresponding cache line in the lower-level cache would also need to be replaced. Because such a replacement affects multiple caches, there is a higher probability of interference with an operation that would cause a transaction rollback.In contrast, an invalid cache line can be replaced without affecting any other memory level. In this example, replacing a cache line with a higher replacement priority level would have a lower probability of triggering a rollback of all transactions than replacing a cache line with a lower replacement priority level.

[0007] In this scheme, a least-recently-used (LRU) cache line in the cache (or in the cache's cache line set in the case of a set-associative cache) is selected that has the highest available replacement priority level. Furthermore, the selected least-recently-used cache line is replaced with the highest available replacement priority level according to a replacement scheme. In one embodiment, a tree-LRU cache line replacement scheme is used to replace the selected cache line in the cache. It should be noted that the highest available replacement priority level describes that if there is no cache line identified by the highest replacement priority level in the cache (or an assigned cache line set in the cache), an LRU cache line is searched which has a next higher replacement priority level.This continues through the replacement priority levels until an LRU cache line is selected that has the highest available replacement priority level. By using a multi-level control scheme that relies on selecting a cache line based on a replacement priority level in addition to a simple replacement approach (e.g., tree LRU), the probability of a transaction being rolled back can be reduced compared to replacing only the least recently used cache line.

[0008] Fig. 1 schematically describes a microprocessor system 100 used in connection with the systems and methods described herein. The microprocessor 100 may be a transaction-based microprocessor. The microprocessor system 100 optionally includes and / or communicates with a memory hierarchy 102, which includes a Level 1 (L1) data cache 104, an L1 instruction cache 106, a Level 2 (L2) cache 108, a Level 3 (L3) cache 110, main memory 114 (e.g., one or more DRAM chips), secondary storage devices 116 (e.g., magnetic and / or optical storage devices), and / or tertiary storage 118 (e.g., a tape farm). Typically, the L1 - L3 caches are implemented on the processor semiconductor element and the higher level memory components are implemented separately outside the processor semiconductor element.In general, lower-level memory may be smaller and faster, while higher-level memory may be larger and slower. A memory controller 112 manages the protocol and provides the signal interface required by main memory 114, which typically determines the timing of memory accesses. The memory controller 112 may be implemented on or off the processor semiconductor device.

[0009] It will be understood that these memory components are listed in ascending order of access times and capacities, although there may be possible exceptions. In some embodiments, one or more of these components of the microprocessor may be omitted. It should also be understood that the memory architecture described above is not limiting, and that other memory hierarchies may be utilized without departing from the scope of this disclosure. The depicted memory hierarchy is an exemplary illustration, and it will be understood that other hierarchies may be utilized without departing from the spirit of the present disclosure.

[0010] In some embodiments, at least some of the different-level caches (e.g., L1, L2, L3) may signal an eviction and / or replacement of a cache line with at least one cache of a different level. In other words, the different-level caches do not silently replace a line (cache line). In one particular example, the L1 data cache 104 and the L1 instruction cache 106 signal an eviction and / or replacement of a cache line to the L2 cache. This example configuration may be particularly suited to the multi-level replacement approach described herein because the L2 cache 108 may make replacement decisions based on the current contents of the L1 cache.

[0011] On the other hand, if the L1 cache allocated cache lines and did not signal the L2 cache when cache lines were dropped, eventually every cache line would be claimed as belonging to the L1 cache. Such cache line ownership would cause all cache lines to be identified by having the same priority level. If all cache lines have the same replacement priority level, the multi-level replacement scheme collapses into a standard LRU replacement scheme because all priorities are equal, and rollback penalty avoidance would be reduced.

[0012] In some embodiments, at least some of the caches at different levels are inclusive caches that allocate cache lines for data duplication from at least one lower-level cache. In one example, the L2 cache is a unified cache, which is an inclusive cache that allocates cache lines for data duplication from the L1 data cache 104 and the L1 instruction cache 106. This example configuration may be particularly suitable for the multi-level replacement approach described herein because the L2 cache 108 may make a replacement decision based on the contents of the L1 cache.

[0013] In some embodiments, microprocessor system 100 is a pipelined processor including call logic 130, decode logic 132, execution logic 134, memory logic 136, and write-back logic 138. Call logic 130 fetches instructions from the L1 instruction cache, backed by the L2-L3 caches, and main memory. Decode logic 132 decodes the fetched instructions, for example, parsing them for opcodes, operands, and addressing modes. After parsing, the instructions are then executed by execution logic 134. For operations that produce a result (e.g., as opposed to those that branch to another location in the executing program), the write-back logic 138 writes the results back to an appropriate location, such as a processor register.

[0014] It should be noted that the above five states are somewhat specific to, and typically included in, a Reducing Instruction Set Computer (RISC) implementation. In general, a microprocessor may include call, decode, and execution logic, with memory and write-back functionalities performed by the execution logic. The present disclosure is equally applicable to these as well as other microprocessor implementations.

[0015] With regard to the L2 cache 108, the current discussion focuses on controlling the operation of the L2 cache 108, and more particularly, on a multi-level replacement scheme for replacing cache lines in the L2 cache 108. The L2 cache 108 includes a memory space divided into a plurality of cache lines. In a particular embodiment, each cache line has 64 bits. The L2 cache is a set-associative cache, and the cache lines are logically divided into a plurality of cache line sets. Of course, each L2 cache may include any suitable number of cache line sets, each of the cache lines may have any suitable size, and the number of bytes in each cache line may vary without departing from the scope of the present disclosure.

[0016] The number of cache lines in a cache line set may define the number of locations in the L2 cache 108 to which a particular location in main memory can be mapped. In one example, the L2 cache has a 16-way set-associative array, where each set of cache lines is associative and has 16 paths in which data can be stored. Those skilled in the art will understand that the L2 cache 108 may have any suitable number of paths or data locations in a cache line set (e.g., 2-way, 8-way, fully associative, etc.) without departing from the scope of the present disclosure.

[0017] Each cache line of the L2 cache 108 is divided into different bit fields to provide different information. In particular, each cache line of the L2 cache 108 contains least recently used (LRU) bits, tag bits including replacement priority level bits, and data bits. The LRU bits indicate a least recently used (or accessed) path in a cache line set. The tag bits identify a selected path where an instruction corresponding to the address is stored. The replacement priority bits identify a replacement priority level that further identifies the cache line. The data bits store the data for the cache line.

[0018] The different bit fields of each of the cache lines are organized into different fields, which are controlled by the cache controller 128. In particular, the L2 cache line 108 includes an LRU field 120, a tag field 122 including replacement priority bits 124, and a data field 126. The LRU field 120 includes the LRU bits for each cache line set in the L2 cache 108. The tag field 122 includes the tag bits for each cache line in the cache line 108 as well as the replacement priority bits for each cache line in the L2 cache 108. The data field 126 contains the data bits for each cache line in the L2 cache line 108.

[0019] It will be understood that the replacement priority bits 124 may be stored in any suitable field of the cache line or in another location without departing from the scope of the present disclosure. It should also be noted that different level caches or other memory / storage components are illustrated in simplified form and may include alternative or additional elements. For example, the L2 cache may include alternative or additional fields.

[0020] The cache controller 128 is configured to control replacement of cache lines in the L2 cache 108. In one example, the cache controller 128 is configured to assign a replacement priority level, selected from a plurality of replacement priority levels, to each cache line in the cache. Furthermore, the cache controller 128 may dynamically update the replacement priority level of a cache line. For example, a replacement priority level in a cache index may be updated whenever an event occurs that changes the state of the cache. Non-limiting examples of events that change the state of the cache include a new entry allocation for a cache line, a read / write request affecting a cache line, a write-back to a cache line, and an eviction of a cache line.It should be noted that the LRU bits can be updated based on the same type of events as the replacement priority levels.

[0021] Although the replacement priority levels are prioritized according to the likelihood of affecting a cache with another level, it should be understood that in some embodiments, the priority levels may be prioritized for different operating characteristics without departing from the scope of the present disclosure. For example, the replacement priority levels may be geared toward optimized processing speed, power reduction, etc.

[0022] The cache controller 128 is configured to select a least recently used cache line from the plurality of cache lines having the highest available replacement priority level in the L2 cache 108. Note that if the L2 cache is a set-associative cache, the cache controller 128 may be configured to select a least recently used cache line having the highest available replacement priority level from a plurality of cache lines in a selected cache line set in the L2 cache. For example, the selected cache line set may include a cache line set containing tag bits corresponding to an address of data to be stored in the L2 cache. The plurality of replacement priority levels may be prioritized according to a likelihood of impacting a lower-level cache.In particular, replacing a cache line with a higher replacement priority level would be less likely to affect a cache with a lower replacement priority level and trigger a transaction rollback than replacing a cache line with a lower replacement priority level. Note that if no cache lines are designated by a particular replacement priority level, the replacement priority level can be ignored during the search, and the next highest available priority level for an LRU cache line can be searched for.

[0023] In one embodiment, cache controller 128 is configured to search all cache lines having the highest replacement priority level and select the least recently used cache line having the highest replacement priority level for replacement. If no cache lines are identified by the highest replacement priority level, cache controller 128 is configured to search all cache lines having the next higher replacement priority level and select the least recently used cache line having the next higher replacement priority level for replacement. Cache controller 128 is configured to search the cache lines, starting from the highest replacement priority level and working down until an LRU cache line having a highest available replacement priority level is found.In addition, the cache controller 128 is configured to replace the selected LRU cache line having the highest available replacement priority level according to a replacement scheme.

[0024] Those skilled in the art will recognize that any suitable cache line replacement scheme may be utilized in conjunction with replacement priority level selection to form a multi-level control approach without departing from the scope of the present disclosure. In one embodiment, the replacement scheme includes a perfect least recently used cache line replacement scheme. In such an implementation, whenever a cache line is used, the LRU bits for all other cache lines in the cache are updated, and the least recently used cache line in the cache is replaced. In another embodiment, the replacement scheme includes a pseudo least recently used cache line replacement scheme, such as a least recently used cache line tree replacement scheme.Such a scheme can be used for caches with high associativity because the implementation cost of tracking a perfect "least recently used" becomes prohibitive. In such a replacement scheme, fewer bits can be used to track LRU in a cache line set compared to a perfect LRU replacement scheme. In yet another embodiment, a first-in-first-out (FIFO) cache line replacement scheme can be used to replace a cache line having the highest replacement priority level. In yet another example, a random replacement scheme can be used to replace a selected cache line having the highest replacement priority level.

[0025] It should be noted that the multi-level replacement scheme described herein may be applied to any level cache or other memory components to reduce the likelihood of a transaction rollback by a microprocessor without departing from the scope of the present disclosure.

[0026] Fig. 2 shows an example list 200 of replacement priority levels used to characterize cache lines in a cache. The list 200 contains five replacement priority levels, ranked from the highest 1 to the lowest 5. The majority of the replacement priority levels are prioritized by a probability of affecting a cache with a lower level, where a replacement of a cache line having a higher replacement priority level has a lower probability of affecting a cache with a lower level and causing a transaction rollback than a replacement of a cache line having a lower replacement priority level.

[0027] The first (1) replacement priority level contains invalid cache lines. The valid cache lines may include cache lines that are not claimed or used by any cache or have invalid data that is not useful for any cache. The second (2) replacement priority level contains cache lines that are awaiting eviction. In one embodiment, each cache line may include an eviction awaiting bit in the tag field to indicate that the cache line is awaiting eviction. The third (3) replacement priority level contains valid cache lines that are not claimed by any other cache. In other words, these cache lines may contain valid information and be claimed by the L2 cache. The fourth (4) replacement priority level contains cache lines that are claimed by the L1 instruction cache 106 and not by the L1 data cache.The fifth (5) replacement priority level contains cache lines owned by the L1 data cache 104. As discussed above, the L2 cache may be present and thus allocate cache lines for duplication of data in the L1 instruction cache and the L1 data cache. These cache lines have lower priority levels because replacing these cache lines may affect the state of the L1 instruction cache and the L1 data cache, resulting in a transaction rollback.

[0028] It should be understood that the replacement priority levels described above are purely examples, and more or fewer replacement priority levels may be used without departing from the scope of the present disclosure. For example, a load / store unit (not shown) in the write-back logic of the processing pipeline may provide additional information to the L2 cache so that the number of cache lines considered for replacement may be reduced. Such a design may be faster, but may also potentially add additional complexity to the microprocessor design.

[0029] Fig. Figure 3 schematically illustrates a tree-LRU cache line replacement scheme 300 that may be utilized by the L2 cache as part of a multi-level replacement scheme of the present disclosure. The tree-LRU cache line replacement scheme 300 is applied to a cache line set of 16 cache lines or paths. In one embodiment, the cache line set is one of a plurality of cache line sets that form a 16-way set-associative L2 cache. Furthermore, the cache line set in the cache may be selected as a candidate for cache line replacement based on the tag bits of cache lines in the cache line set. The tree-LRU replacement scheme selects one of the 16 paths in the cache line set for replacement. The encoding LRU[14:0] represents the temporary ratio of the 16 paths in the LRU tree.Each entry in the encoding can be assigned a value of 0 or 1 to indicate a suitable temporal ratio of nodes in the tree to determine which paths have been least recently used. For example, LRU[4] with a value of 1 indicates that WAY1 is "less recently used" than WAY0; and LRU[4] with a value of 0 indicates that WAY0 is "less recently used" than WAY1.

[0030] As discussed above, in the multi-level replacement scheme, each replacement priority level of the LRU tree is searched to select the LRU way. Then, a highest available replacement priority level LRU way is selected over the lower priority level LRU ways. After the highest replacement priority level LRU way is selected, the LRU[14:0] encoding is updated to reflect the new LRU order. In a particular example, if WAY6 was selected as the LRU way having the highest replacement priority level, the LRU[14:0] encoding is updated to reflect the change in the temporal relationship between the nodes associated with WAY6. In particular, the LRU bits are updated as follows: LRU[8]=1, LRU[6]=0, LRU[1]=0, and LRU[0]=1. The rest of the bits in the LRU[14:0] encoding remain unchanged.

[0031] It should be noted that the LRU tree replacement scheme 300 is merely one example of a replacement scheme that may be used to replace a cache line with a highest replacement priority level in a cache as part of a multi-level replacement scheme of the present disclosure. Furthermore, any suitable replacement scheme may be used in conjunction with the replacement priority level without departing from the scope of the present disclosure.

[0032] Fig. 4 shows an embodiment of a method 400 for controlling a cache to reduce the likelihood of a transaction rollback in a transaction-based microprocessor. The microprocessor may have a plurality of caches with different levels; and at least some of the caches with different levels may indicate an eviction and / or replacement of a cache line to at least one other cache with a different level. Additionally, at least some of the caches with different levels may include caches that allocate cache lines for duplication of data from at least one low-level cache. In a particular example, the method 400 is performed by the cache controller 128 in the L2 cache 108 of the microprocessor system 100, as shown in Fig.1. In this example, the L2 cache is a unified cache, which is an "inclusive cache" that provides cache lines for all duplication of data from the L1 instruction cache 108 and the L1 data cache 104. In addition, the L1 instruction cache 106 and the L1 data cache 104 indicate an eviction and / or replacement of a cache line to the L2 cache 108.

[0033] Furthermore, each cache line in the cache is characterized by a replacement priority level selected from a plurality of replacement priority levels. The plurality of replacement priority levels may be prioritized according to a probability of affecting a cache with a level. In particular, a replacement of a cache line having a higher replacement priority level has a lower probability of affecting the cache with a lower level and triggering a transaction rollback than a replacement of a cache line having a lower replacement priority level.In one example, the plurality of replacement priority levels, ordered from a highest priority level to a lowest priority level, includes (1) invalid cache lines, (2) cache lines awaiting eviction, (3) valid cache lines not claimed by another cache, (4) cache lines claimed by an L1 instruction cache and not by an L1 data cache, and (5) cache lines claimed by an L1 data cache. In a particular example, each cache line includes replacement priority level bits included in the cache line's tag bits.

[0034] It should be noted that in some cases, the replacement priority level of a cache line may be updated dynamically based on events that cause a state change in the cache, as well as on other events.

[0035] At 402, method 400 includes selecting an LRU cache line having the highest replacement priority level in the cache. In some embodiments (e.g., where the cache is a set-associative cache), the cache line may be selected from an assigned cache line set of the cache. In some embodiments, the LRU cache line may be selected from some or all of the cache lines in the cache.

[0036] At 400, method 400 includes determining whether an LRU cache line has been selected as having the highest replacement priority level. If an LRU way has been selected as having the highest replacement priority level, method 400 continues at 408. Otherwise, method 400 continues at 406.

[0037] At 406, no cache line in the cache (or assigned cache line set) has been identified by the highest replacement priority level, and method 400 includes searching the next higher replacement priority level to select an LRU cache line for that replacement priority level. The method iteratively searches the replacement priority levels until an LRU cache line is selected that has a highest available replacement level.

[0038] At 408, method 400 includes replacing the LRU cache line having the highest available replacement priority level according to a replacement scheme. Replacing may include selecting a cache line with a higher replacement priority level over a cache line with a lower replacement priority level, even if the cache line with the low replacement priority level is more recently used than the cache line with the higher replacement priority level. In other words, the most recently used cache line may be selected over the LRU cache line because replacing the most recently used cache line has a lower probability of affecting completion of a transaction relative to the LRU cache line. In this way, penalties associated with transaction rollback may be reduced.

[0039] Furthermore, the cache line with the highest replacement priority level can be replaced using an appropriate replacement scheme. For example, the replacement scheme can include a perfect least-recently-used cache line replacement scheme, a tree least-recently-used cache line replacement scheme, and a first-in-first-out cache line replacement scheme. In cases where a replacement scheme does not select an LRU cache line, a cache line with a higher priority level can be selected for replacement, regardless of whether it is a least-recently-used cache line in a cache line set or a cache.

[0040] It should be noted that method 400 may be implemented by any suitable level cache or memory component of a microprocessor without departing from the scope of the present disclosure. It should be understood that the configurations and / or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be construed in a limiting sense, as numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, various actions may be performed in the order presented, in a different order, in parallel, or in some cases, omitted. Similarly, the order of the processes described above may be changed.

Claims

[1] A microprocessor system (100) comprising: a cache (104-110) comprising: a plurality of cache lines, each characterized by a replacement priority level selected from a plurality of replacement priority levels, wherein the replacement priority level indicates a probability of replacing a cache line causing a rollback of a transaction, each cache line having priority bits (124) indicative of the replacement priority level identifying the cache line, wherein replacing the cache line having a higher replacement priority level has a lower probability of triggering a rollback of a transaction than replacing a cache line having a lower replacement priority level; and a cache controller (128) configured to (1) select a least recently used cache line from the plurality of cache lines having a highest available replacement priority level, and (2) replace the least recently used cache line having the highest available replacement priority level according to a replacement scheme. [2] The microprocessor system (100) of claim 1, wherein the replacement scheme comprises one of a perfect least recently used cache line replacement scheme, a tree least recently used cache line replacement scheme, and a first-in-first-out cache line replacement scheme. [3] The microprocessor system (100) of claim 1, wherein the replacement scheme is a tree-least-used cache line replacement scheme. [4] The microprocessor system (100) of claim 1, wherein the microprocessor comprises a plurality of caches (104-110) of different levels, and wherein at least some of the caches of different levels signal an eviction and / or replacement of a cache line by at least one cache of a different level. [5] The microprocessor system (100) of claim 4, wherein the at least some of the different level caches also include caches that allocate cache lines for duplication of data from a cache of at least one lower level. [6] The microprocessor system (100) of claim 4, wherein the cache (104-110) is a unified L2 cache (108) comprising a cache that allocates cache lines for duplication of data from an L1 instruction cache (106) and an L1 data cache (104). [7] The microprocessor system (100) of claim 1, wherein the microprocessor is a transaction-based microprocessor. [8] The microprocessor system (100) of claim 7, wherein the plurality of replacement priority levels are prioritized according to a probability of affecting a lower level cache, wherein replacement of a cache line having a higher replacement priority level has a lower probability of affecting the lower level cache and triggering a rollback of a transaction than replacement of a cache line having a lower replacement priority level. [9] The microprocessor system (100) of claim 1, wherein the plurality of replacement priority levels comprise: ordered from a highest priority level to a lowest priority level, (1) invalid cache lines, (2) cache lines awaiting eviction, (3) valid cache lines not claimed by another cache, (4) cache lines claimed by an L1 instruction cache (106) and not to an L1 data cache, and (5) cache lines claimed by the L1 data cache (104).

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