Semiconductor building element with edge closure structure with trench insulation areas and manufacturing process

Abstract

Semiconductor device comprising a semiconductor body (100) and an edge termination structure, wherein the edge termination structure comprises: a first oxide layer (211); a second oxide layer (212); a semiconductor mesa region (111) between the first oxide layer (211) and the second oxide layer (212); and a doped field region (11) having a first section (111) in the semiconductor mesa region (111) and a second section (112) in a region below the semiconductor mesa region (111), wherein the second section (112) overlaps the first and second oxide layers (211, 212) in a region below the semiconductor mesa region (111); an insulating layer (22) arranged above the first and second oxide layers (211, 212), which has an opening (23) above the semiconductor mesa region (111) and which partially covers the semiconductor mesa region (111); and a field electrode (12) which is located above the insulation layer (22), electrically connected to the doped field region (11) in the opening of the insulating layer (22), extends above the insulation layer (22) in a first lateral direction beyond the doped field area (11), and above the insulation layer (22) in a second lateral direction opposite to the first lateral direction above the doped field area (11).

Description

[0001] Exemplary embodiments of the present invention relate to a method for producing an edge termination structure in a semiconductor device and a semiconductor device with an edge termination structure.

[0002] Power semiconductor devices, such as power diodes, power MOSFETs, or power IGBTs, are designed to withstand high reverse voltages. These devices incorporate a pn junction formed between a p-doped semiconductor region and an n-doped semiconductor region. The device is reverse-biased (off) when the pn junction is reverse-biased. In this case, a depletion region (space charge region) spreads across the p-doped and n-doped regions. Typically, one of these n-doped and p-doped semiconductor regions is less densely doped than the other, so the depletion region spreads primarily in the less densely doped region, which mainly accepts the voltage applied across the pn junction.

[0003] The ability of a pn junction to withstand high voltages is limited by the avalanche breakdown phenomenon. As the voltage applied to the pn junction increases, an electric field intensifies in the semiconductor regions that form the junction. This electric field causes mobile charge carriers present in the semiconductor region to accelerate. Avalanche breakdown occurs when, due to the electric field, the charge carriers are accelerated to such an extent that they generate electron-hole pairs through impact ionization. Charge carriers generated by impact ionization then create new charge carriers, resulting in a multiplication effect. Upon onset of avalanche breakdown, a significant current flows backward through the pn junction. The voltage at which avalanche breakdown begins is called the breakdown voltage.

[0004] The electric field at which the avalanche breakthrough begins is called the critical electric field (E crit ). The absolute value of the critical electric field depends mainly on the type of semiconductor material used to create the pn junction and is weakly dependent on the doping concentration of the more lightly doped semiconductor region.

[0005] The critical electric field is a theoretical value defined for a semiconductor region that is infinitely large in directions perpendicular to the electric field vectors. However, power semiconductor devices have a semiconductor body of finite size, bounded laterally by edge surfaces. In vertical power semiconductor devices, which are semiconductor devices where the pn junction extends mainly in a horizontal plane of the semiconductor body, the pn junction typically does not extend to the edge surface of the semiconductor body but is spaced laterally from it. In this case, a semiconductor region (edge ​​region) of the semiconductor body, adjacent to the pn junction laterally, must also withstand the reverse voltage.

[0006] In the edge region, an edge termination structure can be implemented to improve the blocking voltage withstand capability. Various types of edge termination structures are known. One such structure comprises a doped field ring surrounding the semiconductor region containing the pn junction and connected to a field plate.

[0007] DE 694 03 251 T2 describes a semiconductor device with an edge termination structure. The edge termination structure comprises several insulating layers arranged in recesses of a semiconductor body, between which semiconductor mesa regions are arranged. In each of the semiconductor mesa regions and in a section below the respective semiconductor mesa region, a p-doped semiconductor region is formed, which forms a pn junction with an adjacent semiconductor region. Each of the semiconductor mesa regions is contacted by a field plate that is applied directly to the semiconductor mesa region and the adjacent insulating layers and is embedded in an insulating layer on which a semi-insulating layer is arranged.

[0008] JP 2009 099863 A describes a semiconductor device with two spaced-apart oxide layers within a semiconductor body, between which a semiconductor measurement area is arranged and which extend upwards beyond the semiconductor measurement area. An insulating layer is arranged on the oxide layers, which has a contact opening above the semiconductor measurement area and on which a field plate is formed that contacts the semiconductor measurement area at the contact opening.

[0009] The object underlying the invention is to provide a semiconductor device with an improved edge termination structure. This object is achieved by a semiconductor device according to claim 1.

[0010] The object underlying the invention is also to provide a method for producing an improved edge closure structure. This object is achieved by a method according to claim 11.

[0011] Examples will now be explained using drawings. The drawings serve to illustrate the basic principle, so only features necessary for understanding the basic principle are shown. The drawings are not to scale. In the drawings, the same reference symbols denote the same features.

[0012] Fig. Figures 1A to 1D illustrate an embodiment of a method for producing an edge closure structure that has a field area.

[0013] Fig. Figure 2 illustrates a top view of a semiconductor body having an edge termination structure with a ring-shaped field region.

[0014] Fig. Figures 3A to 3E illustrate steps of an exemplary implementation of the [document / method] described in the Fig. The procedure shown in 1A to 1D is described in further detail.

[0015] Fig. 4A and Fig. Figure 4B illustrates the steps for making a field electrode that electrically contacts a field ring.

[0016] Fig. Figure 5 illustrates a vertical cross-sectional view of the semiconductor body, which has an edge termination structure with two field rings.

[0017] Fig. Figure 6 illustrates an embodiment of a transistor device that has an edge termination structure with a field ring.

[0018] Fig. Figure 7 illustrates an embodiment of a transistor device that has an edge termination structure with a field ring.

[0019] The following detailed description refers to the accompanying drawings. The drawings form part of the description and illustrate specific embodiments of how the invention can be used. Naturally, the features of the various embodiments described herein can be combined unless explicitly stated otherwise.

[0020] An embodiment of a method for producing an edge termination structure in a semiconductor body is described using the following example: Fig. 1A to 1D explained. Fig. Figures 1A to 1D each illustrate a vertical cross-sectional view of a section of the semiconductor body 100. Referring to the Fig. From 1A to 1D, the semiconductor body 100 comprises a first surface 101. The vertical cross-sectional views shown in the Fig. Figures 1A to 1D show the semiconductor body 100 in a section plane that is essentially perpendicular to the first surface 101.

[0021] The semiconductor body 100 (which can also be referred to as a semiconductor chip) can comprise a conventional semiconductor material, such as silicon (Si), silicon carbide (SiC), silicon germanium (SiGe), gallium nitride (GaN), or combinations thereof. The process sequences described below can be applied simultaneously to multiple semiconductor bodies that are parts of a semiconductor wafer before the wafer is subdivided into the individual semiconductor bodies.

[0022] Fig. Figure 1A shows a vertical cross-sectional view of the semiconductor body 100. Fig. Figure 1A shows only one section of the semiconductor body 100, namely the section in which features of the edge termination structure are produced. In this section, the semiconductor body 100 can have a base doping of a first doping type. According to one embodiment, the first doping type is n-type doping. The doping concentration of the base doping is, for example, between 1E12 cm⁻¹. -3 and 1E15 cm -3 .

[0023] Referring to Fig. In step 1B, a first trench 1201 and a second trench 1202 are fabricated in the first surface 101 and spaced apart from each other such that a semiconductor mesa region 101 remains between the first trench 1201 and the second trench 1202. The fabrication of the first trench 1201 and the second trench 1202 can include conventional process sequences for fabricating trenches in a surface of a semiconductor body, such as etching processes using an etch mask.

[0024] Referring to Fig. 1C a first oxide layer, a first oxide area 211 in the first trench 1201 is produced, and a second oxide layer, a second oxide area 212 is produced in the second trench 1202. The fabrication of each of the first and second oxide layers 211, 212 involves oxidizing the semiconductor body 100 at the bottom and sidewalls of the first trench 1201 and the second trench 1202, respectively. This oxidation process consumes semiconductor material along the bottoms and sidewalls of the first and second trenches 1201, 1202, such that the first and second oxide layers 211, 212 ultimately extend deeper into the semiconductor body 100 from the first surface 101 than the first and second trenches 1201, 1202. Furthermore, a semiconductor mesa region 111 remaining between the first and second oxide layers 211, 212 is narrower than the mesa region 110 between the first and second trenches 1201, 1202, which is located in Fig. Figure 1B shows the semiconductor mesa region 111, which is a section of the semiconductor body 100 bounded by the first and second oxide layers 211, 212.

[0025] According to one embodiment, the width w1 of the mesa region 111 between the first and second oxide layers 211, 212 is greater than 3 micrometers (µm), for example, between 5 micrometers and 10 micrometers. According to another embodiment, the first and second oxide layers 211, 212 are produced such that their surfaces are substantially coplanar to the surface 101 of the semiconductor body 100 on the mesa region 111. For example, the first and second oxide layers 211, 212 do not extend more than 150 nm beyond the first surface 101 of the semiconductor body 100. The depth d1 of the first and second oxide layers 211, 212 can be adjusted by setting the duration of the oxidation process, with the depth d1 increasing as the duration of the oxidation process increases.The depth of the first and second oxide layers 211, 212 is the dimension of the oxide layers 211, 212 in the vertical direction of the semiconductor body 100, which is a direction perpendicular to the first surface 101.

[0026] According to one embodiment, the oxidation process is controlled such that it ends when the first and second oxide layers 211, 212 completely fill the first trench 1201 and the second trench 1202, respectively. If the oxidation process ends when the first and second oxide layers 211, 212 have upper surfaces that are substantially coplanar to the first surface 101, then, in a silicon semiconductor body 100, the depth (thickness) d1 of the first and second oxide layers 211, 212 is substantially twice the depth of the first and second trenches 1201, 1202. Therefore, the depth d1 of the first and second oxide layers 211, 212 can also be adjusted by adjusting the depth of the first and second trenches 1201, 1202.For example, a depth d1 of the first and second oxide layers 211, 212 is greater than 300 nanometers (nm), greater than 500 nanometers, greater than 1 micrometer, greater than 1.5 micrometers, greater than 3 micrometers or even greater than 3 micrometers.

[0027] Referring to Fig. 1D further comprises the introduction of dopant atoms into the semiconductor mesa region 111 between the first and second oxide layers 211, 212 and into a region below the semiconductor mesa region 111 to produce a doped field region 11 in and below the semiconductor mesa region 111. The doping type of the field region 11 is, for example, complementary to the doping type of a base doping of the semiconductor body 100 in a region surrounding the field region 11. According to one embodiment, the field region 11 is a p-region.

[0028] According to one embodiment, the introduction of the dopant atoms to create the field region 11 comprises an implantation process in which dopant atoms are implanted into the mesa region 111, and a subsequent diffusion process in which the implanted dopant atoms diffuse deeper into the semiconductor body 100, and in particular into a region below the mesa region 111. The implantation of the dopant atoms into the mesa region 111 can be accomplished using an implantation mask 200 (in Fig. (1D shown in dashed lines) comprise an implantation mask 200 that has an opening above the mesa region 111. This implantation mask 200 prevents the implantation of dopant atoms into the oxide layers 211, 212 and into sections of the mesa region 111. However, the use of the implantation mask 200 is optional and can be omitted. Alternatively, the first and second oxide layers 211, 212 can act as an implantation mask, preventing dopant atoms from being implanted into regions of the semiconductor body 100 other than the mesa region 111. The dopant atoms are implanted, for example, with a dopant dose between 1E13 and 1E15 cm⁻¹. -3 implanted.

[0029] Referring to Fig. Field area 1D comprises a first section 111 within the mesa area 111 and a second section 112 below the mesa area 111. The second section 112 overlaps the first and second oxide layers 211, 212 in a region below the mesa area 111, such that the second section 112 is wider than the first section 111 in a first lateral direction. That is, w2 > w1, where w1 is the maximum width of the second section in the lateral direction and w1 is the width of the first section 111 (which corresponds to the width of the mesa area 111 and the distance between the first and second oxide layers 211, 212 in the first lateral direction). The vertical cross-sectional view of the field area resembles a mushroom, with the first section 111 resembling the stem and the second section resembling the cap.

[0030] In Fig. 1D denotes d2 as a depth of the second section 112. The depth d2 is a maximum dimension of the second section 112 in the vertical direction and defines how deep the second section 112 extends vertically from the first and second oxide layers 211, 212 into the semiconductor body 100. The depth d2 and the width w2 of the second section can be adjusted by the duration and / or the temperature of the previously described diffusion process. The width w2 and the depth d2 increase as the duration and / or temperature of the diffusion process increases. There is a correlation between the width w2 and the depth d2 such that an increase in the depth d2 is associated with an increase in the width. However, the depth d2 and the width w2 can be adjusted independently over wide ranges.The width w2 of the second section is defined by the width w1 of the mesa region 111 and the lateral diffusion of the dopant atoms introduced during the diffusion process, with this lateral diffusion increasing as the duration and / or temperature of the diffusion process increases. The depth d2 is defined by the depth to which dopant atoms are introduced during the implantation process and the vertical diffusion of the introduced dopant atoms. According to one embodiment, dopant atoms are introduced only into the mesa region 111, from where they diffuse into the region below the mesa region. According to another embodiment, dopant atoms are introduced into both the mesa region 111 and the region below the mesa region 111, from where they diffuse deeper into the semiconductor body.

[0031] This allows the geometry of the field ring 11, which is in Fig. As shown in Figure 1D, the depth d1 of the first and second oxide layers 211, 212 and the lateral distance w1 between these first and second oxide layers 211, 212 are well defined by the implantation depth and by the duration and / or temperature of the diffusion process. A pn ​​junction between the field ring 11 and the surrounding semiconductor region is located a distance from the first surface 101 in a region below the first and second oxide layers 211, 212. Thus, a voltage breakdown, which can occur if the pn junction is reverse-biased, occurs a distance from the first surface 101 in a region below the relatively thick oxide layers 211, 212.This means that the highest electric field occurs at a distance from the first surface 101 below the oxide layers 211, 212, so that parasitic charges that may occur along the first surface 101 are not exposed to the highest electric field and thus are less likely to reduce the reverse voltage withstand capability of the component.

[0032] According to one embodiment, the depth of the second section d2 is between 5 micrometers and 10 micrometers. A difference (w2 - w1) / 2 between the second width w2 and the first width w1 is, for example, between 0.2 µm and 10 µm, in particular between 0.5 µm and 5 µm or between 1 µm and 4 µm.

[0033] Fig. Figure 2 shows a top view of the first surface 101 of the semiconductor body 100 after the Fig. The process sequence described in sections 1A to 1D was carried out. Unlike the Fig. 1A to 1D illustrated Fig. 2 schematically the entire semiconductor body 100.

[0034] Referring to Fig. 2. The semiconductor body 100 can have an inner region 130 and a boundary region 140 surrounding the inner region 130. The inner region 130 can contain active component regions of a semiconductor device integrated into the semiconductor body 100. These active component regions are, for example, source, body, and drain regions of a transistor device, such as a MOS-controlled device, such as an IGBT or MOSFET device. Exemplary embodiments of a transistor device integrated in the inner region 330 of the semiconductor body 100 are shown below with reference to the Fig. 5 and Fig. 6 explained.

[0035] The boundary region 140 can be a region of the semiconductor body 100 between the interior region 130 and a boundary surface 102 of the semiconductor body 100 (as in Fig. 2 shown). However, it is also possible to integrate active component regions of several semiconductor devices into a single semiconductor body 100. In this case, the boundary region surrounding the interior region can separate this interior region from the boundary surface and / or other interior regions. Referring to Fig. 2. The field region 11 is ring-shaped, located in the boundary region 140 and surrounds the inner region 130 of the semiconductor body 100. Hereinafter, the ring-shaped field region is referred to as field ring 11. This field ring 11 can be described using the information provided by the Fig. The procedures described in 1A to 1D can be used if the first and second trenches 1201, 1202 are constructed such that an annular mesa area 110 remains between the first and second trenches. If the border area 140 is an area between the interior area 130 and the border surface 102, one of the first and second trenches may extend to the border surface 102, while the other trench may extend to the border area 130.

[0036] Fig. Figure 2 illustrates only one field ring 11. However, it is also possible to realize several (essentially concentric) spaced-apart field rings in a semiconductor body 100.

[0037] The Fig. Figures 3A to 3D illustrate an embodiment for producing the first and second trenches 1201, 1202 and the first and second oxide layers 211, 212 in further detail. Fig. Figures 3A to 3D each show a vertical cross-sectional view of the semiconductor body 100 during (after) different process steps.

[0038] Referring to Fig. Method 3A comprises the fabrication of a first mask layer 210 on the first surface 101 of the semiconductor body 100 and the fabrication of a second structured mask layer 220 on the first mask layer. The first mask layer 210 is, for example, a hard mask layer, such as a nitride layer. The second mask layer 220 is, for example, a photoresist. The second mask layer 220 is used as an etching mask for etching the hard mask layer and the semiconductor body 100 when fabricating the first and second trenches 1201, 1202. This mask layer can be structured in a conventional manner using a phototechnical technique.

[0039] Fig. Figure 3B shows the semiconductor body 100 after an etching process. In this etching process, the second mask 220 (the etching mask) is used as a mask for etching the first mask layer 210 and for etching the semiconductor body 100 to create the first trench 1201 and the second trench 1202 in the semiconductor body 100. During the etching process, the etching mask 220 covers the semiconductor mesa region 110 and prevents it from being etched. The etching process is, for example, an anisotropic etching process. After etching the first and second trenches 1201 and 1202, the etching mask 220 is removed, while the first mask 210 remains on the semiconductor mesa region 110.

[0040] Fig. Figure 3C shows the semiconductor body 100 after the oxidation process, in which the first and second oxide layers 211, 212 are produced in the first and second trenches 1201, 1202. The bottom and sidewalls of the first and second trenches 1201, 1202 are oxidized during the oxidation process in a similar manner as previously described. In a conventional manner, the oxidation process can involve heating the semiconductor body 100 to an oxidation temperature in an oxidizing atmosphere, that is, in an oxygen-containing atmosphere.

[0041] Referring to Fig. 3C prevents the first mask 210 from exposing the first surface 101 to the oxidizing atmosphere, thus preventing the first surface 101 of the mesa region 110 from being oxidized. However, first and second oxide layers 211, 212 grow on the sidewalls of the first and second trenches 1201, 1202, so that such sections of the semiconductor mesa region 110 below the first mask 210 and along the sidewalls of the first and second trenches 1201, 1202 are oxidized. In particular, such sections of the first and second oxide layers 211, 212 growing along the sidewalls can extend beyond the first surface 101 and can cause edges of the first mask 210 to bend upwards, as schematically shown in Fig. 3C is shown.

[0042] Referring to Fig. In 3D, the first mask 210 is removed. Removing the first mask 210 can involve a conventional etching process.

[0043] Referring to Fig. 3E can planarize the structure with the first and second oxide layers 211, 212 and the semiconductor mesa region 111 to make the first and second oxide layers 211, 212 coplanar to the first surface 101. In the planarization process, those sections of the first and second oxide layers 211, 212 that extend beyond the first surface 101 of the semiconductor body 100 are removed. The planarization process can be a conventional planarization process, such as a chemical polishing process, a mechanical polishing process, or a chemical-mechanical polishing process (CMP process).

[0044] As an alternative to removing the mask layer 210 (compare Fig. 3D) and the subsequent planarization of the resulting structure (compare Fig. 3E) a planarization process can be applied to the structure with the mask layer 210, which is in Fig. The process shown in Figure 3C can be applied. This planarization process planars the oxide layers 211 and 212 and removes at least part of the mask layer. Sections of the mask layer 210 remaining after the planarization process can be removed using an etching process.

[0045] The Fig. 4A and Fig. Figure 4B illustrates process steps for fabricating an optional field electrode 12 of the edge termination structure. Referring to Fig. 4A An insulating layer 22, which has an opening 23 above the field area 11, is produced on the first and second oxide layers 211, 212. Referring to Fig. 4A can cover the insulating layer 22 sections of the mesa area 111. The insulating layer 22 is, for example, a glass layer, such as a BPSG (boron-phosphorus silicate glass) layer or a PSG (phosphorus silicate glass) layer. The insulating layer 22 can be produced using a deposition process. The opening 23 can be produced by an etching process using an etching mask.

[0046] Referring to Fig. In step 4B, an electrode layer 12 is fabricated in the opening 23 of the insulating layer 22 and is electrically connected to the field region 11 in the opening 23. The electrode layer 12 also covers sections of the insulating layer 22 adjacent to the opening 23 to form a field electrode (field plate) 12, which is electrically connected to the field region 11 above the insulating layer 22. The field electrode 12 comprises, for example, a metal or a highly doped polycrystalline semiconductor material, such as polysilicon. Fabrication of the field electrode may include a deposition process, in which an electrode material is deposited in the opening of the insulating layer and on the insulating layer, and a structuring process, which structures the electrode layer to fabricate the field electrode. The structuring process may include an etching process.

[0047] Fig. Figure 5 illustrates a vertical cross-sectional view of an edge termination structure according to a further embodiment. In this embodiment, the edge termination structure comprises two field areas 11. 10 , 11 20 , which are spaced apart and each has a field electrode 12 attached 10 , 12 20 is connected. Each of these field areas 11 10 , 11 20 can be ring-shaped, as shown by Fig. 2 explained. In this case, the first and second field areas can be 11 10 , 11 20 exhibiting the form of concentric rings, each surrounding an inner region of the semiconductor body 100. The edge termination structure according to Fig. 5 can be used based on the Fig. 1, Fig. 3 and Fig. The process sequences described in section 4 are produced, with the difference that three oxide layers 211, 212, 213 are produced in three trenches, these three trenches defining two semiconductor mesa regions, resulting in two mesa regions 111 10 , 111 20 between the oxide layers 211, 212, 213.

[0048] The edge closure structure is not limited to having only one or two field rings, but could also be implemented with more than two spaced field rings.

[0049] The previously based on the Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. The edge termination structure described in section 5 can be used in conjunction with a conventional semiconductor device, in particular a vertical power semiconductor device. Examples of vertical power transistors featuring an edge termination structure as previously described in section 5 are shown. Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. As explained in section 5, are in the Fig. 6 and Fig. 7 shown. Fig. 6 and Fig. Figure 7 each shows a vertical cross-sectional view of a section of a semiconductor body 100. These sections of the semiconductor body 100, which are in the Fig. 6 and Fig. Figure 7 shows a section of the interior area 130, which has active component areas, and a section of the boundary area 140, which has the boundary termination structure.

[0050] Referring to Fig. The transistor device comprises several transistor cells 30 in the interior region 130 of the semiconductor body 100. Each transistor cell 30 includes a source region 31, a body region 32 adjacent to the source region 31, and a drift region 33 adjacent to the body region 32. The drift region 33 is located between the body region 32 and a drain region 34. Optionally, a field-stop region (not shown) of the same doping type as the drift region 33, but less densely doped than the drift region 33, can be located between the drift region 33 and the drain region 34. Furthermore, each transistor cell 30 includes a gate electrode 35 adjacent to the body region 32 and dielectrically insulated from the body region 32 by a gate dielectric 36. The individual transistor cells are connected in parallel by connecting the gate electrodes 35 to a common gate terminal G and by electrically connecting their source regions 31 to a common source electrode 41 or 41.The individual transistor cells 30 are connected to a common source terminal S. Furthermore, the individual transistor cells 30 share the drift region 33 and the drain region 34. The transistor device is a vertical transistor device. The source regions 31 and the drain region 34 are spaced apart in the vertical direction (the direction perpendicular to the first surface 101 of the semiconductor body 100) of the semiconductor body 100.

[0051] The transistor device can be an n-type or a p-type transistor device. In an n-type transistor device, the source region 31 and the drift region 33 are n-doped, while the body region 32 is p-doped. In a p-type transistor device, the source region 31 and the drift region 33 are p-doped if the body region 32 is n-doped. Furthermore, the transistor device can be configured as an enhancement device or a depletion device. In an enhancement device, the body region 32 borders the gate dielectric 36. In a depletion device, there is a channel region with the same doping type as the source region 31 along the gate dielectric 32 between the source region 31 and the drift region 33. The transistor device can also be a MOSFET or an IGBT. In a MOSFET, the drain region 34 has the same doping type as the drift region 33 (which is more heavily doped).In an IGBT, the drain region 34 has a doping type that is complementary to the doping type of the drift region 33. The doping concentration of the semiconductor body 100 in the edge region 140 can correspond to the doping concentration of the drift region 33. The IGBT can be configured as an RC (reverse conducting) IGBT or as a conventional IGBT that is not reverse conducting.

[0052] Referring to Fig. Reference numeral 6 denotes 42 insulation regions that isolate the source electrode 31 from the gate electrode 35. The gate electrodes 35 are electrically connected to the gate terminal G in a region of the semiconductor body 100, which is located in Fig. 6 is outside the illustration. The gate electrodes 35 are shown in the embodiment according to Fig. 6 are configured as trench electrodes. That is, the gate electrodes 35 are arranged in trenches extending from the first surface 101 into the semiconductor body 100. However, this is only one example. The gate electrodes 35 could also be configured as planar electrodes above the first surface 101 of the semiconductor body (not shown).

[0053] In the transistor component according to Fig. 6. A pn ​​junction exists between the drift region 33 and the body regions 32 of the individual transistor cells. When the transistor device is switched off, that is, when the gate electrodes 35 are driven such that a conducting channel between the source regions 31 and the drift region 33 is interrupted, and when a voltage is applied between the drain and source terminals D, S, which reverse-polarizes the pn junction, a space charge region (depletion region) propagates in the drift region 33 starting at the pn junction. In an n-type MOSFET, a positive drain-source voltage (which is a voltage between the drain terminal D and the source terminal S) reverse-polarizes the pn junction, and in a p-type transistor, a negative drain-source voltage reverses the pn junction. Referring to Fig. 6 is the pn junction between the body region 32 and the drift regions 33, essentially parallel to the first surface 101 in the interior region 130, and terminates in a region between the interior region 130 and the boundary region 140. Thus, the space charge region in the interior region 130 extends essentially in the vertical direction of the semiconductor body 100 as the drain-source voltage increases, while in the boundary region 140, the space charge region propagates essentially in the horizontal direction of the semiconductor body 100 as the drain-source voltage increases. An equipotential line of the electric field associated with the space charge region is shown in Fig. 6 shown in dashed lines.

[0054] At the in Fig. In the embodiment shown in section 6, the edge closure structure comprises only one field ring 11. The field ring 11 surrounds the inner area 130 as shown in the illustration. Fig. 2. As explained above. However, the edge termination structure can be modified to have more than one field ring. Furthermore, the edge termination structure can include other conventional edge termination structures, such as a field stop in the area of ​​the edge surface, or similar features.

[0055] Fig. Figure 7 illustrates another embodiment of a transistor device. In this embodiment, each gate electrode 35 is adjacent to a body region 32 on one side of the trench gate electrode and adjacent to a floating semiconductor region 37, doped complementarily to the drift region 33, on the opposite side of the gate electrode 35. The complementary semiconductor regions 37 extend deeper into the semiconductor body than the trench gate electrodes 35 and protect the bottom regions of the trenches against high field strengths. In a region of the outer area 140 adjacent to the inner area 130, another semiconductor region 37', doped complementarily to the drift region 33, may be provided. This semiconductor region 37' may be connected to the source electrode 41.

[0056] As in the embodiment according to Fig.The edge termination structure with the field ring 11 surrounds the inner region 130 with the transistor cell 30 of the transistor device. The semiconductor region 37, 37' and the field ring 11 can have essentially the same doping concentration. According to one embodiment, the field ring 11 and the semiconductor regions 37, 37' are fabricated in a common process sequence.

Claims

[1] Semiconductor device comprising a semiconductor body (100) and an edge termination structure, wherein the edge termination structure comprises: a first oxide layer (211); a second oxide layer (212); a semiconductor mesa region (111) between the first oxide layer (211) and the second oxide layer (212); and a doped field region (11) having a first section (111) in the semiconductor mesa region (111) and a second section (112) in a region below the semiconductor mesa region (111), wherein the second section (112) overlaps the first and second oxide layers (211, 212) in a region below the semiconductor mesa region (111); an insulating layer (22) arranged above the first and second oxide layers (211, 212), which has an opening (23) above the semiconductor mesa region (111) and which partially covers the semiconductor mesa region (111); and a field electrode (12) which is located above the insulation layer (22), electrically connected to the doped field region (11) in the opening of the insulating layer (22), extends above the insulation layer (22) in a first lateral direction beyond the doped field area (11), and above the insulation layer (22) in a second lateral direction opposite to the first lateral direction above the doped field area (11). [2] Semiconductor device according to claim 1, wherein the semiconductor mesa area (111) has a first width (w1) which is at least 3 µm. [3] Semiconductor device according to claim 2, where the second section (112) of the field area (11) has a maximum second width (w2), and where the difference between the maximum second width (w2) and the first width (w1) is between 0.2 µm and 10 µm. [4] Semiconductor device according to claim 3, wherein the second section (112) of the field area (11) has the maximum second width (w2) at an interface of the second section (112) to the first and second oxide layers (211, 212). [5] Semiconductor device according to claim 3, wherein in a vertical direction of the semiconductor body (100) the width of the second section (112) increases with increasing distance to the first oxide layer (211) and the second oxide layer (212). [6] Semiconductor device according to any of the preceding claims, wherein the first oxide layer (211) and the second oxide layer (212) do not extend more than 150 nanometers beyond an upper surface (101) of the semiconductor mesa area (111). [7] Semiconductor device according to one of the preceding claims, wherein a depth (d1) of the first oxide layer (211) and the second oxide layer (212) in a vertical direction of the semiconductor body (100) is between 150 nanometers and 3 µm. [8] Semiconductor device according to one of the preceding claims, wherein the depth of the second section (112) of the field area (11) in a vertical direction of the semiconductor body (100) is between 5 µm and 10 µm. [9] Semiconductor device according to any one of the preceding claims, further comprising: several transistor cells (30), each comprising a source region (31), a body region (32) adjacent to the source region (31), a drift region (33) adjacent to the body region (32), and a gate electrode (35) arranged adjacent to the body region (32) and dielectrically insulated from the body region (32) by a gate dielectric (36); and a semiconductor region (37') doped in a complementary manner to the drift region (33), wherein the gate electrodes (35) are arranged in trenches extending from a first surface (101) of the semiconductor body (100) into the semiconductor body (100), wherein the semiconductor region (37') doped in a manner complementary to the drift region (33) borders the trench of one of the gate electrodes (35), is arranged between the trench and the doped field region (11), extends deeper into the semiconductor body (100) than the trench starting from the first surface (101), and overlaps a bottom of the trench. [10] Semiconductor device according to claim 9, further comprising: a source electrode (41), wherein the source regions (31) of the transistor cells and the semiconductor region (37') doped in a manner complementary to the drift region (33) are connected to the source electrode (41). [11] Method for producing an edge closure structure which has: Creating a first trench (1201) in a first surface (101) of a semiconductor body (100); Producing a second trench (1202) in the first surface (101) of the semiconductor body (100), wherein the second trench (1202) is spaced apart from the first trench (1201) such that a semiconductor mesa region (111) is present between the first trench (1201) and the second trench (1202); Forming a first oxide layer (211) in the first trench (1201) by oxidizing the semiconductor body (100) in areas adjacent to the first trench (1201); Producing a second oxide layer (212) in the second trench (1202) by oxidizing the semiconductor body (100) in regions adjacent to the second trench (1202), wherein the first oxide layer (211) and the second oxide layer (212) are produced such that at least a section of the semiconductor mesa region (111) remains between the first oxide layer (211) and the second oxide layer (212); Introducing dopant atoms into the semiconductor mesa region (111) and into a region below the semiconductor mesa region (111); and Producing a field electrode (12) that is electrically connected to the semiconductor measurement area (111), wherein the production of the field electrode (12) exhibits: Producing an insulating layer (22) which has an opening (23) above the semiconductor mesa region (111) and which covers the semiconductor mesa region (111) section by section; Creating the field electrode (12) in the opening (23) of the insulating layer (22) and above the insulating layer (22); and The field electrode is constructed such that the field electrode extends above the insulating layer (22) in a first lateral direction beyond the doped field region (11) and that the field electrode (12) terminates above the insulating layer (22) in a second lateral direction opposite to the first lateral direction above the doped field region (11). [12] Method according to claim 11, further comprising polishing the semiconductor body (100) in the area of ​​a first surface (101) after producing the first oxide layer (211) and the second oxide layer (212). [13] Method according to claim 11 or 12, wherein the production of the first oxide layer (211) and the production of the second oxide layer (212) comprise a common oxidation process. [14] Method according to any one of claims 11 to 13, in which the first oxide layer (211) is produced in the first trench (1201) such that the first oxide layer (211) substantially fills the first trench (1201) but does not substantially extend beyond the first surface (101), and in which the second oxide layer (212) is produced in the second trench (1202) such that the second oxide layer (212) substantially fills the second trench (1202) but does not substantially extend beyond the first surface (101). [15] Method according to any one of claims 11 to 14, wherein the introduction of the dopant atoms comprises at least one implantation and diffusion process. [16] Method according to any one of claims 11 to 15, wherein the introduction of the dopant atoms comprises: Fabricating a mask layer (200) having an opening above the semiconductor mesa region (111); and Introducing the dopant atoms through the opening in the mask layer into the semiconductor mesa region (111). [17] Method according to any one of claims 11 to 16, wherein the introduction of the dopant atoms involves temperature processes. [18] Method according to any one of claims 11 to 17, in which the semiconductor body (100) has an interior region (130) and in which the first trench (1201) and the second trench (1202) are produced such that the semiconductor mesa region (111) is ring-shaped and surrounds the inner region (130) in a horizontal plane of the semiconductor body (100).

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