Pixel clock signal generator, digital television with the same and method for generating the pixel clock signal

Abstract

A pixel clock generator comprising: a phase-locked loop (PLL) circuit (110) adapted to generate a multi-phase oscillation signal (MOUT1) having a second frequency from an oscillation signal (SIN_OSC) having a first frequency; and a frequency / phase adjustment circuit (120) adapted to synchronize the multi-phase oscillation signal (MOUT1) with a horizontal sync signal (HSYNC) to generate a first oscillation signal (MOUT2), frequency-divide the first oscillation signal (MOUT2) to generate a second oscillation signal, and adjust the phase of the second oscillation signal to generate the pixel clock signal (PCLK), wherein the frequency / phase adjustment circuit (120) includes a phase synchronization circuit (130) adapted to synchronize the multi-phase oscillation signal (MOUT1) with the horizontal sync signal (HSYNC) to generate the first oscillation signal (MOUT2), wherein the multi-phase oscillation signal (MOUT1) comprises a plurality of bit signals, and the phase synchronization circuit (130) comprises: a D-type flip-flop (132) adapted to sample the multiphase oscillation signal (MOUT1) in response to the horizontal sync signal (HSYNC); a decoder (134) adapted to decode output signals of the D-type flip-flop (132); and a multiplexer (136) adapted to select one bit signal from the plurality of bit signals of the multi-phase oscillation signal (MOUT1) based on the outputs of the decoder (134) to generate the first oscillation signal (MOUT2).

Description

Technical field

[0001] Devices, systems, methods, and articles in accordance with the inventive concept relate to a pixel clock generator, a television system, and a video system including the pixel clock generator. Description of the state of the art

[0002] A pixel clock generator is a circuit block used when a video signal is output to a screen in a digital television system. The pixel clock generator generates a clock signal that is used to convert an analog signal to a digital signal.

[0003] US 2005 / 0 162 552A1 discloses a video decoder with a digitally controlled oscillator (DCO). The DCO comprises a first on-the-fly frequency synthesis circuit that measures an input signal frequency, for example, the horizontal synchronizing frequency of an input video signal. In response to this input signal frequency, a frequency control word (FREQ) is generated and applied to a second on-the-fly frequency synthesis circuit, which in turn selects the appropriate phases for the leading and trailing edges of the output clock signal (PIX_CLK). The phase adjustment of the output clock signal (PIX_CLK) can be achieved using an alternative on-the-fly frequency synthesis circuit architecture in combination with a phase signal (PH) generated by a digital controller.Multiple phase-aligned sampling clocks (PIX_CLK_A, PIX_CLK_B, PIX_CLK_C) can be generated similarly from multiple on-the-fly adder frequency synthesis circuits, each controlled by the frequency control word (FREQ) and a corresponding phase signal (PHA, PHB, PHC). The video mode control logic can also be implemented using a similar DCO architecture. The DCO can be used outside the video decoder context to generate a clock signal with a frequency multiple of the input signal.

[0004] US 2009 / 0 128 692 A1 discloses a video signal processing apparatus capable of judging the feasibility of phase locking to a PLL circuit and automatically switching between the PLL circuit and a DLL circuit in accordance with the judgment to generate a sampling clock of an analog input video signal, the apparatus comprising an AD converter for AD converting an analog video signal and a clock signal generating circuit for supplying a clock signal to the AD converter.The clock signal generating circuit includes: a PLL circuit for generating a first clock signal based on a horizontal synchronizing signal obtained from the analog video signal; a DLL circuit for generating a second clock signal based on a composite synchronizing signal obtained from the analog video signal; and a clock selecting section for selecting and outputting either the first clock signal or the second clock signal based on the output of a PLL-specific phase comparator. SUMMARY

[0005] According to one aspect of an exemplary embodiment, a pixel clock generator is provided comprising a phase-locked loop circuit configured to generate, from an oscillation signal having a first frequency of several tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency / phase adjustment circuit for synchronizing the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-dividing the first oscillation signal to generate a second oscillation signal, and adjusting the phase of the second signal to generate a pixel clock signal.

[0006] The second oscillation signal may have a third frequency, and the third frequency may be suitable for controlling an analog-to-digital conversion in a digital television including the PLL circuit.

[0007] The third frequency can be in the range between 10 MHz and about 200 MHz.

[0008] The frequency / phase adjustment circuit may include a phase synchronization circuit and a delay control circuit.

[0009] The phase synchronization circuit may synchronize the multi-phase oscillation signal with the horizontal sync signal to generate a first oscillation signal, and the delay control circuit may frequency-divide the first oscillation signal to generate the second oscillation signal and adjust the phase of the second oscillation signal to generate the pixel clock signal.

[0010] The pixel clock generator may select a bit having a phase closest to the horizontal sync signal from the set of bits of the multi-phase oscillation signal to synchronize the multi-phase oscillation signal with the horizontal sync signal.

[0011] The multi-phase oscillation signal may include a plurality of bit signals, and the phase synchronization circuit may include a D-type flip-flop adapted to sample the multi-phase oscillation signal in response to the horizontal sync signal, a decoder adapted to decode an output signal of the D-type flip-flop, and a multiplexer adapted to select a bit signal from the plurality of bit signals output from the decoder to generate the first oscillation signal.

[0012] The delay control circuit may include a plurality of unit delay control circuits connected in cascade, each of the unit delay control circuits including a D-type flip-flop having a clock terminal to which an input signal is connected and a reset latch terminal to which the horizontal sync signal is connected, the input terminal and an inverted output terminal being electrically connected to each other; and an exclusive-OR gate having a first input terminal electrically connected to the inverted output terminal of the D-type flip-flop, a second input terminal to which a bit of a phase control signal is connected, and an output terminal at which an output signal of the unit delay control circuit is generated.

[0013] Each unit delay control circuit can frequency divide the input signal of the unit delay control circuit by two to generate the output signal of the unit delay control circuit.

[0014] When the horizontal sync signal is activated, all output signals of the unit delay control circuit have the logic level “1”.

[0015] The PLL circuit does not require an off-chip capacitor.

[0016] The pixel clock generator may also include a sync slicer adapted to generate a horizontal sync signal (HSYNC) using an analog video signal.

[0017] According to another aspect of an exemplary embodiment, a pixel clock generator is provided that includes a phase-locked loop (PLL) circuit configured to generate a multi-phase oscillation signal having a second frequency from an oscillation signal having a first frequency; a phase synchronization circuit configured to synchronize the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal; and a delay control circuit configured to frequency-divide the first oscillation signal to generate a second oscillation signal and to adjust the phase of the second oscillation signal to generate a pixel clock signal.

[0018] The first frequency can range from 10 MHz to 90 MHz and the second frequency can range from 10 GHz to 90 GHz.

[0019] The delay control circuit may receive a phase control signal, and bits of the phase control signal may be applied to adjust an initial condition of the delay control signal.

[0020] The time between a first cycle and a second cycle of the pixel clock signal can be changed according to the initial condition of the delay control circuit.

[0021] The delay control circuit may receive a phase control signal, and bits of the phase control signal may be applied to adjust a delay time of the pixel clock signal.

[0022] The delay control circuit may receive a phase control signal, and bits of the phase control signal may be applied to adjust the phase of the pixel clock signal.

[0023] The PLL circuit can have a wide bandwidth.

[0024] According to another aspect of an exemplary embodiment, a digital television is provided, comprising a pixel clock generator configured to generate a pixel clock signal; and an image signal processor configured to perform analog / digital (A / D) conversion and frequency conversion of an image signal in response to the pixel clock signal, wherein the pixel clock generator includes a phase lock loop (PLL) configured to generate, from an oscillation signal having a first frequency of several tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz;and a frequency / phase adjustment circuit configured to synchronize the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency divide the first oscillation signal to generate a second oscillation signal, and adjust the phase of the second oscillation signal to generate a pixel clock signal;

[0025] According to another aspect of an exemplary embodiment, a method is provided for generating a pixel clock signal when outputting a video signal on a display, the method comprising generating an oscillation signal having a first frequency of several tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; synchronizing the multi-phase oscillation signal with a horizontal sync signal (HSYNC) to generate a first oscillation signal; frequency-dividing the first oscillation signal to generate a second oscillation signal; and adjusting the phase of a second oscillation signal to generate the pixel clock signal.

[0026] Adjusting the phase of the second oscillation signal to generate the pixel clock signal may comprise receiving a phase control signal and applying bits of a phase control signal to adjust an initial condition of the delay control circuit.

[0027] The invention is defined in the appended independent claims. Further developments of the invention are specified in the dependent claims. SHORT DESCRIPTION OF THE CHARACTERS

[0028] The foregoing and / or other aspects will become more apparent from the more detailed description of exemplary embodiments illustrated in the following figures, in which like reference characters refer to the same parts throughout the several views. The figures are not necessarily drawn to scale, but are intended essentially to illustrate the principles of the inventive concepts. In the figures: Fig. 1 is a block diagram illustrating a pixel clock generator according to an exemplary embodiment; Fig. 2 is a circuit diagram showing an example of a phase-locked loop (PLL) circuit as used in a pixel clock generator according to Fig. 1; Fig. 3 is a circuit diagram showing an example of a phase synchronization circuit as used in a pixel clock generator of Fig. 1; Fig. 4 is a circuit diagram showing an example of a delay control circuit as used in a pixel clock generator of Fig. 1; Fig. 5 is a diagram showing an example of a process for synchronizing a multi-phase oscillation signal generated by a PLL circuit Fig. 2 with a horizontal sync signal; Fig. 6 a simplified circuit diagram of a delay control circuit from Fig. 4; Fig. 7 is a timing diagram showing the operation of the delay control circuit of Fig. 6 represents; Fig. 8 is a diagram illustrating an example of a process for generating a pixel clock signal using a multi-phase oscillation signal according to an exemplary embodiment; Fig. 9 is a diagram showing a phase change of a pixel clock signal according to a phase control signal in the delay control signal of Fig. 4 represents; Fig. 10 is a block diagram illustrating a pixel clock generator according to another exemplary embodiment; Fig. 11 is a flowchart illustrating a method for generating a pixel clock signal according to an exemplary embodiment; and Fig. 12 is a block diagram illustrating a digital television with a pixel clock generator according to example embodiments. DETAILED DESCRIPTION

[0029] Various exemplary embodiments will now be described in more detail with reference to the accompanying figures, in which some exemplary embodiments are illustrated. However, the inventive concepts may be embodied in other ways and are not limited to the exemplary embodiments described below. Rather, these exemplary embodiments are provided to thoroughly and completely illustrate the invention in order to fully convey the inventive concept to those skilled in the art. For clarity, the sizes and relative sizes of layers and regions in the figures may be exaggerated.

[0030] It is to be understood that when an element or layer is described as being "on", "connected to", or "coupled to" another element or layer, it may be directly on, connected to, or coupled to another element or layer, or there may be intermediate elements or layers. In contrast, if an element is described as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intermediate elements or layers. Like reference numerals always refer to like elements. The term "and / or" as used below includes any and all combinations of one or more of the appropriately listed parts.

[0031] It is to be understood that although the terms "first," "second," "third," etc., are used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections are not limited to these terms. These terms are merely used to distinguish one element, region, component, layer, and / or section from another region, layer, or section. That is, a "first" element, component, region, layer, or section, as referred to below, may also be referred to as a "second" element, component, region, layer, or section without departing from the teachings of the present inventive concept.

[0032] The terms used below serve to describe certain exemplary embodiments and are not intended to be limiting of the present inventive concept. The singular forms "a," "an," and "the" as used below are intended to include the plural forms as well, unless the context dictates otherwise. It is also to be understood that the terms "comprises" and / or "comprising," when used in this description, describe the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the general meaning as understood by one skilled in the art to which the inventive concept pertains. It is also understood that terms used in commonly used dictionaries are to be interpreted as they may be understood in the context of the prior art and are not to be idealized or understood in an overly formal sense unless expressly defined below.

[0034] Fig. 1 shows a block diagram illustrating a pixel clock generator according to an exemplary embodiment.

[0035] Referring to Fig. 1, the pixel clock generator 100 includes a phase-locked loop (PLL) circuit 110 and a frequency / phase adjustment circuit 120.

[0036] The PLL circuit 110 generates a multi-phase oscillation signal MOUT1 with a second frequency on the order of several gigahertz (GHz) from an oscillating input signal SIN_OSC with a first frequency on the order of several tens of megahertz (MHz). For example, the oscillating input signal SIN_OSC may have a first frequency of approximately 10 MHz to approximately 90 MHz, and the multi-phase oscillation signal MOUT1 may have a second frequency of approximately 1 GHz to approximately 9 GHz. Alternatively, the second frequency may also be in the order of tens of gigahertz, for example, from 10 GHz to 90 GHz. The PLL circuit 110 uses the first frequency to generate the second frequency.The frequency / phase adjustment circuit 120 synchronizes the multi-phase oscillation signal MOUT1 with a horizontal sync signal HSYNC to generate a first oscillation signal MOUT2, frequency-divides the first output signal MOUT2 to generate a second output signal having a third frequency, and adjusts the phase of the second oscillation signal to generate a pixel clock signal PCLK. The oscillating input signal SIN_OSC may have a frequency higher than a frequency of the horizontal sync signal (HSYNC).

[0037] The frequency / phase adjustment circuit 120 may include a phase synchronization circuit 130 (PHASE SYNC) and a delay control circuit 150. The phase synchronization circuit 130 synchronizes the multi-phase oscillation signal MOUT1 with the horizontal sync signal HSYNC to generate the first oscillation signal MOUT2. The delay control circuit 150 frequency-divides the first oscillation signal MOUT2 to generate the second oscillation signal and adjusts the phase of the second oscillation signal to generate the pixel clock signal PCLK. In the exemplary embodiment of Fig. 1, the multi-phase oscillation signal MOUT1 is a 16-bit signal. However, this is an example, and the number of bits of the multi-phase oscillation signal MOUT1 can also be greater or less than 16 bits.

[0038] The third frequency may be a frequency suitable for controlling an analog-to-digital conversion in a digital TV that includes the PLL circuit. For example, the third frequency may be in a range from approximately 10 MHz to approximately 200 MHz.

[0039] In a prior-art pixel clock generator, a PLL circuit generates an output signal at several tens or hundreds of MHz using a horizontal sync signal (HSYNC) with a low frequency of tens of kHz. Therefore, the corresponding prior-art pixel clock generator required a large-capacitance off-chip capacitor in the PLL circuit. Furthermore, the bandwidth of the prior-art PLL circuit is typically defined as one-tenth (1 / 10) of the input frequency. Therefore, in a prior-art PLL circuit in which HSYNC has a frequency range of 10-100 kHz, the bandwidth is very narrow.

[0040] In contrast, in the pixel clock generator 100, Fig. 1, the PLL circuit 110 generates a multi-phase oscillation signal MOUT1 with a frequency of several GHz using an oscillating input signal SIN_OSC with a frequency of several tens of MHz. The pixel clock generator 100 according to an exemplary embodiment includes a PLL circuit 110 with a wide bandwidth without the need for an off-chip capacitor. That is, the term "wide" used in the following description with respect to bandwidth refers to a frequency greater than one-tenth of a frequency of a prior art HSYNC. For example, the PLL circuit 110 may have a high-frequency input signal on the order of, for example, 24 MHz, and therefore the bandwidth of the PLL circuit 110 is approximately 2.4 MHz, which is much wider than the bandwidth of a prior art PLL circuit. In addition, the pixel clock generator 100 may be made of Fig. 1, a delay control circuit 150 with a simple circuit structure can be used to adjust the phase of the output signal of the PLL circuit 110. The delay control circuit 150 is a type of frequency divider and can perform a frequency dividing task and a delay adjusting task.

[0041] Fig. 2 shows a circuit diagram of an example of a phase-locked loop (PLL) circuit in a pixel clock generator of Fig. 1.

[0042] Referring to Fig. 2, the PLL circuit 110 comprises a phase / frequency detector (PFD) 112, a charge pump 114, a loop filter 115, a voltage-controlled oscillator (VCO) 116, and a frequency divider 118.

[0043] The PFD 112 generates an up signal UP and a down signal DN based on a phase difference and a frequency difference between an oscillating input signal SIN_OSC and a feedback signal SFEED. The charge pump 114 generates a charging current and a discharging current according to the up signal UP and the down signal DN. The loop filter 115 uses a charging current and a discharging current as they occur in the charge pump 114. The loop filter 115 may include a series-connected resistor R and a capacitor C. An oscillating control voltage applied to the VCO 116 may be an integrated value of the output current of the charge pump 114. The VCO 116 generates the multi-phase oscillation signal MOUT1, the frequency of which is changed according to a magnitude of the oscillating control voltage. The frequency divider 118 divides the frequency of the multi-phase oscillation signal MOUT1 according to a certain value.

[0044] As described above, the PLL circuit 110 can generate a multi-phase oscillation signal MOUT1 having a second frequency of several GHz using an oscillating input signal SIN_OSC having a first frequency of several tens of MHz.

[0045] Fig. 3 is a circuit diagram showing an example of a phase synchronization circuit used in the pixel clock generator 100 of Fig. 1 is included.

[0046] Referring to Fig. 3, the phase synchronization circuit 130 includes a D-type flip-flop 132 adapted to sample the multi-phase oscillation signal MOUT1 in response to the horizontal sync signal HSYNC, a decoder 134 adapted to decode an output signal of the D-type flip-flop 132, and a multiplexer 136 adapted to select the multi-phase oscillation signal MOUT1 to generate the first oscillation signal MOUT2 in response to the output signal of the decoder 134.

[0047] In the example from Fig. 3, the multi-phase oscillation signal MOUT1 may be a 16-bit signal, and the decoder 134 may decode the 16-bit signal to generate a 4-bit signal. However, this is only an example, and the number of bits of the multi-phase oscillation signal MOUT1 may be greater than or less than 16 bits, and the number of bits of the signal output from the decoder may be greater than or less than 4 bits. The multiplexer 136 selects at least one bit from the signal output of the decoder 134 as the first oscillation signal MOUT2.

[0048] Fig. 4 is a circuit diagram showing an example of a delay control circuit used in the pixel clock generator of Fig. 1 is included.

[0049] The delay control circuit may include a plurality of unit delay control circuits. Referring to Fig. 4, for example, the delay control circuit 150 may include a first D-type flip-flop 151, a first exclusive-OR gate (XOR gate) 155, a second D-type flip-flop 152, a second exclusive-OR gate 156, a third D-type flip-flop 153, a third exclusive-OR gate 157, a fourth D-type flip-flop 154, and a fourth exclusive-OR gate 158. In this case, each unit delay control circuit includes one of the D-type flip-flops and one of the exclusive-OR gates. For example, the first unit delay control circuit may include the first D-type flip-flop 151 and the first XOR gate 157, and a second unit delay control circuit may include the second D-type flip-flop 152 and the second XOR gate 156, etc.

[0050] The first D-type flip-flop 151 has a clock terminal CK to which the first oscillation signal MOUT2 is connected, and a reset latch terminal RB to which the horizontal sync signal HSYNC is connected. An input terminal D and an inverted output terminal QB of the first D-type flip-flop 151 are electrically connected to each other. The first exclusive-OR gate 155 has a first input terminal connected to the inverted output terminal QB of the first D-type flip-flop 151, and a second input terminal to which a first bit CON_PH is connected. <0> of the phase control signal. The second D-type flip-flop 152 has a clock terminal CK to which an output signal of the first exclusive-OR gate 155 is connected, and a reset latch terminal RB to which the horizontal sync signal HSYNC is connected. An input terminal D and an inverted output terminal QB of the second D-type flip-flop 152 are electrically connected to each other.The second exclusive-OR gate 156 has a first input terminal connected to the inverted output terminal QB of the second D-type flip-flop 152, and a second input terminal to which a second bit CON_PH <1> of the phase control signal. The third D-type flip-flop 153 has a clock terminal CK to which an output signal of the second exclusive-OR gate 156 is connected, and a reset latch terminal RB to which the horizontal sync signal HSYNC is connected. An input terminal D and an inverted output terminal QB of the third D-type flip-flop 153 are electrically connected. The third exclusive-OR gate 157 has a first input terminal connected to the inverted output terminal QB of the third D-type flip-flop 153, and a second input terminal to which a third bit CON_PH <2> of the phase control signal.The fourth D-type flip-flop 154 has a clock terminal CK to which an output signal of the third exclusive-OR gate 157 is connected, and a reset latch terminal RB to which the horizontal sync signal HSYNC is connected. An input terminal D and an inverted output terminal QB of the fourth D-type flip-flop 154 are electrically connected. The fourth exclusive-OR gate 158 has a first input terminal connected to the inverted output terminal QB of the fourth D-type flip-flop 154, a second input terminal to which a fourth bit CON_PH <3> of the phase control signal, and an output terminal from which the pixel clock signal PCLK is output.

[0051] Fig. Fig. 5 is a diagram showing an example of a process for synchronizing a multi-phase oscillation signal output from the PLL circuit Fig. 1 is output with the horizontal sync signal.

[0052] Referring to Fig. 5, the bits of the multi-phase oscillation signal MOUT1 may have consecutive values of a logic level "1" or "0". The multi-phase oscillation signal MOUT1 may be synchronized with the horizontal sync signal HSYNC by selecting one bit from the number of bits of the multi-phase oscillation signal MOUT1 with a phase closest to a rising edge of the horizontal sync signal HSYNC. According to the exemplary embodiment of Fig. 5 can MOUT1 <0> to MOUT1 <8> from the number of bits of the multi-phase control signal MOUT1 a value “1” and MOUT1 <9> to MOUT1 <15> have a value of “0” when the horizontal sync signal HSYNC is sampled. That is, as in Fig. 5, at a time when the horizontal sync signal HSYNC changes from low to high, MOUT1 <0> to MOUT1 <8> a value of “1” and MOUT1 <9> to MOUT1 <15> have a value of "0". The rising edge of MOUT1 <9> is closest to the rising edge of the horizontal sync signal HSYNC. This means in Fig. 5, a time difference A is greater than a time difference B. Therefore, MOUT1 <9> the first oscillation signal MOUT2 output from the phase synchronization circuit 130.

[0053] Fig. 6 shows a simplified circuit diagram of the delay control circuit of Fig. 4. The simplified delay control circuit 150a corresponds to the circuit diagram of Fig. 4 where the Exclusive-OR (XOR) gates in Fig. 4 were omitted. Fig. 7 shows a timing diagram of an example of the operation of a delay control circuit according to Fig. 6.

[0054] Referring to the simplified delay circuit 150a, an input signal can be applied to a clock terminal CK, if an input terminal D and an inverted output terminal QB of a D-type flip-flop are electrically connected to each other, and an output signal is output from the inverted output terminal QB, then the D-type flip-flop divides the frequency of the input signal by two.

[0055] For example, when the horizontal sync signal HSYNC is enabled, all output voltages V1 to V4 of the D-type flip-flops 151 to 154 have logic levels "1." When the first oscillation signal MOUT2 is 4 GHz, the output voltage V1 of the first D-type flip-flop 151 may have a frequency of 2 GHz, the output voltage V2 of the second D-type flip-flop 152 may have a frequency of 1 GHz, the output voltage V3 of the third D-type flip-flop 153 may have a frequency of 500 MHz, and the output voltage V4 of the fourth D-type flip-flop 154 may have a frequency of 250 MHz. That is, the frequency of the pixel clock signal PCLK may be 250 MHz.

[0056] Referring to Fig. 7 shows examples of the bits for V4, V3, V2 and V1 and can have values from 1111 (2) at t1, values of 1110 (2) at t2, values of 1000 (2) at t3, and values of 0000 (2) at t4. Here, (2)that the number is represented with base 2; ie 1110 (2) means that V4 is binary “1”, V3 is binary “1”, V2 is binary “1” and V1 is binary “0”.

[0057] When reset by the horizontal sync signal HSYNC, in the delay control circuit 150a from Fig. 6, in which the XOR gates were omitted, the output voltages V1 to V4 of the D-type flip-flops 151 to 154 are reset to the logic level "1". In the delay control circuit 150 of Fig. 4, which includes the D-type flip-flops 151 to 154 and XOR gates 155 to 158, an initial condition of the D-type flip-flops 151 to 154 can be set. For example, initial values of the output voltages V1 to V4 of the D-type flip-flops 151 to 154 can be set according to the values of the bits CON_PH <0> to CON_PH <3> of the phase control signal applied to the corresponding XOR gates 155 to 158.

[0058] Referring again to Fig. 4, assumed that the initial values of the output voltages V1 to V4 of the D-type flip-flop 151 to 154 values of 0110 (2) The time to change the initial values from 0110 (2) to 0000 (2) may be shorter than the time to change 1111 (2) to 0000 (2) That is, a delay time between the generation of a first cycle of a pixel clock signal and the generation of a second cycle of a pixel clock signal may be different.

[0059] The Fig. 1 can determine the initial values of the output voltages V1 to V4 of the D-type flip-flops 151 to 154 by controlling the corresponding bits CON_PH <0> to CON_PH <3> of the phase control signal applied to the delay control circuit 150. As such, the delay time of the pixel clock signal PCLK can be adjusted. The phase of the pixel clock signal PCLK can be adjusted by controlling the bits CON_PH <0> to CON_PH <3> of the phase control signal applied to the delay control circuit 150.

[0060] In a prior art pixel clock generator, a delay-locked loop (DLL) circuit should be included to adjust the delay time of the pixel clock of the PCLK. In contrast, in the exemplary embodiments described above, the pixel clock generator 100 controls the phase of the pixel clock signal PCLK without using a DLL circuit.

[0061] Fig. 8 is a diagram illustrating an example of a process for generating a pixel clock signal using a multi-phase oscillation signal according to an exemplary embodiment.

[0062] Referring to Fig. 8, the horizontal sync signal HSYNC is generated based on an analog video signal, and one of the bits of the multi-phase oscillation signal MOUT1 is selected using the horizontal sync signal HSYNC from the PLL circuit 110. The pixel clock signal PCLK is generated in response to the selected bit of the multi-phase oscillation signal MOUT1. Fig. 8, PER_HSY represents the period of a horizontal sync signal HSYNC, SS represents a selected bit of a multi-phase oscillation signal MOUT1, and 11 represents bits of the multi-phase oscillation signal MOUT1. Fig. For illustration purposes, 8 bits of the 16 bits of the multi-phase oscillation signal MOUT1 are shown in Figure 8.

[0063] Fig. 9 is a diagram showing a phase change of a pixel clock signal according to a phase control signal in the delay control signal of Fig. 4 represents.

[0064] Referring to Fig. 9, the phase or delay time of the output signal, which is the pixel clock signal, can be changed according to the values of the phase control signal CON_PH.

[0065] Fig. 10 is a block diagram illustrating a pixel clock generator according to another embodiment.

[0066] Referring to Fig. 10, the pixel clock generator 200 includes a phase-locked loop (PLL) circuit 110, a frequency / phase adjustment circuit 120, and a sync slicer 170. The sync slicer 170 generates a horizontal sync signal (HSYNC) using an analog video signal. The pixel clock generator 200 of Fig. 10 has a similar structure to the pixel clock generator 100 from Fig. 1 except for the Sync Slicer 170, and works similarly to the Fig. 1.

[0067] Fig. 11 shows a flowchart illustrating a method for generating a pixel clock according to an exemplary embodiment.

[0068] Referring to Fig. 11, a multi-phase oscillation signal having a second frequency of several gigahertz (GHz) is generated from an oscillation signal having a first frequency of several tens of megahertz (MHz) (step S1). The multi-phase oscillation signal is synchronized with a horizontal sync signal (HSYNC) to generate a first oscillation signal (step S2). The first oscillation signal is frequency-divided to generate a second oscillation signal having a third frequency (step S3), and a phase of the second oscillation signal is adjusted to generate a pixel clock signal (step S4).

[0069] In the method for generating a pixel clock signal from Fig. 11, the third frequency is suitable for controlling the analog-to-digital conversion in a digital television including a PLL circuit. Furthermore, the method for adjusting a phase of the second oscillation signal for generating the pixel clock signal may include controlling bits of the phase control signal to adjust initial conditions of a delay control circuit.

[0070] Fig. 12 shows a block diagram of a digital television with a pixel clock generator according to example embodiments.

[0071] Referring to Fig.12, a digital television 1000 includes a digital block 1100 and an analog block 1200. The digital block 1100 tunes and demodulates a digital broadcast channel, separates the demodulated signal into video / audio / data, decodes the video / audio / data in MPEG mode, and outputs an image signal DRGB / DCVBS and an audio signal DRL in analog form. The analog block 1200 divides an analog broadcast signal and a digital broadcast signal from a fundamental wave radio frequency signal, and tunes and demodulates an analog channel of an analog broadcast signal, or demodulates an external video signal. Furthermore, the analog block 1200 receives the image signal DRGB / DCVBS and the audio signal DRL from the digital block 1100, displays an image signal on the screen (CPT), and outputs an audio signal to a speaker.

[0072] The digital block 1100 may include a front-end 1110, a central processing unit (CPU) 1120, and an MPEG / GRAPHIC processor 1130. The front-end 1110 acquires a digital channel of the analog transmission signal split by the analog block 1200, demodulates the acquired signal, and outputs the signal as a transport stream TS. The CPU 1120 performs demultiplexing on the transport stream TS to divide the transport stream TS into video / audio / data, and receives a remote control signal from the analog block 1200 and sends the remote control signal to the MPEG / GRAPHIC processor 1130. In some example embodiments, the CPU 1120 processes the remote control signal before sending the remote control signal to the MPEG / GRAPHIC processor 1130. The MPEG / GRAPHIC processor 1130 decodes the video / audio / data into an MPEG mode and outputs the image signal DRGB / DCVBS and the audio signal DRL in analog form to the analog block 1200.In addition, in a user interface mode (User Interface UI mode), the MPEG / GRAPHIC processor 1130 processes the remote control signal from the analog block 1200 and outputs the UI by loading the UI into the DRGB / DCVBS image signal.

[0073] The analog block 1200 includes an RF splitter 1210, an analog tuner 1220, a video signal processor 1230, a pixel clock generator 1235, a microcomputer (MICOM) 1240, an external input 1250, an audio signal processor 1260, and an amplifier 1270.

[0074] The RF splitter 1210 splits the analog transmission signal and the digital transmission signal from a fundamental wave radio frequency signal. The analog tuner 1220 captures an analog channel of the analog transmission signal separated by the RF splitter 1210 and demodulates the captured signal to output an image signal ACVBS and an audio signal ARL. The external input 1250 demodulates an external video signal to output an image signal AVCVBS and an audio signal AVRL. The video signal processor 1230 performs video processing on the image signal ACVBS of the analog tuner 1220, the image signal AVCVBS of the external input 1250, and / or the image signal DRGB / DCVBS received from the digital block 1100 to display an image on the screen CPT. The video signal processor 1230 includes an analog-to-digital (A / D) converter 1232. The pixel clock generator 1235 may include the pixel clock generator according to example embodiments.The audio signal processor 1260 processes audio signals according to the audio signal ARL of the analog tuner 1220, the audio signal AVRL of the external input unit 1250, and / or the audio signal DRL received from the digital block 1100. The amplifier 1270 amplifies an output signal of the audio signal processor 1260 and outputs an audio signal to a speaker. The microcomputer (MICOM) 1240 receives an input signal from a remote control and outputs a remote control signal for a UI display in a digital reception mode to the CPU 1120 of the digital block 1100, and outputs an output signal OSDRGB for the UI to the video signal processing unit 1230 in an analog reception mode.

[0075] The pixel clock generator used in a digital television is mainly described above, but the pixel clock generator according to the exemplary embodiments can also be used in an image signal processing system including a digital television.

[0076] Exemplary embodiments of the inventive concept relate to a pixel clock generator, and / or a television system and / or a video system with a pixel clock generator.

[0077] The pixel clock generator according to exemplary embodiments generates a high-frequency signal using an oscillation signal having a frequency of several tens of MHz, which is higher than a frequency of the horizontal sync signal (HSYNC), and adjusts a phase of the high-frequency signal to generate a pixel clock signal. Therefore, the pixel clock generator does not require an off-chip capacitor. Furthermore, the pixel clock generator according to the exemplary embodiment has a simple circuit configuration, a small chip size, low power consumption, and low flicker noise because the pixel clock generator adjusts the phase of a pixel clock signal using a frequency / phase adjustment circuit including D-type flip-flops and exclusive OR gates connected to the D-type flip-flops.

[0078] The foregoing is illustrative of exemplary embodiments and is not intended to be limiting. Although some exemplary embodiments have been described, it will be apparent to those skilled in the art that many modifications to the exemplary embodiments are possible without materially departing from the scope of the invention as defined by the claims.

Claims

[1] A pixel clock generator comprising: a phase-locked loop (PLL) circuit (110) adapted to generate a multi-phase oscillation signal (MOUT1) having a second frequency from an oscillation signal (SIN_OSC) having a first frequency; and a frequency / phase adjustment circuit (120) adapted to synchronize the multi-phase oscillation signal (MOUT1) with a horizontal sync signal (HSYNC) to generate a first oscillation signal (MOUT2), frequency-divide the first oscillation signal (MOUT2) to generate a second oscillation signal, and adjust the phase of the second oscillation signal to generate the pixel clock signal (PCLK), wherein the frequency / phase adjustment circuit (120) includes a phase synchronization circuit (130) adapted to synchronize the multi-phase oscillation signal (MOUT1) with the horizontal sync signal (HSYNC) to generate the first oscillation signal (MOUT2), wherein the multi-phase oscillation signal (MOUT1) comprises a plurality of bit signals, and the phase synchronization circuit (130) comprises: a D-type flip-flop (132) adapted to sample the multiphase oscillation signal (MOUT1) in response to the horizontal sync signal (HSYNC); a decoder (134) adapted to decode output signals of the D-type flip-flop (132); and a multiplexer (136) adapted to select one bit signal from the plurality of bit signals of the multi-phase oscillation signal (MOUT1) based on the outputs of the decoder (134) to generate the first oscillation signal (MOUT2). [2] The pixel clock generator of claim 1, wherein the second oscillation signal has a third frequency, and the third frequency corresponds to a frequency suitable for controlling an analog-to-digital conversion in a digital television having the PLL circuit (110). [3] The pixel clock generator of claim 1 or 2, wherein the third frequency is in a range of about 10 MHz to about 200 MHz. [4] A pixel clock generator according to any one of claims 1 to 3, wherein the frequency / phase adjustment circuit further comprises: a delay control circuit (150; 150a) adapted to frequency-divide the first oscillation signal (MOUT2) to generate the second oscillation signal and to adjust the phase of the second oscillation signal to generate the pixel clock signal (PCLK). [5] A pixel clock generator according to claim 4, wherein one bit from a plurality of bits of the multi-phase oscillation signal (MOUT1) having a phase closest to the horizontal sync signal (HSYNC) is selected to synchronize the multi-phase oscillation signal (MOUT1) with the horizontal sync signal (HSYNC). [6] A pixel clock generator according to claim 4, wherein the delay control circuit (150) comprises a plurality of unit delay control circuits connected in cascade, each of the unit delay control circuits comprising: a D-type flip-flop (151 to 154) having a clock terminal (CK) to which an input signal is applied and a reset latch terminal (RB) to which the horizontal sync signal (HSYNC) is applied, wherein an input terminal (D) and an inverted output terminal (QB) of the D-type flip-flop (151 to 154) are electrically connected to each other; and an exclusive-OR gate (155-158) having a first input terminal electrically connected to the inverted output terminal (QB) of the D-type flip-flop (151 to 154), a second input terminal to which a bit of the phase control signal (CON_PH <0> -CON_PH <3> ) and an output terminal from which an output signal of the unit delay control circuit is generated. [7] A pixel clock generator according to claim 6, wherein each unit delay control circuit is adapted to frequency-divide the input signal of the unit delay control circuit by two to generate the output signal of the unit delay control circuit. [8] A pixel clock generator according to claim 6, wherein all of said unit delay control circuits are adapted to output said output signal having a logic level "1" when said horizontal sync signal (HSYNC) is activated. [9] A pixel clock generator according to claim 4, wherein the delay control circuit (150) comprises: a first D-type flip-flop (151) having a clock signal terminal (CK) to which the first control signal (MOUT2) is applied and a reset latch terminal (RB) to which the horizontal sync signal (HSYNC) is applied, wherein an input terminal (D) and an inverted output terminal (QB) of the first D-type flip-flop (151) are electrically connected to each other; a first exclusive OR gate (155) having a first input terminal connected to the inverted output terminal (QB) of the first D-type flip-flop (151) and a second input terminal to which a first bit of a phase control signal (CON_PH <0> ) is created; a second D-type flip-flop (152) having a clock terminal (CK) to which an output signal of the first exclusive-OR gate (145) is applied, and a reset latch terminal (RB) to which the horizontal sync signal (HSYNC) is applied, wherein an input terminal (D) and an inverted output terminal (QB) of the second D-type flip-flop (152) are electrically connected to each other; a second exclusive-OR gate (156) having a first input terminal connected to the inverted output terminal (QB) of the second D-type flip-flop (152) and a second input terminal to which a second bit of the phase control signal (CON_PH <1> ) is created; a third D-type flip-flop (153) having a clock terminal (CK) to which an output signal of the second exclusive-OR gate (156) is applied and a reset latch terminal (RB) to which a horizontal sync signal (HSYNC) is applied, wherein an input terminal (D) and an inverted output terminal (QB) of the third D-type flip-flop (153) are electrically connected to each other; a third exclusive OR gate having a first input terminal connected to the inverted output terminal (QB) of the third D-type flip-flop (153) and a second input terminal to which a third bit of the phase control signal (CON_PH_ <2> ) is created; a fourth D-type flip-flop (154) having a clock terminal (CK) to which an output signal of the third exclusive-OR gate (157) is applied, and having a reset latch terminal (RB) to which a horizontal sync signal (HSYNC) is applied, wherein an input terminal (D) and an inverted output terminal (QB) of the fourth D-type flip-flop (154) are electrically connected to each other; and a fourth exclusive-OR gate (158) having a first input terminal connected to the inverted output terminal (QB) of the fourth D-type flip-flop (154), a second input terminal to which a fourth bit of the phase control signal (CON_PH <3> ) and an output terminal from which the pixel clock signal (PCLK) is output. [10] A pixel clock generator according to any one of claims 1 to 9, wherein the PLL circuit (110) does not include an off-chip capacitor. [11] Pixel clock generator according to one of claims 1 to 10, further comprising: a sync slicer (170) adapted to generate the horizontal sync signal (HSYNC) using an analog video signal. [12] A pixel clock generator according to any one of claims 1 to 11, wherein the first frequency is several tens of MHz and the second frequency is several GHz. [13] A pixel clock generator according to claim 4, wherein a phase control signal (CON_PH) is received from the delay control circuit (150) and bits of the phase control signal (CON_PH <0> to CON_PH <3> ) to set an initial condition of the delay control circuit (150). [14] A pixel clock generator according to claim 13, wherein the time between a first cycle and a second cycle of the pixel clock signal (PCLK) is changed according to an initial condition of the delay control circuit (150). [15] Pixel clock generator according to claim 4, wherein a phase control signal (CON_PH) is received from the delay control circuit and bits of the phase control signal (CON_PH <0> to CON_PH <3> to set a delay time of the pixel clock signal (PCLK). [16] Pixel clock generator according to claim 4, wherein a phase control signal (CON_PH) is received from the delay control circuit (150), and bits of the phase control signal (CON_PH <0> to CON_PH <3> ) to adjust a phase of the pixel clock signal (PCLK). [17] A pixel clock generator according to claim 4, wherein the PLL circuit has a wide bandwidth. [18] A digital television comprising: a pixel clock generator (100; 200) according to one of claims 1 to 17; and a video signal processor (1230) adapted to perform analog / digital (A / D) conversion and frequency conversion on an image signal in response to the pixel clock signal (PCLK). [19] A method for generating a pixel clock signal (PCLK) used to output a video signal on a display screen (CPT), comprising: Generating a multi-phase oscillation signal (MOUT1) with a second frequency of several GHz from an oscillation signal (SIN_OSC) with a first frequency of several tens of MHz; Synchronizing the multi-phase oscillation signal (MOUT1) with a horizontal sync signal (HSYNC) to generate a first oscillation signal (MOUT2); Frequency dividing the first oscillation signal (MOUT2) to generate a second oscillation signal; and Adjusting a phase of the second oscillation signal to generate the pixel clock signal (PCLK), wherein the synchronization of the multi-phase oscillation signal (MOUT1) with a horizontal sync signal (HSYNC) sampling a plurality of bit signals of the multi-phase oscillation signal (MOUT1) in response to an edge of the horizontal sync signal (HSYNC); decoding outputs of the scanning; and selecting a bit signal from the plurality of bit signals of the multi-phase oscillation signal (MOUT1) based on the decoding includes. [20] The method of claim 19, wherein the second oscillation signal has a third frequency, and this third frequency corresponds to a frequency suitable for controlling the analog / digital conversion in a digital television including a PLL circuit (110). [21] The method of claim 19, wherein adjusting the phase of the second oscillation signal to generate the pixel clock signal (PCLK) comprises: Receiving a phase control signal (CON_PH), and applying the bits of the phase control signal (CON_PH <0> to CON_PH <3> ) to set an initial condition of the delay control circuit (150).

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