Semiconductor device and method for manufacturing the same

Abstract

Procedure that includes the following: Providing a die (312); Forming a molding compound (320) along side walls of the die (312); Forming a first contact point (318a) directly above the die (312); Forming a second contact point (318b) over the die (312) and the molding compound (320); Forming a dummy pad structure (332) adjacent to the second contact point (318b), wherein no dummy pad structures are formed adjacent to the first contact point (318a), and wherein the dummy pad structure (332) is electrically isolated from the first and the second contact point (318a, 318b); and Forming electrical connection parts (340) at the first and second contact points (318a, 318b); and Attaching a substrate (350) to the electrical connection parts (340).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of different materials over a semiconductor substrate, and then patterning the different material layers using lithography to form circuit components and elements. Dozens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, for example, in multi-chip modules or other types of packages.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum device size, allowing more components to be integrated into a given area. These smaller electronic components, such as integrated circuit die, may also require smaller packages in some applications, requiring less space than previous packages.

[0003] Integrated fan-out (InFO) packaging technology is becoming increasingly popular, especially when combined with wafer-level packaging (WLP) technology, in which integrated circuits are encapsulated in packages typically including a redistribution layer (RDL) or post-passivation interconnect (PPI) used to distribute wiring for package pads, allowing electrical contacts to be made with a wider pitch than integrated circuit pads. Such resulting package structures provide high functional density with relatively low-cost, high-performance packages.

[0004] For the state of the art, reference is made to the documents US 6 118 180 A and US 2007 / 0 246 811 A1.

[0005] The invention provides a method according to claim 1 and a device according to claim 7. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 is a plan view of a portion of an integrated fan-out package, in accordance with some embodiments. Fig. 2 is a plan view of a contact pad having an auxiliary disk device in accordance with some embodiments. Fig. 3A-3J illustrate various intermediate process steps in fabricating a package having a contact pad, in accordance with some embodiments. Fig. 4 is a flowchart illustrating steps that may be performed to fabricate a device in accordance with some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and as such does not impose any relationship between the various embodiments and / or configurations described.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0009] Some embodiments of the present disclosure relate to packaging devices and methods of fabricating them for semiconductor devices. For example, embodiments such as those described herein provide a pad structure and arrangement that may be useful, for example, for integrated fan-out (InFO) packages. In some embodiments, pad sizes are reduced to provide additional area for line routing, such as that provided in redistribution layers (RDLs). As such, embodiments such as those disclosed herein extend the routing capabilities of redistribution layers by reducing pad size without introducing additional reliability issues.Large RDL pads typically cover a large portion of the area of ​​a single RDL layer, limiting routing capability and often requiring an additional layer or layers to ensure routing integrity, which in turn increases costs. Furthermore, reducing the critical dimension of pads often leads to reliability issues on dielectric (e.g., polymer) layers at certain critical locations, such as die corners of ball grid array devices. Similar problems have also been observed in flip-chip packages.

[0010] To solve these problems, some embodiments include an auxiliary disk device, such as an auxiliary metal device, adjacent to a contact pad and located along an edge of the under-bump metallization (UBM). Generally, as described in more detail below, the auxiliary disk device is a device, such as a metal device, that is separate from the contact pad and partially surrounds the contact pad. In some embodiments, the auxiliary disk device is an auxiliary ring that partially surrounds the contact pad. The auxiliary disk is not electrically connected to the contact pad.

[0011] The auxiliary wafer device may be provided when appropriate for a particular design. For example, in some embodiments, the auxiliary wafer device is provided in corners of dies of a ball grid array (BGA) configuration to reduce or avoid reliability issues, particularly when accompanied by the reduction of RDL pad sizes and polymer opening sizes. Additionally, in some embodiments, the auxiliary wafer device is provided in a small region along corners of dies and corners of packages. In some embodiments, a 3x3 region of a BGA array along the corners of a die and the corners of a package includes the auxiliary wafer device. Auxiliary wafer devices may also be provided along an interface between the die and a molding compound.

[0012] As described below, embodiments are disclosed that utilize an auxiliary wafer device and a pad structure for the purpose of attaching one substrate to another substrate, wherein each of the substrates may be a die, a wafer, a circuit board, an encapsulation substrate, or the like, thereby enabling die-to-die, wafer-to-die, wafer-to-wafer, die or wafer-to-circuit board or encapsulation substrate connection, or the like.

[0013] If we now refer to Fig. 1, a top view of a portion of an InFO housing is shown, in accordance with some embodiments. The InFO housing shown in Fig. 1 includes a die region 102 and a molding compound region 104. In embodiments such as these, a die (represented as die region 102) includes a molding compound (represented by molding compound region 104) along sidewalls of the die. Contact pads 106 provide external electrical connection to another substrate, such as a die, a wafer, an encapsulation substrate, a circuit board, an interposer, or the like. Overlying layers, such as redistribution layers, under-bump metallization (UBM) layers, and the like, are not shown to better illustrate the configuration of one embodiment.

[0014] As in Fig. 1, a width W1 of the contact pads is approximately 100 µm to approximately 200 µm, e.g., approximately 140 µm. This reduced size of the contact pads, compared to contact pads having a width of approximately 240 µm or more, provides a larger area for redistribution lines. In some embodiments, the additional area for the redistribution lines allows for fewer routing layers to be used, reducing manufacturing costs.

[0015] Fig. Figure 1 further shows three auxiliary areas 108a, 108b and 108c (collectively referred to as auxiliary areas 108) indicated by dashed rectangles and representing the areas in which the auxiliary disc devices 110 (described below with reference to Fig. 2). The auxiliary regions 108 depict bonding areas subject to higher stress levels, for example, during thermal cycling on board (TCoB), such as the temperature cycling of a package mounted on a printed circuit board. The inclusion of the auxiliary disk device 110 reduces the stress and the risk of delamination or other failures.

[0016] The first auxiliary region 108a is located along a corner of the housing. In the embodiment shown in Fig. 1, the corner of the package includes contact pads 106 disposed over the molding compound 104 along the corner. In one embodiment, the first auxiliary region 108a includes an area of ​​3x3 contact pads disposed over the molding compound 104 along a corner of the package, although other sizes may be used. In a non-inventive example, the second auxiliary region 108b includes an area of ​​4x4 contact pads disposed over a corner of an interface between the die region 102 and the molding compound region 104 along a corner of the die, although other sizes may be used. As shown in Fig. 1, the second auxiliary region 108b may overlap the contact pads in the die region 102 and the molding compound region 104. In a non-inventive example, the third auxiliary region 108c comprises a region of 3 contact pads along an interface between the die region 102 and the molding compound region 104 along an edge of the die, although other sizes may be used. As shown in Fig. 1, the third auxiliary region 108c may overlap the contact pads in the die region 102 and the molding compound region 104. The auxiliary disk devices 110, such as in the embodiments disclosed herein, may be partially useful in these regions or other regions subject to higher stress levels, delamination, and / or other failures.

[0017] Fig. 2 shows an enlarged top view of the contact pads 106 and auxiliary disk devices, in accordance with some embodiments. Fig. 2 also shows parts of sections of a redistribution layer 112. The redistribution layer 112 is a conductive path that connects the electrical signals to the desired locations of the contact pads 106. In the embodiment shown in Fig. As shown in Figure 2, the auxiliary disk devices 110 form rings that partially surround the contact pads 106. In some embodiments, the auxiliary disk devices 110 are located on an opposite side of the contact pad 106 from the die or the center of the die.

[0018] In some embodiments, a width W2 of the auxiliary disk devices is about 15 µm to about 30 µm, e.g., about 20 µm. The width of the auxiliary disk devices can be adjusted according to the requirements of a particular design and pad layout. In some embodiments, a width of 15 µm or more provides a significant reduction in stress and fracture problems, particularly in the polymer regions around the pads. Furthermore, in some embodiments, a width greater than 30 µm offers little or no additional benefit and may require additional space in some embodiments. Other embodiments may use different dimensions.

[0019] Fig. 3A to 3J show various sectional views of intermediate steps in the manufacture of a semiconductor device such as that described above with reference to Fig. 1 and Fig. 2, in accordance with some embodiments. Referring first to Fig. 3A, a carrier substrate 302 is shown having one or more optional backside redistribution layers 304 formed thereon. As described in more detail below, a die is placed on the carrier substrate 302 with the contact pads facing up. The backside redistribution layers 304 provide electrical connections on both sides of the package, enabling stacked packages (e.g., package-on-package (POP) configurations). Alternatively, the backside redistribution layers 304 may be omitted if a die, package, or other substrate is not stacked on the present package.

[0020] In general, the carrier substrate 302 provides temporary mechanical and structural support during subsequent processing steps. In addition, the carrier substrate 302, as shown in Fig. 3A, provides a surface on which the backside redistribution layers 304 are formed. The carrier substrate 302 may comprise, for example, glass, silicon oxide, aluminum oxide, or the like.

[0021] The backside redistribution layers 304 include one or more layers of dielectrics with conductive features (e.g., traces and vias) formed therein. The one or more layers of dielectrics are collectively referred to as backside dielectric layers 304a, and the conductive features are collectively referred to as backside conductive features 304b.

[0022] The one or more backside dielectric layers 304a may be formed from any suitable material (e.g., polyimide (PI), polybenzoxazole (PBO), BCB, epoxy, silicone, acrylates, nanofilled phenolic resin, siloxane, a fluorinated polymer, polynorbornene, an oxide, a nitride, and the like) using any suitable method (e.g., a spin-coating technique, sputtering, and the like). Forming the backside conductive features 304b may include patterning the backside dielectric layers 304a (e.g., using photolithography and / or etching techniques) and forming backside conductive features 304b in the patterned backside dielectric layers 304a (e.g., by depositing a seed layer, using a mask layer to define the shape of the conductive features, and using an electroless / electrochemical plating process).

[0023] Fig. 3B illustrates the formation of optional vias 310, in accordance with some embodiments. The optional vias 310 provide an electrical connection from one side of the package to another side of the package. A die is mounted, for example, on the backside redistribution layers 304, as described in more detail below, and a molding compound is formed around the vias and the die. Subsequently, another device, such as another die, another package, substrate, or the like, may be mounted to the die and the molding compound. The vias 310 provide an electrical connection between the another device and the backside redistribution layers 304 without requiring electrical signals to be passed through the die mounted on the backside redistribution layers 304.

[0024] The vias may be formed, for example, by forming a conductive seed layer (not shown) over the backside redistribution layers 304. A mask, such as a patterned photoresist layer, may be deposited and patterned to define the shape of the vias 310, with openings in the mask exposing the seed layer. The openings may be filled with a conductive material using, for example, an electroless plating process or an electrochemical plating process. The plating process may fill the openings in the patterned photoresist unidirectionally (e.g., from the seed layer upwards). Unidirectional filling may enable such openings to be filled more uniformly, particularly for high aspect ratio vias.Alternatively, a seed layer may be formed on sidewalls of openings in the patterned photoresist, and these openings may be filled multidirectionally. Subsequently, the photoresist may be removed in a plasma etch and / or wet removal process, leaving the vias 310 over and electrically connected to the backside redistribution layers 304, as shown in FIG. Fig. 3B. The vias 310 can also be implemented with metal wire studs arranged by a wire bonding process, such as a copper wire bonding process. Using a wire bonding process can eliminate the need for depositing a seed layer, depositing and patterning a photoresist, and plating to form the vias 310.

[0025] If we now refer to Fig. 3C, a die 312 is shown attached to the backside redistribution layers 304, in accordance with some embodiments. The die 312 may include a substrate having any type of circuitry suitable for a particular application formed thereon. The electrical circuitry may include, for example, various n-type metal oxide semiconductor (NMOS) and / or p-type metal oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like, connected together to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power supplies, input / output circuits, or the like.One skilled in the art will appreciate that the above examples are provided for descriptive purposes only, to further describe applications of some exemplary embodiments, and are not intended to limit the disclosure in any way. Other circuits may be used as appropriate for a given application.

[0026] Die 312 may include one or more dielectric layers overlying the electrical devices, and metal layers may be formed between dielectric layers to connect electrical signals between the electrical devices. Electrical devices may also be formed in one or more dielectric layers. Die 312 includes external contacts, such as contacts 314, in the topmost dielectric layer to provide external electrical connections to the electrical circuitry. In one embodiment, contacts 314 are aluminum pads or aluminum-copper pads, although other metallic materials may be used. Contacts 314 may be pads, pillars, solder balls, wire pins, or other conductive electrical connection to the electrical circuitry of die 312.

[0027] Die 312 may be attached to backside redistribution layer 304, for example, by means of an adhesive layer 316 (e.g., a die attach film (DAF)) disposed on a backside. In one embodiment, adhesive layer 316 may be comprised of any suitable adhesive, such as an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light.

[0028] Fig. 3D illustrates an injection molding process and back grinding of the molding compound, in accordance with some embodiments. In some embodiments, the injection molding process is a wafer-level injection molding process. For example, a molding compound 320 is applied to fill gaps between the die 312 and the vias 310. The molding compound 320 may comprise any suitable material, such as an epoxy resin, a mold underfill, or the like. Suitable methods for forming the molding compound 320 include compression molding, transfer molding, liquid molding injection molding, and the like. For example, the molding compound 320 may be applied between the die 312 and the vias 310 in liquid form. Subsequently, a curing process is performed to solidify the molding compound 320. Filling the mold compound 320 may overfill the die 312 and the vias 310 so that the mold compound 320 covers top surfaces of the die 312 and the vias 310.A mechanical grinding, chemical mechanical polishing (CMP), or other etch-back technique may be applied to remove excess portions of the mold compound 320 and expose the contacts 314 of the die 312. After planarization, top surfaces of the mold compound 320, the die 312, and the vias 310 may be substantially flat.

[0029] If we next refer to Fig. 3E, one or more front-side redistribution layers 330 are shown, in accordance with some embodiments. The front-side redistribution layers 330 may be substantially similar to the back-side redistribution layers 304 in both formation method and composition. The front-side redistribution layers 330 may, for example, include one or more layers of dielectrics (e.g., dielectric layers 330a) with conductive features (e.g., traces and vias 330b) formed therein. The one or more dielectric layers may be formed from any suitable material (e.g., polyimide (PI), polybenzoxazole (PBO), BCB, epoxy, silicone, acrylates, nanofilled phenolic resin, siloxane, a fluorinated polymer, polynorbornene, an oxide, a nitride, and the like) by any suitable method (e.g., a spin-coating technique, sputtering, and the like).Forming the front-side redistribution layers 330 may include patterning the dielectric layers, for example, using photolithography and / or etching techniques, and forming conductive features in the patterned dielectric layers, for example, by forming a conductive material in the openings of the patterned dielectric layers.

[0030] Fig. Figure 3F shows an enlarged view of a reference area 317 shown in Fig. 3E is marked by the dotted rectangle. As in Fig. 3E, the reference region 317 comprises a region belonging to the third auxiliary region 108c and a region adjacent to the third auxiliary region 108c, as described above with reference to Fig. 1 is described. Fig. 3F shows two contact points 318a and 318b (collectively referred to as contact points 318) for the purpose of description, with a first contact point 318a located outside the third auxiliary region 108c and a second contact point 318b located inside the third auxiliary region 108c. It is understood that many more contact points may be present and that similar methods and materials may be used in other regions of the bonding region, such as the first auxiliary region 108a and the second auxiliary region 108b described above with reference to Fig. 1 are described.

[0031] Referring again to Fig. 3F, two contact points 318a and 318b are shown, both of which can be used to make electrical contact. As in Fig. 3F, an auxiliary disk device 332 is formed adjacent to the contact point 318b. For reference, the formation of the contact point 318b and the auxiliary disk device 332 is along the line AA of Fig. 2 shown.

[0032] The contact pads 318 and the auxiliary wafer device 332 can be formed using any suitable method and materials. For example, in one embodiment, a seed layer (not shown) is deposited over a surface of the front-side redistribution layers 330. Thereafter, a patterned mask layer, such as a photoresist layer that has been deposited, exposed, and developed, is formed over the seed layer, which has openings that define the desired shape of the contact pads 318 and the auxiliary wafer device 332. It is understood that the openings can further define a redistribution line to connect the contact pads to the desired location, as shown in Fig. 2. A plating process may be used to form the contact pads 318 and the auxiliary wafer device 332 over the seed layer in the openings of the patterned mask layer. For example, an electroless plating process or an electrochemical plating process may be used. Thereafter, the patterned mask layer may be removed, and exposed portions of the seed layer may be removed using the contact pads and the auxiliary wafer device 332 as a mask. In some embodiments, the contact pads 318 and the auxiliary wafer device 332 are aluminum pads or aluminum-copper pads, although other metallic materials may be used.

[0033] As in Fig. 3F, the contact pads 318 have a width W3 of about 100 µm to about 200 µm, and the auxiliary disk device 332 has a width W4 of about 15 µm to about 30 µm. In some embodiments, the auxiliary disk device 332 is spaced from the contact pad 318b by D1. The space D1 may be such that an overlap between the auxiliary disk device 332 and a subsequently formed under-bump metallization (described in more detail below) can be maintained. In some embodiments, the auxiliary disk device 332 may have a thickness of about 2 µm to about 10 µm. Dimensions such as these have been found to reduce stress while allowing for a smaller contact pad size. The auxiliary disk device 332 may also serve as an anti-cracking agent.

[0034] It is understood that the contact points 318 provide an electrical connection between a further substrate to be subsequently attached (see e.g. Fig. 3I) and the die 102 and / or the vias 310. On the other hand, the auxiliary disk devices 332 do not establish electrical connections and are not components of the electrical circuits. As shown in Fig. As shown in Figure 3F, the contact pads 318 are separate from the auxiliary disk devices 332. As such, the auxiliary disk devices 332 are devices added to reduce stresses and do not make electrical connections.

[0035] Fig. 3G shows one or more protection layers 322 formed over the front-side redistribution layers 330, in accordance with some embodiments. The protection layers 322 may be formed from a polymer such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like. Formation methods may include, for example, spin-coating. The protection layers 322 are patterned to form an opening through which the contact pads 318 are exposed. Patterning the protection layers 322 may include photolithography techniques. A curing step may be performed to cure the protection layers 322.

[0036] Fig. 3H shows an under-bump metallization (UBM) 324 formed and patterned over the one or more protection layers 322 and extending through the one or more protection layers 322, thereby forming an electrical connection to the contact pads 318. The under-bump metallization 324 provides an electrical connection on which an electrical connection part, e.g., a solder ball / bump, may be disposed. In one embodiment, the under-bump metallization 324 comprises a diffusion barrier layer, a seed layer, or a combination thereof. The diffusion barrier layer may comprise Ti, TiN, Ta, TaN, or combinations thereof. The seed layer may comprise copper or copper alloys. However, other metals such as nickel, palladium, silver, gold, aluminum, combinations thereof, and multi-layer structures thereof may also be provided.In one embodiment, the under-bump metallization 324 is formed by sputtering. In other embodiments, electroplating may be used.

[0037] In some embodiments, the under-bump metallization 324 laterally overlaps the auxiliary disk devices, as in Fig. 3H. In some embodiments, the under-bump metallization 324 laterally overlaps the auxiliary disk features by a distance D2 of more than about 7.5 µm. For example, in some embodiments where the width of the auxiliary disk features is about 15 µm, the under-bump metallization overlaps about 50% of the auxiliary disk features. Overlapping the under-bump metallization 324 and the auxiliary disk features helps to further reduce stresses, including stresses in the polymer layer at the edge of the under-bump metallization, such as stresses induced during thermal cycling. In some embodiments, the stress is reduced by about 30%.

[0038] If we next refer to Fig. 3I, a terminal 340 is formed over the under-bump metallization 324, in accordance with some embodiments. In one embodiment, the terminal 340 comprises a eutectic material and may include a bond bump or a solder ball, as examples. The solder material may be comprised of, for example, lead-based or lead-free solders, such as Pb-Sn compositions for lead-based solders; lead-free solders including InSb; tin, silver, and copper (SAC) compositions; and other eutectic materials that share a common melting point and form conductive solder joints in electrical applications. For a lead-free solder, SAC solders with various compositions may be used, such as SAC 105 (Sn 98%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405, as examples. Lead-free connection parts such as solder balls can also be formed from SnCu compounds without the use of silver (Ag).Alternatively, lead-free solder terminations may comprise tin and silver, Sn-Ag, without the use of copper. Terminations 340 may consist of one of an array of terminations formed as a grid, such as a ball grid array (BGA). Termination 340 includes a conductive ball, which in some embodiments may be shaped like a partial sphere. Alternatively, termination 340 may have other shapes. For example, termination 340 may also include non-spherical conductive terminations.

[0039] In some embodiments, the terminal 340 is attached using a solder ball drop process. During the terminal 340 attachment process or after the conductive material attachment process, the eutectic material of the conductive material 340 may be reflowed.

[0040] Fig. 3J illustrates the removal of the carrier substrate 302 and the attachment of a top substrate 350 and a bottom substrate 352, in accordance with some embodiments. Both the top substrate 350 and the bottom substrate 352 may be a die, a wafer, an encapsulation substrate, a motherboard, a printed circuit board, or the like. In some embodiments, a package-on-package structure is formed. For example, the top substrate 350 may be another package, where the die 312 is a processor, and the top substrate 350 may be another package providing memory. In this embodiment, the bottom substrate 352 may be a printed circuit board or an encapsulation substrate.

[0041] As in Fig. 3H, in some embodiments, the auxiliary wafer devices (e.g., auxiliary wafer device 332) are not exposed. Due to differences in the coefficient of thermal expansion (CTE) between the top substrate 350 and the other components, stresses between the terminal 340 and the contact pads 318 may lead to delamination or other undesirable problems. As mentioned above, as the size of the contact pads decreases, the stress at the contact pads 318 increases, which in turn may lead to delamination or other failures. This stress may be particularly high in the auxiliary regions 108, e.g., along the corners of the package and along the interface between the die 312 and the mold compound 320.

[0042] The auxiliary disk devices 332 provide stress relief by reducing the tension exerted on the contact pads 318. The addition of the auxiliary disk devices 332 allows the contact pads to be reduced in size, allowing an increase in the area for routing interconnect lines. This increased routing area may allow for fewer layers to be required, reducing costs.

[0043] As in Fig. 3J, the auxiliary disk devices 332 may also be provided on the backside redistribution layers 304.

[0044] Embodiments such as those described above have been presented with reference to a fan-out package with back and front redistribution layers for descriptive purposes. Other embodiments may use the disclosed features in other configurations. For example, the back redistribution layers, vias, and the like may not be present in all embodiments. Furthermore, embodiments need not use a fan-out configuration. In still other embodiments, the auxiliary wafer features may be used on the back redistribution layers as well as on the front redistribution layers. Additionally, a single redistribution layer may be used in one or both of the back and front redistribution layers.

[0045] Fig. 4 is a flowchart illustrating steps of a method of forming a device, in accordance with some embodiments. The method begins at step 402, in which a substrate is provided. In some embodiments, the substrate is an integrated fan-out package, as described above with reference to Fig. 3A-3E, although other types of substrates may be used. In step 404, contact pads are formed on the substrate, and in step 406, auxiliary disk regions are formed as described above with reference to Fig. 3F. In some embodiments, the contact pads and the auxiliary disks may be formed simultaneously. The auxiliary disk regions may be formed in high voltage regions, as described above, thereby providing additional wiring routing areas. In step 408, external terminals are formed, such as those described above with reference to Fig. 3G-3I. Passivation layers and under-bump metallization layers may also be formed. Thereafter, in step 410, the structure may be bonded to another substrate, as described above with reference to Fig. 3J is described.

Claims

[1] Procedure comprising: Providing a die (312); Forming a molding compound (320) along side walls of the die (312); Forming a first contact point (318a) directly above the die (312); Forming a second contact point (318b) over the die (312) and the molding compound (320); Forming a dummy pad structure (332) adjacent to the second contact point (318b), wherein no dummy pad structures are formed adjacent to the first contact point (318a), and wherein the dummy pad structure (332) is electrically insulated from the first and second contact points (318a, 318b); and Forming electrical connection parts (340) on the first and second contact points (318a, 318b); and Attaching a substrate (350) to the electrical connectors (340). [2] The method according to claim 1, wherein the dummy pad structure (332) is arranged in a corner region (108a) of the molding compound (320). [3] Method according to one of the preceding claims, wherein the dummy pad structure (332) is formed from a same material as the first and second contact points (318). [4] The method of any preceding claim, wherein the dummy pad structure (332) forms a ring partially surrounding the second contact point (318b, 106). [5] A method according to any one of the preceding claims, wherein the electrical connection parts (340) comprise solder balls. [6] The method of any preceding claim, wherein the dummy pad structure (332) comprises a metal. [7] Device comprising: a die (312); a molding compound (320) along side walls of the die (312); a first contact point (318a) directly above the die (312); a second contact point (318b) over the die (312) and the molding compound (320); and a dummy pad structure (332) adjacent to the second contact point (318b) and no dummy pad structure adjacent to the first contact point (318a), where the dummy pad structure does not make any electrical connections. [8] The device according to claim 7, wherein the dummy pad structure (332) is arranged in an outer corner region (108a) of the molding compound (320). [9] The device of claim 7 or 8, wherein the dummy pad structure (332, 110) comprises a ring partially surrounding the second contact point (318b, 106). [10] The device according to any one of claims 7 to 9, wherein the dummy pad structure (332) comprises a metal. [11] The device of any one of claims 7 to 10, further comprising a substrate (350) electrically connected to the first and second contact points (318a, 318b) by means of an electrical connector (340).

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