Resistive work memory devices and methods for their manufacture for improving RAM storage by separating a TI top layer in front of an HK-HFO separation

Abstract

Resistive working memory device (100) comprising: a variable-resistance dielectric layer (110, 604) having a top surface and a bottom surface; a cathode (114, 112, 113, 608, 606, 607) arranged above the variable-resistance dielectric layer (110, 604) adjacent to the top surface; a metal cover layer (108, 602) arranged below the variable-resistance dielectric layer (110, 604) adjacent to the bottom surface; and an anode (106, 502) arranged below the metal cover layer (108, 602), wherein the resistive working memory device (100) further comprises: a semiconductor support area (103, 403) comprising a metal compound structure (101, 401) arranged in a low-k dielectric layer (102, 402) is arranged;and a dielectric protective layer (104, 404) having an opening over a section of the metal compound structure (101, 401), wherein side walls of the dielectric protective layer (104, 404) adjoining the opening terminate over the metal compound structure (101, 401) and wherein the anode (106, 502) lies over the dielectric protective layer (104, 404) and adjoins the metal compound structure (101, 401) through the opening in the dielectric protective layer (104, 404).

Description

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application 61 / 924,504, filed January 7, 2014, entitled "improvement of RRAM retentiqon by depositing Ti capping layer before HK HfO"; its contents are hereby incorporated by reference. BACKGROUND

[0002] Non-volatile memory is used in a wide variety of commercial and military electronic devices and equipment. Resistive random access memory (RRAM) is a promising candidate for next-generation non-volatile memory technology due to its simple structure and CMOS logic-compatible process technology used. Each RRAM cell includes a metal oxide material interposed between a top and bottom electrode. This metal oxide material has a variable resistance whose resistance level corresponds to a data state stored in the RRAM cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with industry practice, various facilities are not drawn to scale. In fact, the dimensions of the various devices can be arbitrarily increased or decreased for the clarity of the description.

[0004] figure 1 shows a sectional view of an RRAM stack, according to some embodiments of the present disclosure.

[0005] figure 2 shows a flow diagram of some embodiments of a method of forming an RRAM stack with a Ti cap layer formed in front of a HK (high-k) HfO (hafnium oxide) dielectric layer, according to the present disclosure.

[0006] figure 3 shows a flow chart of some embodiments of a step-by-step method for forming an RRAM stack according to the present disclosure.

[0007] figure 4- figure 10 show embodiments of cross-sectional views of a step-by-step method of forming an RRAM stack with a Ti cap layer formed under the HK-HfO dielectric layer, according to the present disclosure.

[0008] figure 11 shows a cross-sectional view of some embodiments of an RRAM device having an RRAM stack having a Ti cap layer formed under the HK-HfO, according to the present disclosure. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second Device can be formed so that the first and the second device do not have to be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for the sake of simplicity and clarity and as such does not compel any relationship between the various described embodiments and / or configurations.

[0010] A conventional RRAM cell includes a top electrode (anode) and a bottom electrode (cathode) with a variable resistance dielectric layer sandwiched between the two electrodes. The top electrode is made of a bipolar switching layer and a metal cap layer, both of which share a width with the top electrode measured between outer sidewalls of the top electrode. The variable resistance dielectric layer and the lower electrode have the width of the lower electrode smaller than that of the upper electrode. During write operations to the RRAM cell, a "set" voltage may be applied to the top and bottom electrodes to change the variable resistance dielectric layer from a first resistance to a second resistance. Similarly, a "reset" voltage may be applied to the electrodes to change the variable resistance dielectric layer from the second resistance back to the first resistance. Therefore, in cases where the first and second resistance states correspond to a logical "1" and a logical "0" state (or vice versa), respectively, the "set" and "reset" voltages can be used to set digital store data in the RRAM cell.

[0011] The mechanism by which this resistance switching occurs is believed to be associated with selectively conducting fibers disposed in the variable resistance dielectric layer. These selectively conductive fibers are initially formed at the end of the RRAM manufacturing process when a forming voltage is applied to the anode and cathode. This formation voltage creates a strong electric field that knocks oxygen atoms out of the lattice of the variable resistance dielectric layer, thereby forming local oxygen vacancies. These local oxygen vacancies tend to align to form "fibers" that are relatively permanent and that extend between the top and bottom electrodes. During write operations, the resistance of these fibers can be changed by "filling" them with oxygen atoms or "pulling" oxygen atoms from them. For example, when a first voltage is applied (e.g., a "set" voltage), oxygen atoms are depleted from the metal overlay and introduced into the fibers to provide a first resistance; whereas when the second voltage is applied (e.g., a "reset" voltage), oxygen atoms are removed from the fibers and introduced into the metal overlay to provide a second resistance. Whatever the exact mechanism, it is believed that the movement of the oxygen molecules between the metal top layer, which can serve as an oxygen reservoir, and the fibers greatly reduces the "set" and "reset" resistance of the RRAM cell definitely.

[0012] Unfortunately, in a conventional RRAM manufacturing process, an etch used to form the relatively narrow top electrode structure can at least partially oxidize outer sidewalls of the metal cap layer. During subsequent thermal steps (e.g., curing or annealing), oxygen can unintentionally diffuse from this partially oxidized metal overlay to recombine with the oxygen vacancies in the fibers. For some RRAM cells, this can "pin" some fibers into either of the two variable resistance states, so these RRAM cells can have problems with data storage.

[0013] Thus, the present disclosure relates to a new architecture for RRAM cells in which the anode structure (including the metal cap layer) is disposed under the variable resistance dielectric layer and becomes part of the relatively wide bottom electrode. In this way, the metal cap layer is formed under the variable resistance dielectric layer (i.e. the anode is now formed under the variable resistance dielectric layer) and therefore will not be oxidized when the top electrode is etched. Furthermore, since the metal cap is now part of the relatively wide bottom electrode, any sidewall oxidation for the metal cap occurs a safe distance from the fiber region in the variable resistance dielectric layer. Therefore, the effective change in resistance between the "set" and "reset" resistances is well defined, making it easier to distinguish between high and low resistance states.

[0014] figure 1 shows a sectional view of an RRAM stack 100 according to some embodiments of the present disclosure. The RRAM stack 100 includes a top electrode (cathode) 114 and a lower electrode (anode) 105 with a variable resistance dielectric layer 110 between. The variable resistance dielectric layer 110 includes a fiber area 107 , in which fibers are formed. In some embodiments, the dielectric layer comprises variable resistance 110 HK-(high-k)-HfO (hafnium oxide).

[0015] The RRAM stack 100 lies over a semiconductor workpiece 103 , which has a conductive metal area 101 includes extremely-low-k dielectric ranges 102 has on both sides. Directly above the semiconductor workpiece 103 there is a protective dielectric layer 104 , showing an open area above the metal area 101 having, wherein side walls of the dielectric protective layer 104 over the metal area 101 end up. Above the protective dielectric layer 104 lies an anode 106 connected to the conductive metal area 101 through the opening in the protective dielectric layer 104 adjacent. In some embodiments, the anode comprises 104 a transitional nitride layer. above the anode 106 is a metal top layer 108 arranged. In some embodiments, the metal cap layer comprises 108 Ti, Ta (tantalum) or Hf (hafnium) and serves as an oxygen reservoir. A dielectric layer with variable resistance 110 abuts the entire top surface of the metal skin 108 on. The variable resistance dielectric layer 110 , the metal top layer 108 and the anode 106 have vertical side walls aligned with each other. A cathode 114 lies over the variable resistance dielectric layer 110 in a fixed central region of the variable resistance dielectric layer. the cathode 114 has a first width w1 measured between its outer sidewalls and the variable resistance dielectric layer 110 and the metal cover layer 108 each have a second width w2 measured between their respective outer sidewalls. In some embodiments, the second width w2 is greater than the first width. In one embodiment, the cathode comprises 114 a first transitional nitride layer 112 and a second transitional nitride layer 113 that is on the first transition nitride layer 112 lies. A pair of sidewall spacers 118a and 118b is on either side of the cathode 114 arranged. The spacers 118a and 118b also lie on the two edge portions of the variable resistance dielectric layer 110 . the cathode 114 has outer sidewalls directly mating to mating inner sidewalls of the sidewall spacers 118a and 118b adjoin. An anti-reflective layer 116 is above the top electrode 114 arranged. The anti-reflective layer 116 and the cathode 114have vertical side walls aligned with each other.

[0016] As described in more detail below, the metal overlay 108 , which may comprise Ti in some embodiments, in front of the variable resistance dielectric layer 110 deposited, deviating from conventional methods. In other words were the anode 106 and the cathode 114 exchanged compared to conventional solutions and the metal top layer 108 now becomes part of the lower electrode 105 . This architecture organizes the outer sidewalls of the oxidation-prone metal cap layer 108 away from the fiber area 107 the variable resistance dielectric layer 110 on, while the outer sidewalls of the dielectric layer with variable resistance 110 and the metal cover layer 108 are essentially aligned with each other. Therefore, any oxidation affecting the outer sidewalls of the metal overlay 108 can occur, the fibers of the dielectric layer with variable resistance 110 not negative and thus data storage is improved.

[0017] figure 2 shows a flowchart 200 of some embodiments of a method of forming an RRAM stack with a Ti cap layer formed before the HK-HfO according to the present disclosure. While the disclosed method 200 Although shown and described below as a sequence of acts or events, it is understood that the sequence of acts or events shown should not be construed in a limiting sense. For example, some acts may be performed in different orders and / or concurrently with other acts or events than those shown and / or described herein. In addition, not all acts shown may be necessary to implement one or more aspects or embodiments of the present description. Furthermore, one or more acts depicted herein may be performed in one or more separate acts and / or phases.

[0018] at 202 a semiconductor footprint comprising a metal interconnect structure disposed in an extremely-low-k dielectric layer is provided. In some embodiments, the metal interconnect structure includes copper.

[0019] at 204 a protective dielectric layer having an open area is formed over the semiconductor base surface. In some embodiments, the protective dielectric layer comprises SiC.

[0020] at 206 an anode layer is formed over the protective dielectric layer. In some embodiments, the anode includes TaN.

[0021] at 208 a metal cap is formed over the anode. In some embodiments, the metal cap layer includes Ti.

[0022] at 210 a variable resistance dielectric layer is formed over the metal cap layer. In some embodiments, the variable resistance dielectric layer comprises hafnium oxide (HfO).

[0023] at 212 a cathode layer is formed over the variable resistance dielectric layer. In some embodiments, the cathode includes a first transitional nitride layer with a second transitional nitride layer thereover. In some embodiments, the transitional nitride layer includes TaN and TiN. The first transitional nitride layer may consist of TaN, for example, and the second overlying transitional nitride layer may consist of TiN.

[0024] figure 3 shows a flow chart of some embodiments of a step-by-step method 300 for forming an RRAM stack according to the present disclosure. While the disclosed method 300Although shown and described below as a sequence of acts or events, it is understood that the sequence of acts or events shown should not be construed in a limiting sense. For example, some acts may be performed in different orders and / or concurrently with other acts or events than those shown and / or described herein. In addition, not all acts shown may be necessary to implement one or more aspects or embodiments of the present description. Furthermore, one or more acts depicted herein may be performed in one or more separate acts and / or phases.

[0025] at 302 For example, a horizontal stack of bulk materials comprising an anode, a metal cap layer, a variable resistance dielectric layer, and a cathode is formed over a semiconductor base surface on which lies a protective dielectric layer.

[0026] at 304 a mask is formed over the cathode layer. The mask covers some portions of the cathode layer while leaving other areas of the cathode exposed.

[0027] at 306 a first etch is performed to remove exposed portions of the cathode layer and form a cathode structure. In some embodiments, the first etch comprises a dry etch that uses chlorine-based (Cl 2 / BCl 2 ) or fluorine-based (CF 4 / CHF 3 / CH 2 / SF 6 ) includes caustic.

[0028] at 308 sidewall spacers are formed around the outer sidewalls of the cathode. The sidewall spacers and cathode structure cover some portions of the variable resistance dielectric layer and leave other portions of the variable resistance dielectric layer exposed. In some embodiments, the cathode comprises TaN over TiN and the sidewall spacer material comprises SiN (silicon nitride).

[0029] at 310 a second etch is performed to remove exposed portions of the variable resistance dielectric layer. With the sidewall spacers and cathode structure in place, performing a second etch removes the exposed portions of the variable resistance dielectric layer and the underlying metal cap layer and anode. The second etch stops at the protective dielectric layer. In some embodiments, the anode includes TaN. In some embodiments, the second etch comprises a dry etch that uses chlorine-based (Cl 2 / BCl 2 ) or fluorine-based (CF 4 / CHF 3 / CH 2 / SF 6 ) includes caustic.

[0030] at 312 a metal contact is formed over the cathode structure, which is further connected to a source line during set operations and a bit line during reset operations.

[0031] figure 4- figure 10 show embodiments of cross-sectional views of the step-by-step method of forming an RRAM stack with a Ti cap layer formed under an HK-HfO according to the present disclosure.

[0032] figure 4 shows a sectional view 400 a semiconductor carrier having a dielectric protective layer 404 over a semiconductor workpiece 403 having. The semiconductor workpiece 403 includes a metal interconnection structure 401 operating in extremely-low-k dielectric ranges 402 is arranged. In some embodiments, the metal interconnect structure comprises 401 Copper (Cu) and the extremely-low-k dielectric range 402 includes porous silica, fluorinated fused silica, polyimides, polynorbornene, benzocyclobutene, or PTFE. The protective dielectric layer 404 has an opening to the center created by a masked lithography step. This opening leaves a portion of the metal interconnect structure 401 exposed. In some embodiments, the protective dielectric layer comprises 404 SiC.

[0033] figure 5 shows a sectional view 500of a semiconductor carrier in a subsequent stage of manufacture, in which an anode 502 above the structure in figure 400 is arranged. Through the opening in the protective dielectric layer 404 touches the anode 502 the metal connection structure 401 , which later connects the RRAM stack to the rest of the device.

[0034] figure 6 shows a sectional view 600 of a semiconductor substrate in a subsequent stage of manufacture in which a horizontal stack of base materials is formed. The stack of materials that makes up an anode 502 , a metal top layer 602 , a dielectric layer with variable resistance 604 , a cathode 608 and an anti-reflective coating 610 comprises is applied over a semiconductor carrier area 403 educated. In some embodiments, the anode comprises 502 TaN, the metal top layer 602 includes Ti, the variable resistance dielectric layer 604 includes HfO, the cathode 608 includes a first transitional nitride layer 606 , comprising TiN, and a second transitional nitride layer 607 , which includes TaN, over it and the anti-reflective layer 610 includes SiON.

[0035] figure 7 shows a sectional view 700 at a subsequent stage of manufacture, in which a cathode mask (not shown) is placed over the horizontal stack 600 was formed and a first etch was performed. After the first etch, a cathode structure that is the cathode 608 and the anti-reflective coating 610 comprises, in the middle of the dielectric layer with variable resistance 604 is formed, which exposes portions of the variable resistance dielectric layer 604 leaves exposed on both sides.

[0036] figure 8A shows a sectional view 800a , after spacers 802a and 802b were formed on both sides of the cathode structure. In some embodiments, the spacer material includes silicon nitride (SiN). Usually the spacers 802a , 802b formed by removing the cathode mask and then depositing a uniform layer of spacer material over the workpiece. The deposited layer is then etched to remove the spacer material over the workpiece to a vertically uniform depth, thereby forming the spacers 802a , 802b be left on site.

[0037] figure 8B shows a sectional view 800b , after a second etching on the semiconductor carrier in figure 8A was applied. With the sidewall spacers 802a and 802b and the cathode structure in situ, performing a second etch would expose the exposed portions of the variable resistance dielectric layer 604 and underlying portions of the anode 502 and the top layer 602 remove to form an anode structure. The second etch stops at the protective dielectric layer 404 , so that the anode structure some sections of the dielectric protective layer 404 covered while covering other portions of the protective dielectric layer 404 left exposed. oxidized areas 804 are adjacent to outer sidewalls of the metal overlay 602 intended.

[0038] figure 9 shows a sectional view 900 , after the dielectric protective layer 902 and an insulating layer 904 were deposited, both over the RRAM structure. In some embodiments, the insulating layer comprises 904 SiON. These layers insulate and protect each of the RRAM cells from current leakage and charge diffusion. Furthermore, a dielectric intermediate layer 906 over and around the insulating layer 904 educated. An etched area 908 for a top electrode contact via (TEVA) is formed that extends into the cathode.

[0039] figure 10 shows a sectional view 1000 , after the TEVA 908 and a top metal contact 1002were trained. In some embodiments, the cathode layer thickness is about 220 angstroms, the metal cap layer thickness is about 100 angstroms, the variable resistance dielectric layer thickness is about 50 angstroms, the anode TiN layer thickness is about 100 angstroms, the Thickness of the anode TaN layer is about 250 angstroms.

[0040] figure 11 shows a sectional view 1100 of some embodiments of an RRAM device with an RRAM stack having a Ti cap layer formed under the HK-HfO according to the present disclosure. A plurality of such RRAM devices form a memory array configured to store data. figure 11 comprises a conventional planar MOSFET select transistor 1101 to suppress current leakage (i.e. prevent currents intended for a particular memory cell from going through an adjacent memory cell) while providing enough drive current for the memory cells to operate. The select transistor 1101 includes a source area 1104 and a drain area 1106 that are in a semiconductor carrier 1102 are provided and horizontally through a channel area 1105 are separated. A gate electrode 1108 is on the semiconductor carrier 1102 placed at a position above the canal area 1105 lies. In some embodiments, the gate electrode comprises 1108 Polysilicon, but can also be made of metal. The gate electrode 1108 is from the source 1104 and the drain 1106 through a gate oxide layer or a gate dielectric layer 1107 separated, extending laterally across the surface of the semiconductor substrate 1102 extends. the drain 1106 is with a data storage element or the RRAM stack 1120 through a first metal compound 1112a tied together. The sources 1104 is through a first metal contact 1112b tied together. The gate electrode is connected to a word line 1114a connected, the source is connected to a bit line 1114b via the first metal contact 1112b connected and the RRAM stack 1120 is next with a source line 1114c , which is provided in an upper metallization layer, via a second metal contact 1112g tied together. A target RRAM device can be accessed using word lines and bit lines for read, write, and erase operations. One or more metal contacts that 1112c , 1112d , 1112e , 1112f include, and metal contact vias that 1110a , 1110b , 1110c , 1110d , 1110e , 1110f etc. that contribute to the RRAM memory device being connected to the external circuits can be connected between the drain 1106 and the second metal contact 1112g and between the source 1104 and the first metal contact 1112b to be available. In some embodiments, the metal contacts include copper (Cu).

[0041] The RRAM cell 1120 comprises a variable resistance dielectric layer 1121 passing between a cathode 1122 and an anode 1123 is arranged. A metal cap layer (not shown) is between the variable resistance dielectric layer 1121 and the anode 1123 arranged. A top electrode via (TEVA) 1124 connects the cathode 1122 the storage cell 1120 with the second metal contact 1112g and a bottom electrode via (BEVA) 1125 connects the anode 1123 the RRAM cell 1120 with the first metal connection 1112a .

[0042] It will be appreciated that while this specification references example structures in describing aspects of the methods described herein, these methods are not limited to the corresponding structures identified. Rather, the methods (and structures) are to be considered independent of one another and may stand alone to be practiced without regard to any of the specific aspects shown in the figures. Additionally, layers described herein may be formed in any suitable manner, such as spin coating, sputtering, growth and / or deposition techniques, etc.

[0043] In addition, equivalent changes and / or modifications will become apparent to those skilled in the art based on a reading and / or understanding of the specification and the accompanying drawings. The present disclosure includes all such modifications and alterations and is generally not intended to be limited by them. For example, while the figures provided herein are illustrated and described as having a particular dopant type, it will be apparent that other dopant types may be used as will be appreciated by one skilled in the art.

[0044] Additionally, while a particular feature or aspect has been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more features and / or aspects of other implementations, if desired. Furthermore, to the extent that the terms "comprises," "comprises," "has," "having," and / or variants thereof are used herein, such terms should be construed as inclusive in their meaning--such as "comprises." Also, "exemplary" is intended to indicate an example only, rather than the preferred one. It should also be noted that devices, layers and / or elements shown herein are shown with particular dimensions and / or orientations relative to one another for the purpose of simplicity and convenience of understanding, and that the actual dimensions and / or orientations may differ materially from those shown here may vary.

[0045] The present disclosure relates to a resistive random access memory (RRAM) device that includes a metal cap layer that is deposited before a variable resistance dielectric layer is deposited. This architecture provides that the outer sidewalls of the metal cap layer are substantially aligned with the outer sidewalls of the variable resistance dielectric layer, preventing damage to the sidewalls or partial oxidation of the metal cap layer during the etching process of the cathode or electrode layer on the dielectric layer with variable resistance is prevented. Therefore, any damage that may occur on the sidewalls of the oxidation-prone metal cap layer is located away from the fiber portion of the variable resistance dielectric layer and therefore data storage is unaffected.

[0046] In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) device that includes a variable resistance dielectric layer having a top surface and a bottom surface, a cathode disposed over the variable resistance dielectric layer adjacent to the top surface, a metal cap layer disposed under the variable resistance dielectric layer adjacent the bottom surface, and an anode disposed under the metal cap layer.

[0047] In another embodiment, the present disclosure relates to a resistive random access memory (RRAM) stack of an RRAM device, comprising a bottom electrode comprising TaN, a Ti (titanium) metal cap layer disposed over the bottom electrode, a HK-HfO (high-k hafnium oxide) variable resistance dielectric layer disposed over the Ti metal cap layer, and a top electrode comprising a TaN (tantalum nitride) layer over a TiN (titanium nitride ) layer includes.

[0048] In yet another embodiment, the present disclosure relates to a method of forming a resistive random access memory (RRAM) stack that includes providing a semiconductor substrate surface that includes a metal interconnect structure disposed in a low-k dielectric layer. forming a protective dielectric layer having an open area over the metal interconnect structure, sidewalls of the open area of ​​the protective dielectric layer terminating over the metal interconnect structure, depositing an RRAM top electrode layer over the protective dielectric layer, the RRAM top electrode touching the meta-interconnect structure through the opening in the protective dielectric layer, depositing a metal cap layer over the top RRAM electrode layer, depositing a variable resistance dielectric layer over the metal cap layer, and depositing a bottom RRAM electrode layer over of the variable resistance dielectric layer.

[0049] The foregoing describes features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis to design or modify other methods and structures to achieve the same ends and / or realize the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

[1] Resistive RAM (RRAM) device comprising the following: a dielectric layer with variable resistance, having a top surface and a bottom surface; a cathode that is positioned above the dielectric layer with variable resistance adjacent to the upper surface; a metal top layer arranged beneath the variable-resistance dielectric layer adjacent to the bottom surface; and an anode located beneath the metal cover layer. [2] RRAM device according to claim 1, further comprising: a pair of sidewall spacers arranged laterally around outer sidewalls of the cathode, the cathode having a first width measured between its outer sidewalls; wherein the variable-resistance dielectric layer and the metal cover layer each have a second width, measured between their respective outer side walls, the second width being greater than the first width. [3] RRAM device according to claim 2, wherein the side wall spacers comprise SiN (silicon nitride). [4] RRAM device according to claim 2, wherein outer side walls of the metal cover layer have a distance from a conductive fiber area located below the cathode and in the dielectric layer with variable resistance. [5] RRAM device according to claim 2, further comprising: Oxidized areas adjacent to the outer sidewalls of the metal top layer. [6] RRAM device according to claim 2, wherein the cathode has outer side walls that directly adjoin associated inner side walls of the side wall spacers without an oxidized area between the cathode and the side wall spacers, and wherein the outer side walls of the cathode are arranged at locations near a central region of the dielectric layer with variable resistance. [7] RRAM device according to claim 2, wherein the outer side walls of the variable resistance dielectric layer, the metal cover layer and the anode are substantially aligned with each other. [8] RRAM device according to claim 1, wherein: the cathode comprises a TaN (tantalum nitride) layer over a TiN (titanium nitride) layer; the anode comprises a TaN layer; the dielectric layer with variable resistance HfO x (Hafnium oxide) includes; and the metal top layer comprises Ti (titanium) or Ta (tantalum) or Hf (hafnium). [9] RRAM device according to claim 8, wherein the thickness of the anode is approximately 200 angstroms; the thickness of the metal top layer is approximately 100 angstroms; the thickness of the dielectric layer with variable resistance is approximately 50 Angstroms; the thickness of the TiN layer of the cathode is approximately 100 angstroms; and The thickness of the TaN layer of the cathode is approximately 250 Angstroms. [10] RRAM device according to claim 1, further comprising: a semiconductor support area comprising a metal compound structure arranged in an extremely low k-dielectric layer formed over it; a dielectric protective layer having an open area above the metal, with side walls of the open area of ​​the dielectric protective layer terminating above the metal. [11] Resistive RAM (RRAM) stack of an RRAM device comprising the following: a lower electrode comprising TaN; a Ti (titanium) metal cover layer that is arranged over the lower electrode; a variable-resistance HK-HfO (high-k hafnium oxide) dielectric layer arranged over the Ti metal top layer; and an upper electrode comprising a TaN (tantalum nitride) layer over a TiN (titanium nitride) layer. [12] RRAM device according to claim 11, further comprising: a pair of sidewall spacers arranged laterally around the outer sidewalls of the upper electrode, the upper electrode having a first width measured between its outer sidewalls; wherein the HK-HfO variable resistivity dielectric layer and the Ti metal cover layer each have a second width, measured between their respective outer side walls, the second width being greater than the first width. [13] RRAM device according to claim 11, further comprising: a semiconductor carrier having a source region and a drain region that are horizontally separated by a channel region; a gate structure connected to the channel area; a first contact and a second contact, which are arranged above the source and drain areas respectively; a first metal connection arranged above the drain area, located below the second contact and electrically connected to the second contact; and where the RRAM stack is formed above the first metal connection. [14] RRAM device according to claim 13, wherein the gate structure comprises a polysilicon gate electrode formed over a gate dielectric which electrically isolates the gate electrode from the channel region. [15] RRAM device according to claim 14, wherein one or more metal contacts and one or more metal contact vias are provided between the source area and the first contact and between the drain area and the second contact. [16] RRAM device according to claim 15, wherein the source area is connected to a bit line, the drain area is connected to a source line and the gate electrode is connected to a word line of a memory array. [17] Method for forming a resistive main memory (RRAM) stack comprising the following: Providing a semiconductor substrate surface comprising a metal compound structure arranged in a low-k dielectric layer; Forming a dielectric protective layer that has an open area above the metal compound structure, with side walls of the open area terminating above the metal compound structure; Deposition of an anode layer over the dielectric protective layer, wherein the anode layer contacts the metal compound structure through the opening in the dielectric protective layer; Deposition of a metal top layer over the anode layer; Deposition of a dielectric layer with variable resistance over the metal top layer; and Deposition of a cathode layer over the dielectric layer with variable resistance. [18] The method of claim 17, further comprising: Forming a mask over the cathode layer, the mask covering some sections of the cathode layer while leaving other areas of the cathode layer exposed; Performing an initial etching to remove the exposed sections of the cathode layer and thus form a cathode structure; and Forming sidewall spacers around outer sidewalls of the cathode structure, wherein the sidewall spacers and the cathode structure cover some sections of the variable-resistance dielectric layer and leave other sections of the variable-resistance dielectric layer exposed. [19] The method of claim 18, further comprising: with the sidewall spacers and the cathode structure in place, performing a second etching to remove the exposed sections of the variable resistance dielectric layer as well as underlying sections of the anode and the metal cover layer to form an anode structure; the second etching ends at the dielectric protective layer. [20] The method of claim 19, further comprising: Forming a dielectric protective layer and an insulating layer covering the RRAM stack; Forming vias connected to the cathode; and Forming metal contacts that connect the RRAM stack to a source line.