Method for forming an integrated circuit with a modified insulation structure

Abstract

Procedure (200) comprising: Forming an insulating structure (310) partially buried in a substrate (110), a portion of the insulating structure (310) protruding from a top surface (110a) of the substrate (110); partially removing the insulating structure (310), thereby forming a modified insulating structure (122), wherein an upper surface (122a) of the modified insulating structure (122) is lower than the upper surface (110a) of the substrate (110); Forming a dielectric gate structure (132) lying partly on the substrate (110) and partly on the upper surface (122a) of the modified insulating structure (122); Forming a gate electrode structure (134) over the dielectric gate structure (132), wherein an upper surface (134b) of the gate electrode structure (134) has a first portion (134b-2) directly above the modified insulating structure (122) and a second portion (134b-1) different from the first portion (134b-2), and wherein the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134) is flush with or lower than the second portion (134b-1) of the upper surface (134b) of the gate electrode structure (134); and Forming a conductive path (154) over the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134), wherein the conductive path (154) is not electrically connected to the gate electrode structure (134).

Description

BACKGROUND

[0001] A metal-oxide-semiconductor field-effect transistor (MOSFET) has a gate electrode, a substrate, and a gate dielectric layer between the gate electrode and the substrate. By controlling a voltage level at the gate electrode, a conductive channel is created or modulated in the substrate beneath the gate dielectric layer. In some applications, a gate-source breakdown voltage of a MOSFET is increased by increasing a thickness of the gate dielectric layer. In some applications, a drain-source breakdown voltage of a MOSFET is increased by introducing a diffused drain region. Various types of MOSFETs are configured to have an increased breakdown voltage, including side-diffused metal-oxide-semiconductor (LDMOS) transistors and double-diffused drain metal-oxide-semiconductor (DDDMOS) transistors.

[0002] From DE 10 2010 016 000 A1 a transistor structure is known which has a trench lined with an insulating layer between a source / drain region and an active region.

[0003] US 2007 / 0138551 A1 describes a method for manufacturing a high-voltage transistor comprising an insulating oxide layer with beveled side surfaces over a depressed part of the surface of a substrate.

[0004] US 2009 / 0085112 A1 discloses a method for forming an LDMOS transistor, in which a trench in a semiconductor substrate is filled with a dielectric material and then an upper part of the dielectric material is removed by means of an etching process.

[0005] In I. Cortes et al., Design and optimization of different P-channel LUDMOS architectures on a 0.18 μm SOI-CMOS technology. In: Semicond. Sci. Technol., 26, 2011, 075018, a semiconductor device with a shallow-trench isolation structure is described that extends over the drift region of a transistor and is partially covered by a gate electrode.

[0006] From US 2007 / 0080387 A1 a semiconductor device with a single-transistor bit cell is known, which comprises a finFET transistor whose fin structure protrudes from a surrounding insulation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of description. Fig. 1 is a cross-sectional view of an integrated circuit in accordance with some embodiments. Fig. 2 is a flow diagram of a method of manufacturing an integrated circuit in accordance with some embodiments. Fig. 3A through 3G are cross-sectional views of an integrated circuit at various stages of fabrication in accordance with some embodiments. DETAILED DESCRIPTION

[0008] The invention provides methods for forming an integrated circuit having the features of claim 1 and 10, respectively. Preferred embodiments are set out in the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the invention. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and as such does not impose any relationship between the various embodiments and / or configurations described.

[0009] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0010] In some embodiments, a gate dielectric layer of an LDMOS or a DDDMOS includes at least two or more segments with different thicknesses. In some embodiments, the thickness of the gate dielectric layer is implemented by an insulating structure buried in the substrate and a layer of gate dielectric formed thereon. A top surface of the insulating structure is lower than a top surface of the substrate. As a result, a process window for preventing a short circuit between a conductive line and a gate electrode directly overlying the insulating structure is improved. In some embodiments, the improved process window allows for further reduction of a thickness of an interlayer dielectric (ILD) layer on which the conductive line is formed.

[0011] Fig. 1 is a cross-sectional view of an integrated circuit 100 in accordance with some embodiments. In some embodiments, the integrated circuit 100 shown in Fig. 1, an intermediate product that is further processed by one or more manufacturing processes to form a functional integrated circuit. Other active electrical components and passive electrical components of the integrated circuit 100 are shown in Fig. 1 not shown.

[0012] The integrated circuit 100 includes a substrate 110 that undergoes one or more implantation processes to form a first well 112 and a second well 114. The integrated circuit 100 also includes isolation structures 122, 124, and 126, a gate dielectric structure 132, a gate electrode structure 134, a spacer structure 135, a drain region 136, a source region 138, an etch stop layer 142, an interlayer dielectric layer (ILD) layer 152, and a conductive line 154. In some embodiments, the wells 112 and 114, the isolation structure 122, the gate dielectric structure 132, the gate electrode structure 134, the spacer structure 135, the drain region 136, and the source region 138 together form a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS in Fig. 1 is disclosed as an example. In some embodiments, the disclosed method is applicable to fabricate other types of LDMOS transistors or various types of double-diffused-drain metal-oxide-semiconductor (DDDMOS) transistors.

[0013] In some embodiments, substrate 110 comprises: an elemental semiconductor, such as silicon or germanium in a crystalline, polycrystalline, or amorphous structure; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In at least one embodiment, substrate 110 is an alloy semiconductor substrate having a gradient SiGe feature in which the Si and Ge composition changes from one ratio at one location to a different ratio at another location of the gradient SiGe feature. In another embodiment, the alloy SiGe is formed over a silicon substrate. In yet another embodiment, a SiGe substrate is strained.In some further embodiments, substrate 110 is a semiconductor-on-insulator. In some examples, substrate 110 comprises an epitaxial layer on a buried layer. In other examples, substrate 110 comprises a multilayer compound semiconductor structure.

[0014] In some embodiments, substrate 110 generally exhibits a conduction characteristic similar to that of an intrinsic semiconductor material or a semiconductor material with a predetermined doping type. In some embodiments, the predetermined doping type is a p-type doping.

[0015] The substrate 110 has a first well 112 and a second well 114 formed between isolation structures 124 and 126. The wells 112 and 114 have different types of doping. In some embodiments, when the LDMOS transistor is in Fig. 1 is an n-type transistor, the first well 112 has an n-type doping and the second well 114 has a p-type doping. In some embodiments, when the LDMOS transistor in Fig. 1 is a p-type transistor, the first well 112 has a p-type doping, and the second well 114 has an n-type doping. In some embodiments, one or more deep wells (not shown) are formed beneath the first and second wells 112 and 114 to electrically isolate the first and second wells 112 and 114 from the substrate 110.

[0016] The isolation structure 122 is buried in the first well 112 of the substrate 110. A top surface 122a of the isolation structure 122 is lower than a top surface 110a of the substrate 110. In some embodiments, a vertical distance between the top surface 122a of the isolation structure 122 and the top surface 110a of the substrate 110 is greater than or equal to 30 nm. In some embodiments, the isolation structure 122 comprises silicon oxide.

[0017] The gate dielectric structure 132 lies partially on the second well 114 of the substrate 110, partially on the first well 112 of the substrate 110, and partially on the upper surface 122a of the insulating structure 122. In some embodiments, the gate dielectric structure 132 comprises silicon oxide or a high-k dielectric. In some embodiments, the gate dielectric structure 132 has a multi-layer structure comprising one or more layers of different dielectrics. In some embodiments, the gate dielectric structure 132 is configured to have a sufficient thickness to enable the resulting transistor to have a predetermined gate-source breakdown voltage. In some embodiments, the gate electrode structure 134 of the resulting LDMOS is Fig. 1 is configured to operate at approximately 32 volts, and the gate dielectric structure 132 is configured to have a thickness in the range of 20 nm (200 Å) to 120 nm (1200 Å).

[0018] The gate electrode structure 134 overlies the gate dielectric structure 132. In some embodiments, the gate electrode structure 134 comprises polysilicon or one or more metallic materials, such as copper, aluminum, tungsten, titanium, an alloy thereof, or a combination thereof. In some embodiments, the gate electrode structure 134 has a multilayer structure. Fig. 1, an upper portion of the gate electrode structure 134 includes a silicide layer 134a. In some embodiments, the silicide layer 134a is absent. A top surface 134b of the gate electrode structure 134 has a first portion 134b-2 directly above the isolation structure 122 and a second portion 134b-1 directly above the second well 114. In some embodiments, the first portion 134b-2 of the top surface 134b is flush with or lower than the second portion 134b-1 of the top surface 134b.

[0019] Furthermore, a spacer structure comprising a first spacer 135a and a second spacer 135b lies on sidewalls of the gate dielectric structure 132 and the gate electrode structure 134. In some embodiments, the spacers 135a and 135b comprise a material comprising silicon nitride. The first spacer 135a lies over the isolation structure 122 and the second spacer 135b lies over the second well 114 and between the isolation structure 122 and the isolation structure 126. The drain region 136 lies in the first well 112 and between the isolation structure 122 and the isolation structure 124. The source region 138 lies in the second well 114 between the second spacer 135b of the spacer structure 135 and the isolation structure 126. In some embodiments, when the LDMOS transistor in Fig. 1 is an n-type transistor, the drain region 136 and the source region 138 have an n-type doping with a dopant concentration that is greater than that of the first well 112. In some embodiments, when the LDMOS transistor in Fig. 1 is a p-type transistor, the drain region 136 and the source region 138 have a p-type doping with a dopant concentration greater than that of the first well 112. An upper portion of the drain region 136 includes a silicide layer 136a. An upper portion of the source region 138 includes a silicide layer 138a. In some embodiments, the silicide layers 136a and 138a are omitted.

[0020] Furthermore, the etch stop layer 142 covers the substrate 110 and the LDMOS transistor in Fig. 1. The ILD layer 152 lies over the etch stop layer 142 and the conductive path 154 is formed on the ILD layer 152. The sectional view of Fig. 1 is taken from a position where the conductive line 154 is not in physical contact with the gate electrode structure 134, the drain region 136, or the source region 138. In some embodiments, the conductive line 154 and the gate electrode structure 134 and / or the drain region 136 and / or the source region 138 are electrically connected at a position different from that at which the cross-sectional view in Fig. 1 is recorded.

[0021] In some embodiments, since the upper surface 122a of the insulating structure 122 is lower than the upper surface 110a of the substrate 110, the first portion 134b-2 of the upper surface 134b is also lower than the second portion 134b-1 of the upper surface 134b. As a result, a vertical distance between the conductive line 154 and the gate electrode structure 134 directly above the insulating structure 122 is greater than that between the conductive line 154 and the gate electrode structure 134 directly above the second well 114. In some embodiments, the increased gap between the conductive line 154 and the gate electrode structure 134 above the insulating structure 122 provides an additional process window to prevent unwanted short circuits between the conductive line 154 and the gate electrode structure 134 due to process variations.

[0022] In some embodiments, a layout design rule for the design of the integrated circuit 100 is set to prevent the conductive lines of the same conductive layer of the conductive line 154 from crossing the second portion 134b-1 of the top surface 134b of an LSMOS transistor.

[0023] Fig. 2 is a flowchart of a method 200 for manufacturing an integrated circuit 100 in accordance with some embodiments. Fig. 3A to 3G are cross-sectional views of the integrated circuit 100 at various stages of fabrication in accordance with some embodiments. Components in the Fig. 2 and 3A to 3G, which are those in Fig. 1 have the same reference numerals and a detailed description of them is avoided. It is understood that additional operations may occur before, during and / or after the method 200 described in Fig. 2, and that some further methods can only be briefly described here.

[0024] As in Fig. 2 and Fig. 1, the method 200 begins at operation 210 in which isolation structures are formed in a substrate. The substrate includes a first well having a first doping type and a second well having a second doping type. A first isolation structure is formed in the first well, and second and third isolation structures are formed at edges of the first well and the second well. In some embodiments, the first, second, and third isolation structures are formed by performing a local oxidation of silicon (LOCOS) process or a trench isolation (STI) process. In some embodiments, operation 210 further includes forming a patterned mask to protect the second and third isolation structures from one or more of the following operations.

[0025] Fig. 3A is a cross-sectional view of an integrated circuit 100 after operation 210. A first isolation structure 310 is partially buried within a first well 112 of a substrate 110. An upper portion of the first isolation structure 310 protrudes from a top surface 110a of the substrate 110. A second isolation structure 124 is partially buried within the substrate 110 at an edge of the first well 112. A third isolation structure 126 is partially buried within the substrate 110 at an edge of the second well 114. In some embodiments, the first, second, and third isolation structures 310, 124, and 126 have approximately the same depth below the top surface 110a. The greater part of the first well 112, the second well 114, and the entire first isolation structure 310 lie between the isolation structures 124 and 126. A patterned mask 320 covers the second and third isolation structures 124 and 126.

[0026] The method 200 proceeds to operation 220, in which the first insulating structure is partially removed to form a modified insulating structure. A top surface of the modified insulating structure is lower than the top surface of the substrate. In some embodiments, operation 220 includes performing a dry oxide etching process and / or a wet oxide etching process. In some embodiments, the dry etching process includes an anisotropic carbon-fluorine gas-based etch. In some embodiments, the wet etching process includes using hydrofluoric acid, such as a buffer oxide etchant (BOE) or a buffer solution of hydrofluoric acid (BHF).

[0027] Fig. 3B is a cross-sectional view of an integrated circuit 100 after operation 220. The first isolation structure 310 has been converted into a modified isolation structure 122. A top surface 122a of the modified isolation structure 122 is lower than the top surface 110a of the substrate 110. In some embodiments, a vertical distance between the top surface 122a of the modified isolation structure 122 and the top surface 110a of the substrate 110 is greater than or equal to 30 nm (300 Å). The patterned mask 320 remains to protect the second and third isolation structures 124 and 126 from one or more subsequent operations.

[0028] The method 200 continues with operation 230 in which a gate dielectric structure is formed. The gate dielectric lies partially on a second well of the substrate, partially on the first well of the substrate, and partially on the top surface of the modified insulating structure. In some embodiments, the gate dielectric structure comprises silicon oxide, and operation 230 includes performing a thermal oxidation process. In some embodiments, the thermal oxidation is performed in a furnace at a temperature in the range of 500°C to 1100°C. In some embodiments, after the gate dielectric structure is formed, operation 230 further includes removing the patterned mask formed in operation 210.

[0029] Fig. 3C is a cross-sectional view of an integrated circuit 100 after operation 230. The gate dielectric structure 132 lies on the second well 114, the first well 112, and the top surface 122a of the isolation structure 122. The patterned mask 320 has been removed.

[0030] The method 200 proceeds to operation 240, in which a gate electrode structure is formed. The gate electrode structure overlies the gate dielectric structure. In some embodiments, the gate electrode structure comprises polysilicon or one or more metallic materials.

[0031] Fig. 3D is a cross-sectional view of an integrated circuit according to process 240. The gate electrode structure 134 lies on the gate dielectric structure 132.

[0032] In some embodiments, operation 230 and operation 240 are performed such that one or more layers of gate dielectric materials are formed on the substrate 110 and the insulating structure 122. Then, one or more layers of gate electrode materials are formed on the one or more gate dielectric materials. Finally, the one or more layers of gate dielectric materials and the one or more layers of gate electrode materials are patterned to form a gate dielectric structure 132 and a gate electrode structure 134 in Fig. 3D training.

[0033] The method 200 continues with operation 250, in which a spacer structure is formed on sidewalls of the gate dielectric structure and the gate electrode structure. In some embodiments, operation 250 includes forming a layer of spacer material over the resulting structure in Fig. 3D, followed by an anisotropic etching process. In some embodiments, the spacer structure comprises a material including silicon nitride.

[0034] Fig. 3E is a cross-sectional view of an integrated circuit 100 after operation 250. The spacer structure, including a first spacer 135a and a second spacer 135b, lies on sidewalls of the gate dielectric structure 132 and the gate electrode structure 134. The first spacer 135a lies on the insulating structure 122 over the first well. The second spacer 135b lies over the second well between the modified insulating structure 122 and the third insulating structure 126.

[0035] The method 200 proceeds to operation 260, in which a drain region is formed in the first well and a source region is formed in the second well. In some embodiments, operation 260 includes forming a mask exposing a portion of the first well to form the drain region and exposing a portion of the second well to form the source region, followed by an implantation process.

[0036] Fig. 3F is a cross-sectional view of the integrated circuit 100 after operation 260. A drain region 136 is formed in the first well 112 between the modified isolation structure 122 and the second isolation structure 124. Furthermore, a source region 138 is formed in the second well 114 between the spacer 135b and the third isolation structure 126.

[0037] The method 200 then proceeds to operation 270, in which a silicidation process is applied to the gate electrode structure, the source region, or the drain region. In some embodiments, operation 270 includes forming a layer of a metallic material on the gate electrode structure, the source region, or the drain region, followed by an annealing process to form the silicide layers and a removal process to remove any unreacted metallic material.

[0038] Fig. 3G is a cross-sectional view of an integrated circuit 100 after operation 270. An upper portion of the gate electrode 134 is converted into a silicide layer 134a. An upper portion of the drain region 136 is converted into a silicide layer 136a. Additionally, an upper portion of the source region 138 is converted into a silicide layer 138a. In some embodiments, not all of the gate electrode 134, the drain region 136, and the source region 138 are processed by the silicidation method of operation 270. In some embodiments, operation 270 is omitted.

[0039] The method 200 proceeds to operation 280, which includes forming an etch stop layer over the resulting structure of operation 270, forming an ILD layer over the etch stop layer, and forming a conductive line on the ILD layer. In some embodiments, before forming the conductive line, the ILD is selectively etched to form contact openings, and one or more contact plugs are formed in the contact openings. In some embodiments, chemical mechanical planarization (CMP) is performed along with the formation of the contact plugs.

[0040] Fig. 1 shows a cross-sectional view of an integrated circuit 100 according to operation 260.

[0041] The method 200 then proceeds to operation 290, in which additional operations are performed to form a side-diffused metal-oxide-semiconductor (LDMOS) transistor based on the modified isolation structure 122 and the gate dielectric structure 132. In some embodiments, operations 210 through 280 may also be used to form a resulting structure based on a double-diffused-drain metal-oxide-semiconductor (DDDMOS) transistor.

[0042] In accordance with one embodiment, a method comprises forming an insulating structure partially buried in a substrate. A portion of the insulating structure protrudes from a top surface of the substrate. The insulating structure is partially removed, forming a modified insulating structure. A top surface of the modified insulating structure is lower than the top surface of the substrate. A gate dielectric structure is formed to lie partially on the substrate and partially on the top surface of the modified insulating structure.

[0043] In accordance with another embodiment, a method comprises forming a first insulating structure partially buried in a first well of a substrate. The first well has a first doping type, and an upper portion of the first insulating structure protrudes from an upper surface of the substrate. The first insulating structure is partially removed, thereby forming a modified insulating structure. An upper surface of the modified insulating structure is lower than the upper surface of the substrate. A gate dielectric structure is formed to partially lie on a second well of the substrate, partially on the first well of the substrate, and partially on the upper surface of the modified insulating structure. The second well has a second doping type.

[0044] In accordance with another embodiment, a method comprises forming an insulating structure partially buried in a first well of a substrate. The first well has a first doping type, and an upper portion of the first insulating structure protrudes from an upper surface of the substrate. The first insulating structure is partially removed, thereby forming a modified insulating structure. An upper surface of the modified insulating structure is lower than the upper surface of the substrate. A gate dielectric structure is formed to partially lie on a second well of the substrate, partially on the first well of the substrate, and partially on the upper surface of the modified insulating structure. The second well has a second doping type. A gate electrode structure is formed over the gate dielectric structure.A top surface of the gate electrode structure has a first portion directly above the modified insulating structure and a second portion directly above the second well. The first portion of the top surface of the gate electrode structure is flush with or lower than the second portion of the top surface of the gate electrode structure.

Claims

[1] Procedure (200), which includes: Forming an insulating structure (310) partially buried in a substrate (110), a portion of the insulating structure (310) protruding from a top surface (110a) of the substrate (110); partially removing the insulating structure (310), thereby forming a modified insulating structure (122), wherein an upper surface (122a) of the modified insulating structure (122) is lower than the upper surface (110a) of the substrate (110); Forming a dielectric gate structure (132) lying partly on the substrate (110) and partly on the upper surface (122a) of the modified insulating structure (122); Forming a gate electrode structure (134) over the dielectric gate structure (132), wherein an upper surface (134b) of the gate electrode structure (134) has a first portion (134b-2) directly above the modified insulating structure (122) and a second portion (134b-1) different from the first portion (134b-2), and wherein the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134) is flush with or lower than the second portion (134b-1) of the upper surface (134b) of the gate electrode structure (134); and Forming a conductive path (154) over the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134), wherein the conductive path (154) is not electrically connected to the gate electrode structure (134). [2] The method (200) of claim 1, wherein a vertical distance between the upper surface (122a) of the modified insulating structure (122) and the upper surface (110a) of the substrate (110) is greater than or equal to 30 nm. [3] The method (200) of claim 1, further comprising: Forming a source region (138) and a drain region (136) in the substrate (110) after the modified insulating structure (122) has been formed. [4] The method (200) of claim 1, further comprising: Forming a spacer structure (135a, 135b) on sidewalls of the dielectric gate structure (132) and the gate electrode structure (134); and Forming a source region (138) and a drain region (136) in the substrate (110). [5] The method (200) of claim 4, further comprising: Applying a silicidation process to the gate electrode structure (134), the source region (138) or the drain region (136). [6] The method (200) of claim 1, wherein forming the isolation structure (310) comprises performing a local oxidation of silicon process, hereinafter referred to as LOCOS process, or a trench isolation process, hereinafter referred to as STI process. [7] The method (200) of claim 1, further comprising: Forming a metal oxide semiconductor transistor with a double diffused drain, hereinafter referred to as a DDDMOS transistor, or a side-diffused metal oxide semiconductor transistor, hereinafter referred to as an LDMOS transistor, based on the modified insulating structure (122) and the dielectric gate structure (132). [8] The method (200) of any preceding claim, wherein the conductive trace (154) above the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134) is not in physical contact with the gate electrode structure (134). [9] The method (200) of any preceding claim, wherein conductive traces of a conductive layer of the conductive trace (154) above the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134) are prevented from crossing the second portion (134b-1). [10] Procedure (200), which includes: Forming a first insulating structure (310) partially buried in a first well (112) of a substrate (110), the first well (112) having a first doping type and an upper portion of the first insulating structure (310) protruding from an upper surface (110a) of the substrate (110); partially removing the first insulating structure (310), thereby forming a modified insulating structure (122), wherein an upper surface (122a) of the modified insulating structure (122) is lower than an upper surface (110a) of the substrate (110); Forming a dielectric gate structure (132) lying partly on a second well (114) of the substrate (110), partly on the first well (112) of the substrate (110), and partly on the upper surface (122a) of the modified insulating structure (122), the second well (114) having a second doping type; Forming a gate electrode structure (134) over the dielectric gate structure (132), wherein an upper surface (134b) of the gate electrode structure (134) has a first portion (134b-2) directly above the modified insulating structure (122) and a second portion (134b-1) directly above the second well (114), and wherein the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134) is flush with or lower than the second portion (134b-1) of the upper surface (134b) of the gate electrode structure (134); and Forming a conductive path (154) over the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134), wherein the conductive path (154) is not electrically connected to the gate electrode structure (134). [11] The method (200) of claim 10, wherein the first doping type is an n-doping and the second doping type is a p-doping. [12] The method (200) of claim 10, wherein a vertical distance between the upper surface (122a) of the modified insulating structure (122) and the upper surface (110a) of the substrate (110) is greater than or equal to 30 nm. [13] The method (200) of claim 10, further comprising: Forming a drain region (136) in the first well (112), the drain region (136) being located between the modified insulating structure (122) and a second insulating structure (124); and Forming a source region (138) in the second well (114), the source region (138) being located between the modified insulating structure (122) and a third insulating structure (126). [14] The method (200) of claim 13, wherein forming the drain region (136) and forming the source region (138) comprises performing an implantation process associated with the first doping type. [15] The method (200) of claim 10, further comprising: Forming a spacer structure (135a, 135b) on sidewalls of the dielectric gate structure (132) and the gate electrode structure (134); Forming a drain region (136) in the first well (112), the drain region (136) being located between the modified insulating structure (122) and a second insulating structure (124); and Forming a source region (138) in the second well (114), wherein the source region (138) is located between the modified insulating structure (122) and a third insulating structure (126) and between the spacer structure (135b) and the third insulating structure (126). [16] The method (200) of claim 15, further comprising: Applying a silicidation process to the gate electrode structure (134), the source region (138) or the drain region (136). [17] The method (200) of claim 10, wherein forming the isolation structure (310) comprises performing a local oxidation of silicon process, hereinafter referred to as LOCOS process, or a trench isolation process, hereinafter referred to as STI process. [18] The method (200) of claim 10, further comprising: Forming a metal oxide semiconductor transistor with a double diffused drain, hereinafter referred to as a DDDMOS transistor, or a side-diffused metal oxide semiconductor transistor, hereinafter referred to as an LDMOS transistor, based on the modified insulating structure (122) and the dielectric gate structure (132). [19] The method (200) of any one of claims 10 to 18, wherein a vertical distance between the conductive line (154) and the gate electrode structure (134) directly above the modified insulating structure (122) is greater than that between the conductive line (154) and the gate electrode structure (134) directly above the second well (114). [20] The method (200) of any one of claims 10 to 19, wherein conductive traces of a conductive layer of the conductive trace (154) above the first portion (134b-2) of the upper surface (134b) of the gate electrode structure (134) are prevented from crossing the second portion (134b-1).

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