Stacked component and method for its manufacture

Abstract

Structure comprising: a first semiconductor column (408) extending vertically from a substrate (400) in a first region (402) and a second semiconductor column (410) extending vertically from the substrate (400) in a second region (404), wherein the first region (402) is a p-type region and the second region (404) is an n-type region; a first-level first-source / drain region (418) in the first semiconductor column (408) and a first-level second-source / drain region (420) in the second semiconductor column (410), wherein the conductivity type of the first-level second-source / drain region (420) is opposite to the conductivity type of the first-level first-source / drain region (418);a first-level gate electrode layer (428) that laterally surrounds the first and second semiconductor columns (408, 410) and is arranged vertically above the first-level first-source / drain region (418) and the first-level second-source / drain region (420), wherein a first-level dielectric gate layer (426) is layered between the first-level gate electrode layer (428) and, in the first region (402), the first semiconductor column (408), and in the second region (404), the second semiconductor column (410); a second-level first-source / drain region (440) in the first semiconductor column (408) and a second-level second-source / drain region (442) in the second semiconductor column (410), both vertically above the first-level gate electrode layer (428), wherein the Second-level first-source / drain area (440) is connected to a first power supply node (436, 444);a second-level gate electrode layer (452) that laterally surrounds the first and second semiconductor columns (408, 410) and is arranged vertically above the second-level first-source / drain region (440) and the second-level second-source / drain region (442), wherein a second-level dielectric gate layer (450) is layered between the second-level gate electrode layer (452) and in the first region (402) of the first semiconductor column (408) and in the second region of the second semiconductor column (410); a third-level first-source / drain region (466) in the first semiconductor column (408) and a third-level second-source / drain region (468) in the second semiconductor column (410), both arranged vertically above the second-level gate electrode layer (452);and a first-level metal-semiconductor interconnection area (422) that is fabricated on and / or in a first-level first junction semiconductor material (414) and a first-level second junction semiconductor material (416) and electrically connects the first-level first source / drain area (418) to the first-level second source / drain area (420), wherein the conductivity type of the first-level first junction semiconductor material (414) is opposite to the conductivity type of the first-level second junction semiconductor material (416).

Description

BACKGROUND OF THE INVENTIONFrom the actual intention of the integrated circuit, the aim of packaging more and more components into integrated circuits is of importance in the production of semiconductors. Conventional higher density circuits allow for the fabrication of increasingly high performance devices with a significant cost reduction per transistor cost. In the conventional arrangement of switching elements, these are formed side by side on the surface of a semiconductor substrate. This allows simple production and lower complexity. However, semiconductor design engineers currently combat with numerous limitations on side-by-side or lateral devices. A structure having two vertical FETs stacked on top of each other is known from JP 2011-23 543 A. Stacked structures of vertical FETs using a common semiconductor pillar are also known from US 2015 / 0 017 767 A1 and JP 2007-250 652 A. US 2012 / 0 228 677 A1 and US 2010 / 0 194 438 A1 teach local connections of vertical FETs of different conductivity types in a plane at the lower source / drain regions.The limits of lithography present a great challenge. The layers of integrated circuits are typically formed by patterning various components using photolithography. In photolithography, a layer of photosensitive material, referred to as photoresist, is deposited on the device. The photoresist is then exposed to a pattern of light corresponding to the desired patterns in a particular layer. However, the components in integrated circuits have become so small that they are only about as large as the wavelength of the light used to expose the photoresist. While various methods have been used to move this physical constraint away from all expectation, at some time this constraint becomes insurgeable. Engineers continue to develop device structures to overcome these and other physical limitations.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1-10 are cross-sectional views of intermediate steps in a process of manufacturing stacked structures for vertical gate all around (VGAA) devices, for explaining partial aspects of embodiments.Figs. 11A to 11E are superimposed layouts of different levels of the structure shown in Fig. 10. FIG. 12 is a circuit diagram of the circuit formed by the structure of FIG. 10.FIGS. 13-27 are cross-sectional views of intermediate steps in a process for manufacturing stacked structures for VGAA devices, in accordance with some embodiments.FIGS. 28A through 28E are superimposed layouts of various levels of the structure shown in FIG. 27, in accordance with some embodiments. FIG. 29 is a circuit diagram of the circuit formed by the structure of FIG. 27, in accordance with some embodiments.FIGS. 30-33 are cross-sectional views of intermediate steps in a process for fabricating stacked structures for VGAA devices, in accordance with some embodiments.FIGS. 34A through 34E are superimposed layouts of different levels of the structure shown in FIG. 33, in accordance with some embodiments. FIG. 35 is a circuit diagram of the circuit formed by the structure of FIG. 33, in accordance with some embodiments.FIGS. 36, 37, 38A, and 38B are cross-sectional views of intermediate steps in a process of manufacturing stacked structures for VGAA devices, in accordance with some embodiments.FIGS. 39A through 39E are superimposed layouts of different levels of the structure shown in FIGS. 38A and 38B, in accordance with some embodiments. FIG. 40 is a circuit diagram of the circuit formed by the structure in FIGS. 38A and 38B, in accordance with some embodiments.FIGS. 41, 42, 43A, and 43B show cross-sectional views of intermediate steps in a process for manufacturing stacked structures for VGAA devices, in accordance with some non-claimed examples.Figs. 44A to 44E are superimposed layouts of different levels of the structure shown in Figs. 43A and 43B. FIG. 45 is a circuit diagram of the circuit formed by the structure in FIGS. 43A and 43B. FIG. 46 includes example configurations that may have one or more semiconductor pillars, in accordance with some embodiments.Detailed DescriptionMoreover, spatially relative terms such as "below," "below," "lower(r)" / "lower," "above," "upper(r)" / "upper," and the like may be used herein to easily describe the relationship of an element or feature to one or more other elements or features depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or in operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly.The present invention will be described in a specific context by way of embodiments, structures using stacked VGAA transistors, for example. Some variations of the embodiments are also discussed. Concepts described herein are not limited to the fabrication of specific structures. Rather, other structures may be fabricated using the concepts described herein. Moreover, method embodiments discussed herein may be discussed as methods performed in a particular order, but other method embodiments may be performed in a logical order.FIGS. 1-10 show cross-sectional views of intermediate steps in a process for manufacturing stacked structures for VGAA devices, in accordance with some embodiments. Figs. 11A to 11E are mutually superimposed layouts of different levels of the structure shown in Fig. 10, and Fig. 12 is a circuit diagram of the circuit constituted by the structure of Fig. 10. In the discussion of these figures, general concepts for fabricating a stacked structure of a device and a circuit formed by that structure are described.Figure 1 shows a substrate 60 with mask caps 62 thereover. The substrate 60 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like. The semiconductor of the substrate 60 may be a semiconductor material such as an elemental semiconductor such as silicon, germanium, or the like; a compound or alloy semiconductor such as SiC, SiP, SiPC, GaAs, GaP, InP, InAs, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or the like; or a combination thereof. The substrate 60 may further be, for example, a wafer, which in turn may be a solid silicon wafer.Although not shown in detail, the substrate 60 may have a doped well in which the semiconductor pillars 64 of FIG. 2 are to be formed, as will be discussed later. A p-well may be fabricated for an n-type device, such as an n-type VGAA field effect transistor (FET). An n-well may be fabricated for a p-type device, such as a p-VGAA FET. The doped wells may be formed by an implantation process. Exemplary p-dopants are boron (B), BF 2 or the like, or a combination thereof. Exemplary n-dopants are arsenic (As), phosphorus (P), or the like, or a combination thereof. The doping concentration in a p- or n-well may be in the range of about 1×10 14 cm -3 to about 5×10 18 cm -3.A mask layer, such as a hard mask, is deposited on the substrate 60. The mask layer may be made of, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride, or the like, and may be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. The mask layer is patterned with openings corresponding to the semiconductor pillars to be formed, and a mask cap 62 is formed in each opening in the mask layer. The mask layer may be formed using a suitable photolithography and etching process, such as reactive ion etching (RIE), or the like. The mask caps 62 may be formed by depositing a material having a different etch selectivity than the mask layer in the openings and on the mask layer. The material of the mask caps 62 may be, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride, or the like, and may be formed by CVD, PECVD, ALD, or the like. The material for the mask caps 62 may then be planarized, such as by chemical mechanical polishing (CMP), to form the mask caps 62 such that their tops are in the same plane as the top of the mask layer. Then, the mask layer is removed with, for example, a suitable etchant that is selective to the mask layer.In FIG. 2, semiconductor pillars 64 are formed from the substrate 60. Using the mask caps 62 as a mask, the substrate 60 is recessed, such as by appropriate anisotropic etching such as RIE or the like, to form the semiconductor pillars 64. The semiconductor pillars 64 may be nanotubes, nanowires, or similar structure, and may have cross sections that are circles, squares, rectangles, ovals, ellipses, or the like in a plane parallel to the top of the substrate 60, as set forth below with reference to FIG. 46. In the illustrated embodiment, three semiconductor pillars 64 are drawn for each device fabricated in the method described herein, and in other embodiments, each transistor or device may have more or fewer semiconductor pillars, which may have a suitable shape or combination of shapes. In other embodiments, the semiconductor pillars 64 may be epitaxially grown semiconductor pillars 64. For the epitaxial growth, Si, Ge, SiGe, SiC, SiP, SiPC, a III-V material, or the like, or a combination thereof may be used. Exemplary III-V materials are InP, InAs, GaAs, AlInAs, InGaP, InGaAs, GaAsSb, GaPN, and AlPN.In FIG. 3, a first-level pad semiconductor material 66 is epitaxially grown on the substrate 60. The first-level pad semiconductor material 66 may be a crystalline material that is epitaxially grown. The first-level pad semiconductor material 66 may be an elemental semiconductor such as silicon, germanium, or the like; a compound or alloy semiconductor such as SiC, SiP, SiPC, GaAs, GaP, InP, InAs, InSb, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or the like; or a combination thereof. The epitaxial growth may be performed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), ultra high vacuum chemical vapor deposition (UHVCVD), or the like, or a combination thereof. The epitaxial growth may be anisotropic such that the growth occurs substantially only in the vertical direction and does not form substantially any nuclei on crystalline sidewalls, such as the sidewalls of the semiconductor pillars 64. in other embodiments, the first-level pad semiconductor material 66 may be deposited as an amorphous or polycrystalline material by, for example, CVD, low pressure CVD (LPCVD), MOCVD, ALD, evaporation, or the like, and may be etched back by, for example, RIE or the like.In some embodiments, the first-level pad semiconductor material 66 is in situ doped during the growth and / or deposition of the first-level pad semiconductor material 66. In other embodiments, the first-level pad semiconductor material 66 may be doped by an implantation process after growth and / or deposition. The doping concentration for the first-level pad semiconductor material 66 may be in the range of about 1×10 20 cm -3 to about 1×10 21 cm -3. The dopant may be for a p-type device such as a p-FET, a p-type dopant such as boron (B), BF 2 or the like. The dopant may be an n-type device such as an n-type FET, an n-type dopant such as arsenic (As), phosphorus (P), or the like.The structure may then be annealed to diffuse the dopants into first level source / drain regions 68 of the semiconductor pillars 64 from the first level pad semiconductor material 66. The annealing may be carried out at a temperature in the range of about 800°C to about 1100°C and for a period of time in the range of about 3600 seconds to about 1 millisecond. The doping concentration for the first-level source / drain regions 68 after the anneal may be in the range of about 5×10 19 cm -3 to about 5×10 20 cm -3. Moreover, when the first-level pad semiconductor material 66 is deposited as an amorphous material, by the annealing, the first-level pad semiconductor material 66 can be crystallized using the substrate 60 as a template for crystal orientation.In FIG. 3, spacers 70 are formed around the sidewalls of the semiconductor pillars 64 and over the first-level pad semiconductor material 66. In some embodiments, a spacer layer is conformally deposited over the substrate 60 and along the sidewalls of the semiconductor pillars 64, such that the spacer layer has substantially the same thickness throughout the layer. In some embodiments, the spacer layer is SiN, SiON, SiC, SiCN, SiOCN, or the like, or a combination thereof. The spacer layer may be deposited using a suitable deposition method, such as ALD, CVD, physical vapor deposition (PVD), or the like, or a combination thereof. The spacer layer is then anisotropically etched, for example using a plasma etching process such as RIE or the like, to remove substantially horizontal portions of the conformal spacer layer. The remaining vertical portions of the conformal spacer layer form the spacers 70 around and along the side wall(s) of the semiconductor pillars 64.In FIG. 4, a first level metal-semiconductor interconnect region 72 is formed in and / or on the first level pad semiconductor material 66. The first-level metal-to-semiconductor interconnect region 72 may be formed by depositing a metal on the first-level pad semiconductor material 66 and / or the substrate 60 and reacting the metal with the first-level pad semiconductor material 66 and / or the substrate 60. In some embodiments, the metal may be cobalt, titanium, nickel, tungsten, or the like, or a combination thereof, and may be deposited by PVD, ALD, CVD, or the like, or a combination thereof. The metal may be reacted with the semiconductor by annealing. Unreacted metal remaining after annealing can be removed using an etchant that is selective to the unreacted metal. The first-level metal-semiconductor connection region 72 may be: a silicide such as CoSi, TiSi, NiSi, WSi, or the like; a germanicide; or the like; or a combination thereof. The spacers 70 and the mask caps 62 prevent the metal from reacting with the semiconductor pillars 64 during the anneal. The first-level metal-semiconductor interconnect region 72 is formed on and / or in the exposed portions of the first-level pad semiconductor material 66. As shown, the first-level metal-semiconductor interconnect region 72 is formed in less than all exposed portions of the first-level pad semiconductor material 66 that are not under or protected by the spacers 70, and occupies less than all exposed portions of the first-level pad semiconductor material 66. In other embodiments, the first-level metal-semiconductor interconnect region 72 may be formed to a greater or lesser extent in the first-level pad semiconductor material 66 and / or the substrate 60. Then, the spacers 70 are removed with, for example, an etchant that is selective to the material of the spacers 70.In FIG. 5, a first dielectric layer 74 is formed over the first-level metal-semiconductor connection region 72 and around the semiconductor pillars 64. The first dielectric layer 74 may be silicon nitride, SiCN, or the like, deposited by CVD, PECVD, ALD, or the like. In some embodiments, the first dielectric layer 74 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surfaces of the mask caps 62 to be in a plane with the top surface of the first dielectric layer 74. Subsequently, by controlled etchback, such as anisotropic etching, the first dielectric layer 74 is etched to a corresponding thickness. The first dielectric layer 74 may serve various purposes, such as an etch stop layer for making contacts to the first level metal-semiconductor interconnect region 72 and / or a gate spacer.A first level gate dielectric layer 76 and a first level gate electrode layer 78 are formed over the first dielectric layer 74 and around the semiconductor pillars 64. The first level gate dielectric layer 76 is conformally deposited on the semiconductor pillars 64, such as over the tops of the mask caps 62 and along the sidewalls of the semiconductor pillars 64, and over the first dielectric layer 74. In some embodiments, the first level gate dielectric layer 76 is comprised of silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the first level gate dielectric layer 76 is made of a high-k dielectric material, and in these embodiments, the first level gate dielectric layer 76 may have a k value that is greater than about 7.0, or even greater than about 10.0. A high-k dielectric material may be SiON, Si 3 N 4, Ta 2 O 5, Al 2 O 3, an Hf oxide, a Ta oxide, an Al oxide, or the like, or a combination thereof. The methods of forming the first level gate dielectric layer 76 may be molecular beam deposition (MBD), ALD, CVD, or the like, or a combination thereof. Then, the first level gate electrode layer 78 is deposited over the first level gate dielectric layer 76. The first level gate electrode layer 78 may be comprised of: a metal-containing material, such as TiN, TaN, TiAl, TaAl; a Ti-containing material; a Ta-containing material; an Al-containing material; a W-containing material; TiSi; NiSi; PtSi; polysilicon with a silicide; a Cu-containing material; a refractory material; or the like; a combination thereof or multiple layers thereof. In some embodiments, the first level gate electrode layer 78 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surfaces of the first level gate electrode layer 78 to be in a plane with the top surfaces of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the first-level gate electrode layer 78 is etched to a corresponding thickness. The first level gate electrode layer 78 and the first level gate dielectric layer 76 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like. The resulting first-level gate electrode layer 78 and first-level gate dielectric layer 76 define first-level channel regions 80 in the semiconductor pillars 64.In FIG. 6, a second dielectric layer 82 is formed over the first dielectric layer 74 and the first level gate electrode layer 78 and around the semiconductor pillars 64. The second dielectric layer 82 may have, for example, a first sub-layer and a second sub-layer over the first sub-layer. The first sub-layer of the second dielectric layer 82 may be made of silicon oxide, tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, a combination thereof, or the like, which is / are manufactured by a suitable method such as CVD, PECVD, spin-on, or the like, or a combination thereof. In some embodiments, the first sub-layer of the second dielectric layer is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surface of the first sub-layer of the second dielectric layer 82 to be in a plane with the top surfaces of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the first sub-layer of the second dielectric layer 82 is etched to a corresponding thickness, such as a thickness at which the first sub-layer of the second dielectric layer 82 may overlay the first level gate electrode layer 78, or a thickness substantially equal to the thickness of the first level gate dielectric layer 76 and the first level gate electrode layer 78. The first sub-layer of the second dielectric layer 82 may serve various purposes, such as an inter-layer dielectric (ILD).The second sub-layer of the second dielectric layer 82 is then formed over the first sub-layer of the second dielectric layer 82 and the first level gate electrode layer 78. The second sub-layer of the second dielectric layer 82 may be made of silicon nitride, SiCN, or the like deposited by CVD, PECVD, ALD, or the like. In some embodiments, the second sub-layer of the second dielectric layer 82 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surfaces of the mask caps 62 to be in a plane with the top surface of the second sub-layer of the second dielectric layer 82. Subsequently, by controlled etchback, such as anisotropic etching, the second sub-layer of the second dielectric layer 82 is etched to a corresponding thickness. The second sub-layer of the second dielectric layer 82 may serve various purposes, such as an etch stop layer for making contacts to the first level gate electrode layer 78 and / or as a gate spacer.A second level pad semiconductor material 84 is deposited and patterned over the second dielectric layer 82 and around the semiconductor pillars 64. The second-level pad semiconductor material 84 may be an amorphous or polycrystalline material. The second-level pad semiconductor material 84 may be an elemental semiconductor such as silicon, germanium, or the like; a compound or alloy semiconductor such as SiC, SiP, SiPC, GaAs, GaP, InP, InAs, InSb, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or the like; or a combination thereof. The second-level pad semiconductor material 84 may be formed by CVD, deposition of a doped amorphous semiconductor followed by solid-phase epitaxial growth (SPE), epitaxial lateral growth (ELO), epitaxy, or the like. In some embodiments, the second-level pad semiconductor material 84 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surface of the second level pad semiconductor material 84 to be in a plane with the top surfaces of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the second-level pad semiconductor material 84 is etched to a corresponding thickness. The second level pad semiconductor material 84 is then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like.In some embodiments, the second-level pad semiconductor material 84 is in situ doped during the deposition of the second-level pad semiconductor material 84. In other embodiments, the second-level pad semiconductor material 84 may be doped by an implantation process after deposition. The doping concentration for the second-level pad semiconductor material 84 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The dopant may be for a p-type device such as a p-FET, a p-type dopant such as boron (B), BF 2 or the like. The dopant may be an n-type device such as an n-type FET, an n-type dopant such as arsenic (As), phosphorus (P), or the like.The structure may then be annealed to diffuse the dopants into second-level source / drain regions 86 of the semiconductor pillars 64 from the second-level pad semiconductor material 84. The annealing may be carried out at a temperature in the range of about 800°C to about 1100°C and for a period of time in the range of about 3600 seconds to about 1 millisecond. The doping concentration for the second-level source / drain regions 86 after the anneal may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Spacers 87 are then formed around the sidewalls of the semiconductor pillars 64 and over the second-level pad semiconductor material 84. In some embodiments, a spacer layer is conformally deposited over the substrate 60 and along the sidewalls of the semiconductor pillars 64, such that the spacer layer has substantially the same thickness throughout the layer. In some embodiments, the spacer layer is SiN, SiON, SiC, SiCN, SiOCN, or the like, or a combination thereof. The spacer layer may be deposited using a suitable deposition method, such as ALD, CVD, PVD, or the like, or a combination thereof. The spacer layer is then anisotropically etched, for example using a plasma etching process such as RIE or the like, to remove substantially horizontal portions of the conformal spacer layer. The remaining vertical portions of the conformal spacer layer form the spacers 87 around and along the sidewalls of the semiconductor pillars 64.In FIG. 7, a second-level metal-semiconductor interconnect region 88 is formed in and / or on the second-level pad semiconductor material 84. The second-level metal-semiconductor interconnect region 88 may be formed by depositing a metal on the second-level pad semiconductor material 84 and reacting the metal with the second-level pad semiconductor material 84. In some embodiments, the metal may be cobalt, titanium, nickel, tungsten, or the like, or a combination thereof, and may be deposited by PVD, ALD, CVD, or the like, or a combination thereof. The metal may be reacted with the semiconductor by annealing. Unreacted metal remaining after annealing can be removed using an etchant that is selective to the unreacted metal. The second-level metal-semiconductor connection region 88 may be: a silicide such as CoSi, TiSi, NiSi, WSi, or the like; a germanicide; or the like; or a combination thereof. The spacers 87 and the mask caps 62 prevent the metal from reacting with the semiconductor pillars 64 during the anneal. The second-level metal-semiconductor interconnect region 88 is formed on and / or in the exposed portions of the second-level pad semiconductor material 84. As shown, the second-level metal-semiconductor interconnect region 88 is formed in less than all exposed portions of the second-level pad semiconductor material 84 that are not under or protected by the spacers 87 and occupies less than all exposed portions of the second-level pad semiconductor material 84. In other embodiments, the second-level metal-semiconductor interconnect region 88 may be formed to a greater or lesser extent in the second-level pad semiconductor material 84. Then, the spacers 87 are removed with, for example, an etchant that is selective to the material of the spacers 87.In FIG. 8, a third dielectric layer 90 is formed over the second dielectric layer 82 and the second-level metal-semiconductor connection region 88 and around the semiconductor pillars 64. The third dielectric layer 90 may have, for example, a first sub-layer and a second sub-layer over the first sub-layer. The first sub-layer of the third dielectric layer 90 may be made of silicon oxide, TEOS, PSG, BSG, FSG, SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, a combination thereof, or the like, which is / are manufactured by a suitable method such as CVD, PECVD, spin-on, or the like, or a combination thereof. In some embodiments, the first sub-layer of the third dielectric layer 90 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surface of the first sub-layer of the third dielectric layer 90 to be in a plane with the top surfaces of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the first sub-layer of the third dielectric layer 90 is etched to a corresponding thickness, such as a thickness that the first sub-layer of the third dielectric layer 90 may overlie the second-level metal-semiconductor interconnect region 88, or a thickness that is substantially equal to the thickness of the second-level metal-semiconductor interconnect region 88. The first sub-layer of the third dielectric layer 90 may serve various purposes, such as an ILD.The second sub-layer of the third dielectric layer 90 is then formed over the first sub-layer of the third dielectric layer 90 and the second-level metal-semiconductor connection region 88. The second sub-layer of the third dielectric layer 90 may be made of silicon nitride, SiCN, or the like deposited by CVD, PECVD, ALD, or the like. In some embodiments, the second sub-layer of the third dielectric layer 90 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surfaces of the mask caps 62 to be in a plane with the top surface of the second sub-layer of the third dielectric layer 90. Subsequently, by controlled etchback, such as anisotropic etching, the second sub-layer of the third dielectric layer 90 is etched to a corresponding thickness. The second sub-layer of the third dielectric layer 90 may serve various purposes, such as an etch stop layer for making contacts to the second-level metal-semiconductor connection region 88 and / or as a gate spacer.A second-level gate dielectric layer 92 and a second-level gate electrode layer 94 are formed over the third dielectric layer 90 and around the semiconductor pillars 64. The second level gate dielectric layer 92 is conformally deposited on the semiconductor pillars 64, for example, over the top surfaces of the mask caps 62 and along the sidewalls of the semiconductor pillars 64, and over the third dielectric layer 90. In some embodiments, the second-level gate dielectric layer 92 is comprised of silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the second-level gate dielectric layer 92 is made of a high-k dielectric material, and in these embodiments, the second-level gate dielectric layer 92 may have a k value that is greater than about 7.0, or even greater than about 10.0. A high-k dielectric material may be SiON, Si 3 N 4, Ta 2 O 5, Al 2 O 3, an Hf oxide, a Ta oxide, an Al oxide, or the like, or a combination thereof. The methods of forming the second level gate dielectric layer 92 may be MBD, ALD, PECVD, or the like, or a combination thereof. Then, the second-level gate electrode layer 94 is deposited over the second-level gate dielectric layer 92. The second-level gate electrode layer 94 may be composed of: a metal-containing material, such as TiN, TaN, TiAl, TaAl; a Ti-containing material; a Ta-containing material; an Al-containing material; a W-containing material; TiSi; NiSi; PtSi; polysilicon with a silicide; a Cu-containing material; a refractory material; or the like; a combination thereof or multiple layers thereof. In some embodiments, the second-level gate electrode layer 94 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surfaces of the second level gate electrode layer 94 to be in a plane with the top surfaces of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the second-level gate electrode layer 94 is etched to a corresponding thickness. The second level gate electrode layer 94 and the second level gate dielectric layer 92 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like. The resulting second-level gate electrode layer 94 and second-level gate dielectric layer 92 define second-level channel regions 96 in the semiconductor pillars 64.A fourth dielectric layer 98 is formed over the third dielectric layer 90 and the second-level gate electrode layer 94 and around the semiconductor pillars 64. The fourth dielectric layer 98 may have, for example, a first sub-layer and a second sub-layer over the first sub-layer. The first sub-layer of the fourth dielectric layer 98 may be made of silicon oxide, TEOS, PSG, BSG, FSG, SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, a combination thereof, or the like, which is / are manufactured by a suitable method, such as CVD, PECVD, spin-on, or the like, or a combination thereof. In some embodiments, the first sub-layer of the fourth dielectric layer 98 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surface of the first sub-layer of the fourth dielectric layer 98 to be in a plane with the top surfaces of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the first sub-layer of the fourth dielectric layer 98 is etched to a corresponding thickness, such as a thickness at which the first sub-layer of the fourth dielectric layer 98 may overlie the second-level gate electrode layer 94, or a thickness substantially equal to the thickness of the stack of the second-level gate dielectric layer 92 and the second-level gate electrode layer 94. The first sub-layer of the fourth dielectric layer 98 may serve various purposes, such as an ILD.The second sub-layer of the fourth dielectric layer 98 is then formed over the first sub-layer of the fourth dielectric layer 98 and the second-level gate electrode layer 94. The second sub-layer of the fourth dielectric layer 98 may be formed of silicon nitride, SiCN, or the like deposited by CVD, PECVD, ALD, or the like. In some embodiments, the second sub-layer of the fourth dielectric layer 98 is deposited to a thickness such that it extends over the tops of the mask caps 62. Then, a planarization process such as CMP is performed to form the top surfaces of the mask caps 62 to be in a plane with the top surface of the second sub-layer of the fourth dielectric layer 98.An opening is then made through the fourth dielectric layer 98, the third dielectric layer 90, the second dielectric layer 82, and the first dielectric layer 74 for a contact 100 to the first-level metal-semiconductor connection region 72 by means of one or more etching steps. The opening may be formed using suitable photolithography and etching techniques. In the opening, a capping layer such as a diffusion barrier layer, an adhesion layer, or the like and a conductive material are deposited. The capping layer may be titanium, titanium nitride, tantalum, tantalum nitride, or the like, and is formed by ALD, CVD, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like, and is deposited by ALD, CVD, PVD, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the fourth dielectric layer 98, and to shape the tops of the fourth dielectric layer 98, the conductive material, and the capping layer to be in a plane with the tops of the mask caps 62. Subsequently, by controlled etchback, such as anisotropic etching, the second sub-layer of fourth dielectric layer 98, the conductive material, and the capping layer are etched to respective thicknesses. The second sub-layer of the fourth dielectric layer 98 may serve various purposes, such as an etch stop layer for making contacts to the second level gate electrode layer 94 and / or a spacer layer. The remaining cap layer and conductive material form the contact 100 in the opening. The contact 100 is physically and electrically connected to the first-level metal-semiconductor connection region 72. The mask caps 62 may then be removed using, for example, an etchant that is selective to the material of the mask caps 62.A third level first pad semiconductor material 102 and a third level second pad semiconductor material 104 are deposited and patterned on the fourth dielectric layer 98. The third level first pad semiconductor material 102 is deposited on and around the semiconductor pillars 64 protruding from the fourth dielectric layer 98. The third level second pad semiconductor material 104 is deposited on the contact 100. The third level first pad semiconductor material 102 and the third level second pad semiconductor material 104 may be an amorphous or polycrystalline material. The third-level first pad semiconductor material 102 and the third-level second pad semiconductor material 104 may be an elemental semiconductor such as silicon, germanium, or the like; a compound or alloy semiconductor such as SiC, SiP, SiPC, GaAs, GaP, InP, InAs, InSb, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or the like, or a combination thereof. The third-level first pad semiconductor material 102 and the third-level second pad semiconductor material 104 may be formed by CVD, deposition of a doped amorphous semiconductor with subsequent SPE, ELO, epitaxy, or the like. In some embodiments, the third level first pad semiconductor material 102 and the third level second pad semiconductor material 104 are deposited to a thickness such that they extend over the tops of the semiconductor pillars 64. Then, a planarization process such as CMP is performed to form a planar top surface of the third level first pad semiconductor material 102 and the third level second pad semiconductor material 104. The third level first pad semiconductor material 102 and the third level second pad semiconductor material 104 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like.In some embodiments, the third level first pad semiconductor material 102 and the third level second pad semiconductor material 104 are in situ doped during the deposition of the third level first pad semiconductor material 102 and the third level second pad semiconductor material 104. In other embodiments, the third level first pad semiconductor material 102 and the third level second pad semiconductor material 104 may be doped by an implantation process after deposition. The doping concentrations for the third-level first pad semiconductor material 102 and the third-level second pad semiconductor material 104 may be in the range of about 1×10 20 cm -3 to about 1×10 21 cm -3. The dopant may be for a p-type device such as a p-FET, a p-type dopant such as boron (B), BF 2 or the like. The dopant may be an n-type device such as an n-type FET, an n-type dopant such as arsenic (As), phosphorus (P), or the like.The structure may then be annealed to diffuse the dopants into third level source / drain regions 106 of the semiconductor pillars 64 from the third level first pad semiconductor material 102. The annealing may be carried out at a temperature in the range of about 800°C to about 1100°C and for a period of time in the range of about 3600 seconds to about 1 millisecond. The doping concentration for the third-level source / drain regions 106 after the anneal may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a third level first metal-semiconductor connection region 108 is formed in and / or on the third level first pad semiconductor material 102, and a third level second metal-semiconductor connection region 110 is formed in and / or on the third level second pad semiconductor material 104. The third-level first metal-semiconductor interconnect region 108 and the third-level second metal-semiconductor interconnect region 110 may be fabricated by depositing a metal on the third-level first pad semiconductor material 102 and the third-level second pad semiconductor material 104 and reacting the metal with the third-level first pad semiconductor material 102 and the third-level second pad semiconductor material 104. In some embodiments, the metal may be cobalt, titanium, nickel, tungsten, or the like, or a combination thereof, and may be deposited by PVD, ALD, CVD, or the like, or a combination thereof. The metal may be reacted with the semiconductor by annealing. Unreacted metal remaining after annealing can be removed using an etchant that is selective to the unreacted metal. The third-level first metal-semiconductor connection region 108 and the third-level second metal-semiconductor connection region 110 may be: a silicide such as CoSi, TiSi, NiSi, WSi, or the like; a germanicide; or the like; or a combination thereof. As shown, the third level first metal-semiconductor interconnect region 108 and the third level second metal-semiconductor interconnect region 110 are fabricated in less than all parts of the third level first pad semiconductor material 102 and the third level second pad semiconductor material 104, respectively, and occupy less than all parts. In other embodiments, the third-level first metal-semiconductor connection region 108 and the third-level second metal-semiconductor connection region 110 may be formed to a greater or lesser extent in the third-level first pad semiconductor material 102 and the third-level second pad semiconductor material 104.In FIG. 9, a fifth dielectric layer 112, such as an ILD, is formed over the fourth dielectric layer 98, the third-level first metal-semiconductor interconnect region 108, and the third-level second metal-semiconductor interconnect region 110, and contacts 114, 116, 118, 120, and 122 are formed into different components through different dielectric layers. The fifth dielectric layer 112 may be made of silicon oxide, TEOS, borophosphosilicate glass (BPSG), FSG, SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, a combination thereof, or the like, and is formed by a suitable method such as CVD, PECVD, spin-on, or the like, or a combination thereof. Then, a planarization process such as CMP may be performed to planarize the fifth dielectric layer 112.Openings for contacts 114, 116, 118, 120, and 122 may be formed using one or more etch steps. An opening for contact 114 is etched through fifth dielectric layer 112, fourth dielectric layer 98, and third dielectric layer 90 to second-level metal-semiconductor interconnect region 88. An opening for contact 116 is etched through fifth dielectric layer 112 to third-level first metal-semiconductor interconnect region 108. An opening for contact 118 is etched through fifth dielectric layer 112 and fourth dielectric layer 98 to second level gate electrode layer 94. An opening for contact 120 is etched through fifth dielectric layer 112, fourth dielectric layer 98, third dielectric layer 90, and second dielectric layer 82 to first level gate electrode layer 78. An opening for contact 122 is etched through fifth dielectric layer 112 to third-level second metal-semiconductor interconnect region 110. The openings may be formed using suitable photolithography and etching techniques.In the openings, a capping layer such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are deposited. The capping layer may be titanium, titanium nitride, tantalum, tantalum nitride, or the like, and is formed by ALD, CVD, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like, and is deposited by ALD, CVD, PVD, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the fifth dielectric layer 112. The remaining cap layer and conductive material form the contacts 114, 116, 118, 120, and 122 in the openings. The contact 114 is physically and electrically connected to the second-level metal-semiconductor connection region 88. The contact 116 is physically and electrically connected to the third-level first metal-semiconductor connection region 108. The contact 118 is physically and electrically connected to the second-level gate electrode layer 94. The contact 120 is physically and electrically connected to the first level gate electrode layer 78. The contact 122 is physically and electrically connected to the third-level second metal-semiconductor connection region 110.In FIG. 10, a sixth dielectric layer 124 is formed with metallizations 128, 132, 136, 140, and 144 having vias 126, 130, 134, 138, and 142, respectively, over the fifth dielectric layer 112. The sixth dielectric layer 124, such as an intermetallization dielectric (IMD), is formed over the fifth dielectric layer 112. The sixth dielectric layer 124 may be made of silicon oxide, TEOS, BPSG, FSG, SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, a combination thereof, or the like, and is formed by a suitable method, such as CVD, PECVD, spin-on, or the like, or a combination thereof. Then, a planarization process, such as CMP, may be performed to planarize the sixth dielectric layer 124.Then, recesses and openings corresponding to the metallizations 128, 132, 136, 140, and 144 and the contact holes 126, 130, 134, 138, and 142 are formed in the sixth dielectric layer 124. The recesses and openings may be formed by suitable photolithography and etching techniques. In the openings and recesses, a capping layer such as a diffusion barrier layer, an adhesion layer or the like and a conductive material are deposited. The capping layer may be titanium, titanium nitride, tantalum, tantalum nitride, or the like, and is formed by ALD, CVD, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, or the like, and is deposited by ALD, CVD, PVD, film deposition, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of the sixth dielectric layer 124. The remaining portions of the capping layer and the conductive material form metallizations 128, 132, 136, 140, and 144 with vias 126, 130, 134, 138, and 142. The contact hole 126 is physically located between the contact 114 and the metallization 128 and electrically connects the two to each other. The contact hole 130 is physically located between the contact 116 and the metallization 132 and electrically connects the two to each other. The contact hole 138 is physically located between the contact 120 and the metallization 140 and electrically connects the two to each other. The contact hole 142 is physically located between the contact 122 and the metallization 144 and electrically connects the two to each other.FIG. 10 shows a stacked device having a first device M 1 and a second device M 2. The first device M 1 is a VGAA FET in this example, having the first level source / drain regions 68, the first level channel regions 80, the second level source / drain regions 86, the first level gate dielectric layer 76, and the first level gate electrode layer 78. The second device M 2 is a VGAA FET in this example that is located over the first device M 1 and has the second-level source / drain regions 86, the second-level channel regions 96, the third-level source / drain regions 106, the second-level gate dielectric layer 92, and the second-level gate electrode layer 94. The devices M 1 and M 2 may have more or fewer semiconductor pillars 64 than shown in FIG. 10. For example, the devices M 1 and M 2 may have one semiconductor pillar 64, two semiconductor pillars 64, four semiconductor pillars 64, etc. In addition, as will be illustrated later, the first device M 1 may have a different number of semiconductor pillars 64 than the second device M 2. The first device M 1 may, for example, have one or more additional semiconductor pillars 64 with respect to the second device M 2 to produce an asymmetry between the devices M 1 and M 2 for a corresponding functionality of the devices.FIG. 10 also shows a first level source / drain SD 1, a first level gate G 1, a second level source / drain SD 2, a second level gate G 2, and a third level source / drain SD 3. The first-level source / drain SD 1 is shown drawn one above the other in FIG. 11A. The first-level gate G 1 is shown drawn one above the other in FIG. 11B. The second-level source / drain SD 2 is shown drawn one above the other in FIG. 11C. The second-level gate G 2 is shown drawn one above the other in FIG. 11D. The third-level source / drain SD 3 is shown drawn one above the other in FIG. 11E.FIG. 12 is a circuit diagram showing the structure shown in FIG. 10. The components in the circuit diagram of Fig. 12 are denoted by reference symbols corresponding to those of the structure of Fig. 10. As shown, the first and second devices M 1 and M 2 share a source / drain region 86 connected to a node 88 / 84, which may be a power supply node, such as a VDD node or a VSS node.FIGS. 13-27 show cross-sectional views of intermediate steps in a process for manufacturing stacked structures for VGAA devices, in accordance with some embodiments. Figs. 28A to 28E are mutually superimposed layouts of various levels of the structure shown in Fig. 27, and Fig. 29 is a circuit diagram of the circuit constituted by the structure of Fig. 27. The circuit formed by the structure of Fig. 7 is a NAND gate as will be explained in more detail later. A large part of the processing in FIGS. 13 to 27 is the same as the processing described in FIGS. 1 to 10, so that a large part of the description will be omitted for brevity.In FIG. 13, semiconductor pillars 208 and 210 are formed on a substrate 200 using mask caps 206 as a mask. The substrate 200 has a first region 202, such as a p-type device region, and a second region 204, such as an n-type device region. Although not shown in detail, the substrate 200 may have an n-doped well in the first region 202 and a p-doped well in the second region 204. The dopants for the individual doped wells may be the dopants set forth above, and the doping concentration in the individual doped wells may be in the range of about 1×10 12 cm -3 to about 5×10 13 cm -3. The first region 202 has semiconductor pillars 208 formed in the n-doped well in the substrate 200, and the second region 204 has semiconductor pillars 210 formed in the p-doped well in the substrate 200.In FIG. 14, a first-level first pad semiconductor material 214 is epitaxially grown on the substrate 200 in the first region 202. Prior to growth, a mask 212, such as a hard mask, is formed over the second region 204. The mask 212 may be, for example, SiN, SiON, SiCN, or the like, and is deposited by CVD, PECVD, or the like. The mask 212 may be patterned using suitable photolithography and etching techniques such that masking of the second region 204 remains while the first region 202 is exposed. While the second region 204 is covered by the mask 212, the first-level first pad semiconductor material 214 is grown in the first region 202, for example, with one of the materials and one of the methods discussed above with reference to FIG. 3. The epitaxial growth may be anisotropically performed such that the growth is substantially only in the vertical direction in the first region 202 and substantially does not form any nuclei on crystalline sidewalls, such as the sidewalls of the semiconductor pillars 208. In addition, substantially no nuclei can be formed on non-crystalline material, such as mask 212, by the epitaxial growth. After epitaxially growing the first-level first pad semiconductor material 214, the mask 212 may be removed by, for example, etching that is selective to the material of the mask 212.In FIG. 15, a first-level second pad semiconductor material 218 is epitaxially grown on the substrate 200 in the second region 204. Prior to growth, a mask 216, such as a hard mask, is formed over the first region 202. The mask 216 may be, for example, SiN, SiON, SiCN, or the like, and is deposited by CVD, PECVD, or the like. The mask 216 may be patterned using suitable photolithography and etching techniques such that masking of the first region 202 remains while the second region 204 is exposed. While the first region 202 is covered by the mask 216, the first-level second pad semiconductor material 218 is grown in the second region 204, for example, with one of the materials and one of the methods discussed above with reference to FIG. 3. The epitaxial growth may be anisotropically performed such that the growth is substantially only in the vertical direction in the second region 204 and substantially no nuclei are formed on crystalline sidewalls, such as the sidewalls of the semiconductor pillars 210. Epitaxial growth also does not allow substantially any nuclei to be formed on non-crystalline material, such as mask 216. The first-level second pad semiconductor material 218 is in physical contact with the first-level first pad semiconductor material 214. After epitaxially growing the first-level second pad semiconductor material 218, the mask 216 may be removed by, for example, an etching process selective to the material of the mask 216.In other embodiments, the first-level first pad semiconductor material 214 may be deposited as an amorphous or polycrystalline material in the first region 202 and the second region 204. The first-level first pad semiconductor material 214 may be deposited with a thickness such that it extends over the top surfaces of the mask caps 206. The first level first pad semiconductor material 214 may then be planarized, for example, by CMP. The first level first pad semiconductor material 214 is then removed from the second region 204 using, for example, a suitable photolithography and etching process. Then, the first-level second pad semiconductor material 218 may be deposited as an amorphous or polycrystalline material in the second region 204 to a thickness such that it extends over the tops of the mask caps 206 and, possibly, over the first-level first pad semiconductor material 214 in the first region 202. Then, a planarization process such as CMP is performed to form the top surfaces of the first level first pad semiconductor material 214 and the first level second pad semiconductor material 218 to be in a plane, and with the planarization process, a portion of the first level second pad semiconductor material 218 may be removed from the first region 202. Subsequently, by controlled etchback, such as anisotropic etching, the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218 are etched to a corresponding thickness. The first level first pad semiconductor material 214 and the first level second pad semiconductor material 218 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like. The first-level second pad semiconductor material 218 has physical contact with the first-level first pad semiconductor material 214.In some embodiments, the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218 are in situ doped during growth and / or deposition of the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218, respectively. In other embodiments, the first level first pad semiconductor material 214 and the first level second pad semiconductor material 218 may be doped by an implantation process after growth and / or deposition. In still further embodiments, a single growth and / or deposition process may be used to form the first level first pad semiconductor material 214 and the first level second pad semiconductor material 218 across the first region 202 and the second region 204, followed by dopant implantation processes.The first-level first pad semiconductor material 214 in the first region 202 may be doped with a p-dopant, and the doping concentration for the first-level first pad semiconductor material 214 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The first-level second pad semiconductor material 218 in the second region 204 may be doped with an n-dopant, and the doping concentration for the first-level second pad semiconductor material 218 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.The structure may then be annealed to diffuse dopants into first-level first source / drain regions 220 of the semiconductor pillars 208 in the first region 202 and diffuse dopants into first-level second source / drain regions 222 of the semiconductor pillars 210 in the second region 204. The first level first source / drain regions 220 may be doped with a p-type dopant diffused from the first level first pad semiconductor material 214, and the first level second source / drain regions 222 may be doped with an n-type dopant diffused from the first level second pad semiconductor material 218. The annealing may be carried out at a temperature in the range of about 800°C to about 1100°C, respectively, and for a time in the range of about 3600 seconds to about 1 millisecond. The doping concentration for the first level first source / drain regions 220 and the first level second source / drain regions 222 after the anneal may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3. Moreover, when the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218 are deposited as an amorphous material, by the annealing, the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218 may be crystallized using the substrate 200 as a template for crystal orientation.Spacers 224 are then formed around the sidewalls of the semiconductor pillars 208 and 210 and over the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218. A first level metal-to-semiconductor interconnect region 226 is then formed on and / or in the first level first pad semiconductor material 214 and the first level second pad semiconductor material 218. The first-level metal-semiconductor connection region 226 electrically connects the first-level first source / drain regions 220 to the first-level second source / drain regions 222 without forming a pn junction in the current flow therebetween. The first-level metal-semiconductor interconnect region 226 is formed on and / or in the exposed portions of the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218. As shown, the first-level metal-semiconductor interconnect region 226 is formed in less than all exposed portions of the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218 that are not under or protected by the spacers 224, and occupies less than all exposed portions. In other embodiments, the first-level metal-semiconductor interconnect region 226 may be formed to a greater or lesser extent in the first-level first pad semiconductor material 214 and the first-level second pad semiconductor material 218 and / or in the substrate 200. Then, the spacers 224 are removed with, for example, an etchant that is selective to the material of the spacers 224.In FIG. 17, a first dielectric layer 228 is formed over the first-level metal-semiconductor connection region 226 and around the semiconductor pillars 208 and 210. A first level gate dielectric layer 230 and a first level gate electrode layer 232 are formed over the first dielectric layer 228 and around the semiconductor pillars 208 and 210. The first level gate electrode layer 232 and the first level gate dielectric layer 230 define first level first channel regions 234 in the semiconductor pillars 208 and define first level second channel regions 236 in the semiconductor pillars 210. A second dielectric layer 238 is formed over the first dielectric layer 228 and the first level gate electrode layer 232 and around the semiconductor pillars 208 and 210.In FIG. 18, a second level first pad semiconductor material 240 is deposited over the second dielectric layer 238 and around the semiconductor pillars 208 in the first region 202. The second-level first pad semiconductor material 240 may be deposited as an amorphous or polycrystalline material in the first region 202 and the second region 204 to a thickness such that it extends over the top surfaces of the mask caps 206. The second-level first pad semiconductor material 240 may be one of the materials and deposited using any of the methods discussed above with reference to FIG. 6. The second level first pad semiconductor material 240 may then be planarized, for example, by CMP. The second level first pad semiconductor material 240 is then removed from the second region 204 using, for example, a suitable photolithography and etching process.In FIG. 19, a second-level second pad semiconductor material 242 is deposited over the second dielectric layer 238 and around the semiconductor pillars 210 in the second region 204 and, in some circumstances, on the second-level first pad semiconductor material 240 in the first region 202. The second-level second pad semiconductor material 242 may be deposited as an amorphous or polycrystalline material in the second region 204 to a thickness such that it extends over the tops of the mask caps 206 and, possibly, over the second-level first pad semiconductor material 240 in the first region 202. The second-level second pad semiconductor material 242 may be one of the materials and deposited using any of the methods discussed above with reference to FIG. 6. Then, a planarization process such as CMP is performed to form the top surfaces of the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 to be in a plane, and with the planarization process, a portion of the second-level second pad semiconductor material 242 can be removed from the first region 202.In FIG. 20, controlled etchback, such as anisotropic etching, will etch the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 to a corresponding thickness. The second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like. The second-level second pad semiconductor material 242 is physically separated from the second-level first pad semiconductor material 240.In some embodiments, the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 are in situ doped during deposition of the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242, respectively. In other embodiments, the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 may be doped by an implantation process after deposition. The second-level first pad semiconductor material 240 in the first region 202 may be doped with a p-dopant, and the doping concentration for the second-level first pad semiconductor material 240 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The second-level second pad semiconductor material 242 in the second region 204 may be doped with an n-dopant, and the doping concentration for the second-level second pad semiconductor material 242 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.The structure may then be annealed to diffuse dopants into second-level first source / drain regions 244 of the semiconductor pillars 208 in the first region 202 and diffuse dopants into second-level second source / drain regions 246 of the semiconductor pillars 210 in the second region 204. The second-level first source / drain regions 244 may be doped with a p-type dopant diffused from the second-level first pad semiconductor material 240, and the second-level second source / drain regions 246 may be doped with an n-type dopant diffused from the second-level second pad semiconductor material 242. The annealing may be carried out at a temperature in the range of about 800°C to about 1100°C, respectively, and for a time in the range of about 3600 seconds to about 1 millisecond. The doping concentration for the second-level first source / drain regions 244 and the second-level second source / drain regions 246 after the anneal may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Spacers 248 are then formed around the sidewalls of the semiconductor pillars 208 and 210 and over the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242. Subsequently, a second-level first metal-semiconductor connection region 252 is formed on and / or in the second-level first pad semiconductor material 240, and a second-level second metal-semiconductor connection region 254 is formed on and / or in the second-level second pad semiconductor material 242. Since the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 are physically separated, the second-level first metal-semiconductor connection region 252 and the second-level second metal-semiconductor connection region 254 are also physically separated. As shown, the second-level first metal-semiconductor interconnect region 252 and the second-level second metal-semiconductor interconnect region 254 are fabricated in less than all corresponding exposed portions of the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242 that are not under or protected by the spacers 248 and occupy less than all corresponding exposed portions. In other embodiments, the second-level first metal-semiconductor connection region 252 and the second-level second metal-semiconductor connection region 254 may be formed to a greater or lesser extent in the second-level first pad semiconductor material 240 and the second-level second pad semiconductor material 242. Then, the spacers 248 are removed, for example, with an etchant that is selective to the material of the spacers 248.In FIG. 22, a third dielectric layer 256 is formed over the second-level first metal-semiconductor connection region 252, the second-level second metal-semiconductor connection region 254, and the third dielectric layer 238 and around the semiconductor pillars 208 and 210. A second level gate dielectric layer 258 and a second level gate electrode layer 260 are formed over the third dielectric layer 256 and around the semiconductor pillars 208 and 210. The second-level gate electrode layer 260 and the second-level gate dielectric layer 258 define second-level first channel regions 262 in the semiconductor pillars 208 and define second-level second channel regions 264 in the semiconductor pillars 210. A fourth dielectric layer 268 is formed over the third dielectric layer 256 and the second-level gate electrode layer 260 and around the semiconductor pillars 208 and 210. A contact 270 is made to the first-level metal-semiconductor connection region 226 through the fourth dielectric layer 268, the third dielectric layer 256, the second dielectric layer 238, and the first dielectric layer 228. The contact 270 is physically and electrically connected to the first-level metal-semiconductor connection region 226.In FIG. 23, a third level first pad semiconductor material 272 is deposited over the fourth dielectric layer 268 and around the semiconductor pillars 208 in the first region 202. The third level first pad semiconductor material 272 may be deposited as an amorphous or polycrystalline material in the first region 202 and the second region 204 to a thickness such that it extends over the tops of the semiconductor pillars 208 and 210. The third level first pad semiconductor material 272 may be one of the materials and deposited using any of the methods discussed above with reference to FIG. 8. The third level first pad semiconductor material 272 may then be planarized, for example, by CMP. The third level first pad semiconductor material 272 is then removed from the second region 204 using, for example, a suitable photolithography and etching process.In FIG. 24, a third level second pad semiconductor material 274 is deposited over the fourth dielectric layer 268 and around the semiconductor pillars 210 in the second region 204 and, possibly, on the third level first pad semiconductor material 272 in the first region 202. The third level second pad semiconductor material 274 may be deposited as an amorphous or polycrystalline material in the second region 204 to a thickness such that it extends over the tops of the semiconductor pillars 210 and possibly over the third level first pad semiconductor material 272 in the first region 202. The third level second pad semiconductor material 274 may be one of the materials and deposited using any of the methods discussed above with reference to FIG. 8. Then, a planarization process such as CMP is performed to form the top surfaces of the third level first pad semiconductor material 272 and the third level second pad semiconductor material 274 to be in a plane, and with the planarization process, a portion of the third level second pad semiconductor material 274 may be removed from the first region 202.In FIG. 25, third level first pad semiconductor material 272 and third level second pad semiconductor material 274 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like. The third-level second pad semiconductor material 274 is physically separated from the third-level first pad semiconductor material 272. The third level first pad semiconductor material 272 is on and physically and electrically connected to the contact 270.In some embodiments, the third level first pad semiconductor material 272 and the third level second pad semiconductor material 274 are doped in situ during deposition of the third level first pad semiconductor material 272 and the third level second pad semiconductor material 274, respectively. In other embodiments, the third level first pad semiconductor material 272 and the third level second pad semiconductor material 274 may be doped by an implantation process after deposition. The third level first pad semiconductor material 272 in the first region 202 may be doped with a p-dopant, and the doping concentration for the third level first pad semiconductor material 272 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The third-level second pad semiconductor material 274 in the second region 204 may be doped with an n-dopant, and the doping concentration for the third-level second pad semiconductor material 272 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.The structure may then be annealed to diffuse dopants into third-level first source / drain regions 276 of the semiconductor pillars 208 in the first region 202 and diffuse dopants into third-level second source / drain regions 278 of the semiconductor pillars 210 in the second region 204. The third level first source / drain regions 276 may be doped with a p-type dopant diffused from the third level first pad semiconductor material 272, and the third level second source / drain regions 278 may be doped with an n-type dopant diffused from the third level second pad semiconductor material 274. The annealing may be carried out at a temperature in the range of about 800°C to about 1100°C, respectively, and for a time in the range of about 3600 seconds to about 1 millisecond. The doping concentration for the third-level first source / drain regions 276 and the third-level second source / drain regions 278 after annealing may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.In FIG. 26, a third level first metal-semiconductor interconnect region 280 is formed on and / or in the third level first pad semiconductor material 272, and a third level second metal-semiconductor interconnect region 282 is formed on and / or in the third level second pad semiconductor material 274. As shown, the third level first metal-semiconductor interconnect region 280 and the third level second metal-semiconductor interconnect region 282 are formed in less than all corresponding portions of the third level first pad semiconductor material 272 and the third level second pad semiconductor material 274, and occupy less than all corresponding portions. In other embodiments, the third-level first metal-semiconductor connection region 280 and the third-level second metal-semiconductor connection region 282 may be formed to a greater or lesser extent in the third-level first pad semiconductor material 272 and the third-level second pad semiconductor material 274.Next, a fifth dielectric layer 284 is formed over the fourth dielectric layer 268 and the third-level first metal-semiconductor interconnect portion 280 and the third-level second metal-semiconductor interconnect portion 282, and contacts 286, 288, 290, 292, 294 and 296 are formed into various components through various dielectric layers. The contact 286 passes through the fifth dielectric layer 284 and is physically and electrically connected to the third level first metal-semiconductor connection region 280. The contact 288 passes through the fifth dielectric layer 284, the fourth dielectric layer 268, and the third dielectric layer 256 and is physically and electrically connected to the second-level first metal-semiconductor connection region 252. The contact 292 passes through the fifth dielectric layer 284 and the fourth dielectric layer 268 and is physically and electrically connected to the second level gate electrode layer 260. The contact 294 passes through the fifth dielectric layer 284, the fourth dielectric layer 268, the third dielectric layer 256, and the second dielectric layer 238 and is physically and electrically connected to the first level gate electrode layer 232. The contact 296 passes through the fifth dielectric layer 284 and is physically and electrically connected to the third-level second metal-semiconductor connection region 282.Although the contact 288 appears to pass through the third-level first metal-semiconductor connection region 280 and the third-level first pad semiconductor material 272, it is not electrically connected to the third-level first metal-semiconductor connection region 280 and the third-level first pad semiconductor material 272; rather, the contact 288 is shown drawn one above the other in the view of FIG. 26. Likewise, although the contact 294 appears to pass through the second-level gate dielectric layer 258 and the second-level gate electrode layer 260, it is not electrically connected to the second-level gate dielectric layer 258 and the second-level gate electrode layer 260; rather, the contact 294 is shown drawn one above the other in the view of FIG. 26 to show other aspects. The location of contacts 288 and 294 can be seen more clearly in Figures 28A-28E.In FIG. 27, a sixth dielectric layer 298 is formed with metallizations 302, 306, 310, 318, and 322 having vias 300, 304, 308, 312, 316, and 320, respectively, over the fifth dielectric layer 284. The contact hole 300 is physically located between and electrically connects the contact 286 and the metallization 302. The contact hole 304 is physically located between and electrically connects the contact 288 and the metallization 306. The contact hole 308 is physically located between the contact 292 and the metallization 310 and electrically connects them to each other. The contact hole 312 is physically located between and electrically connects the contact 294 and the metallization 314. Contact hole 316 is physically located between contact 296 and metallization 318 and electrically connects them together.FIG. 27 shows a stacked device having a first p-device P 1 and a second p-device P 2 in the first region 202 and having a first n-device N 1 and a second n-device N 2 in the second region 204. The first p-type device P 1 is, in this example, a VGAA PFET having the first level first source / drain regions 220, the first level first channel regions 234, the second level first source / drain regions 244, the first level gate dielectric layer 230, and the first level gate electrode layer 232. The second p-type device P 2 is, in this example, a VGAA PFET disposed over the first p-type device P 1 and having the second-level first source / drain regions 244, the second-level first channel regions 262, the third-level first source / drain regions 276, the second-level gate dielectric layer 258, and the second-level gate electrode layer 260. The first n-type device N 1 is a VGAA NFET in this example, having the first level second source / drain regions 220, the first level second channel regions 236, the second level second source / drain regions 246, the first level gate dielectric layer 230, and the first level gate electrode layer 232. The second n-type device N 2 is, in this example, a VGAA NFET disposed over the first n-type device N 1 and having the second-level second source / drain regions 246, the second-level second channel regions 264, the third-level second source / drain regions 278, the second-level gate dielectric layer 258, and the second-level gate electrode layer 260.The devices P 1, P 2, N 1, and N 2 may have more or fewer semiconductor pillars 208 and 210 than is shown in FIG. 27. For example, devices P 1, P 2, N 1, and N 2 may have one semiconductor pillar 208 and 210, two semiconductor pillars 208 and 210, four semiconductor pillars 208 and 210, etc. Moreover, as will be shown later, the first devices P 1 and / or N 1 may have a different number of semiconductor pillars 208 and / or 210 than the corresponding second devices P 2 and / or N 2.FIG. 27 further shows a first level source / drain SD 1, a first level gate G 1, a second level source / drain SD 2, a second level gate G 2, and a third level source / drain SD 3. The first-level source / drain SD 1 is shown drawn one above the other in FIG. 28A. The first-level gate G 1 is shown drawn one above the other in FIG. 28B. The second-level source / drain SD 2 is shown drawn one above the other in FIG. 28C. The second-level gate G 2 is shown drawn one above the other in FIG. 28D. The third-level source / drain SD 3 is shown drawn one above the other in FIG. 28E.Fig. 29 is a circuit diagram of the structure shown in Fig. 27, which may be a two-input NAND gate. The components in the circuit diagram of Fig. 29 are denoted by reference symbols corresponding to those of the structure in Fig. 27. A node 252 / 240 may be a first power supply node, such as a VDD node, and a node 282 / 274 may be a second power supply node, such as a VSS node. A node 280 / 272 / 270 / 226 / 214 / 218 is an output node of the NAND gate circuit. A node 260 is a first input and a node 232 is a second input. As shown, the first and second p-type devices P 1 and P 2 are connected in parallel, and the first and second n-type devices N 1 and N 2 are connected in series. The parallel connected p-type devices P1 and P2 are connected to the series connected n-type devices N1 and N2 at the output node.FIGS. 30-33 are cross-sectional views of intermediate steps in a process for fabricating stacked structures for VGAA devices, in accordance with some embodiments. Figs. 34A to 34E are mutually superimposed layouts of different levels of the structure shown in Fig. 33, and Fig. 35 is a circuit diagram of the circuit constituted by the structure of Fig. 33. The circuit formed by the structure in Fig. 33 is a buffer circuit as will be discussed in more detail later. A large part of the processing in Figs. 30 to 33 is the same as or similar to the processing described in Figs. 1 to 10 and / or 13 to 27, so that a large part of the description is omitted for brevity.In FIG. 30, semiconductor pillars 408 and 410 are formed on a substrate 400 using mask caps 406 as a mask. The substrate 400 has a first region 402, such as a p-type device region, and a second region 404, such as an n-type device region. Although not shown in detail, the substrate 400 may have an n-doped well in the first region 402 and a p-doped well in the second region 404. The dopants for the individual doped wells may be the dopants set forth above, and the doping concentration in the individual doped wells may be in the range of about 1×10 12 cm -3 to about 5×10 13 cm -3. The first region 402 has semiconductor pillars 408 formed in the n-doped well in the substrate 400, and the second region 404 has semiconductor pillars 410 formed in the p-doped well in the substrate 400.A first level first pad semiconductor material 414 is deposited on the substrate 400 in the first region 402, and a first level second pad semiconductor material 416 is deposited on the substrate 400 in the second region 404. The first-level first pad semiconductor material 414 in the first region 402 may be doped with a p-dopant, and the doping concentration for the first-level first pad semiconductor material 414 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The first-level second pad semiconductor material 416 in the second region 404 may be doped with an n-dopant, and the doping concentration for the first-level second pad semiconductor material 416 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. First level first source / drain regions 418 are formed in the semiconductor pillars 408, and first level second source / drain regions 420 are formed in the semiconductor pillars 410. The first-level first source / drain regions 418 may be doped with a p-type dopant and the first-level second source / drain regions 420 may be doped with an n-type dopant. The doping concentration for the first level first source / drain regions 418 and the first level second source / drain regions 420 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.A first level metal-to-semiconductor interconnect region 422 is then formed on and / or in the first level first pad semiconductor material 414 and the first level second pad semiconductor material 416. The first-level metal-semiconductor connection region 422 electrically connects the first-level first source / drain regions 418 to the first-level second source / drain regions 420 without forming a pn junction in the current flow therebetween. The first-level metal-to-semiconductor interconnect region 422 may be formed to a greater or lesser extent in the first-level first pad semiconductor material 414 and the first-level second pad semiconductor material 416 and / or in the substrate 400.A first dielectric layer 424 is then formed over the first-level metal-semiconductor connection region 422 and around the semiconductor pillars 408 and 410. A first level gate dielectric layer 426 and a first level gate electrode layer 428 are formed over the first dielectric layer 424 and around the semiconductor pillars 408 and 410. The first level gate electrode layer 428 and the first level gate dielectric layer 426 define first level first channel regions 430 in the semiconductor pillars 408 and define first level second channel regions 432 in the semiconductor pillars 410. A second dielectric layer 434 is formed over the first dielectric layer 424 and the first level gate electrode layer 428 and around the semiconductor pillars 408 and 410.Subsequently, a second level first pad semiconductor material 436 is deposited over the second dielectric layer 434 and around the semiconductor pillars 408 in the first region 402, and a second level second pad semiconductor material 438 is deposited over the second dielectric layer 434 and around the semiconductor pillars 410 in the second region 404. The second-level first pad semiconductor material 436 is physically separated from the second-level second pad semiconductor material 438. The second-level first pad semiconductor material 436 in the first region 402 may be doped with a p-dopant, and the doping concentration for the second-level first pad semiconductor material 436 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The second-level second pad semiconductor material 438 in the second region 404 may be doped with an n-dopant, and the doping concentration for the second-level second pad semiconductor material 438 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. Second level first source / drain regions 440 are formed in the semiconductor pillars 408, and second level second source / drain regions 442 are formed in the semiconductor pillars 410. The second-level first source / drain regions 440 may be doped with a p-type dopant and the second-level second source / drain regions 442 may be doped with an n-type dopant. The doping concentration for the second-level first source / drain regions 440 and the second-level second source / drain regions 442 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a second-level first metal-semiconductor connection region 444 is formed on and / or in the second-level first pad semiconductor material 436, and a second-level second metal-semiconductor connection region 446 is formed on and / or in the second-level second pad semiconductor material 438. Since the second-level first pad semiconductor material 436 and the second-level second pad semiconductor material 438 are physically separated, the second-level first metal-semiconductor connection region 444 and the second-level second metal-semiconductor connection region 446 are also physically separated. The second-level first metal-semiconductor connection region 444 and the second-level second metal-semiconductor connection region 446 may be formed to a greater or lesser extent in the second-level first pad semiconductor material 436 and the second-level second pad semiconductor material 438. Then, a third dielectric layer 448 is formed over the second-level first metal-semiconductor connection region 444, the second-level second metal-semiconductor connection region 446, and the second dielectric layer 434 and around the semiconductor pillars 408 and 410.A second level gate dielectric layer 450 and a second level gate electrode layer 452 are formed over the third dielectric layer 448 and around the semiconductor pillars 408 and 410. A second level gate dielectric layer 450 is conformally deposited on the semiconductor pillars 408 and 410, for example, over the top surfaces of the mask caps 406 and along the sidewalls of the semiconductor pillars 408 and 410, and over the third dielectric layer 448. A second level gate electrode layer 452 is then deposited over the second level gate dielectric layer 450. In some embodiments, the second level gate electrode layer 452 is deposited to a thickness such that it extends over the tops of the mask caps 406. The deposition methods and materials for the second-level gate dielectric layer 450 and the second-level gate electrode layer 452 may be those discussed above with reference to FIG. 8. Then, a planarization process such as CMP is performed to form the top surfaces of the second level gate electrode layer 452 and the second level gate dielectric layer 450 to be in a plane with the top surfaces of the mask caps 406.In FIG. 31, a contact 454 to the first-level metal-semiconductor connection region 422 is formed through the second-level gate electrode layer 452, the third dielectric layer 448, the second dielectric layer 434, and the first dielectric layer 424. An opening for contact 454 is formed using one or more etching steps. The opening is formed through the second-level gate electrode layer 452, the second-level gate dielectric layer 450, the third dielectric layer 448, the second dielectric layer 434, and the first dielectric layer 424 to the first-level metal-semiconductor connection region 422. The opening may be formed using suitable photolithography and etching techniques. In the opening, a capping layer such as a diffusion barrier layer, an adhesion layer, or the like and a conductive material are deposited. The capping layer may be titanium, titanium nitride, tantalum, tantalum nitride, or the like, and is formed by ALD, CVD, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like, and is deposited by ALD, CVD, PVD, or the like. A planarization process, such as CMP, may be performed to remove excess material from the tops of the second level gate electrode layer 452 and the mask caps 406. The remaining cap layer and conductive material form the contact 454 in the opening. The contact 454 is physically and electrically connected to the second-level gate electrode layer 452 and the first-level metal-semiconductor connection region 422. Although contact 454 appears to pass through first level gate electrode layer 428, it is not electrically connected to first level gate electrode layer 428; rather, contact 454 is shown drawn over one another in the view of FIG. 31 to show further aspects.In FIG. 32, controlled etchback, such as anisotropic etching, will etch second-level gate electrode layer 452 and contact 454 to a corresponding thickness. The second level gate electrode layer 452 and the second level gate dielectric layer 450 are then patterned, for example, using a suitable photolithography and etching process, such as RIE or the like. The resulting second-level gate electrode layer 452 and the second-level gate dielectric layer 450 define second-level first channel regions 456 in the semiconductor pillars 408 and define second-level second channel regions 458 in the semiconductor pillars 410.In FIG. 33, a fourth dielectric layer 460 is formed over the third dielectric layer 448 and the second-level gate electrode layer 452 and around the semiconductor pillars 408 and 410. A third level first pad semiconductor material 462 is deposited over the fourth dielectric layer 460 and around the semiconductor pillars 408 in the first region 402, and a third level second pad semiconductor material 464 is deposited over the fourth dielectric layer 460 and around the semiconductor pillars 410 in the second region 404. The third-level second pad semiconductor material 464 is in physical contact with the third-level first pad semiconductor material 462. The third-level first pad semiconductor material 462 in the first region 402 may be doped with a p-type dopant, and the doping concentration for the third-level first pad semiconductor material 462 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The third-level second pad semiconductor material 464 in the second region 404 may be doped with an n-dopant, and the doping concentration for the third-level second pad semiconductor material 464 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. Third level first source / drain regions 466 are formed in the semiconductor pillars 408, and third level second source / drain regions 468 are formed in the semiconductor pillars 410. The third level first source / drain regions 466 may be doped with a p-type dopant and the third level second source / drain regions 468 may be doped with an n-type dopant. The doping concentration for the third-level first source / drain regions 466 and the third-level second source / drain regions 468 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a third level metal-semiconductor interconnect region 470 is formed on and / or in the third level first pad semiconductor material 462 and the third level second pad semiconductor material 464. The third-level metal-semiconductor connection region 470 electrically connects the third-level first source / drain regions 466 to the third-level second source / drain regions 468 without forming a pn junction in the current flow therebetween. The third level metal-semiconductor interconnect region 470 may be formed to a greater or lesser extent in the third level first pad semiconductor material 462 and the third level second pad semiconductor material 464.Next, a fifth dielectric layer 472 is formed over the third level metal-semiconductor connection region 470 and the fourth dielectric layer 460. Then, contacts 474, 476, 478 and 480 are formed into various components through various dielectric layers. The contact 474 passes through the fifth dielectric layer 472, the fourth dielectric layer 460, and the third dielectric layer 448 and is physically and electrically connected to the second-level first metal-semiconductor connection region 444. The contact 476 passes through the fifth dielectric layer 472 and is physically and electrically connected to the third level metal-semiconductor connection region 470. The contact 478 passes through the fifth dielectric layer 472, the fourth dielectric layer 460, the third dielectric layer 448, and the second dielectric layer 434 and is physically and electrically connected to the first level gate electrode layer 428. The contact 480 passes through the fifth dielectric layer 472, the fourth dielectric layer 460, and the third dielectric layer 448 and is physically and electrically connected to the second-level second metal-semiconductor connection region 446.Although contact 478 appears to pass through third level metal-semiconductor interconnect region 470, third level first pad semiconductor material 462, and second level gate electrode layer 452, it is not electrically connected to third level metal-semiconductor interconnect region 470, third level first pad semiconductor material 462, and second level gate electrode layer 452; rather, contact 478 is shown drawn over one another in the view of FIG. 33 to show further aspects. The location of contact 478 is more clearly seen in Figures 34A-34E.A sixth dielectric layer 482 is then formed with metallizations 486, 490, 494 and 498 with vias 484, 488, 492 and 496, respectively. Contact hole 484 is physically located between and electrically connects contact 474 and metallization 486. The contact hole 488 is physically located between and electrically connects the contact 476 and the metallization 490. The contact hole 492 is physically located between and electrically connects the contact 478 and the metallization 494. The contact hole 496 is physically located between and electrically connects the contact 480 and the metallization 498.FIG. 33 shows a stacked device having a first p-device P 1 and a second p-device P 2 in the first region 402, and having a first n-device N 1 and a second n-device N 2 in the second region 404. The first p-type device P 1 is, in this example, a VGAA PFET having the first level first source / drain regions 418, the first level first channel regions 430, the second level first source / drain regions 440, the first level gate dielectric layer 426, and the first level gate electrode layer 428. The second p-type device P 2 is, in this example, a VGAA PFET disposed over the first p-type device P 1 and having the second-level first source / drain regions 440, the second-level first channel regions 456, the third-level first source / drain regions 466, the second-level gate dielectric layer 450, and the second-level gate electrode layer 452. The first n-type device N 1 is a VGAA NFET in this example, having the first level second source / drain regions 420, the first level second channel regions 432, the second level second source / drain regions 442, the first level gate dielectric layer 426, and the first level gate electrode layer 428. The second n-type device N 2 is, in this example, a VGAA NFET disposed over the first n-type device N 1 and having the second-level second source / drain regions 442, the second-level second channel regions 458, the third-level second source / drain regions 468, the second-level gate dielectric layer 450, and the second-level gate electrode layer 452.The devices P 1, P 2, N 1, and N 2 may have more or fewer semiconductor pillars 408 and 410 than is shown in FIG. 33. For example, the devices P 1, P 2, N 1, and N 2 may have one semiconductor pillar 408 and 410, two semiconductor pillars 408 and 410, four semiconductor pillars 408 and 410, etc. Moreover, as will be shown later, the first devices P 1 and / or N 1 may have a different number of semiconductor pillars 408 and / or 410 than the corresponding second devices P 2 and / or N 2.FIG. 33 further shows a first level source / drain SD 1, a first level gate G 1, a second level source / drain SD 2, a second level gate G 2, and a third level source / drain SD 3. The first-level source / drain SD 1 is shown drawn one above the other in FIG. 34A. The first-level gate G 1 is shown drawn one above the other in FIG. 34B. The second-level source / drain SD 2 is shown drawn one above the other in FIG. 34C. The second-level gate G 2 is shown drawn one above the other in FIG. 34D. The third-level source / drain SD 3 is shown drawn one above the other in FIG. 34E.FIG. 35 is a circuit diagram of the structure shown in FIG. 33, which may be a buffer circuit. The components in the circuit diagram of Fig. 35 are denoted by reference symbols corresponding to those of the structure in Fig. 33. Respective first sources / drains of the first and second p-type devices P 1 and P 2 (node 440) are electrically connected to a node 444 / 436, which may be a first power supply node, such as a VDD node. A second source / drain of the first p-type device (node 418) is electrically connected to a first source / drain of the first n-type device N1 (node 420). The gates of the first p-type device P 1 and the first n-type device N 1 are interconnected at a node 428, an input node. A second source / drain of the second p-type device P2 (node 466) is electrically connected to a first source / drain of the second n-type device N2 (node 468) at a node 470, an input node. The gates of the second p-type device P2 and the second n-type device N2 are connected together (node 452) and are connected to the second source / drain of the first n-type device N1 (node 420) and the first source / drain of the first p-type device P1 (node 418) by a node 422 / 454. The respective second sources / drains of the first and second n devices N 1 and N 2 (node 442) are electrically connected to a node 446 / 438, which may be a second power supply node, such as a VSS node.FIGS. 36, 37, 38A, and 38B show cross-sectional views of intermediate steps in a process for fabricating structures for stacked VGAA devices, in accordance with some embodiments. Figs. 39A to 39E are mutually superimposed layouts of different levels of the structure shown in Figs. 38A and 38B, and Fig. 40 is a circuit diagram of the circuit constituted by the structure shown in Figs. 38A and 38B. The circuit formed by the structure in Figs. 38A and 38 is a NAND gate as will be explained in more detail later. A large part of the processing in FIGS. 36, 37, 38A, and 38B is the same as or similar to the processing described in FIGS. 1 to 10, 13 to 27, and / or 30 to 33, so a large part of the description is omitted for brevity. FIGS. 36, 37 and 38A show a first sectional view A-A during machining, and FIG. 38B shows a second sectional view B-B in the manufactured structure. The sectional views A-A and B-B are shown in Figs. 39A to 39E.In FIG. 36, a separation region 502 is formed in a substrate 500. The separation region 502 separates at least a portion of a first region 504 of the substrate 500 from a second region 506 of the substrate 500. Although not shown in detail, the substrate 500 may have an n-doped well in the first region 504 and a p-doped well in the second region 506. The dopants for the individual doped wells may be the dopants set forth above, and the doping concentration in the individual doped wells may be in the range of about 1×10 12 cm -3 to about 5×10 13 cm -3.A mask layer 508, such as a hard mask, is deposited on the substrate 500. The mask layer 508 may be made of, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride, or the like, and may be formed by CVD, PECVD, ALD, or the like. The mask layer 508 is then patterned to expose the substrate 500, and a recess or trench is etched into the substrate 500. For the patterning and etching, a suitable photolithography and etching method, such as RIE or the like, may be used.The recess in the substrate 500 is then filled with a dielectric material to form the separation region 502. The separation region 502 may also be referred to as a trench isolation region. The separation region 502 may be made of silicon oxide deposited with a high density plasma, for example, but other dielectric materials deposited with various methods may also be used. A planarization process, such as CMP, may be performed to remove excess dielectric material and form the top surface of the isolation region 502 to be in a plane with the top surface of the mask layer 508. In other embodiments, the separation regions may be formed by thermal oxidation to grow a dielectric material such as silicon oxide.The mask layer 508 is then patterned with openings corresponding to channel structures to be formed, and a mask cap 510 is formed in each opening in the mask layer 508. The mask layer 508 may be patterned using a suitable photolithography and etching process, such as RIE or the like. The mask caps 510 may be formed by depositing a material having a different etch selectivity than the mask layer 508 in the openings and on the mask layer 508. The material for the mask caps 510 may be, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride, or the like, and may be deposited by CVD, PECVD, ALD, or the like. The material for the mask caps 510 may then be planarized, for example, by CMP, to form the tops of the mask caps 510 to be in a plane with the top of the mask layer 508.Then, the mask layer 508 is removed, for example, with a suitable etchant that is selective to the mask layer 508. As shown in FIG. 37, semiconductor pillars 512 and 514 (see FIG. 38B ) are formed in the n-doped well in the substrate 500 in the first region 504, and semiconductor pillars 516 and 518 (see FIG. 38B ) are formed in the p-doped well in the substrate 500 in the second region 506. Using the mask caps 510 as a mask, the substrate 500 is recessed, such as by corresponding anisotropic etching such as RIE or the like, to form the semiconductor pillars 512, 514, 516, and 518.A dielectric filler layer (not shown) is formed on the substrate 500 and around the semiconductor pillars 512, 514, 516 and 518. In some embodiments, the dielectric filler layer is an oxide formed by flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system) and post-curing, such as annealing. In other embodiments, the dielectric filler layer may be formed by another deposition method, such as CVD, PECVD, or the like, or a combination thereof, and may be a dielectric material, such as silicon oxide, PSG, BSG, BPSG, undoped silicate glass (USG), a nitride, oxynitride, or the like. CMP may be performed after the deposition to planarize the dielectric filler layer such that its top surface is in a plane with the top surface of the mask caps 510 and the separation region 502. Then, the dielectric filler layer and the separation region 502 are etched back, for example, using a suitable etching method such as RIE or the like, thereby removing the dielectric filler layer while leaving the separation region 502 as shown in FIG. 37.A first-level first pad semiconductor material 520 is deposited on the substrate 500 in the first region 504 and around the semiconductor pillars 512 and 514. A first-level second pad semiconductor material 522 is deposited on the substrate 500 in the second region 506 and around the semiconductor pillars 516. And a first-level third pad semiconductor material 524 is deposited on the substrate 500 in the second region 506 and around the semiconductor pillars 518. The first-level first pad semiconductor material 520 and the first-level third pad semiconductor material 524 are physically connected. A first-level second pad semiconductor material 522 is physically separated from the first-level first pad semiconductor material 520 and the first-level third pad semiconductor material 524. For example, during epitaxial growth, the pad semiconductor material may form substantially no seeds in the separation region 502 such that the first-level second pad semiconductor material 522 is physically separated from the first-level first pad semiconductor material 520 and the first-level third pad semiconductor material 524. In other embodiments, the first-level second pad semiconductor material 522 may be patterned to be separated from the first-level first pad semiconductor material 520 and the first-level third pad semiconductor material 524.The first-level first pad semiconductor material 520 in the first region 504 may be doped with a p-type dopant, and the doping concentration in the first-level first pad semiconductor material 520 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The first-level second pad semiconductor material 522 and the first-level third pad semiconductor material 524 in the second region 506 may be doped with an n-dopant, and the doping concentration in the first-level second pad semiconductor material 522 and the first-level third pad semiconductor material 524 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. First level first source / drain regions 526 are formed in the semiconductor pillars 512, first level second source / drain regions 528 are formed in the semiconductor pillars 514, first level third source / drain regions 530 are formed in the semiconductor pillars 516, and first level fourth source / drain regions 532 are formed in the semiconductor pillars 518. The first level first source / drain regions 526 and the first level second source / drain regions 528 may be doped with a p-type dopant, and the first level third source / drain regions 530 and the first level fourth source / drain regions 532 may be doped with an n-type dopant. The doping concentration for the first level first source / drain regions 526, the first level second source / drain regions 528, the first level third source / drain regions 530, and the first level fourth source / drain regions 532 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a first level first metal-semiconductor interconnect region 534 is formed on and / or in the first level first pad semiconductor material 520 and the first level third pad semiconductor material 524, and a first level second metal-semiconductor interconnect region 536 is formed on and / or in the first level second pad semiconductor material 522. The first-level first metal-semiconductor connection region 534 together electrically connects the first-level first source / drain regions 526, the first-level second source / drain regions 528, and the first-level fourth source / drain regions 532 to a pn junction arising in the current flow therebetween. Because the first-level first pad semiconductor material 520 and the first-level third pad semiconductor material 524 are physically separated from the first-level second pad semiconductor material 522, the first-level first metal semiconductor connection region 534 is also physically separated from the first-level second metal semiconductor connection region 536. The first-level metal-semiconductor interconnect region 534 and the first-level second metal-semiconductor interconnect region 536 may be fabricated to a greater or lesser extent in the corresponding first-level first pad semiconductor material 520, the first-level second pad semiconductor material 522 and the first-level third pad semiconductor material 524 and / or the substrate 500.A first dielectric layer 538 is then formed over the first-level metal-semiconductor interconnect region 534 and the first-level second metal-semiconductor interconnect region 536 and around the semiconductor pillars 512, 514, 516 and 518. A first level first gate dielectric layer 540 and a first level first gate electrode layer 544 are formed over the first dielectric layer 538 and around the semiconductor pillars 512 and 516, and a first level second gate dielectric layer 542 and a first level second gate electrode layer 546 are formed over the first dielectric layer 538 and around the semiconductor pillars 514 and 518. The first level first gate dielectric layer 540 and the first level second gate dielectric layer 542 may be formed in same processing steps, and the first level first gate electrode layer 544 and the first level second gate electrode layer 546 may also be formed in same processing steps. The first level first gate electrode layer 544 and the first level first gate dielectric layer 540 define first level first channel regions 548 in the semiconductor pillars 512 and define first level third channel regions 552 in the semiconductor pillars 516. The first level second gate electrode layer 546 and the first level second gate dielectric layer 542 define first level second channel regions 550 in the semiconductor pillars 514 and define first level fourth channel regions 554 in the semiconductor pillars 518. A second dielectric layer 556 is formed over the first dielectric layer 538, the first level first gate electrode layer 544, and the first level second gate electrode layer 546 and around the semiconductor pillars 512, 514, 516, and 518. A contact 558 is formed through the second dielectric layer 556 and the first dielectric layer 538 to the first-level second metal-semiconductor connection region 536. The contact 558 is physically and electrically connected to the first-level second metal-semiconductor connection region 536.A second-level first pad semiconductor material 560 is formed over the second dielectric layer 556 in the first region 504 and around the semiconductor pillars 512 and 514. A second-level second pad semiconductor material 562 is deposited over the second dielectric layer 556 in the second region 506 and around the semiconductor pillars 516, and a second-level third pad semiconductor material 564 is deposited over the second dielectric layer 556 in the second region 506, around the semiconductor pillars 518, and on the contact 558. The second-level first pad semiconductor material 560 in the first region 504 may be doped with a p-dopant, and the doping concentration for the second-level first pad semiconductor material 560 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The second-level second pad semiconductor material 562 and the second-level third pad semiconductor material 564 in the second region 506 may be doped with an n-dopant, and the doping concentration for the second-level second pad semiconductor material 562 and the second-level third pad semiconductor material 564 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The second-level first pad semiconductor material 560, the second-level second pad semiconductor material 562, and the second-level third pad semiconductor material 564 are physically separated from each other. Second level first source / drain regions 566 are formed in the semiconductor pillars 512, second level second source / drain regions 568 are formed in the semiconductor pillars 514, second level third source / drain regions 570 are formed in the semiconductor pillars 516, and second level fourth source / drain regions 572 are formed in the semiconductor pillars 518. The second-level first source / drain regions 566 and the second-level second source / drain regions 568 may be doped with a p-type dopant, and the second-level third source / drain regions 570 and the second-level fourth source / drain regions 572 may be doped with an n-type dopant. The doping concentration for the second-level first source / drain regions 566, the second-level second source / drain regions 568, the second-level third source / drain regions 570, and the second-level fourth source / drain regions 572 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a second-level first metal-semiconductor connection region 574 is formed on and / or in the second-level first pad semiconductor material 560, a second-level second metal-semiconductor connection region 578 is formed on and / or in the second-level second pad semiconductor material 562, and a second-level third metal-semiconductor connection region 580 is formed on and / or in the second-level third pad semiconductor material 564. Since the second-level first pad semiconductor material 560, the second-level second pad semiconductor material 562, and the second-level third pad semiconductor material 564 are physically separated from each other, the second-level first metal semiconductor connection region 574, the second-level second metal semiconductor connection region 578, and the second-level third metal semiconductor connection region 580 are also physically separated from each other. The second-level first metal-semiconductor connection region 574, the second-level second metal-semiconductor connection region 578 and the second-level third metal-semiconductor connection region 580 may be formed to a greater or lesser extent in the corresponding second-level first pad semiconductor material 560, the second-level second pad semiconductor material 562 and the second-level third pad semiconductor material 564.Next, a third dielectric layer 582 is formed over the second dielectric layer 556, the second-level first metal-semiconductor connection region 574, the second-level second metal-semiconductor connection region 578 and the second-level third metal-semiconductor connection region 580 and around the semiconductor pillars 512, 514, 516 and 518. A second level first gate dielectric layer 584 and a second level first gate electrode layer 588 are formed over the third dielectric layer 582 and around the semiconductor pillars 512 and 516, and a second level second gate dielectric layer 586 and a second level second gate electrode layer 590 are formed over the third dielectric layer 582 and around the semiconductor pillars 514 and 518. The second-level first gate dielectric layer 584 and the second-level second gate dielectric layer 586 may be formed in equal processing steps, and the second-level first gate electrode layer 588 and the second-level second gate electrode layer 590 may also be formed in equal processing steps. The second-level first gate electrode layer 588 and the second-level first gate dielectric layer 584 define second-level first channel regions 594 in the semiconductor pillars 512 and define second-level third channel regions 598 in the semiconductor pillars 516. The second level second gate electrode layer 590 and the second level second gate dielectric layer 586 define second level second channel regions 596 in the semiconductor pillars 514 and second level fourth channel regions 600 in the semiconductor pillars 518. A contact 592 is formed through the second level second gate electrode layer 590, the second level second gate dielectric layer 586, the third dielectric layer 582 and the second dielectric layer 556 to the first level second gate electrode layer 546. The contact 592 is physically and electrically connected to the second level second gate electrode layer 590 and the first level second gate electrode layer 546. A fourth dielectric layer 602 is formed over the third dielectric layer 582, the second level first gate electrode layer 588, and the second level second gate electrode layer 590 and around the semiconductor pillars 512, 514, 516, and 518. A contact 604 is formed through the fourth dielectric layer 602, the third dielectric layer 582, the second dielectric layer 556, and the first dielectric layer 538 to the first-level first metal-semiconductor connection region 534. The contact 604 is physically and electrically connected to the first-level first metal-semiconductor connection region 534.A third level first pad semiconductor material 610 is formed over the fourth dielectric layer 602 in the first region 504, around the semiconductor pillars 512 and 514, and on the contact 604. A third level second pad semiconductor material 612 is deposited over the fourth dielectric layer 602 in the second region 506 and around the semiconductor pillars 516, and a third level third pad semiconductor material 614 is deposited over the fourth dielectric layer 602 in the second region 506 and around the semiconductor pillars 518. The third level first pad semiconductor material 610, the third level second pad semiconductor material 612, and the third level third pad semiconductor material 614 are physically separated from each other. The third level first pad semiconductor material 610 in the first region 504 may be doped with a p-dopant, and the doping concentration for the third level first pad semiconductor material 610 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The third-level second pad semiconductor material 612 and the third-level third pad semiconductor material 614 in the second region 506 may be doped with an n-dopant, and the doping concentration for the third-level second pad semiconductor material 612 and the third-level third pad semiconductor material 614 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. Third level first source / drain regions 616 are formed in the semiconductor pillars 512, third level second source / drain regions 618 are formed in the semiconductor pillars 514, third level third source / drain regions 620 are formed in the semiconductor pillars 516, and third level fourth source / drain regions 622 are formed in the semiconductor pillars 518. The third level first source / drain regions 616 and the third level second source / drain regions 618 may be doped with a p-type dopant, and the third level third source / drain regions 620 and the third level fourth source / drain regions 622 may be doped with an n-type dopant. The doping concentration for the third level first source / drain regions 616, the third level second source / drain regions 618, the third level third source / drain regions 620, and the third level fourth source / drain regions 622 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a third level first metal-semiconductor connection region 624 is formed on the third level first pad semiconductor material 610, a third level second metal-semiconductor connection region 626 is formed on the third level second pad semiconductor material 612, and a third level third metal-semiconductor connection region 628 is formed on the third level third pad semiconductor material 614. Because the third-level first pad semiconductor material 610, the third-level second pad semiconductor material 612, and the third-level third pad semiconductor material 614 are physically separated from each other, the third-level first metal semiconductor connection region 624, the third-level second metal semiconductor connection region 626, and the third-level third metal semiconductor connection region 628 are also physically separated from each other. The third-level first metal-semiconductor connection region 624, the third-level second metal-semiconductor connection region 626, and the third-level third metal-semiconductor connection region 628 may be formed to a greater or lesser extent in the corresponding third-level first pad semiconductor material 610, third-level second pad semiconductor material 612, and third-level third pad semiconductor material 614.Next, a fifth dielectric layer 630 is formed over the fourth dielectric layer 556, the third level first metal-semiconductor interconnect portion 624, the third level second metal-semiconductor interconnect portion 626, and the third level third metal-semiconductor interconnect portion 628. Then contacts 632, 634, 636, 638, 640, 642, 644 and 646 are formed through different dielectric layers into different components. The contact 632 passes through the fifth dielectric layer 630 and is physically and electrically connected to the third-level first metal-semiconductor connection region 624. The contact 634 passes through the fifth dielectric layer 630 and the fourth dielectric layer 602 and is physically and electrically connected to the second level first gate electrode layer 588. The contact 636 passes through the fifth dielectric layer 630, the fourth dielectric layer 602, the third dielectric layer 582, and the second dielectric layer 556 and is physically and electrically connected to the first level first gate electrode layer 544. The contact 638 passes through the fifth dielectric layer 630 and is physically and electrically connected to the third-level second metal-semiconductor connection region 626. The contact 640 passes through the fifth dielectric layer 630, the fourth dielectric layer 602, and the third dielectric layer 582 and is physically and electrically connected to the second-level first metal semiconductor connection region 574. The contact 642 passes through the fifth dielectric layer 630 and the fourth dielectric layer 602 and is physically and electrically connected to the second level second gate electrode layer 590 and / or the contact 592. The contact 644 is a bump contact in the fifth dielectric layer 630 and is physically and electrically connected to the third-level first metal-semiconductor connection region 624 and the third-level third metal-semiconductor connection region 628. The contact 646 passes through the fifth dielectric layer 630 and is physically and electrically connected to the third-level third metal-semiconductor connection region 628.Although contact 636 appears to pass through second-level first gate electrode layer 588, it is not electrically connected to second-level first gate electrode layer 588; rather, contact 636 is shown drawn over one another in the view of FIG. 38A to show further aspects. Although contact 642 appears to pass through contact 644, it is not electrically connected to node 644; rather, contact 642 is shown drawn over one another in the view of FIG. 38B to show further aspects. The location of contacts 636 and 644 will be more clearly seen in Figures 39A-39E.Next, a sixth dielectric layer 650 having metallizations 654, 658, 662, 666, 670, 674 and 678 having vias 652, 656, 660, 664, 668, 672 and 676, respectively, is formed over the fifth dielectric layer 630. The contact hole 652 is physically located between and electrically connects the contact 632 and the metallization 654. The contact hole 656 is physically located between and electrically connects the contact 634 and the metallization 658. The contact hole 664 is physically located between the contact 638 and the metallization 666 and electrically connects them to each other. The contact hole 668 is physically located between the contact 640 and the metallization 670 and electrically connects them to each other. The contact hole 672 is physically located between and electrically connects the contact 642 and the metallization 674. The contact hole 676 is physically located between and electrically connects the contact 646 and the metallization 678.FIGS. 38A and 38B show a stacked device having a first p-type device P 1, a second p-type device P 2, and a third p-type device P 3 in the first region 504, and having a first n-type device N 1, a second n-type device N 2, and a third n-type device N 3 in the second region 506. The first p-type device P 1 is, in this example, a VGAA PFET having the first level second source / drain regions 528, the first level second channel regions 550, the second level second source / drain regions 568, the second level second channel regions 596, the third level second source / drain regions 618, the first level second gate dielectric layer 542, the first level second gate electrode layer 546, the second level second gate dielectric layer 586, and the second level second gate electrode layer 590. The second p-type device P 2 is a VGAA PFET in this example, having the first level first source / drain regions 526, the first level first channel regions 548, the second level first source / drain regions 566, the first level first gate dielectric layer 540, and the first level gate electrode layer 544. The third p-type device P 3 is, in this example, a VGAA PFET that is over the second p-type device P 2 and has the second-level first source / drain regions 566, the second-level first channel regions 594, the third-level first source / drain regions 616, the second-level first gate dielectric layer 584, and the second-level first gate electrode layer 588. In this configuration, since the first p-type device P 1 has the first-level second channel regions 550 and the second-level second channel regions 596, the first p-type device P 1 has an effective channel width that is twice as large as the corresponding effective channel width of the second p-type device P 2 and the third p-type device P 3.The first n-type device N 1 is a VGAA NFET in this example, having the first level fourth source / drain regions 532, the first level fourth channel regions 554, the second level fourth source / drain regions 572, the second level fourth channel regions 600, the third level fourth source / drain regions 622, the first level second gate dielectric layer 542, the first level second gate electrode layer 546, the second level second gate dielectric layer 586, and the second level second gate electrode layer 590. The first level fourth source / drain regions 532 and the third level fourth source / drain regions 622 in the first n-type device N 1 are electrically connected to each other via a third level third metal-semiconductor connection region 628, a contact 644, a third level first metal-semiconductor connection region 624, a contact 604, and a first level first metal-semiconductor connection region 534. The second n-type device N 2 is a VGAA NFET in this example, having the first level third source / drain regions 530, the first level third channel regions 552, the second level third source / drain regions 570, the first level gate dielectric layer 540, and the first level first gate electrode layer 544. The third n-type device N 3 is, in this example, a VGAA NFET disposed over the second n-type device N 2 and having the second-level third source / drain regions 570, the second-level third channel regions 598, the third-level third source / drain regions 620, the second-level first gate dielectric layer 584, and the second-level first gate electrode layer 588. In this configuration, since the first n-type device N 1 has the first-level fourth channel regions 554 and the second-level fourth channel regions 600, the first n-type device N 1 has an effective channel width that is twice as large as the corresponding effective channel width of the second n-type device N 2 and the third n-type device N 3.The devices P 1, P 2, P 3, N 1, N 2, and N 3 may have more or fewer semiconductor pillars 512, 514, 516, and 518 than shown in FIGS. 38A and 38B. For example, the devices P 1, P 2, P 3, N 1, N 2, and N 3 may have one semiconductor pillar 512, 514, 516, or 518, two semiconductor pillars 512, 514, 516, or 518, four semiconductor pillars 512, 514, 516, or 518, etc. Moreover, as will be shown later, the devices may have a different number of semiconductor pillars 512, 514, 516 and / or 518 than other devices.FIGS. 38A and 38B further show a first level source / drain SD 1, a first level gate G 1, a second level source / drain SD 2, a second level gate G 2, and a third level source / drain SD 3. The first-level source / drain SD 1 is shown drawn one above the other in FIG. 39A. The first-level gate G 1 is shown drawn one above the other in FIG. 39B. The second-level source / drain SD 2 is shown drawn one above the other in FIG. 39C. The second-level gate G 2 is shown drawn one above the other in FIG. 39D. The third-level source / drain SD 3 is shown drawn one above the other in FIG. 39E. Figs. 39A to 39E show the cross section A-A shown in Fig. 38A and the cross section B-B shown in Fig. 38B.FIG. 40 is a circuit diagram of the structure shown in FIGS. 38A and 38B, which may be a three-input NAND gate. The components in the circuit diagram of Fig. 40 are denoted by reference symbols corresponding to those of the structure in Figs. 38A and 38B. A node 560 / 574 may be a first power supply node, such as a VDD node, and a node 612 / 626 may be a second power supply node, such as a VSS node. A node 520 / 524 / 534 / 604 / 610 / 624 / 644 / 614 / 628 is an output node of the NAND gate circuit. Node 590 / 546 is a first input, node 544 is a second input, and node 588 is a third input. As shown, the first, second, and third p-type devices P 1, P 2, and P 3 are connected in parallel, and the first, second, and third n-type devices N 1, N 2, and N 3 are connected in series. The parallel-connected p-type devices P1, P2 and P3 are connected to the series-connected n-type devices N1, N2 and N3 at the output node.FIGS. 41, 42, 43A, and 43B are sectional views of intermediate steps in a process of manufacturing stacked structures. Figs. 44A to 44E are mutually superimposed layouts of different levels of the structure shown in Figs. 43A and 43B, and Fig. 45 is a circuit diagram of the circuit constituted by the structure shown in Figs. 43A and 43B. The circuit formed by the structure in Figs. 43A and 43B is a NAND gate, as will be discussed in more detail later. A large part of the processing in FIGS. 41, 42, 43A, and 43B is the same as or similar to the processing described in FIGS. 1 to 10, 13 to 27, 30 to 33, and / or 36 to 38B, so that a large part of the description is omitted for brevity. FIGS. 41, 42 and 43A show a first sectional view A-A in the machining, and FIG. 43B shows a second sectional view B-B of the manufactured structure. The sectional views A-A and B-B are shown in Figs. 44A to 44E.A separation region 702 is formed in a substrate 700. The separation region 702 separates at least a portion of a first region 704 of the substrate 700 from a second region 706 of the substrate 700. Although not shown in detail, the substrate 700 may have an n-doped well in the first region 704 and a p-doped well in the second region 706. The dopants for the individual doped wells may be the dopants set forth above, and the doping concentration in the individual doped wells may be in the range of about 1×1012cm-3to about 5×1013cm -3. Semiconductor pillars 712 and 714 (see FIG. 43B ) are fabricated in the n-doped well in the substrate 700 in the first region 704, and semiconductor pillars 716 and 718 (see FIG. 43B ) are fabricated in the p-doped well in the substrate 700 in the second region 706.A first level first pad semiconductor material 720 is deposited on the substrate 700 in the first region 704 and around the semiconductor pillars 712 and 714, and a first level second pad semiconductor material 722 is deposited on the substrate 700 in the second region 706 and around the semiconductor pillars 716 and 718. The first-level second pad semiconductor material 722 is physically separated from the first-level first pad semiconductor material 720. The first-level first pad semiconductor material 720 in the first region 704 may be doped with a p-dopant, and the doping concentration for the first-level first pad semiconductor material 720 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The first-level second pad semiconductor material 722 in the second region 706 may be doped with an n-dopant, and the doping concentration for the first-level second pad semiconductor material 722 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. First level first source / drain regions 724 are formed in the semiconductor pillars 712, first level second source / drain regions 726 are formed in the semiconductor pillars 714, first level third source / drain regions 728 are formed in the semiconductor pillars 716, and first level fourth source / drain regions 730 are formed in the semiconductor pillars 718. The first level first source / drain regions 724 and the first level second source / drain regions 726 may be doped with a p-type dopant, and the first level third source / drain regions 728 and the first level fourth source / drain regions 730 may be doped with an n-type dopant. The doping concentration for the first level first source / drain regions 724, the first level second source / drain regions 726, the first level third source / drain regions 728, and the first level fourth source / drain regions 730 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a first level first metal-semiconductor connection region 732 is formed on and / or in the first level first pad semiconductor material 720, and a first level second metal-semiconductor connection region 734 is formed on and / or in the first level second pad semiconductor material 722. The first-level first metal-semiconductor connection region 732 electrically connects the first-level first source / drain regions 724 to the first-level second source / drain regions 726. The first-level second metal-semiconductor connection region 734 electrically connects the first-level third source / drain regions 728 to the first-level fourth source / drain regions 730. Since the third-level first pad semiconductor material 720 and the first-level second pad semiconductor material 722 are physically separated from each other, the first-level first metal-semiconductor connection region 732 is also physically separated from the first-level second metal-semiconductor connection region 734. The first-level first metal-semiconductor interconnect region 732 and the first-level second metal-semiconductor interconnect region 734 may be formed to a greater or lesser extent in the corresponding first-level first pad semiconductor material 720 and the first-level second pad semiconductor material 722 and / or the substrate 700.A first dielectric layer 736 is then formed over the first-level first metal-semiconductor interconnect region 732 and the first-level second metal-semiconductor interconnect region 734 and around the semiconductor pillars 712, 714, 716, and 718. A first level first gate dielectric layer 740 and a first level first gate electrode layer 744 are formed over the first dielectric layer 736 and around the semiconductor pillars 712 and 716, and a first level second gate dielectric layer 742 and a first level second gate electrode layer 746 are formed over the first dielectric layer 736 and around the semiconductor pillars 714 and 718. The first level first gate dielectric layer 740 and the first level second gate dielectric layer 742 may be formed in same processing steps, and the first level first gate electrode layer 744 and the first level second gate electrode layer 746 may also be formed in same processing steps. The first level first gate electrode layer 744 and the first level first gate dielectric layer 740 define first level first channel regions 748 in the semiconductor pillars 712 and define first level third channel regions 752 in the semiconductor pillars 716. The first level second gate electrode layer 746 and the first level second gate dielectric layer 742 define first level second channel regions 750 in the semiconductor pillars 714 and define first level fourth channel regions 754 in the semiconductor pillars 718. A second dielectric layer 756 is formed over the first dielectric layer 736, the first level first gate electrode layer 744, and the first level second gate electrode layer 746 and around the semiconductor pillars 712, 714, 716, and 718.A second level first pad semiconductor material 760 is formed over the second dielectric layer 756 in the first region 704 and around the semiconductor pillars 712 and 714. A second-level second pad semiconductor material 762 is deposited over the second dielectric layer 756 in the second region 706 and around the semiconductor pillars 716, and a second-level third pad semiconductor material 764 is deposited over the second dielectric layer 756 in the second region 706 and around the semiconductor pillars 718. The second-level first pad semiconductor material 760 in the first region 704 may be doped with a p-dopant, and the doping concentration for the second-level first pad semiconductor material 760 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The second-level second pad semiconductor material 762 and the second-level third pad semiconductor material 764 in the second region 706 may be doped with an n-dopant, and the doping concentration for the second-level second pad semiconductor material 762 and the second-level third pad semiconductor material 764 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The second-level first pad semiconductor material 760, the second-level second pad semiconductor material 762, and the second-level third pad semiconductor material 764 are physically separated from each other. Second level first source / drain regions 766 are formed in the semiconductor pillars 712, second level second source / drain regions 768 are formed in the semiconductor pillars 714, second level third source / drain regions 770 are formed in the semiconductor pillars 716, and second level fourth source / drain regions 772 are formed in the semiconductor pillars 718. The second-level first source / drain regions 766 and the second-level second source / drain regions 768 may be doped with a p-type dopant, and the second-level third source / drain regions 770 and the second-level fourth source / drain regions 772 may be doped with an n-type dopant. The doping concentration for the second-level first source / drain regions 766, the second-level second source / drain regions 768, the second-level third source / drain regions 770, and the second-level fourth source / drain regions 772 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a second-level first metal-semiconductor interconnect region 774 is formed on and / or in the second-level first pad semiconductor material 760, a second-level second metal-semiconductor interconnect region 776 is formed on and / or in the second-level second pad semiconductor material 762, and a second-level third metal-semiconductor interconnect region 778 is formed on and / or in the second-level third pad semiconductor material 764. Since the second-level first pad semiconductor material 760, the second-level second pad semiconductor material 762, and the second-level third pad semiconductor material 764 are physically separated from each other, the second-level first metal semiconductor connection region 774, the second-level second metal semiconductor connection region 776, and the second-level third metal semiconductor connection region 778 are also physically separated from each other. The second-level first metal-semiconductor connection region 774, the second-level second metal-semiconductor connection region 776, and the second-level third metal-semiconductor connection region 778 may be formed to a greater or lesser extent in the corresponding second-level first pad semiconductor material 760, the second-level second pad semiconductor material 762, and the second-level third pad semiconductor material 764.Next, a third dielectric layer 780 is formed over the second dielectric layer 756, the second-level first pad semiconductor material 760, the second-level second pad semiconductor material 762, and the second-level third pad semiconductor material 764 and around the semiconductor pillars 712, 714, 716, and 718.As shown in FIG. 41, a mask 782 is then formed over the third dielectric layer 780 in the first region 704 and partially in the second region 706. The mask 782 covers the semiconductor pillars 712 and 714 in the first region, covers some of the semiconductor pillars 716 while exposing other semiconductor pillars 716, and covers the semiconductor pillars 718 in the second region 706. The mask 782 may be a photoresist that is spin coated and patterned using photolithography.Then, in FIG. 42, the portions of the exposed semiconductor pillars 716 in the second region 706 protruding from the third dielectric layer 780 are removed with an etching process. The etching process may be any suitable etching process selective to the material of the semiconductor pillars 716, and may be a wet or dry etching process. After the etching process, the mask 782 is removed, for example, with a lift-off process, if the mask 782 is a photoresist.Then, a second level first gate dielectric layer 784 and a second level first gate electrode layer 790 are formed over the third dielectric layer 780 and around the semiconductor pillars 712, a second level second gate dielectric layer 786 and a second level second gate electrode layer 792 are formed over the third dielectric layer 780 and around the semiconductor pillars 716, and a second level third gate dielectric layer 788 and a second level third gate electrode layer 794 are formed over the third dielectric layer 780 and around the semiconductor pillars 714 and 718. The second level first gate dielectric layer 784, the second level second gate dielectric layer 786, and the second level third gate dielectric layer 788 may be formed in equal processing steps, and the second level first gate electrode layer 790, the second level second gate electrode layer 792, and the second level third gate electrode layer 794 may also be formed in equal processing steps. The second-level first gate electrode layer 790 and the second-level first gate dielectric layer 784 define second-level first channel regions 796 in the semiconductor pillars 712. The second level second gate electrode layer 792 and the second level second gate dielectric layer 786 define second level third channel regions 800 in the semiconductor pillars 716. The second level third gate electrode layer 794 and the second level third gate dielectric layer 788 define second level second channel regions 798 in the semiconductor pillars 714 and second level fourth channel regions 802 in the semiconductor pillars 718.A fourth dielectric layer 804 is formed over the third dielectric layer 780, the second level first gate electrode layer 790, the second level second gate electrode layer 792 and the second level third gate electrode layer 794 and around the semiconductor pillars 712, 714, 716 and 718. A contact 806 is formed through the fourth dielectric layer 804, the third dielectric layer 780, the second dielectric layer 756, and the first dielectric layer 736 to the first-level first metal-semiconductor connection region 732. The contact 806 is physically and electrically connected to the first-level first metal-semiconductor connection region 732.A third level first pad semiconductor material 810 is formed over the fourth dielectric layer 804 in the first region 704, around the semiconductor pillars 712 and 714, and on the contact 806. A third level second pad semiconductor material 812 is deposited over the fourth dielectric layer 804 in the second region 706 and around the semiconductor pillars 716, and a third level third pad semiconductor material 814 is deposited over the fourth dielectric layer 804 in the second region 706 and around the semiconductor pillars 718. The third level first pad semiconductor material 810, the third level second pad semiconductor material 812, and the third level third pad semiconductor material 814 are physically separated from each other. The third level first pad semiconductor material 810 in the first region 704 may be doped with a p-dopant, and the doping concentration for the third level first pad semiconductor material 810 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. The third-level second pad semiconductor material 812 and the third-level third pad semiconductor material 814 in the second region 706 may be doped with an n-dopant, and the doping concentration for the third-level second pad semiconductor material 812 and the third-level third pad semiconductor material 814 may be in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3. Third level first source / drain regions 816 are formed in the semiconductor pillars 712, third level second source / drain regions 818 are formed in the semiconductor pillars 714, third level third source / drain regions 820 are formed in the semiconductor pillars 716, and third level fourth source / drain regions 822 are formed in the semiconductor pillars 718. The third level first source / drain regions 816 and the third level second source / drain regions 818 may be doped with a p-type dopant, and the third level third source / drain regions 820 and the third level fourth source / drain regions 822 may be doped with an n-type dopant. The doping concentration for the third level first source / drain regions 816, the third level second source / drain regions 818, the third level third source / drain regions 820, and the third level fourth source / drain regions 822 may be in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.Then, a third level first metal-semiconductor connection region 824 is formed on the third level first pad semiconductor material 810, a third level second metal-semiconductor connection region 826 is formed on the third level second pad semiconductor material 812, and a third level third metal-semiconductor connection region 828 is formed on the third level third pad semiconductor material 814. Since the third level first pad semiconductor material 810, the third level second pad semiconductor material 812, and the third level third pad semiconductor material 814 are physically separated from each other, the third level first metal semiconductor connection region 824, the third level second metal semiconductor connection region 826, and the third level third metal semiconductor connection region 828 are also physically separated from each other. The third-level first metal-semiconductor connection region 824, the third-level second metal-semiconductor connection region 826, and the third-level third metal-semiconductor connection region 828 may be formed to a greater or lesser extent in the corresponding third-level first pad semiconductor material 810, the third-level second pad semiconductor material 812, and the third-level third pad semiconductor material 814.Next, a fifth dielectric layer 830 is formed over the fourth dielectric layer 804, the third level first metal-semiconductor interconnect region 824, the third level second metal-semiconductor interconnect region 826, and the third level third metal-semiconductor interconnect region 828. Then contacts 832, 834, 836, 838, 840, 842 and 844 are formed into different components through different dielectric layers. The contact 832 passes through the fifth dielectric layer 830, the fourth dielectric layer 804, and the third dielectric layer 780 and is physically and electrically connected to the second-level first metal-semiconductor connection region 774. The contact 834 passes through the fifth dielectric layer 830, the fourth dielectric layer 804, the third dielectric layer 780, and the second dielectric layer 756 and is physically and electrically connected to the first level first gate electrode layer 744. The contact 836 passes through the fifth dielectric layer 830, the fourth dielectric layer 804, and the third dielectric layer 780 and is physically and electrically connected to the second-level second metal-semiconductor connection region 776. The contact 838 passes through the fifth dielectric layer 830 and is physically and electrically connected to the third-level first metal-semiconductor connection region 824. The contact 840 passes through the fifth dielectric layer 830 and the fourth dielectric layer 804 and is physically and electrically connected to the second-level third gate electrode layer 794. The contact 842 passes through the fifth dielectric layer 830, the fourth dielectric layer 804, the third dielectric layer 780, and the second dielectric layer 756 and is physically and electrically connected to the first-level second gate electrode layer 746. The contact 844 passes through the fifth dielectric layer 830 and is physically and electrically connected to the third-level third metal-semiconductor connection region 828.Although contact 842 appears to pass through second-level third gate electrode layer 794, it is not electrically connected to second-level third gate electrode layer 794; rather, contact 842 is shown drawn over one another in the view of FIG. 43B to show further aspects. The location of contact 842 is more clearly seen in Figs. 44A-44E.Next, a sixth dielectric layer 846 is formed with metallizations 850, 854, 858, 862, 866, 870 and 874 with contact holes 848, 852, 856, 860, 864, 868 and 872, respectively, over the fifth dielectric layer 830. The contact hole 848 is physically located between the contact 832 and the metallization 850 and electrically connects them to one another. The contact hole 852 is physically located between the contact 834 and the metallization 854 and electrically connects them to each other. The contact hole 856 is physically located between and electrically connects the contact 836 and the metallization 858. The contact hole 860 is physically located between the contact 838 and the metallization 862 and electrically connects them to each other. The contact hole 864 is physically located between the contact 840 and the metallization 866 and electrically connects them to each other. The contact hole 868 is physically located between the contact 842 and the metallization 870 and electrically connects them to each other. The contact hole 872 is physically located between and electrically connects the contact 844 and the metallization 874 to each other.FIGS. 43A and 43B show a stacked device having a first p-device P 1, a second p-device P 2, a third p-device P 3, and a floating p-device PF in the first region 704, and having a first n-device N 1, a second n-device N 2, a third n-device N 3, and a floating n-device NF in the second region 706. The first p-type device P 1 is, in this example, a VGAA PFET having the first level first source / drain regions 724, the first level first channel regions 748, the second level first source / drain regions 766, the first level first gate dielectric layer 740, and the first level first gate electrode layer 744. The floating p-type device PF is, in this example, a VGAA PFET disposed over the first p-type device P 1 and having the second-level first source / drain regions 766, the second-level first channel regions 796, the third-level first source / drain regions 816, the second-level first gate dielectric layer 784, and the second-level first gate electrode layer 790. The second p-type device P 2 is a VGAA PFET in this example, having the first level second source / drain regions 726, the first level second channel regions 750, the second level second source / drain regions 768, the first level second gate dielectric layer 742, and the first level second gate electrode layer 746. The third p-type device P 3 is, in this example, a VGAA PFET disposed over the second p-type device P 2 and having the second-level second source / drain regions 768, the second-level second channel regions 798, the third-level second source / drain regions 818, the second-level third gate dielectric layer 788, and the second-level third gate electrode layer 794.The first n-type device N 1 is a VGAA NFET in this example, having the first level third source / drain regions 728, the first level third channel regions 752, the second level third source / drain regions 770, the first level first gate dielectric layer 740, and the first level first gate electrode layer 744. The floating n-type device NF is, in this example, a VGAA NFET that is disposed over the first n-type device N 1 and that has the second-level third source / drain regions 770, the second-level third channel regions 800, the third-level third source / drain regions 820, the second-level second gate dielectric layer 786, and the second-level second gate electrode layer 792. The second level third source / drain regions 770 in the first n-type device N 1 and the first level first source / drain regions 724, the first level second source / drain regions 726, and the third level second source / drain regions 818 in the p-type devices P 1, P 2, and P 3, respectively, are electrically connected to each other via metallizations and / or vias, for example. The second n-type device N 2 is a VGAA NFET in this example, having the first level fourth source / drain regions 730, the first level fourth channel regions 754, the second level fourth source / drain regions 772, the first level second gate dielectric layer 742, and the first level second gate electrode layer 746. The third n-type device N 3 is, in this example, a VGAA NFET disposed over the second n-type device N 2 and having the second-level fourth source / drain regions 772, the second-level fourth channel regions 802, the third-level fourth source / drain regions 822, the second-level third gate dielectric layer 788, and the second-level third gate electrode layer 794.The first n-type device N 1 has more semiconductor pillars (semiconductor pillars 716) than the second and third n-type devices N 1 and N 2 and than the first, second and third p-type devices P 1, P 2 and P 3, and therefore the first n-type device N 1 has an effective channel width larger than that of the other devices. And since the floating n device NF has fewer semiconductor pillars 716 than the first n device N 1, the first n device N 1 may have a set channel width, thereby enabling greater uniformity of upper level processing. In some embodiments, the effective channel width of the first n-type device N 1 may be twice or even greater than corresponding effective channel widths of the devices N 2, N 3, NF, P 1, P 2, P 3, and PF. The devices P 1, P 2, P 3, PF, N 1, N 2, N 3, and NF may have more or fewer semiconductor pillars 712, 714, 716, and 718 than shown in FIGS. 43A and 43B. For example, the devices P 1, P 2, P 3, PF, N 1, N 2, N 3, and NF may have one semiconductor pillar 712, 714, 716, and 718, two semiconductor pillars 712, 714, 716, and 718, four semiconductor pillars 712, 714, 716, and 718, and so forth.FIGS. 43A and 43B further show a first level source / drain SD 1, a first level gate G 1, a second level source / drain SD 2, a second level gate G 2, and a third level source / drain SD 3. The first-level source / drain SD 1 is shown drawn one above the other in FIG. 44A. The first-level gate G 1 is shown drawn one above the other in FIG. 44B. The second-level source / drain SD 2 is shown drawn one above the other in FIG. 44C. The second-level gate G 2 is shown drawn one above the other in FIG. 44D. The third-level source / drain SD 3 is shown drawn one above the other in FIG. 44E. Figs. 44A to 44E show the cross section A-A shown in Fig. 43A and the cross section B-B shown in Fig. 43B.Fig. 45 is a circuit diagram of the structure shown in Figs. 43A and 43B, which may be a three-input NAND gate. The components in the circuit diagram of Fig. 45 are denoted by reference symbols corresponding to those of the structure in Figs. 43A and 43B. A node 760 / 774 may be a first power supply node, such as a VDD node, and a node 814 / 828 may be a second power supply node, such as a VSS node. A node 720 / 732 / 806 / 810 / 824 / 762 / 776 is an output node of the NAND gate circuit. A node 744 is a first input, a node 746 is a second input, and a node 794 is a third input. As shown, the first, second, and third p-type devices P 1, P 2, and P 3 are connected in parallel, and the first, second, and third n-type devices N 1, N 2, and N 3 are connected in series. The parallel-connected p-type devices P1, P2 and P3 are connected to the series-connected n-type devices N1, N2 and N3 at the output node.FIG. 46 shows in perspective views example configurations that may have one or more semiconductor pillars in various embodiments. FIG. 46 shows a semiconductor pillar 900 having a circular cross section, a semiconductor pillar 902 having an elliptical cross section, a semiconductor pillar 904 having a rectangular cross section, a semiconductor pillar 906 whose cross section is a rectangle having rounded corners, a semiconductor pillar 908 having a square cross section, a semiconductor pillar 910 whose cross section is a square having rounded corners, a semiconductor pillar 912 having a triangular cross section, and a semiconductor pillar 914 having a hexagonal cross section. Other cross-sectional configurations may also be used, and different cross-sectional configurations between different devices within a structure and / or within a device in a structure may be used.In some embodiments, the following advantages may be obtained. In some embodiments, the area required for a circuit may be reduced, such that the density may be increased without encountering the boundaries of photolithography. In some embodiments, by using different contacts and / or metal-semiconductor connection regions within a circuit across devices, the number of vias that are otherwise needed to connect the circuit may also be reduced. Moreover, by arranging some power supply nodes at a second-level source / drain, for example, delay in a circuit can be reduced.One embodiment is a structure. The structure includes a first semiconductor pillar extending vertically from a substrate in a first region and a second semiconductor pillar extending vertically from the substrate in a second region, the first region being a p-type device region and the second region being an n-type device region. A first source / drain region is in the first semiconductor pillar and a first level second source / drain region is in the second semiconductor pillar, wherein the conductivity type of the first level second source / drain region is opposite to the conductivity type of the first level first source / drain region. A first level gate electrode layer laterally surrounds the first and second semiconductor pillars and is vertically above the first source / drain region and the first level second source / drain region, and a first level gate dielectric layer is laminated between the first level gate electrode layer and the first semiconductor pillar in the first region and the second semiconductor pillar in the second region. A second level first source / drain region is in the first semiconductor pillar and a second level second source / drain region is in the second semiconductor pillar, both vertically disposed over the first level gate electrode layer. The second level first source / drain region is connected to a first power supply node. A second level gate electrode layer laterally surrounds the first and second semiconductor pillars and is vertically above the second level first source / drain region and the second level second source-drain region, and a second level gate dielectric layer is laminated between the second level gate electrode layer and the first semiconductor pillar in the first region and the second semiconductor pillar in the second region. A third level first source / drain region is in the first semiconductor pillar and a third level second source / drain region is in the second semiconductor pillar, both vertically disposed over the second gate electrode layer. A first level metal-semiconductor connection region is formed on and / or in a first level first pad semiconductor material and a first level second pad semiconductor material and electrically connects the first level first source / drain region to the first level second source / drain region, wherein the conductivity type of the first level first pad semiconductor material is opposite to the conductivity type of the first level second pad semiconductor material.The invention further relates to a method for producing a semiconductor structure according to claim 11.

Claims

A structure comprising: a first semiconductor pillar (408) extending vertically from a substrate (400) in a first region (402); and a second semiconductor pillar (410) extending vertically from the substrate (400) in a second region (404), wherein the first region (402) is a p-type device region and the second region (404) is an n-type device region; a first-level first source / drain region (418) in the first semiconductor pillar (408) and a first-level second source / drain region (420) in the second semiconductor pillar (410), wherein the conductivity type of the first-level second source / drain region (420) is opposite to the conductivity type of the first-level first source / drain region (418); a first level gate electrode layer (428) laterally surrounding the first and second semiconductor pillars (408, 410) and vertically disposed over the first level first source / drain region (418) and the first level second source / drain region (420), wherein a first level gate dielectric layer (426) is sandwiched between the first level gate electrode layer (428) and the first semiconductor pillar (408) in the first region (402) and the second semiconductor pillar (410) in the second region (404); a second-level first source / drain region (440) in the first semiconductor pillar (408) and a second-level second source / drain region (442) in the second semiconductor pillar (410) both vertically above the first-level gate electrode layer (428), the second-level first source / drain region (440) being connected to a first power supply node (436, 444); a second-level gate electrode layer (452) laterally surrounding the first and second semiconductor pillars (408, 410) and vertically disposed over the second-level first source / drain region (440) and the second-level second source / drain region (442), a second-level gate dielectric layer (450) being sandwiched between the second-level gate electrode layer (452) and in the first region (402) of the first semiconductor pillar (408) and in the second region of the second semiconductor pillar (410); a third level first source / drain region (466) in the first semiconductor pillar (408) and a third level second source / drain region (468) in the second semiconductor pillar (410) both vertically above the second level gate electrode layer (452); and a first-level metal-semiconductor connection region (422) formed on and / or in a first-level first pad semiconductor material (414) and a first-level second pad semiconductor material (416) and electrically connecting the first-level first source / drain region (418) to the first-level second source / drain region (420), wherein the conductivity type of the first-level first pad semiconductor material (414) is opposite to the conductivity type of the first-level second pad semiconductor material (416).The structure of claim 1, wherein the first-level first pad semiconductor material (414) is doped with a p-dopant in the first region (402), and the doping concentration for the first-level first pad semiconductor material (414) is in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.The structure of claim 1 or 2, wherein the first-level second pad semiconductor material (416) is doped with an n-dopant in the second region (404), and the doping concentration for the first-level second pad semiconductor material (416) is in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.The structure of any of claims 1 to 3, wherein the doping concentration for the first-level first source / drain region (418) and the first-level second source / drain region (420) is in the range of about 5×10 19 cm -3 to about 1×10 21 cm -3.The structure of any preceding claim, wherein the first power supply node (436, 444) comprises a second-level first pad semiconductor material (436) and a second-level first metal-semiconductor connection region (444), the second-level first pad semiconductor material (436) doped with a p-dopant, wherein the doping concentration for the second-level first pad semiconductor material (436) is in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.The structure of claim 5, further comprising: a second power supply node (446, 438) connected to the second level second source / drain region (442), the second power supply node (446, 438) comprising a second level second pad semiconductor material (438) and a second level second metal semiconductor connection region (446), the second level first pad semiconductor material (436) and the second level second pad semiconductor material (438) being physically separated, thereby also physically separating the second level first metal semiconductor connection region (444) and the second level second metal semiconductor connection region (446).The structure of any preceding claim, further comprising: a contact (454) physically and electrically connecting the first-level metal-semiconductor connection region (422) to the second-level gate electrode layer (452).The structure of any preceding claim, wherein a third level first pad semiconductor material (462) is layered around the first semiconductor pillar (408) in the first region (402) and a third level second pad semiconductor material (464) is layered around the second semiconductor pillar (410) in the second region (404), wherein the third level second pad semiconductor material (464) is in physical contact with the third level first pad semiconductor material (462).The structure of claim 8, wherein the third-level first pad semiconductor material (462) is doped with a p-dopant in the first region (402), and the doping concentration for the third-level first pad semiconductor material (462) is in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.The structure of claim 8 or 9, wherein the third-level second pad semiconductor material (464) is doped with an n-dopant in the second region (404), and the doping concentration for the third-level second pad semiconductor material (464) is in the range of about 1×10 20 cm -3 to about 2×10 21 cm -3.A method of manufacturing a semiconductor structure, the method comprising: forming at least one first semiconductor pillar (408) in a first region (402) and at least one second semiconductor pillar (410) in a second region (404) on a substrate (400), wherein the first region (402) is a p-type device region and the second region (404) is an n-type device region; depositing a first level first pad semiconductor material (414) in the first region (402) and a first level second pad semiconductor material (416) in the second region (404) on the substrate (400), wherein the conductivity type of the first level first pad semiconductor material (414) is opposite to the conductivity type of the first level second pad semiconductor material (416); forming a first level first source / drain region (418) in the first semiconductor pillar (408) and a first level second source / drain region (420) in the second semiconductor pillar (410); and forming a first level metal-semiconductor interconnect region (422) on and / or in the first level first pad semiconductor material (414) and the first level second pad semiconductor material (416), wherein the first level metal-semiconductor interconnect region (422) electrically connects the first level first source / drain region (418) to the first level second source / drain region (420); forming a first level gate dielectric layer (426) and a first level gate electrode layer (428) around the first and second semiconductor pillars (408, 410) and vertically above the first level first source / drain region (418) and the first level second source / drain region (420); depositing a second level first pad semiconductor material (436) around the first semiconductor pillar (408) in the first region (402); and depositing a second level second pad semiconductor material (438) around the second semiconductor pillar (410) in the second region (404); forming a second level first source / drain region (440) in the first semiconductor pillar (408) and forming a second level second source / drain region (442) in the second semiconductor pillar (410) both vertically above the first level gate electrode layer (428); forming a second level first metal-semiconductor connection region (444) on and / or in the second level first pad semiconductor material (436) and forming a second level second metal-semiconductor connection region (446) on and / or in the second level second pad semiconductor material (438); thereafter forming a second level gate dielectric layer (450) and a second level gate electrode layer (452) around the first and second semiconductor pillars (408, 410) and vertically above the second level first source / drain region (440) and the second level second source / drain region (442); forming a third level first source / drain region (466) in the first semiconductor pillar (408) and a third level second source / drain region (468) in the second semiconductor pillar (410) both vertically above the second level gate electrode layer (452).The method of claim 11, further comprising: prior to forming the first level gate dielectric layer (426) and the first level gate electrode layer (428), forming a first dielectric layer (424) over the first level metal-semiconductor connection region (422) and around the first and second semiconductor pillars (408, 410), wherein the first level gate dielectric layer (426) and the first level gate electrode layer (428) are formed over the first dielectric layer (424).The method of claim 12, further comprising: prior to depositing the second-level first pad semiconductor material (436) and the second-level second pad semiconductor material (438), forming a second dielectric layer (434) over the first dielectric layer (424) and the first-level gate electrode layer (428) and around the first and second semiconductor pillars (408, 410), wherein depositing the second-level first pad semiconductor material (436) and the second-level second pad semiconductor material (438) over the second dielectric layer (434).The method of claim 13, further comprising: prior to forming the second-level gate dielectric layer (450) and the second-level gate electrode layer (452): forming a third dielectric layer (448) over the second-level first metal-semiconductor connection region (444), the second-level second metal-semiconductor connection region (446), the second dielectric layer (434), and around the first and second semiconductor pillars (408, 410), wherein forming the second-level gate dielectric layer (450) and the second-level gate electrode layer (452) over the third dielectric layer.The method of claim 14, further comprising: contacting (454) the first level metal-semiconductor connection region (422) through the second level gate electrode layer (452), the third dielectric layer (448), the second dielectric layer (434), and the first dielectric layer (424).The method of claim 15, further comprising: forming a fourth dielectric layer (460) over the third dielectric layer (448) and the second level gate electrode layer (452) and around the first and second semiconductor pillars (408, 410); depositing a third level first pad semiconductor material (462) over the fourth dielectric layer (460) and around the first semiconductor pillar (408) in the first region (402); and depositing a third level second pad semiconductor material (464) over the fourth dielectric layer (460) and around the second semiconductor pillar (410) in the second region (404).The method of any of claims 11 to 16, wherein forming the second-level gate dielectric layer (450) and the second-level gate electrode layer (452) comprises: conformally depositing the second-level gate dielectric layer (450) on the first and second semiconductor pillars (408, 410); depositing the second-level gate electrode layer (452) over the second-level gate dielectric layer (450).The method of any of claims 11 to 17, wherein forming the contact (454) to the first level metal-semiconductor interconnect region (422) comprises: forming an opening for the contact (454) using one or more etching steps, the opening being formed through the second level gate electrode layer (452), the second level gate dielectric layer (450), the third dielectric layer (448), the second dielectric layer (434), and the first dielectric layer (424) to the first level metal-semiconductor interconnect region (422).The method of claim 18, wherein a capping layer, such as a diffusion barrier layer, an adhesion layer and a conductive material, are deposited in the opening.

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