Semiconductor components and a circuit for controlling a field-effect transistor of a semiconductor component

Abstract

A semiconductor device (240), comprising: a plurality of drift regions (101) of a plurality of field-effect transistor structures arranged in a semiconductor substrate (102), wherein the plurality of drift regions (101) has a first conductivity type; a plurality of compensation regions (103) arranged in the semiconductor substrate (102), wherein the plurality of compensation regions (103) has a second conductivity type, wherein each drift region (101) from the plurality of drift regions (101) is arranged adjacent to at least one compensation region (103) from the plurality of compensation regions (103), wherein a field-effect transistor structure of the majority of field-effect transistor structures has a transistor gate (244) in a gate-trough structure (248), wherein a body region (241) is arranged adjacent to a first side wall of the gate-trough structure (248) of the field-effect transistor structure; a transistor gate-shielding doping region (247) located adjacent to a second side wall of the gate trench structure (248) of the field-effect transistor structure; and at least one Schottky diode structure (104) arranged on the semiconductor substrate (102), wherein the Schottky diode structure (104) is arranged between two adjacent field-effect transistor structures of the plurality of field-effect transistor structures.

Description

Technical field

[0001] Examples of implementation refer to concepts for semiconductor device structures and, in particular, semiconductor devices. background

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs; MOSFET = metal oxide semiconductor field-effect transistor) (e.g., double-diffused MOSFETs) are short-circuited between the source and body regions. A pn-diode structure is present between the source and drain regions of a MOSFET structure at a junction or interface between the body and drift regions of the MOSFET structure. For example, the pn-diode is connected antiparallel to the MOS channel of the MOSFET structure. In components with a large band gap (e.g., silicon carbide-based components), the pn-diode exhibits a high forward threshold voltage (in reverse bias) due to the large band gap of the semiconductor. This forward voltage is significantly higher than the voltage drop across the MOS component in forward bias, which can, for example, thermally limit the current-carrying capacity of the assembly.

[0003] Document US 2009 / 0108303 A1 describes semiconductor components, document DE 10 2012 216 648 A1 discloses an electronic circuit with a transistor with depletion control, document DE 11 2004 002 608 B4 describes a power semiconductor device and document US 6240010 B1 discloses a semiconductor memory cell. Summary

[0004] There is a need to provide concepts for semiconductor devices with reduced on-state losses in blocking mode and / or reduced switching losses.

[0005] Such a need can be met by the subject matter of independent claims 1, 10 and 14. The dependent claims define preferred embodiments.

[0006] Claim 1 relates to a semiconductor device. The semiconductor device comprises a plurality of drift regions of a plurality of field-effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions exhibit a first conductivity type. The semiconductor device further comprises a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions exhibit a second conductivity type. Each drift region from the plurality of drift regions is arranged adjacent to at least one compensation region from the plurality of compensation regions. A field-effect transistor structure of the plurality of field-effect transistor structures has a transistor gate in a gate-trough structure. A body region is arranged adjacent to a first side wall of the gate-trough structure of the field-effect transistor structure.The semiconductor device also includes a transistor gate-shielding diode region located adjacent to a second side wall of the gate-trough structure of the field-effect transistor structure. The semiconductor device further includes at least one Schottky diode structure located within the semiconductor substrate, wherein the Schottky diode structure is positioned between two adjacent field-effect transistor structures of the plurality of field-effect transistor structures.

[0007] Claim 10 relates to a semiconductor device comprising a plurality of drift regions of a plurality of field-effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions have a first conductivity type. The semiconductor device further comprises a plurality of compensation regions arranged in the semiconductor substrate, the plurality of compensation regions having a second conductivity type, wherein each drift region from the plurality of drift regions is arranged adjacent to at least one compensation region from the plurality of compensation regions. A field-effect transistor structure of the plurality of field-effect transistor structures has a transistor gate in a gate-trough structure, wherein a body region is arranged adjacent to a first side wall of the gate-trough structure (248) of the field-effect transistor structure.Furthermore, the semiconductor device has a transistor gate-shielding doping region which is located adjacent to a second side wall of the gate trench structure of the field-effect transistor structure, wherein the transistor gate-shielding doping region is in ohmic contact with the source potential of the field-effect transistor structure, and wherein the transistor gate-shielding doping region electrically connects a compensation region of the plurality of compensation regions to the source potential.

[0008] Claim 14 relates to a semiconductor device comprising a field-effect transistor structure arranged on a silicon carbide substrate; a trench structure extending from a surface of the silicon carbide substrate into the silicon carbide substrate, the trench structure comprising a gate of a gate-controlled metal-insulation semiconductor diode structure within the trench structure; and a shielding doping region arranged at a bottom of the trench structure of the field-effect transistor structure. Brief description of the characters

[0009] Some exemplary embodiments of devices and / or methods are described below only by way of example and with reference to the accompanying figures, in which Fig. 1A shows a schematic representation of a semiconductor device; Fig. Figure 1B shows a schematic representation of a section of a semiconductor device with a Schottky contact interface; Fig. Figure 1C shows a schematic representation of a section of a semiconductor device with a plurality of compensation regions; Fig. Figure 1D shows a schematic representation of a plurality of compensation regions in a top view; Fig. 1E shows a schematic representation of a compensation region in a top view; Fig. 1F shows a schematic representation of a compensation region in a top view; Fig. Figure 2A shows a schematic representation of a semiconductor device with a plurality of junction field-effect transistor structures; Fig. Figure 2B shows a schematic representation of another semiconductor device with a plurality of junction field-effect transistor structures; Fig. Figure 2C shows a schematic representation of another semiconductor device with a metal-oxide-semiconductor field-effect transistor structure and a gate-controlled metal-insulation-semiconductor diode structure; Fig. Figure 2D shows a schematic representation of a semiconductor device with at least one metal-oxide-semiconductor field-effect transistor structure and at least one Schottky diode structure; Fig. Figure 2E shows a schematic representation of a semiconductor device with at least one junction field-effect transistor structure and at least one Schottky diode structure; Fig. Figure 2F shows a schematic representation of another semiconductor device with at least one junction field-effect transistor structure and at least one Schottky diode structure; Fig. Figure 2G shows a schematic representation of another semiconductor device with at least one junction field-effect transistor structure and at least one further shielding doping region; Fig. Figures 3A to 3C show schematic representations of possible layouts of a semiconductor device; Fig. Figure 4 shows a schematic representation of a semiconductor device with a trench structure; Fig. Figure 5A shows a schematic representation of a semiconductor device with a gate-controlled metal-insulation semiconductor diode structure; Fig. Figure 5B shows a schematic representation of another semiconductor device with a gate-controlled metal-insulation semiconductor diode structure; Fig. Figure 6 shows a schematic representation of a semiconductor device with an electrode structure; Fig. Figure 7 shows a schematic representation of a semiconductor device with a plurality of junction field-effect transistor structures and at least one gate-controlled metal-insulation semiconductor diode structure; Fig. Figure 8 shows a schematic representation of a semiconductor device with a plurality of junction field-effect transistor structures and vertical channel regions; Fig. Figure 9 shows a schematic representation of a semiconductor device with a plurality of junction field-effect transistor structures and at least one Schottky diode structure; and Fig. Figure 10 shows a schematic representation of a semiconductor device with a junction field-effect transistor structure and a Schottky diode structure. Detailed description

[0010] Several embodiments are now described in more detail with reference to the accompanying drawings, in which some of these embodiments are illustrated. The thickness of lines, layers, and / or areas in the figures may be exaggerated for clarity.

[0011] While exemplary embodiments are suitable for various modifications and alternative forms, such embodiments are accordingly shown by way of example in the figures and described in detail here. It is understood, however, that the intention is not to limit the exemplary embodiments to the specific forms disclosed, but rather that the exemplary embodiments are intended to cover all modifications, correspondences, and alternatives falling within the scope of the disclosure. Throughout the entire description of the figures, identical reference numerals refer to identical or similar elements.

[0012] It is understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as "directly" "connected" or "coupled" to another element, there are no intermediate elements. Other expressions used to describe the relationship between elements should be interpreted similarly (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0013] The terminology used here is intended only to describe specific embodiments and is not meant to be limiting. According to our usage, the singular forms "ein, eine" and "das, der, die" are to include the plural forms as well, unless otherwise clearly indicated in the context. Furthermore, it is understood that the terms "umfassungt," "umfassend," "aufweisen," and / or "aufweisend," as used here, indicate the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0014] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they would normally be understood by a person skilled in the art in the field to which the embodiments belong. Furthermore, it is understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning corresponding to their meaning in the context of the relevant technology. However, should the present disclosure give a term a specific meaning that differs from a meaning normally understood by a person skilled in the art, that meaning must be taken into account in the specific context in which that definition is given.

[0015] Fig. Figure 1A shows a schematic representation of a semiconductor device 100 according to an exemplary embodiment.

[0016] The semiconductor device 100 comprises a plurality of drift regions 101 of a plurality of field-effect transistor structures arranged in a semiconductor substrate 102. The plurality of drift regions 101 exhibit a first conductivity type.

[0017] The semiconductor device 100 further comprises a plurality of compensation regions 103 arranged in the semiconductor substrate 102. The plurality of compensation regions 103 exhibit a second conductivity type.

[0018] Each drift region 101 from the plurality of drift regions 101 is arranged adjacent to at least one compensation region 103 from the plurality of compensation regions 103.

[0019] The semiconductor device 100 further comprises at least one Schottky diode structure or gate-controlled metal-insulation semiconductor diode structure 104 arranged on the semiconductor substrate 102.

[0020] Since the semiconductor device 100 comprises at least one Schottky diode (SD) structure or one gate-gated metal-insulation-semiconductor (MGD) structure 104 arranged on the semiconductor substrate 102, the SD or MGD structure can provide a unipolar current path with a lower forward voltage than a bipolar / pn-body diode between a drift region and a body region. This can reduce the forward (or conduction) losses in body diode operation. The majority of compensation regions 103 arranged in the semiconductor substrate can inject charge carriers during a high rise in forward voltage in body diode operation, which can lead to improved electrical conductivity in the drift zone.Overall, the switching and / or on-state losses of the semiconductor device 100 can be reduced and / or the switching speeds of the semiconductor device 100 can be increased.

[0021] An SD structure can, for example, include a Schottky contact that connects a Schottky contact interface (e.g., a Schottky junction) to a section of the semiconductor substrate 102. The Schottky contact can be formed in a trench structure extending from a surface of the semiconductor substrate 102 into the semiconductor substrate 102. For example, the trench structure in which at least part of the SD structure or the MGD structure 104 is formed can extend vertically into the semiconductor substrate 102 from the first lateral side or surface (e.g., the front surface). Alternatively or optionally, the Schottky contact can be formed on or at the surface of the semiconductor substrate 102. For example, the Schottky contact can be a lateral electrode or contact that does not extend vertically into the semiconductor substrate 102.

[0022] A material for the Schottky contact can be selected such that a Schottky barrier is formed between the Schottky contact and the semiconductor substrate 102. The Schottky interface can be located between the Schottky contact and a drift region of the Schottky diode structure in the semiconductor substrate 102. The drift region of the SD structure can be part of a common drift zone of the semiconductor substrate 102. The common drift zone can comprise the majority of drift regions 101 of the majority of field-effect transistor structures (and / or drift regions of other SD structures and / or drift regions of other MGD structures) that are interconnected to form the interconnected (or common) drift zone.

[0023] The Schottky contact can comprise (or be formed from) a material with a lower work function than the electron affinity of the semiconductor substrate 102, provided the semiconductor substrate 102 is an n-type doped semiconductor substrate. For example, if the semiconductor substrate 102 is an n-type doped, silicon carbide-based substrate, the material of the Schottky contact in the Schottky diode structure can be, for example, aluminum, aluminum-copper alloy, copper, tungsten, tungsten nitride, titanium, titanium nitride, molybdenum, molybdenum nitride, boron nitride, or carbon nitride.

[0024] An MGD structure 104 can comprise a gate electrode material and a gate insulating layer arranged in a (vertical) trench structure. The MGD structure can be formed within the trench structure, which extends from the (first lateral) surface of the semiconductor substrate 102 into the semiconductor substrate 102. The gate insulating layer (e.g., a silicon oxide layer) can be arranged, for example, on side walls (e.g., on a first vertical side wall and a second vertical side wall) and at the bottom of the trench structure. For example, the electrically conductive gate electrode material (e.g., polysilicon) can be arranged within the trench structure (or at least partially fill it) such that the gate insulating layer is located between the gate electrode material and the semiconductor substrate 102. For example, the gate insulation layer of the MGD structure 104 can have a maximum thickness between 10 nm and 150 nm (or e.g.The maximum thickness can be between 20 nm and 100 nm, or, for example, between 30 nm and 60 nm. The maximum thickness can be the greatest thickness of the gate insulation layer between a side wall (or bottom) of the trench and the gate electrode material. The gate insulation layer of MGD structure 104 can have a different thickness between a side wall of the trench and the gate electrode material, and between the bottom of the trench and the gate electrode material. For example, the thickness of the gate insulation of MGD structure 104 can be greater at the bottom of the trench than at the side walls.

[0025] For an MGD diode structure, at least a portion of a (first) sidewall of the trench structure can be located adjacent to an (n-type doped) drift region of the MGD diode structure and / or a (p-type doped) body region of the MGD diode structure 104. For example, the drift region of the MGD diode structure 104 and / or the body region of the MGD diode structure can be located adjacent to a (first) sidewall of the trench structure. The drift region of the MGD structure can be part of (or connected to) the common drift zone of the semiconductor substrate 102.

[0026] A maximum lateral dimension of the trench structure can be, for example, between 0.5 µm and 6 µm (or, for example, between 1 µm and 3 µm). The maximum lateral dimension of the trench structure can be the greatest distance between a first (essentially) vertical sidewall and a second (opposite) sidewall of the trench structure in a direction horizontal or parallel to the first lateral surface of the semiconductor substrate 102. A maximum vertical dimension of the trench structure can be, for example, between 200 nm and 6 µm (or, for example, between 500 nm and 2 µm). The maximum vertical dimension of the trench structure can be the greatest distance between a first lateral surface of the semiconductor substrate and a bottom of the trench structure in a direction orthogonal or perpendicular to the first lateral surface of the semiconductor substrate 102.

[0027] The Schottky diode (SD) structure or the gate-controlled metal-insulation semiconductor (MGD) structure 104 can be at least partially formed in the semiconductor substrate 102. For example, at least part of the SD structure or at least part of the MGD structure can be formed in the semiconductor substrate 102.

[0028] Each diode structure 104 (e.g., which can be the SD structure or the MGD structure) can, for example, be arranged between the (first lateral) surface of the semiconductor substrate 102 and a compensation region 103 from the plurality of compensation regions 103. Optionally, the SD structure or MGD structure 104 can be arranged adjacent to (e.g., directly adjacent to) a compensation region 103. Alternatively or optionally, other doping regions or layers can, for example, be arranged between the SD structure or MGD structure 104 and the compensation region 103. Optionally, at least a portion of the SD structure or MGD structure 104 can be arranged on the (first lateral) surface of the semiconductor substrate 102.

[0029] The diode structure 104, for example, can exhibit a lower forward threshold voltage than a SiC pn diode. For example, the forward threshold voltage of the Schottky diode structure or the gate-controlled metal-insulation-semiconductor diode structure can be between 0.2 V and 1 V, compared to a forward voltage between 1.5 V and 6 V or more than 2.8 V for a SiC pn diode.

[0030] The majority of compensation regions 103 can be regions of the semiconductor substrate 102 that have a striped, circular, hexagonal, or polygonal shape in a top view of the semiconductor device 100. A striped shape can be a geometry that extends significantly further in a second lateral direction than in an orthogonal first lateral direction. For example, a compensation region 103 can have a lateral length greater than 10 times (or greater than 100 times or greater than 1000 times) of a lateral width of a compensation region 103 from the majority of compensation regions. The lateral length of the compensation regions 103 can be the greatest extent along the front surface of the semiconductor substrate and a lateral width (e.g. between 1 µm and 5 µm or between 2 µm and 3 µm) of the compensation region can be a shortest dimension of the compensation regions 103 along the front surface of the semiconductor substrate.The compensation regions from the plurality of compensation regions can all have the same lateral length and / or the same lateral width. Alternatively, the lateral length and / or the lateral width of the compensation regions from the plurality of compensation regions 103 can differ at least partially from one another. Adjacent compensation regions 103 from the plurality of compensation regions 103 can, for example, be separated in at least one lateral direction (e.g., the first lateral direction) by a lateral distance of less than 20 µm (or less than 10 µm, or less than 5 µm, or, for example, about 4 µm).

[0031] Furthermore, the compensation regions 103 from the plurality of compensation regions 103 exhibit a lateral extent (e.g., a vertical depth). In other words, the compensation regions 103 can be (laminar) planar structures or can (each) have, for example, the geometry of a column, a wall, a plate, a hexagonal prism, or the geometry of ellipses, stacks of (cut) ellipses, or cuboids. The vertical extent can, for example, be greater than the lateral width and shorter than the lateral length. For example, the compensation regions 103 from the plurality of compensation regions 103 can extend from a front surface of the semiconductor substrate 102 to a depth of more than 5 µm (or more than 10 µm, or more than 20 µm, or more than 50 µm).For example, a compensation region 103 from the plurality of compensation regions 103 can extend vertically from a body region 104 of a FET structure or from the trench (in which at least part of the diode structure is formed) into the semiconductor substrate 102 towards the back surface of the semiconductor substrate 102. In the case of a silicon carbide semiconductor substrate, the critical electric field can be an order of magnitude higher than that of a silicon semiconductor substrate, which can allow the reverse voltage region to be thinner than that of a silicon semiconductor substrate at the same reverse voltage. For example, a drift zone thickness of 20 µm in a silicon carbide semiconductor substrate may be sufficient to support, for example, a reverse voltage of 2000 V.

[0032] The compensation regions 103 from the plurality of compensation regions 103 can, for example, extend laterally in one direction through a vertical FET array of a plurality of FET structures. Optionally, the compensation regions 103 from the plurality of compensation regions 103 can extend in one direction into an edge termination region. Alternatively, the compensation regions 103 from the plurality of compensation regions 103 can be significantly smaller than the lateral extent of the FET structures of the vertical FET array (e.g., several compensation structures can be arranged in a line, and several lines of compensation structures can be arranged parallel to each other). For example, at least some of the compensation regions 103 from the plurality of compensation regions can be arranged substantially parallel to each other (e.g., neglecting manufacturing tolerances).

[0033] In a cross-section orthogonal to the lateral length of the plurality of compensation regions 103, the compensation regions 103 can, for example, have a column shape, a wall shape, a plate shape, a hexagonal prism shape, an elliptical shape, or a cuboid shape. The plurality of compensation regions 103 can be arranged alternately with the plurality of drift regions 101 of the vertical FET arrangement (in a cross-section orthogonal to a lateral length of the compensation regions). For example, the plurality of compensation regions 103 can be arranged alternately with the plurality of drift regions 101 in a (first) lateral direction. For example, a drift region 101 of the vertical FET structures can extend into the semiconductor substrate 102 between two compensation regions 103 within the semiconductor device 100.

[0034] The compensation regions 103 can exhibit doping of a second conductivity type. For example, the doping type of the compensation region can be opposite to that of the drift regions 101. The compensation region 103 can, for example, have an average doping concentration of at least 1 × 10 17 Dopant atoms per cm 3 (or e.g. between 1×10 17 Dopant atoms per cm 3 and 1x10 19 Dopant atoms per cm 3 ). The average doping concentration can, for example, be a measured number of dopant atoms (e.g., acceptor dopant atoms) per volume averaged over the compensation region 103.

[0035] The majority of drift regions 101 of the majority of FET structures can be part of a common drift zone of the vertical FET arrangement. For example, the majority of drift regions 101 of the majority of FET structures can be part of a common drift zone located, for example, in the semiconductor substrate 102. For example, the majority of drift regions 101 can be interconnected or joined together to form a jointly doped drift zone with the same doping concentration and conductivity type. The drift regions 101 can be interconnected below the compensation regions 103 by a common or jointly used portion of the drift zone. Optionally, the drift regions 101 can be combined, for example, with drift regions of the SD structures 104 and / or drift regions of the MGD structures 104 between the channel regions of the majority of FET structures and the drain or collector regions (e.g.between the compensation regions 103 or among the compensation regions 103).

[0036] The majority of drift regions 101 of the majority of FET structures can extend vertically from the body regions or channel regions of the majority of (vertical) FETs between the compensation regions 103 into the semiconductor substrate 102. For example, each drift region 101 from the majority of drift regions 101 can be located between adjacent compensation regions 103 in the semiconductor substrate and can extend vertically from a body region or channel region into the semiconductor substrate 102.

[0037] The drift regions 101 of most FET structures can, for example, carry most or all of the current flowing between the front and back surfaces of the semiconductor substrate 102 in an on-state of most FET structures. For example, each drift region 101 of a FET structure can carry charge carriers (or current) between a channel of the FET structure and an electrode located on the back surface of the semiconductor substrate 102. The drift regions 101 can be lightly doped regions located, for example, on (or in) a highly (or more highly) doped semiconductor substrate 102. Optionally, a field-stop region of the first conductivity type (e.g., n-doped) and with a higher doping concentration than the drift region 101 can be located between the drift region and the back surface or substrate of the FET structure.

[0038] The majority of drift regions 101 in the majority of FET structures can exhibit doping of the first conductivity type. Drift region 101 can have an average doping concentration of at least 1 × 10 17 Dopant atoms per cm 3 (or e.g. between 1×10 17 Dopant atoms per cm 3 and 1x10 19 Dopant atoms per cm 3 ). The average doping concentration can, for example, be a measured number of dopant atoms (e.g., acceptor dopant atoms) per volume averaged over the drift region 101.

[0039] Each drift region 101 from the plurality of drift regions 101 is arranged adjacent to at least one compensation region 103 from the plurality of compensation regions 103. Additionally or optionally, each drift region 101 can, for example, be arranged between adjacent compensation regions 103. Additionally or optionally, the drift regions 101 in the semiconductor substrate 102 can be separated from each other by the compensation regions 103 down to the depth of the compensation regions 103.

[0040] The semiconductor device 100 can, for example, be a compensation device. Compensation devices can be based on the mutual compensation of at least part of the charge of n- and p-type doped regions in the drift region of the vertical field-effect transistor (FET) array. For example, in a vertical FET array, alternating p- and n-type columns or plates (e.g., a plurality of drift regions 101 and a plurality of compensation regions 103 in an alternating arrangement in a lateral direction) can be arranged in pairs.A compensation region 103 from the plurality of compensation regions 103 may comprise a laterally summed number of dopants per unit area of ​​the second conductivity type (p or n) that differs from half of a laterally summed number of dopants per unit area of ​​the first conductivity type (n or p) contained in two drift regions 101 adjacent to opposite sides of the compensation region by less than ±25% or (less than ±15%, ±10%, ±5%, ±2%, or ±1%) of the laterally summed number of dopants per unit area of ​​the first conductivity type contained in the compensation region 103. The laterally summed number of dopants per unit area may be essentially constant or may vary for different depths.The laterally summed number of dopants per unit area can, for example, be equal to or proportional to the number of free charge carriers within a compensation region 103 or a drift region 101 that is to be compensated at a specific depth. Optionally or alternatively, a planar cross-section parallel to the lateral surface of the semiconductor substrate and intersecting the drift regions 101 and the compensation region 103 can be defined, and doping in the cross-sectional plane can be added with the correct sign. The result can be analogous, in that the addition of the correct sign can be less than ±25% (etc.) of the addition of the individual doping species (n or p).

[0041] Each FET structure, from the plurality of FET structures, can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) structure, an insulated-gate bipolar transistor (IGBT) structure, or a junction field-effect transistor (JFET) structure. For example, the examples can refer to SiC semiconductor circuits (e.g., SiC MOSFETs, SiC compensation transistors, SiC MOSFETs, SiC compensation MOSFETs, SiC JFETs, and SiC compensation JFETs).

[0042] Each MOSFET or IGBT structure can include a source or emitter region with a first conductivity type (e.g., n+-doped), a body region with a second conductivity type (e.g., p-type doped), and a drift region (e.g., n-type doped) adjacent to a transistor gate or transistor gate trench structure.

[0043] If the FET structure is a MOSFET structure, the drift region 101 of the MOSFET structure can be located between a body region of the MOSFET structure and a drain region of the MOSFET structure, which are located on a second lateral side (e.g., a back side) of the semiconductor substrate 102. The drain region of the MOSFET structure can, for example, have the first conductivity type (e.g., n+-doped).

[0044] If the FET structure is an IGBT structure, the drift region 101 of the IGBT structure can be located between a body region and a collector region of the IGBT structure, both situated on the second lateral side (e.g., a back surface) of the semiconductor substrate 102. The collector region of the IGBT structure can have the second conductivity type (e.g., p+-doped). Optionally, a field-stop region with the first conductivity type (e.g., n+-doped) and a higher doping density than the drift region 101 can be located between the drift region and the collector region of the IGBT structure.

[0045] When an initial gate voltage is applied to the transistor gate of a MOSFET or IGBT-FET structure, the FET structure can be switched to an on-state. When the MOSFET or IGBT-FET structure is in an on-state, a conductive channel (e.g., an n-channel) can be formed (or induced) in the body region between the source region and the drift region of the MOSFET or IGBT-FET structure. The conductive channel can be formed in a portion of the body region adjacent to the transistor gate, for example, by forming an inversion channel, and current can flow between the source region of the FET structure and the drift region.

[0046] When a second gate voltage is applied to the transistor gate of the MOSFET or IGBT-FET structure, the FET structure can be switched to an off state. When the MOSFET or IGBT-FET structure is in an off state, a depletion region can partially form in the drift region 101 of the MOSFET or IGBT-FET structure, and, for example, current flow between the source region of the FET structure and the drift region can be reduced or stopped.

[0047] If the FET structure is a JFET structure, a drift region 101 of the JFET structure can be located between the channel region of the JFET structure and a drain region of the JFET structure, both situated on the second lateral side (e.g., a back surface) of the semiconductor substrate 102. The drain region of the JFET structure can, for example, have a first conductivity type (e.g., n+-doped). The channel region of the JFET structure can be located between the drift region 101 of the JFET structure and the source region of the JFET structure, both situated on the first lateral side of the semiconductor substrate 102. The channel region of the JFET structure and the drift region 101 of the JFET structure can, for example, have the same (e.g., first) conductivity type (e.g., n-type doped) and / or doping concentration.A transistor gate of the JFET structure can be used to control the electrical conductivity or resistance of the channel region and thus the current flowing through the channel region from the source region of the JFET structure towards the drain region. For example, at least one pn junction can be formed between one side of the channel region (n-type doped) and a gate doping region (e.g., p-type doped) located adjacent to the channel region. The transistor gate can control the pn junction between the gate doping region and the channel region, and thus control the electrical conductivity or resistance of the channel region by controlling the size of a depletion region created by the pn junction. For example, the conductive channel region in the n-type doped region (or, for example, the n-channel) of mobile carriers can be depleted or pinched off by the pn junction.

[0048] When an initial gate voltage is applied to the transistor gate of a JFET structure, the FET structure can be switched into an on state (e.g., forward-biased) (or may already be in the same state). When the JFET structure is in an on state, a conductive channel (e.g., an n-channel) can be formed (or may exist) between the source region and the drift region of the JFET structure. Current flow can then occur, for example, between the source region and the drift region of the JFET structure.

[0049] When a second gate voltage is applied to the transistor gate of the JFET structure, the FET structure can be switched to an off state. When the JFET structure is in an off state, the depletion region of the pn junction can increase and extend into the channel region of the JFET structure, thereby reducing or limiting the electrical conductivity or increasing the resistance of the channel region. Because the channel region is depleted of charge carriers, the current flow between the source region and the drift region of the JFET structure can, for example, be reduced or stopped.

[0050] The source or emitter region of the FET structure (e.g., the MOSFET, IGBT, or JFET structure) can have an average doping concentration of more than 1×10 18 Dopant atoms per cm 3 (or e.g. between 1×10 18 Dopant atoms per cm 3 and 1x1020 Dopant atoms per cm 3 ). The average doping concentration can, for example, be a measured number of dopant atoms per volume averaged over the source or emitter region of the FET structure 102.

[0051] The drain or collector region of the FET structure (e.g., the MOSFET, IGBT, or JFET structure) can have an average doping concentration of more than 1×10 18 Dopant atoms per cm 3 (or e.g. between 1×10 17 Dopant atoms per cm 3 and 1x10 20 Dopant atoms per cm 3 ). The average doping concentration can, for example, be a measured number of dopant atoms per volume averaged over the drain or collector region of the FET structure 102.

[0052] The body region of the MOSFET or IGBT structure can have an average doping concentration between 5×10 16Dopant atoms per cm 3 and 1x10 17 Dopant atoms per cm 3 (or e.g. between 2×10 17 Dopant atoms per cm 3 and 1x10 18 Dopant atoms per cm 3 ). The average doping concentration can, for example, be a measured number of dopant atoms per volume averaged over the body region of the FET structure 102.

[0053] A region exhibiting the first conductivity type can be a p-type doped region (e.g., caused by the introduction of aluminum or boron ions) or an n-type doped region (e.g., caused by the introduction of nitrogen, phosphorus, or arsenic ions). Consequently, the second conductivity type indicates the opposite: an n-type doped region or a p-type doped region. In other words, the first conductivity type can indicate n-type doping, and the second conductivity type can indicate p-type doping, or vice versa.

[0054] The semiconductor device 100 can comprise a source or emitter contact structure that is electrically connected to the source or emitter regions of most FET structures. To establish a source-to-body region short circuit, the source or emitter contact structure can further be electrically connected to body regions of most FET structures. The semiconductor device 100 can further comprise a drain or collector contact structure that is electrically connected to the drain or collector regions of most FET structures. The semiconductor device 100 can further comprise a transistor gate contact structure that is electrically connected to the transistor gates of the FET structures.Each of the source or emitter contact structure, the drain or collector contact structure, and the transistor gate contact structure can comprise or be formed from one or more metallization layers, which may be formed on surfaces of the semiconductor substrate 102. Each of the source or emitter contact structure, the drain or collector contact structure, and the transistor gate contact structure can, for example, be electrically isolated from each other outside the semiconductor substrate.

[0055] The majority of FET structures can, for example, be electrically connected in parallel with at least one SD structure or the MGD structure 104. For example, a FET structure from the majority of FET structures can be connected in parallel (e.g., antiparallel) with the diode structure 104. The diode structure 104 can be (either) the Schottky diode structure or the gate-controlled metal-insulation-semiconductor diode structure 104 described herein.

[0056] The diode structure 104 can be connected antiparallel to the FET structure such that the diode structure 104 can be reverse-biased (switched off) when the FET structure is forward-biased (e.g., switched on or off), and vice versa. In this way, the diode structure 104 can act as a freewheeling diode, providing a path for charge carriers from the drain or drift region of the FET structure when the FET structure is reverse-biased. For an n-channel transistor in forward-biased operation (e.g., when a positive voltage is applied to the drain of the transistor), the freewheeling diode can be in reverse polarity (e.g., because a positive voltage is applied to the cathode and a negative voltage is applied to the anode of the freewheeling diode).For an n-channel transistor in reverse bias operation (or body diode operation), if a more negative voltage is applied to the drain than to the source, the freewheeling diode can carry the current, regardless of whether the transistor is in a conducting on-state or a blocking off-state. It is understood that the inverse voltage polarities (compared to those applied to the n-channel transistor) can be applied to the drain and source of a p-channel transistor to achieve forward bias operation or reverse bias operation.

[0057] The source or emitter contact structure can furthermore be electrically connected to the Schottky contact interface (or, for example, to the Schottky contact) of the SD structure if the diode structure 104 is an SD structure, or to the gate electrode of the MGD structure if the diode structure 104 is an MGD structure. The source or emitter contact structure can furthermore be electrically connected, for example, to a body region of the MGD structure. The source or emitter contact structure can furthermore be electrically connected to the plurality of compensation regions. Optionally, the source or emitter contact structure can be electrically connected to the plurality of compensation regions 103, for example, via (or through) the SD structure or MGD structure 104 located between the source or emitter contact structure and the plurality of compensation regions 103.

[0058] The drain or collector contact structure can be electrically connected to the drift regions of the SD structure or MGD structures 104 and / or the drift regions of the FET structures. For example, the drain or collector contact structure can be electrically connected to the common drift zone.

[0059] Each semiconductor device 100 can, for example, be a power semiconductor device with a breakdown voltage or blocking voltage of more than 10 V (e.g., a breakdown voltage of 10 V, 20 V or 50 V), more than 100 V (e.g., a breakdown voltage of 200 V, 300 V, 400 V or 500 V), more than 500 V (e.g., a breakdown voltage of 600 V, 700 V, 800 V or 1000 V), or more than 1000 V (e.g., a breakdown voltage of 1200 V, 1500 V, 1700 V, 2000 V, 3300 V or 6500 V).

[0060] The semiconductor substrate 102 can be a silicon-based semiconductor substrate (e.g., a silicon substrate). For example, the semiconductor substrate 102 can be a high-bandgap semiconductor substrate with a bandgap greater than that of silicon (1.1 eV). For example, the semiconductor substrate 102 can be a binary or ternary III-V semiconductor substrate, a binary or ternary II-VI semiconductor substrate, diamond, a silicon carbide-based (SiC-based) semiconductor substrate, a gallium arsenide-based (GaAs-based) semiconductor substrate, or a gallium nitride-based (GaN-based) semiconductor substrate.

[0061] The first lateral surface, or front surface, of the semiconductor substrate 102 can be a surface of the semiconductor substrate 102 facing metal layers, insulating layers, and / or passivation layers on top of the substrate surface or a surface of one of these layers. These layers can each, for example, cover a portion or section of the surface of the semiconductor substrate 102. For example, a front surface of the semiconductor substrate 102 can be the side where active elements of the chip are formed. In a power semiconductor chip, a chip front surface can, for example, be a side of the chip where a source region and a gate region are formed, and a chip back surface can be a side of the chip where a drain region is formed. For example, more complex structures can be located on the chip front surface than on the chip back surface. It is understood that other configurations are also possible.In a source-down configuration, for example, a source region and a gate region can be located on the back of the chip, and the drain region can be located on the front of the chip.

[0062] A lateral surface of the semiconductor substrate 102 can be an essentially flat plane (e.g., neglecting any unevenness of the semiconductor structure due to the manufacturing process or, for example, structured layers and / or structured grooves). For example, the lateral dimension of the lateral surface of the semiconductor substrate 102 can be more than 100 times (or more than 1000 times or more than 10000 times) larger than the maximum height of any structures on the main surface. Compared to a fundamentally vertical boundary (resulting, for example, from separating the chip substrate from others) of the semiconductor substrate 102, the lateral surface can be a fundamentally horizontal surface extending laterally.The lateral dimension of the lateral surface of the semiconductor substrate 102 can, for example, be more than 2 times (or more than 10 times or more than 100 times) larger than a basically vertical edge of the semiconductor substrate 102.

[0063] A first lateral direction can, for example, be a direction essentially parallel to a lateral surface of the semiconductor substrate. A second lateral direction can, for example, be a direction essentially parallel to the lateral surface of the semiconductor substrate and orthogonal (or perpendicular) to the first lateral direction. A vertical direction can, for example, be a direction essentially orthogonal (or perpendicular) to the lateral surface of the semiconductor substrate.

[0064] The semiconductor device can further comprise at least one (e.g., one or more) shielding doping regions (e.g., as in Fig. 2A). The at least one shielding doping region may exhibit (or have) the second conductivity type (e.g., p-type doped). A doping concentration of the at least one shielding doping region may, for example, be higher than a doping concentration of the majority of compensation regions. For example, the shielding doping region may have an average doping concentration greater than 1 × 10 16 Dopant atoms per cm 3 (or e.g. larger than 1×10 17 Dopant atoms per cm 3 or e.g. larger than 1×10 18 Dopant atoms per cm 3 The average doping concentration can, for example, be a measured number of dopant atoms (e.g., acceptor dopant atoms) per volume averaged over the shielding doping region.

[0065] Each shielding doping region can be located adjacent to the diode structure 104. For example, a shielding doping region can be located between the diode structure 104 and a drift region 101 of the FET structure. Alternatively, additionally, or optionally, a shielding doping region can be located between a compensation region 103 from the plurality of compensation regions and the diode structure 104. Alternatively, additionally, or optionally, a shielding doping region can extend from the diode structure 104 towards a channel region of a FET structure from the plurality of FET structures (e.g., as in Fig. 2A shown).

[0066] The shielding doping region can, for example, have a maximum lateral dimension of less than 800 nm (or, for example, less than 500 nm, or, for example, between 10 nm and 400 nm, or, for example, between 50 nm and 100 nm). For example, a maximum lateral dimension of the shielding doping region can be the greatest distance measured between a first (essentially) vertical side of the shielding doping region and a second (essentially) vertical side of the shielding doping region in a direction parallel to the first lateral surface of the semiconductor substrate 102. A maximum vertical dimension of the shielding doping region can, for example, be between 200 nm and 4 µm (or, for example, between 500 nm and 3 µm).For example, the maximum vertical dimension of the shielding doping region can be the greatest distance between a first lateral surface of the semiconductor substrate and a bottom of the shielding doping region in a direction orthogonal or perpendicular to the first lateral surface of the semiconductor substrate 102.

[0067] The shielding doping regions can be electrically connected, for example, to the source or emitter contact structure or to the gate contact structure on the first lateral surface of the semiconductor substrate 102.

[0068] The pn junction between the body region and the drift region of a FET structure can, for example, exhibit a comparatively high forward threshold voltage (e.g., forward voltage) due to the large band gap of the semiconductor substrate (e.g., in a SiC-based semiconductor substrate). For instance, the threshold voltage may be substantially higher than the voltage drop across the MOS component in forward operation. For a SiC-based semiconductor device, the conductivity in the p-type doped region (e.g., the body region) may be low due to the high activation energy of the dopants for p-type conduction and the low mobility of holes in the SiC substrate. Additionally, the bipolar operation of SiC structures can present further challenges regarding crystal stability.The diode structure 104 provides a body diode function of a SiC semiconductor circuit (or device) that can exhibit a forward voltage in normal operation that is lower (or smaller) than the forward voltage of the pn junction (between the body region and the drift region of a FET structure) in the SiC semiconductor substrate.

[0069] The discrete diode structure 104 (e.g., a SiC Schottky diode or an MGD diode) with a lower forward threshold voltage can be implemented antiparallel to the SiC (FET structure) semiconductor circuit. Adding a second chip can increase the total chip area and / or costs, and the thermal efficiency (e.g., in motor operation of an inverter (cos φ ≈ 1) and in generator operation (cos φ ≈ -1)) can be worse in a parallel circuit with the same total semiconductor area, since only a portion of the total area can be used for heat dissipation. Because the diode structure 104 is implemented monolithically within the same (or common) semiconductor substrate 102 as the FET structure, a second chip (or semiconductor substrate) is not necessary, for example. Thus, manufacturing costs can be kept low. Furthermore, the thermal capabilities (e.g.,(in motor or generator operation). Furthermore, the need for a parallel circuit with the same total semiconductor area and the use of only a portion of the total area for heat dissipation can be avoided.

[0070] The examples described herein may refer to monolithically integrated (body) diode structure functionality in SiC semiconductor circuits (e.g., SiC MOSFETs, SiC compensation MOSFETs, SiC JFETs, and / or SiC compensation JFETs) with a lower forward threshold voltage than a SiC pn diode. The body diode structure may also be integrated with p-regions (shielding doping regions) of SiC JFETs at source potential, with or without additional compensation regions. The integration of MGD and / or SD body diode structures may be possible, for example, with a JFET channel for forward biasing of a SiC transistor.

[0071] In some examples, the body diode functionality in the chip can be spatially separated from the switching region (e.g., to simplify structuring). For instance, the body diode structure 104 can be arranged in a ring shape around the cell or trench region. The distance between the two regions can be small enough that power dissipation in the regions can diffuse under other regions, allowing, for example, the entire chip area to be used for thermal dissipation. With a connection offering high thermal conductivity close to the semiconductor body, such as a copper layer with a thickness of several micrometers, the distance between the regions can be comparable to the chip thickness. At higher thermal conductivities, the distance can increase, for example, due to heat propagation effects.

[0072] The various examples described herein refer to the operating state in which an external voltage applied to a power semiconductor has an inverse polarity compared to "normal" forward bias operation, and in which, by a signal from a control circuit, the power semiconductor switches between forward bias operation and reverse bias operation. In the reverse bias operating state (e.g., reverse bias operation or "reverse" operation), for example, a body diode, which is structurally always present in the power semiconductor, is polarized in the forward direction.

[0073] In the examples described herein, a unipolar current path is proposed that runs parallel to the pn-body diode. This unipolar current path can have a lower forward voltage than the pn diffusion voltage, which can be 2.8 V or more for a high-bandgap semiconductor (e.g., silicon carbide). This allows for a significant reduction in forward (or conduction) losses during body diode operation. This unipolar current path can be implemented using either the Schottky or the MGD structure described in connection with the examples. Neither the Schottky nor the MGD structures cause carrier flooding, thus eliminating the need for carrier removal during normal operation.

[0074] Under normal operating conditions, no current flows through the pn diode, which is why, for example, no charge carrier injection occurs in the drift zone and no drift zone flooding takes place. Due to the lack of flooding charges, switching losses in the body diode during an externally induced switching from forward conduction to reverse conduction (e.g., by an external reversal of the load terminal polarity) are reduced.

[0075] Due to the lack of carrier injection, the electrical conductivity in the drift zone is limited. This means that the device cannot conduct high current densities in body diode operation (e.g., in a fault condition). Therefore, deep p-regions (e.g., compensation regions) that are ohmically connected to the source electrode can extend into the drift zone. During a high rise in the forward current flowing through the body diode, which leads to a high rise in the body diode's forward voltage, these compensation regions inject charge carriers, thus improving the electrical conductivity in the drift zone and increasing the overall conductivity of the body diode (e.g., the overall conductivity of the body diode structure, which includes the pn junction between the compensation regions and the drift regions, and the SD or MGD structure).These measures can improve the shortcomings inherent in unipolar body diodes. The compensation regions can also lead to a faster lateral removal of bipolar charge carriers, resulting in higher reverse current peaks and harsh switching behavior (in other operating states).

[0076] The shielding structures (e.g., the shielding doping regions) can prevent or reduce overload (e.g., due to overvoltages) of the Schottky diode or MGD diode. Additionally or optionally, the shielding doping regions can protect the gate regions of the semiconductor device from breakdown caused by high electric fields in the direction of the gate region.

[0077] Fig. Figure 1B shows a schematic representation of a section of the semiconductor device 120 according to an exemplary embodiment.

[0078] The semiconductor device 120 can be similar to the one used in conjunction with Fig. 1A described semiconductor component 100.

[0079] The diode structure 104 can be a monolithically integrated Schottky diode structure, as in Fig. Figure 1B shows that the SD structure 104 can comprise a Schottky contact 123 (e.g., a Schottky contact material) that is directly located on a compensation region 103 (e.g., a p-type doped column). For example, the bottom of a trench structure in which the SD contact 123 is formed can be adjacent to the top of the compensation region 103. For example, at least part of the Schottky contact 123 can form at least one Schottky contact interface 121 with a section of the semiconductor substrate 102. The Schottky interface 121 can be located, for example, on the sidewalls of the trench structure in which the SD contact 123 is formed. The Schottky interface 121 can be located, for example, on the sidewalls of the trench structure between the Schottky contact 123 and the drift region 122 of the SD structure 104. The drift region 122 of the SD structure 104 can, for example, be part of the common drift zone of the semiconductor substrate 102.

[0080] Optionally, the Schottky contact material 123 can be formed only on (or at) the side walls of the trench, and not at the bottom of the trench structure. A different (or second) electrically conductive material (or a layer stack of electrically conductive materials) can be formed in the trench structure between the Schottky contact material 123 formed on or at the side walls of the trench structure. The second electrically conductive material can, for example, make contact with a top surface of the compensation region 103 at the bottom of the trench structure. Optionally, the barrier height can differ on different surfaces of the trench structure. For example, a barrier that is higher on the side walls of the trench structure can be higher than a barrier height at the bottom of the trench structure.For example, the Schottky contact material 123 on the side walls of the trench structure can be a layer that has a smaller thickness and a reinforcing conductive material.

[0081] The Schottky interface 121, provided by the Schottky contact 123 to the drift region 122 of the SD structure 104 (e.g., N-SiC), can be located on a side wall of the trench structure. The (p-type doped) shielding doping region for blocking the electric field can be located below (or at) the bottom of the trench structure. The p-type doped shielding doping region can, for example, be a flat structure or a p-type column of a compensation structure (or the compensation structure 103). The electric field at the bottom of the trench structure can be reduced due to the p-type doped shielding doping region. For example, due to the arrangement of the Schottky diode in the upper region of the p-type column, the field strength in reverse bias mode can be reduced.

[0082] Various ways to reduce the leakage current in the Schottky metal of the Schottky contact 123 can include, for example, selecting different materials or metals and / or selectively adjusting the threshold voltage of the Schottky diode structure 104. To reduce the leakage current, for example, a Schottky metal of the Schottky contact with a higher barrier can be selected. Alternatively, additionally, or optionally, a shielding p-doping region can be implemented to lower or reduce the electric field at the Schottky barrier.

[0083] Since the deep-reaching, p-type doped columns 103 (e.g., compensation regions) are at source potential, the voltage drop across the entire forward-biased drift zone lies, for example, across the pn junction. Thus, the pn junction can inject at low current densities, leading to improved conductivity of the (body) diode structure 104 at high current densities. This can result in better surge current withstand capability compared to fused pin Schottky structures, potentially causing the pn junction to inject only when the voltage drop across the Schottky contact, combined with the low track voltage drop in the n region along the p region, is sufficiently high. Depending on the structure, this may only occur when very high currents are reached.

[0084] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 1B may have one or more additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A) or below ( Fig. Examples of embodiments described in sections 1C to 10 are mentioned.

[0085] Fig. Figure 1C shows a schematic representation of a section of a semiconductor device 130 according to an exemplary embodiment. As in Fig. As shown in Figure 1C, the semiconductor device 130 can, for example, comprise a plurality of compensation regions 103 and a plurality of SD structures 104. The semiconductor device 130 can be similar to those associated with Fig. Semiconductor components described in 1A and / or 1B.

[0086] Optionally, the compensation regions 103 can include interface regions 124 located at an interface between the compensation regions 103 and the SD contact 123. The interface regions 124 can, for example, include (or be) a highly doped region (p+-doped region). The doping concentration of the highly doped interface regions 124 of the compensation region 103 can be chosen to control or vary the contact resistance between the SD contact 123 and the compensation region 103. The highly doped interface regions 124 can have an average doping concentration of at least 1 × 10⁻⁶ 18 Dopant atoms per cm 3 (or e.g. between 1×10 18 Dopant atoms per cm 3 and 1x10 19 Dopant atoms per cm 3The average doping concentration can, for example, be a measured number of dopant atoms (e.g., acceptor dopant atoms) per volume averaged over the interface region 104. For example, a doping concentration of the highly doped interface region 124 can be higher than a doping concentration of the compensation region 103.

[0087] As in Fig. As shown in Figure 1C, the drain regions 125 of the majority of FET structures with the first conductivity type (e.g., n+-doped) can be located, for example, on a second lateral side (e.g., a back surface) of the semiconductor substrate 102. The SD contact 123 and the compensation region 103 below the SD contact 123 can be used, for example, for semiconductor devices with high blocking voltages exceeding 2000 V.

[0088] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 1C may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 1B) or below ( Fig. Examples of implementation described in sections 2A to 10 are mentioned.

[0089] Fig. Figure 1D shows a schematic top view of a section of a semiconductor device 140 according to an exemplary embodiment. As in Fig. As shown in 1D, the semiconductor device 140 can comprise a plurality of compensation regions 103.

[0090] The majority of FET structures and the diode structures 104 of the semiconductor device can be arranged in an active section (or region) 151 of the semiconductor substrate 102. An edge termination section 153 can, for example, laterally surround the active section of the semiconductor substrate 102 in the top view (or enclose it laterally or be formed around it).

[0091] The majority of compensation regions 103 can be formed in the active section 151 of the semiconductor substrate 102. Additionally or optionally, the majority of compensation regions 103 can extend towards or into the edge termination section 153 of the semiconductor substrate. Optionally, all compensation regions 103 can extend towards or into the edge termination section 153 of the semiconductor substrate.

[0092] Optionally, a first group of compensation regions 103 from the plurality of compensation regions 103 can be associated with the SD or MGD structure. For example, the first group of compensation regions 103 from the plurality of compensation regions 103 can be formed at the bottom of a trench structure in which the diode (SD or MGD) structure is formed, as in connection with Fig. 1B or Fig. 1C described.

[0093] Optionally or additionally, a second group of compensation regions 103 can be derived from the plurality of compensation regions 103, each associated with FET structures. For example, the compensation regions 103 of the second group of compensation regions 103 can each be located under a source region or body region of a FET structure. For example, the second group of compensation regions 103 can be derived from the plurality of compensation regions 103 without the SD or MGD structure, as in connection with Fig. 1B or Fig. 1C described.

[0094] Optionally, the first group of compensation regions 103 and the second group of compensation regions 103 can be arranged alternately with each other in the first lateral direction L1. For example, one compensation region 103 (or, for example, two, or three or more compensation regions 103) from the first group of compensation regions can be located between two adjacent compensation regions of the second group of compensation regions 103.

[0095] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 1D may have one or more additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 1C) or below ( Fig. Examples of embodiments described in sections 1E to 10 are mentioned.

[0096] Fig. Figure 1E shows a schematic representation of a compensation region 103 in a top view of the semiconductor device 150 according to an exemplary embodiment.

[0097] As in Fig. As shown in Figure 1E, a plurality of first sections of the compensation region can be connected to a plurality of diode (SD or MGD) structures 104. Additionally or optionally, a plurality of second sections of the compensation region can be connected to FET structures. Instead of the diode structure 104, for example, a plurality of source regions or body regions (of FET structures) on the compensation region 103 can be arranged on the plurality of second sections of the compensation region 103.

[0098] Optionally, the majority of first (or diode) sections of the compensation region 103 and the majority of second (or transistor) sections of the compensation region 103 can be arranged relative to each other in the second lateral direction L2.

[0099] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 1E may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 1D) or below ( Fig. Examples of embodiments described in sections 1F to 10 are mentioned.

[0100] Fig. Figure 1F shows a schematic representation of a compensation region 103 in a top view of the semiconductor device 160 according to an exemplary embodiment.

[0101] As in Fig. As shown in Figure 1F, the compensation region 103 can have a needle shape in the top view. For example, the ratio of a lateral dimension of the compensation region 103 in the first lateral direction to a lateral dimension of the compensation region in the second lateral direction may be less than 5:1.

[0102] The Schottky contact interfaces 121 can be formed on a first pair of sidewalls of a trench structure located on (or above) the compensation region 103. For example, the compensation region 103 can be connected to a FET structure on a second pair of sidewalls.

[0103] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 1F may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 1E) or below ( Fig. Examples of implementation described in sections 2A to 10 are mentioned.

[0104] Fig. Figure 2A shows a schematic representation of a semiconductor device 210 according to an exemplary embodiment. The semiconductor device 210 can be similar to the one shown in connection with Fig. 1A described semiconductor component 100.

[0105] The semiconductor device 210 can comprise a plurality of FET structures. In the case of the Fig. In the example shown in Figure 2A, the plurality of FET structures can, for example, comprise a plurality of JFET structures. Each JFET structure from the plurality of JFET structures can comprise a source region 233. Each source region 233 of the JFET structure can, for example, be located adjacent to a source contact structure 232 on the first lateral surface 229 of the semiconductor substrate 103.

[0106] Each source region 233 of the majority of JFET structures can be located, for example, adjacent to the source contact structure 232 and at least part of the shielding doped region 226. The shielding doped region 226 can form part of the structure that controls the channel 228 of the JFET. For example, the n-channel 228 can be located between the p-doped gate doped region 231 and the shielding doped region 226. Each source region 233 of the JFET structure can be separated from a gate doped region 231 of the JFET structure by a lateral separation distance. At least part of the channel region 228 (e.g., a second segment of the channel region) of the JFET structure can be located in the semiconductor substrate 102 between the source region 233 of the JFET structure and the gate doped region 231 of the JFET structure.

[0107] The p-doped gate doping region 231 can, for example, be in ohmic contact with the gate electrode and control the channel region 228. In the off state, a space charge region can extend to (or towards) the nearest pn junction (e.g., towards the shielding doping region 226), which can deplete the channel region 228 and prevent current flow.

[0108] The semiconductor device 210 can comprise the plurality of compensation regions 103 arranged alternately with the plurality of drift regions 101 (in a cross-section orthogonal to a lateral length of the compensation regions).

[0109] The semiconductor device 210 can comprise the diode structure 104 (which can be an SD structure or an MGD structure). In the Fig. In the example shown in Figure 2A, the diode structures 104 are, for example, MGD structures. Each MGD structure 104 can comprise the gate electrode material 235 and the gate insulating layer 236, which are arranged in the trench structure 227. The gate insulating (e.g., oxide) layer 236 can, for example, be arranged on side walls (e.g., on a first vertical side wall and a second vertical side wall) and on the bottom of the trench structure 227. The electrically conductive gate electrode material 235 (e.g., polysilicon) can, for example, be arranged in the trench structure 227 (or at least partially fill it), such that the gate insulating layer 236 is located between the gate electrode material 235 and the semiconductor substrate 102.

[0110] At least part of a (first) side wall of the trench structure 227 can, for example, be located adjacent to a drift region 237 (n-type doped) of the MGD diode structure 104 and / or a body region 238 (p-type doped) of the MGD diode structure 104. For example, the drift region 237 of the MGD diode structure 104 and / or the body region 238 of the MGD diode structure 104 can be located adjacent to a (first) side wall of the trench structure 227. The body region 238 of the MGD diode structure 104 can, for example, be located between a source region 239 of the MGD diode structure 104 and the drift region 237 of the MGD diode structure. The source region 239 of the MGD diode structure 104 can be located, for example, on the (first) side wall of the trench structure 227 between the body region 238 of the MGD diode structure 104 and the first lateral surface 229 of the semiconductor substrate 102.

[0111] The semiconductor device 210 can further comprise at least one (e.g., one or more) shielding doping regions 226. The (or each) shielding doping region 226 can, for example, be located adjacent to a side wall (e.g., a second side wall opposite the first side wall) and / or at the bottom of a trench structure 227. For example, the shielding doping region 226 can extend deeper into the semiconductor substrate 102 than the trench structure 227. For example, the shielding doping region 226 can extend from the first lateral surface 229 of the semiconductor substrate 102 along the first side wall of the trench structure 227 to the bottom of the trench structure 227, where a section of the shielding doping region 226 is formed at the bottom of the trench structure 227.

[0112] Each shielding doping region 226 can be located between a compensation region 103 from the plurality of compensation regions and the diode structure 104 (e.g., the SD structure or the MGD structure). At least one portion of the (or each) shielding doping region 226 can be located between the first lateral surface 229 of the semiconductor substrate 102 and a compensation region 103. For example, at least one portion of the shielding doping region 226 can be located (directly) adjacent between the first lateral surface 229 of the semiconductor substrate 102 and a top surface of the compensation region 103.

[0113] A first section of the shielding doping region 226 can have a lateral dimension smaller than a second section of the shielding doping region 226. For example, the second section of the shielding doping region can project (or extend) laterally from (or compared to) the first section of the shielding doping region 226. The second section of the shielding doping region 226 can, for example, have a lateral dimension larger than the lateral dimension of the first section of the shielding doping region 226 and / or the lateral dimension of the compensation region 103. For example, the shielding doping region 226 can be T-shaped or L-shaped. Optionally, the first section of the shielding doping region 226 can have a lateral dimension smaller than the lateral dimension of the compensation region 103.Optionally, a (maximum) lateral dimension of at least a portion of the shielding doping region 226 can be larger, for example, than a lateral dimension of the compensation region 103 from the plurality of compensation regions 103. The shielding doping region 226 can control the conductivity of the channel region 228. Without the shielding doping region 226, it may be impossible to turn off the channel, even when a high gate blocking voltage is applied to the gate. The shielding doping region 226 can extend from the section of at least one side wall (e.g., the first side wall) and / or the bottom of the trench structure 227 toward the channel region 228 of a JFET structure from the plurality of FET structures. For example, at least a portion of the shielding doping region 226 can extend toward the channel region 228 of a JFET structure or can be located directly adjacent to it.For example, the second section of the shielding doping region 226 can extend (or protrude) towards the gate doping region 231, which is located adjacent to a transistor gate contact structure 234 of the JFET structure, such that the second section of the shielding doping region 226 is located adjacent to (or parallel to) the gate doping region 231.

[0114] At least a portion of the channel region 228 of the JFET structure can be located between the second section of the shielding doping region 226 and the gate doping region 231 of the JFET structure. For example, at least a portion of the channel region 228 located in the semiconductor substrate 102 can be substantially horizontal (or parallel) to the surface of the semiconductor substrate 102. In other words, a flux of charge carriers in the horizontal portion of the channel region 228 can, for example, be in a direction parallel to the surface of the semiconductor substrate 102.

[0115] Each JFET structure can be located, for example, between adjacent MGD diode structures 104 and / or between adjacent (or successive) shielding doping regions 226 and / or between adjacent compensation regions 103 from the plurality of compensation regions 103.

[0116] The semiconductor device 210 can comprise the source contact structure 232, which is electrically connected to the majority of source regions 233 of the majority of JFET structures on the first lateral surface 229 of the semiconductor substrate 102. The shielding doping regions 226, the gate electrode material 235 of the MGD structures 104, the source region of the MGD structures 104, and / or the body regions of the MGD structures 104 can, for example, be electrically connected to the source or emitter contact structure 232 on the first lateral surface 229 of the semiconductor substrate 102.

[0117] The drain region 125 of the majority of FET structures with the first conductivity type (e.g., n-doped) can be located, for example, on a second lateral side (e.g., a back surface) of the semiconductor substrate 102. The drain regions 125 of the majority of FET structures can be electrically connected to the drain contact structure on the second lateral surface of the semiconductor substrate 102.

[0118] Optionally, the lateral dimension of the drift regions 101 between the compensation regions 103 can be made narrower. For example, the maximum lateral dimension of a drift region of a FET structure can be equal to the maximum lateral dimension of a compensation region 103.

[0119] The JFET channel region 228 can be located at source potential between the transistor gate 234 of the JFET structure (or between the gate doping region 231) and the p-type doped shielding doping region 226. The semiconductor device 200 can be stable against an avalanche because the gate 234 (and the gate doping region 231) can be protected by the shielding doping region 226 from breakdown caused by the high electric fields in the direction towards the gate doping region 231 and the transistor gate 234.

[0120] JFET structures can be used in SiC technology because the channel includes a doping region and exhibits the high electron mobility of the substrate, unlike a SiC MOSFET where the mobility in the channel is limited in the on-state during forward bias operation. Thus, the device can have a lower on-resistance. In forward operation of the body diode, meaning that the drain electrode is at a lower potential than the source electrode, the electrons from the drain must overcome the high barrier to the p-type SiC (shielding doping region 226 at source potential) at a negative gate-source voltage (JFET channel cut-off), which can generate high conduction losses due to the band gap.

[0121] The MGD structure 104 with a low forward threshold voltage can help remove electrons from the drain region 125. The gate electrode material 235 of the MGD structure 104 can be formed in the trench structure 227, and a source potential can be applied to the gate electrode material 235. The gate electrode material 235 of the MGD structure 104 can be separated from the body region 238, which is doped with material of the second conductivity type (e.g., p-type) of the MGD structure 104, and the source region 239, which is doped with material of the first conductivity type (e.g., n-type) of the MGD structure 104, above (or adjacent to) the p-type region (the body region), by the gate insulating layer 236 (e.g., a dielectric layer). The body region 238 of the MGD structure 104 and the source region 239 of the MGD structure 104 can, for example, be connected to the source contact structure 232 (source electrode).

[0122] If the potential in the drift zone is reduced, the potential directly at the pn junction (between body region 238 and drift region 237 of the MGD structure) can also be reduced below the source potential. Thus, an n-channel can be formed or controlled by appropriately doping the p-type-doped body region 238 of the MGD structure and by appropriately dimensioning the thickness of the gate insulating layer 236 (dielectric). The n-channel can, for example, conduct electrons from the drain (e.g., the drain region) directly to the n-source region (the source region) without the pn junction being driven in a forward direction and injecting holes.

[0123] The use of SiC can further simplify the design of the MGD cell due to its high band gap compared to silicon (Si). At high current densities of the body diode structure 104 and with high channel voltage drop and channel mobility, the pn junction can be implemented, which can lead to a reduced rise in forward voltage at higher forward currents and good surge current capability of the body diode structure 104.

[0124] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2A may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 1C) or below ( Fig. Examples of implementation described in sections 2B to 10 are mentioned.

[0125] Fig. Figure 2B shows a schematic representation of a semiconductor device 220 according to an exemplary embodiment. The semiconductor device 220 can be similar to the one in conjunction with Fig. 2A described semiconductor device. For example, semiconductor device 220 can be one, more, or all of the semiconductor devices associated with the semiconductor device of Fig. exhibit the characteristics described in 2A.

[0126] The semiconductor device 220 can comprise two JFET structures arranged between successive (or adjacent) diode structures 104 arranged sequentially in a later direction. For example, the semiconductor device 220 can comprise two JFET structures arranged between successive, adjacent, shielding doping regions 226 arranged sequentially in a later direction. For example, the two JFET structures can have a common (or shared) transistor gate and / or a common (or shared) gate doping region 231. For example, a channel region 228 of the first JFET structure and a channel region 228 of the second JFET structure can be arranged between a source region 233 of the first JFET structure and a first source region 233 of the second JFET structure.For example, the channel region 228 of the first JFET structure can be located between a first section of the gate doping region 231 and a first shielding doping region 226. Similarly, the channel region 228 of the second JFET structure can be located between a second (different) section of the same gate doping region 231 and a second (different) shielding doping region 226. The source region 233 of the first JFET structure and the source region 233 of the second JFET structure can be located, for example, between the first shielding doping region 226 and the second (adjacent or consecutive) shielding doping region 226 in the first lateral direction. Optionally, the pair of JFET structures can be arranged repeatedly in the lateral direction of the semiconductor substrate.Optionally, a body region 238 of an MGD diode structure 104 and a body region 238 of an adjacent MGD diode structure 104 can overlap between each pair of JFET structures. For example, a continuous body region 238 of a first MGD diode structure 104 and a second MGD diode structure 104 can be arranged between each pair of JFET structures.

[0127] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2B may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 2A) or below ( Fig. Examples of embodiments described in sections 2C to 10 are mentioned.

[0128] Fig. Figure 2C shows a schematic representation of a semiconductor device 230 according to an exemplary embodiment. In the case of the Fig. In the example shown in 2C, the majority of FET structures can be, for example, a majority of MOSFET or IGBT structures.

[0129] Each MOSFET structure can include a transistor gate 244. The transistor gate 244 can include a transistor gate electrode material 245 and a transistor gate insulating layer 246, arranged in a gate trench structure 248. The transistor gate insulating (e.g., oxide) layer 246 can be located on side walls (e.g., on a first vertical side wall and a second vertical side wall) and at the bottom of the gate trench structure 248. The electrically conductive transistor gate electrode material 245 (e.g., polysilicon) can, for example, be arranged in (or at least partially fill) the gate trench structure 248 such that the transistor gate insulating layer 246 is located between the transistor gate electrode material 245 and the semiconductor substrate 102. The transistor gate 244 of the MOSFET structure can be isolated from the source region by a (thicker) gate dielectric and can be externally connected in the plane to an electrode (e.g.a gate contact structure).

[0130] At least a portion of at least one sidewall of the gate-trench structure 248 can be located adjacent to a drift region 101 of a first conductivity type (e.g., n-type doped) of the MOSFET or IGBT structure and / or a body region 241 of a second conductivity type (e.g., p-type doped) of the MOSFET or IGBT structure. For example, the drift region 101 of the MOSFET or IGBT structure and / or the body region 241 of the MOSFET or IGBT structure can be located adjacent to a (first) sidewall of the gate-trench structure 248. The body region 241 of the MOSFET or IGBT structure can be located between a source or emitter region 242 of the MOSFET or IGBT structure and the drift region 101 of the MOSFET or IGBT structure.The source or emitter region 242 of the MOSFET or IGBT structure can be located on the (first) side wall of the gate trench structure 248 between the body region 241 of the MOSFET or IGBT structure and the first lateral surface 229 of the semiconductor substrate 102.

[0131] Optionally, the body region 241 of the MOSFET or IGBT structure can be connected (e.g., electrically connected) to the shielding doping region 226, which is located on the side wall of the trench structure 227. For example, the body region 241 of the MOSFET or IGBT structure and the shielding doping region 226 can be adjacent to each other or can form a common doping region. Optionally, the body region 241 of the MOSFET or IGBT structure and the shielding doping region 226 can have the same doping concentration.

[0132] The semiconductor device 230 can further comprise at least one (e.g., one or more) transistor gate shielding doping regions 247. The (or each) transistor gate shielding doping region 247 can be located adjacent to at least one side wall (e.g., a second side wall opposite the first side wall) and / or the bottom of a transistor gate trench structure 248. The transistor gate shielding doping region 247 can extend deeper into the semiconductor substrate 102 than the transistor gate trench structure 248. For example, the transistor gate shielding doping region 247 can extend from the first lateral surface 229 of the semiconductor substrate 102 along the first side wall of the transistor gate trench structure 248 to the bottom of the transistor gate trench structure 248, with a portion of the transistor gate shielding doping region 247 located at the bottom of the transistor gate trench structure. 248 is formed.

[0133] The transistor gate shielding doping region 247 can be located adjacent to a compensation region 103 from the plurality of compensation regions and the transistor gate trench structure 248. At least part of (or all of) the transistor gate shielding doping region 247 can be located between the first lateral surface 229 of the semiconductor substrate 102 and a top surface of the compensation region 103. For example, at least a portion of the transistor gate shielding doping region 247 can be located (directly) adjacent to the first lateral surface 229 of the semiconductor substrate 102 and the compensation region 103.

[0134] Optionally, the transistor gate shielding doping region 247 can have the same conductivity type and / or doping concentration as the shielding doping region 226. The transistor gate shielding doping region 247 can have similar (or identical) dimensions to the shielding doping regions 226.

[0135] Optionally, the gate-shielding doped region 247 and / or the shielding doped region 226 can be in ohmic contact with the body and / or source potential of the transistor. This can be advantageous if the gate-shielding doped region 247 and / or the shielding doped region 226 serve to electrically connect the compensation region 103 to the source potential, as e.g., in Fig. 2C shown. However, this is not necessarily the case. The gate-shielding doping region 247 and the shielding doping region 226 can only be maintained at a voltage that does not deviate too much from the voltage of the gate electrode 245 and / or the gate electrode 235 of the MGD structure, in order to avoid overstressing the transistor gate insulation layer 246 and / or the gate insulation layer 236. This can also be achieved, for example, by maintaining only a small distance between the gate-shielding doping region 247 and / or the shielding doping region 226 with a low doping of the opposite conductivity type, e.g., the doping of the drift region 102.

[0136] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2C may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 2B) or below ( Fig. Examples of implementation described in sections 2D to 10 are mentioned.

[0137] Fig. Figure 2D shows a schematic representation of a semiconductor device 240 according to an exemplary embodiment. In the Fig. In the 2D example, the majority of FET structures can be, for example, a majority of MOSFET or IGBT structures.

[0138] The diode structure 104, arranged between two adjacent (vertical) MOSFET structures, is in Fig. Shown in 2D. The diode structure 104 can be an SD structure 104. The SD structure 104 can, for example, include a Schottky contact 123 that forms a Schottky contact interface 121 with a section of the semiconductor substrate 102. The Schottky contact 123 can be located at (or on or above) the first lateral surface 229 of the semiconductor substrate 102. For example, the Schottky contact interface 121 can extend along the first lateral surface 229 of the semiconductor substrate 102. The Schottky interface 121 can be located between the Schottky contact 123 and the drift region 122 of the Schottky diode structure 104. The Schottky contact interface 121 can, for example, be arranged on the first lateral surface 229 of the semiconductor substrate 102 between the Schottky contact 123 and the semiconductor substrate 102.

[0139] The Schottky contact 123 and the Schottky contact interface 121 can extend laterally along the first lateral surface 229 of the semiconductor substrate 102 from a gate-shielding doping region 247, which is adjacent to at least one side wall and / or bottom of a transistor gate trench structure 248 of a first (vertical) MOSFET structure, towards a second adjacent (vertical) MOSFET structure. For example, the Schottky contact 123 and the Schottky contact interface 121 can extend laterally from the gate-shielding doping region 247 of the first MOSFET structure towards (or to) a body region 241 of the second MOSFET structure. A first section of the Schottky contact 123 can overlap the gate-shielding doping region 247 of the first MOSFET structure on the first lateral surface 229 of the semiconductor substrate 102.A second section of the Schottky contact 123 can overlap the body region 241 of the second MOSFET structure at the first lateral surface 229 of the semiconductor substrate 102. For example, the first section of the laterally extending Schottky contact 123 (vertically) can be arranged between the gate-shielding doping region 247 of the first MOSFET structure and the source contact structure 232, which is located at the first lateral surface 229 of the semiconductor substrate 102. For example, the second section of the laterally extending Schottky contact 123 (vertically) can be arranged between the body region 241 of the second MOSFET structure and the first source contact structure 232, which is located at the first lateral surface 229 of the semiconductor substrate 102.

[0140] The (maximum) thickness of the laterally extending Schottky contact 123 can be, for example, less than 300 nm (or, for example, less than 200 nm or, for example, less than 100 nm). A power metallization located on or above the Schottky contact 123 can have a thickness between 2 µm and 10 µm. It is understood that the Schottky contact 123 can optionally be used in conjunction with Fig. The trench structure described in sections 1A to 2C may be formed.

[0141] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2D may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 2C) or below ( Fig. Examples of embodiments described in sections 2E to 10 are mentioned.

[0142] Fig. Figure 2E shows a schematic representation of a semiconductor device 250 according to an exemplary embodiment. In the case of the Fig. In the example shown in 2E, the plurality of FET structures can, for example, be a plurality of JFET structures.

[0143] The Schottky contact 123 can be located between adjacent (vertical) JFET structures. For example, the JFET structures can be similar to those associated with Fig. 2A describes the JFET structures. For example, each JFET structure can include the first source region 233, which is adjacent to at least part of the shielding doping region 226. Each JFET structure can, for example, include the gate doping region 231 and a channel region 228, which are located in the semiconductor substrate 102.

[0144] The Schottky contact 123 and / or the Schottky contact interface 121 can, for example, extend laterally along the first lateral surface 229 of the semiconductor substrate 102 between a (first) shielding doping region 226 and a (essentially) vertically extending shielding doping region 249.

[0145] The vertically extending, shielding doping region 249 can be a doping region that extends (essentially) vertically into the semiconductor substrate 102 from the first lateral surface 229 of the semiconductor substrate 102. The vertically extending, shielding doping region 249 can be located between a first diode structure 104 and a second (adjacent) diode structure 104. For example, the vertically extending, shielding doping region 249 can be located between a (first) shielding doping region 226 that is adjacent to a first diode structure 104 and a (first) shielding doping region 226 that is adjacent to an adjacent (successive) second diode structure 104.The vertically extending, shielding doping region 249 can be arranged between a gate doping region 231 of a first JFET structure and (first) shielding doping region 226, which is adjacent to a source region 233 of an adjacent second JFET structure.

[0146] The Schottky contact 123 and / or the Schottky contact interface 121 can, for example, extend laterally from the shielding doped region 226 towards (or to) the vertically extending shielding doped region 249. The first shielding doped region 226 can, for example, be located between a compensation region 103 from the plurality of compensation regions and the diode structure 104. A first section of the Schottky contact 123 can overlap the shielding doped region 226 at the first lateral surface 229 of the semiconductor substrate 102. A second section of the Schottky contact 123 can overlap the vertically extending shielding doped region 249 at the first lateral surface 229 of the semiconductor substrate 102.For example, the first section of the laterally extending Schottky contact 123 (vertically) can be arranged between the shielding doping region 226 of the first MOSFET structure and the first source contact structure 232, which is located on the first lateral surface 229 of the semiconductor substrate 102. For example, the second section of the laterally extending Schottky contact 123 (vertically) can be arranged between the vertically extending shielding doping region 249 and the first source contact structure 232, which is located on the first lateral surface 229 of the semiconductor substrate 102.

[0147] The vertically extending, shielding doping region 249 can be of the second conductivity type (e.g., p-type doped). The doping concentration of the vertically extending, shielding doping region 249 can be higher than the doping concentration of the majority of compensation regions. For example, the vertically extending, shielding doping region 249 can have a net doping concentration greater than 1 × 10⁻⁶ 16 Dopant atoms per cm 3 (or e.g. larger than 1×10 17 Dopant atoms per cm 3 or e.g. larger than 1×10 18 Dopant atoms per cm 3 ). Optionally, the vertically extending, shielding doping region 249 can, for example, have the same (or similar) doping concentration as the shielding doping region 226.

[0148] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2E may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 2D) or below ( Fig. Examples of embodiments described in sections 2F to 10 are mentioned.

[0149] Fig. Figure 2F shows a schematic representation of a semiconductor device 260 according to an exemplary embodiment. The semiconductor device 260 can be similar to the one shown in conjunction with Fig. 2E described semiconductor device.

[0150] The vertically extending, shielding doping region 249 can be omitted, as shown in Fig. Figure 2E shows that the shielding doping region 226 can, for example, have a T-shaped structure. The shielding doping region 226 can comprise a first section extending vertically from the first lateral surface 229 of the semiconductor substrate 102 toward (or to) the compensation region 103 adjacent to the shielding doping region 226. A second section of the shielding doping region 226 can project (or extend) laterally from the first section of the shielding doping region 226 toward the channel region 228 of the first JFET structure. At least part of the channel region 228 of the JFET structure can be located between the second section of the shielding doping region 226 and the gate doping region 231 of the JFET structure.The second section of the shielding doping region 226 can extend laterally such that the second section of the shielding doping region 226 is arranged parallel to more than 50% of the laterally extending gate doping region 231 of the JFET.

[0151] A third section of the shielding doped region 226 can optionally project (or extend) laterally from the first section of the shielding doped region 226 in a direction opposite to that of the second section of the shielding doped region 226. The third section of the shielding doped region 226 can extend toward an adjacent shielding doped region 226 and / or an adjacent second JFET structure. For example, at least part of the (n-doped) drift region 122 of the Schottky diode structure 104 can be located laterally between the Schottky contact 123 and the third section of the shielding doped region 226.

[0152] For example, the third section of the shielding doping region 226 does not extend further in the direction of the gate doping region 231 than the compensation region 103. The lateral distance between the second section of a first shielding doping region 226 and a third section of an adjacent second shielding doping region 226 can be controlled, since the lateral distance determines the range (or breakdown) of the electric field in the direction of the gate 234 and the Schottky contact 123.

[0153] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2F may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above ( Fig. 1A to 2E) or below ( Fig. Examples of implementation described in sections 2G to 10 are mentioned.

[0154] Fig. Figure 2G shows a schematic representation of a semiconductor device 270 according to an exemplary embodiment.

[0155] Similar to those associated with Fig. According to the semiconductor device described in Figure 2B, the semiconductor device 270 can comprise two JFET structures arranged between successive (or adjacent) diode structures 104 that are arranged consecutively in a lateral direction. For example, the semiconductor device 270 can comprise two JFET structures arranged between adjacent shielding doping regions 226 that are arranged consecutively in a lateral direction. For example, two JFET structures can be arranged between a shielding doping region 226 adjacent to a first diode structure 104 and a shielding doping region 226 adjacent to an adjacent second diode structure 104. For example, the two JFET structures can have a common (or shared) transistor gate and / or a common (or shared) gate doping region 231.

[0156] Similar to the one associated with Fig. In the semiconductor device described in Section 2E, the Schottky contact 123 and / or the Schottky contact interface 121 of the diode structure 104 can, for example, extend laterally along the first lateral surface 229 of the semiconductor substrate 102 between a (first) shielding doping region 226 and a vertically extending shielding doping region 249. Optionally, each vertically extending shielding doping region 249 can be located between a shielding doping region 226 of a first JFET structure and a shielding doping region 226 of an adjacent second JFET structure.

[0157] The in connection with Fig. The various examples described in Sections 2A to 2G each show different arrangements of diode structures 104 and FET structures relative to each other. In some examples, the MGD / SD cells and the MOSFET / JFET cells are shown to be directly adjacent to each other. For example, each MGD / SD structure 104 can be adjacent to a MOSFET / JFET structure (an MGD-MOSFET-MGD-MOSFET arrangement). In some examples, the semiconductor device can comprise repeated blocks of two (or more) laterally adjacent MOSFET / JFET cell structures for each one (or more) laterally adjacent MGD / SD structure 104 (e.g., two MOS cells for each MGD cell, or, for example, a MOSFET-MOSFET-MGD-MOSFET-MOSFET-MGD arrangement). Alternatively or optionally, the semiconductor device can comprise repeated blocks of three laterally adjacent MOSFET / JFET cell structures per two laterally adjacent MGD / SD structures 104 (e.g., three MOS cells per two MGD cells, or e.g.,a MOSFET-MOSFET-MOSFET-MGD-MGD-MOSFET-MOSFET-MGD-MGD arrangement). Alternatively or optionally, the semiconductor device can comprise repeated blocks of one MOSFET / JFET cell structure per two laterally adjacent MGD / SD structures (e.g., one MOS cell per two MGD cells or, for example, a MOSFET-MGD-MGD-MOSFET-MGD-MGD arrangement). Alternatively or optionally, the MOSFET / JFET and MGD / SD cells can be arranged laterally alternating in a lateral direction. Alternatively or optionally, two, three, or four MOSFET / JFET cells can be arranged laterally adjacent to a plurality of MGD / SD cells.

[0158] The spacing (pitch) of the MOSFET / JFET and MGD / SD diode cells can vary, for example, depending on the required current-carrying capacity of the diodes compared to the MOSFET or JFET structures. A mixed arrangement of MOSFET / JFET and MGD / SD cells can improve the thermal performance of the transistor, as they can be activated alternately, and the adjacent inactive section of the chip can be used, for example, for heat dissipation.

[0159] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 2G may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or to one or more of the above (e.g. 1A to 2F) or below ( Fig. Examples of implementation described in sections 3A to 10 are mentioned.

[0160] Fig. Figures 3A to 3C show schematic top-view drawings of possible layouts for a semiconductor device according to various embodiments. For example, they show Fig. 3A to 3C, that MOSFET / JFET structures and MGD / SD structures can be separated into large blocks in different regions of the semiconductor substrate 102.

[0161] Fig. Figure 3A shows a schematic top view of a layout of a semiconductor device 310.

[0162] The majority of FET structures of the semiconductor device 310 can be arranged in a first section 351 (e.g., a transistor cell region) of the semiconductor substrate 102. The diode structures 104 of the semiconductor device 310 can be formed in a second section 352 of the semiconductor substrate 102. The second section 352 of the semiconductor substrate 102 can laterally surround the first section 351 of the semiconductor substrate 102 in a top view. For example, an edge termination section 353 can laterally surround (or laterally enclose or be formed around) the second section of the semiconductor substrate 102 in a top view.

[0163] Fig. Figure 3B shows a schematic top view of a layout of a semiconductor device 320.

[0164] The majority of FET structures of the semiconductor device 310 can be arranged in a first section 351 (e.g., a transistor cell region) of the semiconductor substrate 102. The diode structures 104 of the semiconductor device 310 can be formed in a second section 352A and a third section 352A of the semiconductor substrate 102. The second section 352A of the semiconductor substrate 102 can be formed on (or adjacent to) a first lateral side of the first section 351 of the semiconductor substrate 102 in the top view. The third section 352B of the semiconductor substrate 102 can be formed on (or adjacent to) a second lateral side (opposite the first lateral side) of the first section 351 of the semiconductor substrate 102 in the top view.For example, an edge termination section 353 can surround the second section 352A of the semiconductor substrate 102, the third section 352B of the semiconductor substrate 102 and the first section 352A of the semiconductor substrate 102 in the top view (or enclose the same laterally or be formed around the same).

[0165] Fig. Figure 3C shows a schematic top view of a layout of a 330 semiconductor device.

[0166] The majority of FET structures of the semiconductor device 310 can be arranged in a first section 351 (e.g., a transistor cell region) of the semiconductor substrate 102. The diode structures 104 of the semiconductor device 310 can be formed in a second section 352 of the semiconductor substrate 102. The first section 351 of the semiconductor substrate 102 can laterally surround the second section 352 of the semiconductor substrate 102 in a top view. An edge termination section 353 can, for example, laterally surround the first section of the semiconductor substrate 102 in a top view (or laterally enclose it or be formed around it).

[0167] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 3A to 3C may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 2G) or below ( Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. 10) described embodiments are mentioned.

[0168] Fig. Figure 4 shows a schematic representation of a semiconductor device 400 according to an exemplary embodiment.

[0169] The semiconductor device 400 comprises a field-effect transistor structure 461, which is arranged on a semiconductor substrate 102.

[0170] The semiconductor device 400 further comprises a trench structure 227 extending from a surface 229 of the semiconductor substrate 102 into the semiconductor substrate 102. The trench structure 227 includes a Schottky contact interface of a Schottky diode structure or a gate of a gate-controlled metal-insulation semiconductor diode structure within the trench structure 227.

[0171] The semiconductor device 400 further comprises a shielding doping region 226, which extends from a section of at least one side wall 462 of the trench structure 227 towards a channel region 228 of the field-effect transistor structure 461.

[0172] Since the semiconductor device 400 comprises the Schottky contact interface of a Schottky diode structure or the gate of a gate-controlled metal-insulation semiconductor diode structure, a unipolar current path with a lower forward voltage than a bipolar / pn-body diode can be provided between the drift region and a body region. This can, for example, reduce switching losses of the semiconductor device 400, increase switching speeds, and / or improve forward voltage drop or forward losses. Since the shielding doped region 226 extends from a section of at least one side wall 462 of the trench structure 227 toward a channel region 228 of the field-effect transistor structure 461, the shielding doped region 226 can protect the gate of the field-effect transistor structure 461 from breakdown caused by high electric fields in the direction toward the gate.

[0173] The semiconductor device 400 can be similar to the one used in conjunction with Fig. Semiconductor components described in 1A to 3C.

[0174] The field-effect transistor structure 461 can be, for example, a metal-oxide-semiconductor field-effect transistor structure (MOSFET structure), a bipolar transistor structure with an insulated gate (IGBT structure), or a junction field-effect transistor structure (JFET structure).

[0175] The Schottky diode structure can, for example, include a Schottky contact that forms a Schottky contact interface (e.g., a Schottky junction) with a section of the semiconductor substrate 102. For example, the Schottky interface can be located between the Schottky contact and a drift region of the Schottky diode structure (at a first sidewall of the trench structure 227). For example, the drift region of the SD structure can be part of a common drift zone of the semiconductor substrate 102.

[0176] The gate of the MGD structure can be located adjacent to a drift region of a first conductivity type (e.g., n-type doped) of the MGD structure 104 and / or a body region of a second conductivity type (e.g., p-type doped) of the MGD diode structure 104 (at the first side wall of the trench structure 227). For example, the drift region of the MGD structure 104 can be part of a common drift zone of the semiconductor substrate 102.

[0177] The (first) sidewall of the trench structure 227 can, for example, be located adjacent to the drift region of the SD structure or to the drift region of the MGD structure 104. The shielding doping region 226 can, for example, be located adjacent to at least one sidewall (e.g., a second sidewall opposite the first sidewall) and / or the bottom of a trench structure 227. For example, the shielding doping region 226 can extend deeper into the semiconductor substrate than the trench structure 227.

[0178] For example, at least part of the channel region 228, which is arranged in the semiconductor substrate 102, can be essentially horizontal to the surface 229 of the semiconductor substrate 102.

[0179] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The four embodiments shown may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 2C) or below ( Fig. Examples of implementation described in sections 5A to 10 are mentioned.

[0180] Fig. Figure 5A shows a schematic representation of a semiconductor device 510 according to an exemplary embodiment.

[0181] The semiconductor device 510 comprises the trench structure 227, which includes a gate of a gate-controlled metal-insulation semiconductor diode structure 104 within the trench structure 227. The gate of the MGD structure 104 can, for example, comprise the gate electrode material 235 and the gate insulation layer 236, which are arranged in the trench structure 227.

[0182] At least part of a first side wall of the trench structure 227 can be located adjacent to a drift region 237 of a first conductivity type (e.g., n-type doped) of the MGD diode structure 104 and / or a body region 238 of a second conductivity type (e.g., p-type doped) of the MGD diode structure 104. The body region 238 of the MGD diode structure 104 can, for example, be located between a source region 239 of the MGD diode structure 104 and the drift region 237 of the MGD diode structure.

[0183] For example, the first source contact structure 232 can be electrically connected to the source region of the MGD structure 104 and to the gate (e.g., the gate electrode 235) of the MGD structure 104. The MGD structure 104 can include the gate electrode 235, which is located in the trench structure 227 and connected to source potential. The gate electrode 235 can be separated from the body region 238 of the MGD structure 104 by the gate insulating layer 236 (e.g., a dielectric material). The n-channel of the MGD structure 104 can, for example, have a lower threshold voltage than the threshold voltage of the MOSFET.

[0184] The semiconductor device 510 can, for example, include the shielding doping region 226, which is located adjacent to at least one side wall (e.g., a second side wall opposite the first side wall) and / or the bottom of the trench structure 227. The p-shielding doping region 226 can protect the gate insulation layer 236 (e.g., gate dielectric) against higher electric fields.

[0185] Optionally, the doping concentration of the shielding doping region 226 can be varied laterally. For example, the doping concentration of the shielding doping region 226 can be varied laterally such that the shielding doping region 226 has a lower doping concentration (e.g., between 1 × 10⁻⁶). 16 Dopant atoms per cm 3 and 1x10 17 Dopant atoms per cm 3) towards the channel or body region of the MGD structure 104, and a higher doping concentration (e.g. at least 1×10 18 Dopant atoms per cm 3 ) towards an adjacent FET structure and / or adjacent to the region of lower doping concentration. Due to the lateral variations of the doping in the p-type doped shielding region 226, for example, a lower threshold voltage and shielding doping may be possible, which shield the electric field in the off-state and prevent penetration of the depletion zone to the n-source region. The shielding doping can be reduced to pin the breakdown site (e.g., spaced away from the channel) and thus improve the avalanche resistance of the MOSFET.

[0186] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 5A may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 4) or below ( Fig. Examples of implementation described in sections 5B to 10 are mentioned.

[0187] Fig. Figure 5B shows a schematic representation of a semiconductor device 520 according to an exemplary embodiment.

[0188] The 520 semiconductor device can be similar to the one used in conjunction with Fig. 5A described semiconductor device. For example, the semiconductor device 520 can comprise the MGD diode structure 104, which in conjunction with Fig. 5A is described. For example, the semiconductor device 520 can be a superjunction device.

[0189] Additionally or optionally, the thickness of the gate insulation layer 236, which is arranged on (or at) the second side wall of the trench structure 227, can be greater than the thickness of the gate insulation layer 236, which is arranged on (or at) the first side wall of the trench structure 227. For example, the thickness of the gate insulation layer 236 between the gate electrode 235 and the shielding doping layer 226 on the second side wall of the trench structure 227 can be greater than the thickness of the gate insulation layer 236, which is arranged on (or at) the first side wall of the trench structure 227. For example, the thicker gate insulation layer 236 (oxide) can allow a higher blocking voltage.

[0190] The shielding doping region 226 can, for example, be part of a vertical column structure (e.g., a compensation region) with the same conductivity type as the shielding doping region 226 (or can be connected to one).

[0191] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 5B may have one or more optional additional features corresponding to one or more aspects related to the proposed concept or one or more of the above (e.g. Fig. 1A to 5A) or below ( Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. 10) described embodiments are mentioned.

[0192] Fig. Figure 6 shows a schematic representation of a section of a semiconductor device 600 according to an exemplary embodiment.

[0193] The semiconductor device 600 can comprise an electrode structure that extends vertically from the first lateral surface of the semiconductor substrate 102 into the semiconductor substrate 102. The electrode structure can, for example, have a vertical dimension (or extent). For example, the electrode structure can extend from a first lateral surface of the semiconductor substrate 102 to a depth of more than 5 µm (or more than 10 µm or more than 20 µm) into the semiconductor substrate 102.

[0194] The electrode structure can comprise a first section 623 and a second section 123. The first section 623 of the electrode structure can have a smaller lateral dimension than the second section 123 of the electrode structure. The second section 123 of the electrode structure can be arranged vertically between the first lateral surface of the semiconductor substrate 102 and the first section 623 of the electrode structure. The second section 123 of the electrode structure can form (or be) a Schottky contact of a Schottky diode structure 104, which forms a Schottky contact interface 121 between the Schottky contact 123 and at least one drift region 122 of the SD structure 104. For example, the second section 123 of the electrode structure can be laterally surrounded by the (n-type doped) drift region 122 of the SD structure 104.

[0195] The first section 623 of the electrode structure can extend vertically from a base of the second section 123 into the semiconductor substrate 102. The first section 623 of the electrode structure can, for example, be laterally surrounded by a p-type doped region 626. The p-type doped region 626 can, for example, be arranged laterally between the first section 623 of the electrode structure and the (n-type doped) drift zone.

[0196] The second section 123 of the electrode structure (above the p-type doped region) can form at least one Schottky contact on one or more of the side walls of the trench structure 227 by being connected to source potential. The first section 623 of the electrode structure can form an ohmic source contact and can be buried in a trench lined or filled with metal in (or laterally surrounded by) the p-type doped region(s) 626. Optionally, it is not required that the trench in which the first section 623 of the electrode structure is formed has sharp edges. For example, the edges of the trench can be rounded by an etching process (e.g., a modified dry etching process and / or a temperature process in a hydrogen (H₂) solution). 2- ) Low-pressure flux atmosphere).

[0197] Since the ohmic contact (e.g., the first section 623 of the electrode structure) is not only flat along the bottom of the trench but extends into the trench in (or is laterally surrounded by) the p-type doped region(s) 626, a further improvement in dynamic operation can be achieved. If the trench is filled with highly conductive material, the ohmic path resistance in the p-SiC column can be reduced. The highly conductive material can be a metal (e.g., aluminum, copper, tungsten, or molybdenum), highly doped poly-Si, or a metal silicide (tungsten-titanium). Thus, the series resistance of a pn diode (between the p-shielding doping region and the FET drift region) can be reduced. The high-current performance of the body diode structure 104 can be improved, and the problem of low hole mobility in SiC can be solved.The deep contact of the p-pillars can improve the avalanche resistance of the FET transistor structure, as the outflowing hole current can flow laterally into the metal, flow vertically in a low-resistance region, and thus does not affect the electric field in the p-type doped shielding doping region.

[0198] Several processes can be used to fabricate the deep, p-type doped regions. The p-type doping region can be formed using local p-implantation. For example, the deep vertical p-type doped regions can be formed by repeatedly alternating between the growth of epitaxial semiconductor layers and implantation processes. Optionally, implantation in the uppermost layer (or section) can be omitted before performing a masked etching process to form a trench structure (in which the electrode structure material is to be deposited). This can reduce Schottky contact scattering.

[0199] Optionally, the high p-type doping can be implanted in the trench bottom above a spacer (e.g., an oxide layer) which can prevent scattering of doping atoms in the side walls (e.g., lateral scattering of acceptor ions after contact with the trench bottom).

[0200] Alternatively or optionally, an electrode trench can be etched. The electrode trench can be lined with a p-type epi-substrate (e.g., a p-type epiaxial semiconductor) using high p-surface doping via epitaxial growth or plasma doping. Back-etching can be performed near the surface (e.g., using reactive ion etching; RIE) to form a trench structure. To protect the bottom of the trench structure, the top of the electrode trench can be lined with a stop layer (e.g., SiO₂, poly-Si, carbon, or a photoresist), which can be removed after RIE etching.

[0201] Alternatively, the entire sidewalls and bottom of the trench can be plasma-doped or implanted, and the upper portion of the electrode trench can be widened by etching to remove the p-type doping in the upper region (followed by deposition of electrode material in the widened section of the trench). Alternatively, the upper part of the trenches can be protected by a covering layer, so that the p-type doping remains only in the lower region of the column, and the second back-etching step can be omitted.

[0202] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 6 may have one or more additional optional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 5B) or below ( Fig. 7, Fig. 8, Fig. 9 to Fig. 10) described embodiments are mentioned.

[0203] Fig. Figure 7 shows a schematic representation of a semiconductor device 700 according to an exemplary embodiment.

[0204] The semiconductor device 700 comprises a plurality of junction field-effect transistor structures 771 of a junction field-effect transistor array arranged on a semiconductor substrate 102. The semiconductor device further comprises at least one gate-controlled metal-insulation semiconductor diode structure 704.

[0205] Since the semiconductor device 700 comprises the Schottky contact interface of a Schottky diode structure or the gate of a gate-controlled metal-insulation semiconductor diode structure, a unipolar current path with a lower forward voltage than a bipolar / pn-body diode can be provided between the drift region and a body region. This can, for example, reduce on-state losses and switching losses of the semiconductor device 700, increase switching speeds, and / or improve forward voltage drop or forward losses.

[0206] The majority of junction field-effect transistor structures 771 can be electrically connected in parallel with at least one gate-controlled metal-insulation semiconductor diode structure 704.

[0207] A channel region of a junction field-effect transistor structure 771, from the plurality of junction field-effect transistor structures 771, can be arranged in the semiconductor substrate 102. At least part of the channel region can, for example, extend substantially horizontally with respect to a surface of the semiconductor substrate 102.

[0208] The semiconductor device 700 can further comprise a shielding doping region located between the gate-controlled metal-insulation semiconductor diode structure 704 and a channel region of a junction field-effect transistor structure 771 from the plurality of junction field-effect transistor structures 771.

[0209] The semiconductor device 700, for example, can be similar to the one used in conjunction with Fig. 2A described semiconductor component. For example, however, those in connection with Fig. The compensation regions described in section 2A are omitted.

[0210] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The 7 embodiments shown may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above ( Fig. 1A to 6) or below ( Fig. 8, Fig. 9 to Fig. 10) described embodiments are mentioned.

[0211] Fig. Figure 8 shows a schematic representation of a semiconductor device 800 according to an exemplary embodiment.

[0212] The semiconductor device 800 can comprise a plurality of JFET structures 771. Each JFET structure 771 can include a gate doping region 731 extending vertically from the first lateral surface 229 of the semiconductor substrate 102 into the semiconductor substrate 102. The gate doping region 731 can be controlled by or connected to a gate contact of the JFET structure 771 to control the electrical conductivity of a channel region 728 between the source region 233 of the JFET structure 771, located at the first lateral surface 229 of the semiconductor substrate 102, and a drain region of the JFET structure 771, located at the second (opposite) lateral surface of the semiconductor substrate 102. The channel region 728 can, for example, be arranged vertically between the adjacent gate doping region 731 and / or between a gate doping region and the shielding doping region 226.Charge carriers in the channel region 728 can flow vertically between the source region of the JFET structure 771 and a drift region 101 of the JFET structure. The drift region 101 of the JFET structure 771 can, for example, be located adjacent to the drain region of the JFET structure 771 on the second lateral surface of the semiconductor substrate 102.

[0213] Each shielding doping region 226 can be located adjacent to at least one side wall and / or bottom of a trench structure in which a Schottky contact interface of an SD structure or a gate of an MGD structure is formed. At least part of a first side wall of the trench structure 227 can be located adjacent to a drift region 237 (n-type doped) of the MGD diode structure 104 and / or a body region 238 (p-type doped) of the MGD diode structure 104. The body region 238 of the MGD diode structure 104 can, for example, be located between a source region 239 of the MGD diode structure 104 and the drift region 237 of the MGD diode structure.

[0214] Alternatively or optionally, the shielding doping regions 226 can be electrically connected to a transistor gate contact structure. The transistor gate contact structure can, for example, be in contact with (or electrically connected to) the transistor gates (for controlling the gate doping region 731) of the majority of FET structures.

[0215] The channel regions 728 of the JFET structures 771 can, for example, be arranged between adjacent (or successive) diode structures 104. For example, at least one channel region 728 (e.g., more than one channel region 728) can be arranged between, for example, adjacent (or successive) diode structures 104.

[0216] The source regions 233 of the JFET structure can be (partially or completely) shielded from the p-gates 731 of the JFET structure by the space charge regions. The MGD structure 104, for example, allows electrons to be removed from the drain at the terminals of the MGD structure 104. The control drive can be used, for example, for low or medium load currents.

[0217] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 8 may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 7) or below ( Fig. 9 to Fig. 10) described embodiments are mentioned.

[0218] Fig. Figure 9 shows a schematic representation of a semiconductor device 900 according to an exemplary embodiment.

[0219] The semiconductor device 900 can be similar to the one used in conjunction with Fig. 8 described semiconductor device. For example, the semiconductor device 900 can comprise a plurality of vertically extending gate doping regions 731 and vertical channel regions 728, as in conjunction with Fig. 8 described.

[0220] The semiconductor device 900 can include one or more Schottky contacts 123, as in conjunction with Fig. Described in 2D. A first section of each Schottky contact 123 can overlap a first vertically extending, shielding doping region 249 on the first lateral surface 229 of the semiconductor substrate 102. A second section of the Schottky contact 123 can, for example, overlap a second vertically extending, shielding doping region 249 on the first lateral surface 229 of the semiconductor substrate 102.

[0221] Optionally, the Schottky contacts 123 can be located on the first lateral surface 229 of the semiconductor substrate 102. Alternatively or optionally, the Schottky contacts 123 can, for example, extend deeper into the semiconductor substrate 102 than the first vertically extending, shielding doping region 249 and the second vertically extending, shielding doping region 249.

[0222] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 9 may include one or more optional additional features which, in conjunction with the proposed concept or one or more of the above (e.g. Fig. 1A to 8) or below ( Fig. 10) described embodiments are mentioned.

[0223] Fig. Figure 10 shows a schematic representation of a semiconductor device 910 according to an exemplary embodiment.

[0224] The semiconductor device 910 comprises a field-effect transistor structure 771 arranged on a semiconductor substrate. The semiconductor device 910 further comprises a Schottky contact 123 of a Schottky diode structure. The semiconductor device 910 also comprises a shielding doped region 226 extending from a Schottky interface of the Schottky diode structure towards a channel region of the field-effect transistor structure 771.

[0225] The 771 field-effect transistor structure can be a 771 JFET structure, as in conjunction with Fig. 2A described.

[0226] The semiconductor device 910 can include a laterally extending Schottky contact 123, as in conjunction with Fig. Described in 2D. A first section of the Schottky contact 123 can overlap a vertically extending, shielding doping region 249 on the first lateral surface 229 of the semiconductor substrate 102. A second section of the Schottky contact 123 can overlap the shielding doping region 226 on the first lateral surface 229 of the semiconductor substrate 102. The shielding doping region 226 can be located between the source region 233 of the JFET structure 771 and the laterally extending Schottky contact 123 on the first lateral surface 229 of the semiconductor substrate 102.

[0227] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 10 may have one or more optional additional features corresponding to one or more aspects that are related to the proposed concept or one or more of the above (e.g. Fig. 1A to 9) or the embodiments described below.

[0228] Several examples relate to body diode functionalities for SiC circuits with a low threshold voltage.

[0229] Aspects and features (e.g., the semiconductor device, the field-effect transistor structure, the semiconductor substrate, the shielding doping region, the trench structure, the first sidewall of the trench structure, the bottom of the trench structure, the second sidewall of the trench structure, the drift region of the FET structure, the body region of the FET structure, the vertically extending shielding doping region, the source or emitter region of the FET structure, the drain or collector region of the FET structure, the drift region of the MGD structure, the drift region of the SD structure, the body region of the MGD structure, the source region of the MGD structure, the Schottky contact, the Schottky contact interface, the gate of the MGD structure, the channel region of the JFET structure) mentioned in connection with one or more specific examples can be combined with one or more of the other examples.

Claims

[1] A semiconductor device (240), comprising: a plurality of drift regions (101) of a plurality of field-effect transistor structures arranged in a semiconductor substrate (102), wherein the plurality of drift regions (101) has a first conductivity type; a plurality of compensation regions (103) arranged in the semiconductor substrate (102), wherein the plurality of compensation regions (103) has a second conductivity type, wherein each drift region (101) from the plurality of drift regions (101) is arranged adjacent to at least one compensation region (103) from the plurality of compensation regions (103), wherein a field-effect transistor structure of the majority of field-effect transistor structures has a transistor gate (244) in a gate-trough structure (248), wherein a body region (241) is arranged adjacent to a first side wall of the gate-trough structure (248) of the field-effect transistor structure; a transistor gate-shielding doping region (247) located adjacent to a second side wall of the gate trench structure (248) of the field-effect transistor structure; and at least one Schottky diode structure (104) arranged on the semiconductor substrate (102), wherein the Schottky diode structure (104) is arranged between two adjacent field-effect transistor structures of the plurality of field-effect transistor structures. [2] The semiconductor device according to claim 1, wherein the Schottky diode structure (104) is arranged between a surface of the semiconductor substrate (229) and a compensation region (103) from the plurality of compensation regions (103). [3] The semiconductor device according to one of the preceding claims, further comprising a source or emitter contact structure (232) which is electrically connected to the plurality of compensation regions (103) and to the Schottky diode structure (104). [4] The semiconductor device according to claim 3, wherein the source or emitter contact structure (232) is electrically connected to the body region (238) of the gate-controlled metal-insulation semiconductor diode structure (104). [5] The semiconductor device according to one of the preceding claims, wherein the semiconductor substrate (102) is a silicon carbide substrate. [6] The semiconductor device according to one of the preceding claims, wherein the plurality of field-effect transistor structures are electrically connected in parallel with the at least one Schottky diode structure. [7] The semiconductor device according to one of the preceding claims, wherein the Schottky diode structure (104) extends from the transistor gate shielding doping region (247) towards a body region of a second field-effect transistor structure of the plurality of field-effect transistor structures. [8] The semiconductor device according to one of the preceding claims, wherein the Schottky diode structure (104) has a thickness of less than 300 nm. [9] The semiconductor device according to any of the preceding claims, wherein a blocking voltage of the semiconductor device is greater than 10 V. [10] A semiconductor device (230) comprising: a plurality of drift regions (101) of a plurality of field-effect transistor structures arranged in a semiconductor substrate (102), wherein the plurality of drift regions (101) has a first conductivity type; a plurality of compensation regions (103) arranged in the semiconductor substrate (102), wherein the plurality of compensation regions (103) has a second conductivity type, wherein each drift region (101) from the plurality of drift regions (101) is arranged adjacent to at least one compensation region (103) from the plurality of compensation regions (103), wherein a field-effect transistor structure of the plurality of field-effect transistor structures has a transistor gate (244) in a gate-trough structure (248), wherein a body region (241) is arranged adjacent to a first side wall of the gate-trough structure (248) of the field-effect transistor structure; and a transistor gate shielding doping region (247) which is arranged adjacent to a second side wall of the gate trench structure (248) of the field effect transistor structure, wherein the transistor gate shielding doping region (247) is in ohmic contact with the source potential of the field effect transistor structure, wherein the transistor gate shielding doping region (247) electrically connects a compensation region of the plurality of compensation regions (103) to the source potential. [11] The semiconductor device according to claim 10, comprising a gate-controlled metal-insulation semiconductor diode structure (104) arranged on the semiconductor substrate (102). [12] The semiconductor device according to claim 11, wherein a shielding doping region (226) extends from a side wall of a trench structure (227) of the gate-controlled metal-insulation semiconductor diode structure (104) to the body region (241) of the field-effect transistor structure. [13] The semiconductor device according to claim 11 or 12, wherein the shielding doping region (226) is in ohmic contact with the source potential of the gate-controlled metal-insulation semiconductor diode structure (104), wherein the shielding doping region (226) electrically connects a second compensation region of the plurality of compensation regions (103) to the source potential. [14] A semiconductor device (230) comprising: a field-effect transistor structure arranged on a silicon carbide substrate (102); a trench structure (227) extending from a surface (229) of the silicon carbide substrate (102) into the silicon carbide substrate (102), wherein the trench structure (227) includes a gate of a gate-controlled metal-insulation semiconductor diode structure within the trench structure (227); and a shielding doping region (226) which is arranged at a bottom of the trench structure (227) of the field-effect transistor structure. [15] The semiconductor device according to claim 14, wherein the shielding doping region (226) extends from a section of at least one side wall (462) of the trench structure (227) to the bottom of the trench structure (227) of the field-effect transistor structure. [16] The semiconductor device according to one of claims 14 to 15, further comprising: a plurality of drift regions (101) of a plurality of field-effect transistor structures arranged in the silicon carbide substrate (102), wherein the plurality of drift regions (101) has a first conductivity type; a plurality of compensation regions (103) arranged in the silicon carbide substrate (102), wherein the plurality of compensation regions (103) has a second conductivity type, wherein each drift region (101) from the plurality of drift regions (101) is arranged adjacent to at least one compensation region (103) from the plurality of compensation regions (103).

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