Fin field-effect transistor device structure and methods for its formation

Abstract

Fin field-effect transistor device structure comprising: a substrate (102); a fin structure (104) extending over the substrate (102); an epitaxial structure (210) formed on the fin structure (104), wherein the epitaxial structure (210) has a first height; fin sidewall spacers (105) formed adjacent to the epitaxial structure (210), wherein the fin sidewall spacers (105) have a second height and the first height is greater than the second height, and wherein the fin sidewall spacers (105) are arranged such that a volume and the first height of the epitaxial structure (210) are regulated;and an insulation structure (108), wherein the fin structure (104) is embedded in the insulation structure (108), wherein a bottom surface of the epitaxial structure (210) lies in a plane with the top surface of the insulation structure (108), wherein the epitaxial structure (210) has a rhombus-shaped upper part and a columnar lower part, and wherein the columnar lower part has a bottom surface and side walls adjoining the bottom surface, and wherein an angle between the bottom surface and the side walls is approximately 90 degrees.

Description

GENERAL STATE OF THE ART Semiconductor devices are used in a wide variety of electronic applications, such as desktop computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of a material onto a semiconductor substrate and structuring these diverse material layers using lithography to create components and circuit elements. Many integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer are separated by sawing between the integrated circuits along a scribed line. The individual dies are then usually packaged separately into multi-chip modules or other package types. As the semiconductor industry has advanced to nanometer-scale process nodes in its pursuit of higher device density, improved performance, and lower costs, the challenges posed by both fabrication and design have led to the development of three-dimensional device structures, such as the fin field-effect transistor (FinFET). FinFETs are fabricated with a thin, vertical "fin" (or fin structure) extending from a substrate. The FinFET channel is formed within this vertical fin, and a gate is located above the fin. Advantages of FinFETs include reduced short-channel effects and higher current flow. Although the existing FinFET devices and methods for manufacturing FinFET devices were generally sufficient for their intended purpose, they were not entirely satisfactory in every respect. Prior art relating to the subject matter of the invention can be found, for example, in US 2014 / 0 167 264 A1, US 2014 / 0 035 066 A1, US 2012 / 0 319 211 A1, US 2013 / 0 313 619 A1, US 2013 / 0 200 455 A1, and US 2014 / 0 203 338 A1. The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. The terms Fin field-effect transistor device structure, Fin field-effect transistor device structure, FinFET device structure, FinFET device structure, and FinFET device are used interchangeably in the following. The abbreviation FinFET stands for Fin field-effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the present disclosure are best understood with reference to the following detailed description, when read together with the accompanying figures. It should be noted that, in accordance with common industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity. Fig. 1 shows a perspective view of a fin field-effect transistor device structure according to some embodiments of the disclosure. Figs. 2A-2F show side views of various shaping stages of a fin field-effect transistor device structure according to some embodiments of the disclosure. Fig. 2G is an enlarged view of region A of Fig. 2F according to some embodiments of the disclosure.Figures 3A-3B show side views of various forming stages of a fin field-effect transistor device structure according to some embodiments of the disclosure. Figure 3C is an enlarged view of region B of Figure 3B according to some embodiments of the disclosure. Figures 4A-4D show side views of various forming stages of a fin field-effect transistor device structure according to some embodiments of the disclosure. Figure 4E is an enlarged view of region C of Figure 4D according to some embodiments of the disclosure. DETAILED DESCRIPTION Embodiments for the formation of a Fin field-effect transistor device structure are provided. Fig. 1 shows a perspective view of a Fin field-effect transistor device structure 10 according to some embodiments of the disclosure. The FinFET device structure 10 comprises an n-channel FinFET device structure (NMOS) 15 and a p-channel FinFET device structure (PMOS) 25. The FinFET device structure 10 comprises a substrate 102. The substrate 102 can consist of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 can comprise other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 102 consists of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 consists of an alloy semiconductor, such as silicon-germanium, silicon-germanium carbide, gallium arsenide phosphide, or gallium-indium phosphide. In some embodiments, the substrate 102 has an epitaxial layer. For example, the substrate 102 can have an epitaxial layer that is located on a semiconductor body. The FinFET device structure 100 also features one or more fin structures 104 (e.g., Si fins) extending from the substrate 102. Optionally, the fin structure 104 can comprise germanium (Ge). The fin structure 104 can be formed using suitable processes, such as photolithography and etching. In some embodiments, the fin structure 104 is etched from the substrate 102 using dry etching or plasma processes. In some other embodiments, the fin structure 104 can be formed by a double structuring lithography (DPL) process. DPL is a method for creating a structure on a substrate by subdividing the structure into two nested structures. DPL enables an increased density of features (e.g., the fins). An isolation structure 108, such as shallow trench isolation (STI), is formed to enclose the fin structure 104. In some embodiments, a lower part of the fin structure 104 is enclosed by the isolation structure 108, and an upper part of the fin structure 104 protrudes from the isolation structure 108, as shown in Fig. 1. In other words, part of the fin structure 104 is embedded within the isolation structure 108. The isolation structure 108 prevents electrical interference or cross-coupling. The FinFET device structure 100 further comprises a gate stacking structure, which includes a gate electrode 110 and a gate dielectric layer (not shown). The gate stacking structure is formed over a central part of the Fin structure 104. In some other embodiments, several gate stacking structures are formed over the Fin structure 104. In some other embodiments, the gate stack structure is a dummy gate stack which is later replaced by a metal gate (MG) after the processes with high heat conversion have been carried out. The gate dielectric layer (not shown) can consist of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material(s), or combinations thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, and the like, or combinations thereof. The gate electrode 110 can be made of polysilicon or metal. The metal includes tantalum nitride (TaN), nickel-silicon (NiSi), cobalt-silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials. The gate electrode 110 can be formed in a gate-loading (or gate-exchange) process. In some embodiments, the gate stack structure includes additional layers, such as interface layers, cover layers, diffusion / barrier layers, or other suitable layers. The gate stack structure is formed through a deposition process, a photolithography process, and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma lithography (HDPCVD), metal-organic lithography (MOCVD), remote plasma lithography (RPCVD), plasma-enhanced lithography (PECVD), plating, other suitable methods, and / or combinations thereof. The photolithography processes include photoresist coating (e.g., rotary coating), low-temperature annealing, mask alignment, exposure, post-exposure annealing, photoresist development, rinsing, and drying (e.g., curing). The etching process includes a dry or wet etching process. Alternatively, the photolithography process is implemented or replaced by other suitable methods, such as maskless lithography, electron beam writing, and ion beam writing. Figures 2A-2F show side views of various shaping stages of a fin field-effect transistor device structure according to some embodiments of the disclosure. Figures 2A-2F show side views taken along arrow 1 of Figure 1, where arrow 1 is parallel to the X-axis. Referring to Fig. 2A, a first hard mask layer 112 is formed on the gate electrode 110, and a second hard mask layer 114 is formed on the first hard mask layer 112. In some embodiments, the first hard mask layer 112 consists of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the second hard mask layer 114 consists of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. Gate sidewall spacers 115 are formed on the opposite sidewalls of the gate electrode 110, and fin sidewall spacers 105 are formed on the opposite sidewalls of the fin structure 104. A bottom antireflection coating (BARC) layer 202 is then formed on the gate sidewall spacers 115. The BARC layer 202 is placed under a photoresist layer to facilitate the transfer of the structure to the hard mask layers 112 and 114 during a structuring process. When an implantation process is performed on an n-channel FinFET device structure (NMOS) 15, then in some embodiments, the BRAC 202 and a (not shown) photoresist formed on the BRAC 202 are produced on the gate electrode 110 to cover the gate electrode 110 in the p-channel FinFET device structure (PMOS) 25. Subsequently, the (not shown) photoresist and the BRAC 202 are removed by an etching process, as shown in Fig. 2B, according to some embodiments of the disclosure. The etching process can be a dry etching process or a wet etching process. In some embodiments, a first dry etching process is carried out at a pressure in the range of approximately 3 millitorr to approximately 50 millitorr. In some embodiments, the gas used in the first dry etching process comprises methane (CH4), nitrogen (N2), helium (He), oxygen (O2), or combinations thereof. In some embodiments, the first dry etching process is carried out at a power in the range of approximately 50 watts to approximately 1000 watts. In some embodiments, the first dry etching process is carried out at a temperature in the range of approximately 20 °C to approximately 80 °C. After the BRAC 202 is removed, according to some embodiments of the disclosure, a portion of the gate sidewall spacers 115 and a portion of the fin sidewall spacers 105 are removed, as shown in Fig. 2C. More precisely, a head portion of the gate sidewall spacers 115 is removed to expose the second hard mask layer 114. A head portion of the fin sidewall spacers 105 is removed to expose the fin structure 104. In some embodiments, if the gate sidewall spacers 115 and the fin sidewall spacers 105 are made of silicon nitride, a second etching process is performed to remove the silicon nitride. In some embodiments, the second etching process is a second dry etching process performed at a pressure in the range of approximately 3 millitorr to approximately 50 millitorr. In some embodiments, the gas used in the second dry etching process includes fluoromethane (CH3F), difluoromethane (CH2F2), methane (CH4), argon (Ar), hydrogen bromide (HBr), nitrogen (N2), helium (He), oxygen (O2), or combinations thereof. In some embodiments, the second dry etching process is performed at a power in the range of approximately 50 watts to approximately 1000 watts. In some embodiments, the second dry etching process is performed at a temperature in the range of approximately 20 °C to approximately 70 °C. After the second dry etching process, each of the fin sidewall spacers 105 has a first height H1. In some embodiments, the first height H1 lies in a range from approximately 0.1 nm to approximately 100 nm. After the portion of the gate sidewall spacers 115 and the portion of the fin sidewall spacers 105 have been removed, according to some embodiments of the disclosure, a portion of the remaining fin sidewall spacers 105 is removed, as shown in Fig. 2D. The upper portions of the fin sidewall spacers 105 are removed by a third etching process. The third etching process can be a dry etching process or a wet etching process. In some embodiments, the third etching process is a third dry etching process performed at a pressure in the range of approximately 3 millitorr to approximately 50 millitorr. In some embodiments, the gas used in the third dry etching process comprises fluoromethane (CH3F), difluoromethane (CH2F2), methane (CH4), argon (Ar), hydrogen bromide (HBr), nitrogen (N2), helium (He), or oxygen (O2), or combinations thereof. In some embodiments, the third dry etching process is performed at a power in the range of approximately 50 watts to approximately 1000 watts. In some embodiments, the third dry etching process is performed at a temperature in the range of approximately 20 °C to approximately 70 °C. After the third dry etching process, the height of the fin sidewall spacers 105 has been reduced from a first height H1 to a second height H2. In some embodiments, the second height H2 lies in a range of approximately 0.1 nm to approximately 90 nm. It should be noted that the second height H2 of the fin sidewall spacer 105 is critical for an epitaxial structure (such as the epitaxial structure 210 in Fig. 2E-2). The height and volume of the epitaxial structure are influenced by the second height H2 of the fin sidewall spacer 105. In other words, the fin sidewall spacers 105 are designed to regulate the height and volume of the epitaxial structure 210. According to some embodiments of the disclosure, after the third dry etching process, part of the Fin structure 104 is removed, as shown in Fig. 2E. The Fin structure 104 is removed by an etching process, such as a dry etching process or a wet etching process. As shown in Fig. 2E, a cover surface of the remaining fin structure 104 lies on a plane with a cover surface of the insulation structure 108. By omitting a portion of the fin structure 104 that lies above the insulation structure 108, a trench 204a is formed. The side walls of the trench 204a are vertically parallel to each other. In some embodiments, the angle θ1 between the side wall of the trench 204a and a cover surface of the fin structure 104 is approximately 90 degrees. After the part of the fin structure 104 is removed, according to some embodiments of the disclosure an epitaxial structure 210 is formed in the trenches 204a, as shown in Fig. 2F. The epitaxial structure 210 features a source / drain epitaxial structure. In some embodiments, the source / drain epitaxial structures feature epitaxially grown silicon (epi-Si) when an n-channel FET (NFET) device is required. Alternatively, if a p-channel FET (PFET) device is required, the source / drain epitaxial structures feature epitaxially grown silicon-germanium (SiGe). Fig. 2G is an enlarged view of region A of Fig. 2F according to some embodiments of the disclosure. As shown in Fig. 2G, the epitaxial structure 210 has a rhombus-shaped upper part and a columnar lower part. The rhombus-shaped upper part of the epitaxial structure 210 has four facets 210A, 210B, 210C, and 210D. Each facet has a crystallographic orientation (111). The columnar lower part of the epitaxial structure 210 has a base surface and sidewalls adjoining the base surface. An angle θ1 between the base surface and the sidewalls is approximately 90 degrees. Furthermore, the base surface of the columnar lower part of the epitaxial structure 210 lies substantially in the same plane as the top surface of the insulation structure 108. As shown in Fig. 2G, the epitaxial structure 210 has a height Ht1 and a width W1. In some embodiments, the height Ht1 ranges from approximately 10 nm to approximately 300 nm. If the height Ht1 is too large, the electrical resistance decreases. If the height Ht1 is too small, the electrical resistance increases, thus impairing the device speed. In some embodiments, the width W1 ranges from approximately 10 nm to approximately 100 nm. If the width W1 is too large, the epitaxial structure 210 can overlap with the adjacent one and cause a short circuit. If the width W1 is too small, the contact window for contacting the epitaxial structure 210 becomes too narrow, and consequently, the circuit effect can be interrupted. Furthermore, the ratio (Ht1 / H2) of the height Ht1 of the epitaxial structure 210 to the height H2 of the fin sidewall spacer 105 is in the range of approximately 1.5 to approximately 10. If the ratio is too small, then the fin sidewall cannot provide effective support for the EPI height and can cause an EPI structure short circuit. Figures 3A-3B show side views of different shaping stages of a fin field-effect transistor device structure according to some embodiments of the disclosure. As shown in Fig. 3A, in some embodiments a cover surface of the remaining fin structure 104 is located deeper than a cover surface of the insulation structure 108. By omitting a portion of the fin structure 104 that lies beneath the insulation structure 108, a trench 204b is formed. In some other embodiments, the angle θ2 between the side wall of the trench 204b and a cover surface of the fin structure 104 is approximately 90 degrees. The trench 204b extends from a cover surface of the insulation structure 108 to a depth D1 in a range of approximately 0.1 nm to approximately 50 nm. After the portion of the fin structure 104 is removed, an epitaxial structure 212 is formed in the trenches 204b according to some embodiments of the disclosure, as shown in Fig. 3B. The epitaxial structure 212 has a source / drain epitaxial structure. In some embodiments, the source / drain epitaxial structures have epitaxially grown silicon (epi-Si) when an n-channel FET (NFET) device is required. Alternatively, if a p-channel FET (PFET) device is required, then the source / drain epitaxial structures have epitaxially grown silicon germanium (SiGe). Fig. 3C is an enlarged view of region B of Fig. 3B according to some embodiments of the disclosure. As shown in Fig. 3C, the epitaxial structure 212 has a rhombus-shaped upper part and a columnar lower part. The rhombus-shaped upper part of the epitaxial structure 212 has four facets 212A, 212B, 212C, and 212D. Each facet has a crystallographic orientation (111). The columnar lower part of the epitaxial structure 212 has a base and sidewalls adjoining the base. An angle θ2 between the base and the sidewalls is approximately 90 degrees. Furthermore, the base of the columnar lower part of the epitaxial structure 212 is recessed below a top surface of the insulation structure 108. As shown in Fig. 3C, the epitaxial structure 212 has a height Ht2 and a width W2. The height Ht1 is smaller than the height Ht2, and the width W1 is larger than the width W2. In some embodiments, the height Ht2 is in a range of approximately 15 nm to approximately 150 nm. In some embodiments, the width W2 is in a range of approximately 10 nm to approximately 100 nm. The epitaxial structures 210 and an epitaxial structure 212 independently feature a single-element semiconductor material, such as germanium (Ge) or silicon (Si), or compound semiconductor materials, such as gallium arsenide (GaAs), aluminium gallium arsenide (AlGaAs), or a semiconductor alloy, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). The epitaxial structures 210 and 212 are formed by an epi-process. The epi-process may include selective epitaxy growth (SEG), CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other applicable epi-processes. The epitaxial structures 210 and 212 can be doped in situ during the epi-process or left undoped. For example, the epitaxially grown SiGe epitaxial structure can be doped with boron, and the epitaxially grown Si epitaxial structure can be doped with carbon to form a Si:C epitaxial structure, with phosphorus to form a Si:P epitaxial structure, or with both carbon and phosphorus to form a SiCP epitaxial structure. Doping can be performed by an ion implantation process, plasma immersion ion implantation (PIII) process, a gas and / or solid source diffusion process, or another suitable process. The epitaxial structures 210 and 212 can also be subjected to tempering processes, such as a rapid thermal annealing process. If the epitaxial structures 210 and 212 are not doped in situ, then a second implantation process (e.g. a junction implantation process) is performed to dope the epitaxial structures 210 and 212. The Fin structure 104 has a channel region (not shown) that is enclosed or surrounded by the gate electrode 110. The lattice constants of the epitaxial structures 210 and 212 differ from that of the substrate 102. The channel region is deformed or strained to allow charge carrier mobility in the FinFET device structure and to increase its performance. It should be noted that the volume and heights Ht1, Ht2 of the epitaxial structures 210 and 212 are regulated by adjusting the height H2 of the Fin sidewall spacers 105 and / or the depth D1. Once the volume and heights Ht1, Ht2 of the epitaxial structures 210 and 212 are correctly adjusted, a further improvement in the performance of the FinFET device structure is achieved. For example, the device mobility (Id_Sat) will increase when the FinFET device structure is improved. Figures 4A-4D show side views of various shaping stages of a fin field-effect transistor device structure according to some embodiments of the disclosure. Figure 4E is an enlarged view of region C of Figure 4D according to some embodiments of the disclosure. Figures 4A-4D show side views taken along arrow 1 of Figure 1, with arrow 1 being parallel to the X-axis. With reference to Fig. 4A, the gate sidewall spacers 115 are formed on the opposite sidewalls of the gate electrode 110 and the fin sidewall spacers 105 are formed on the opposite sidewalls of the fin structure 104. According to some embodiments of the disclosure, the fin sidewall spacers 105 are then completely removed, as shown in Fig. 4B. As a result, the top surface and part of the sidewalls of the fin structure 104 are exposed. No fin sidewall spacers 105 are formed on the fin structure 104. After the fin sidewall spacers 105 are completely removed, according to some embodiments of the disclosure, a portion of the fin structure 104 is removed, as shown in Fig. 4C. As a result, a groove 304 is formed by omitting a portion of the fin structure 104. The trench 304 has a depth D2 that is below the insulation structure 108. In some embodiments, the depth D2 is in a range of approximately 0.1 nm to approximately 50 nm. In some embodiments, the angle θ2 between the side wall of the trench 304 and a top surface of the fin structure 104 is approximately 90 degrees. After the part of the fin structure 104 is removed, according to some embodiments of the disclosure, an epitaxial structure 214 is formed in the trench 304 and on the fin structure 104, as shown in Fig. 4D. The epitaxial structures 214 feature a single-element semiconductor material, such as germanium (Ge) or silicon (Si), or compound semiconductor materials, such as gallium arsenide (GaAs), aluminium gallium arsenide (AlGaAs), or a semiconductor alloy, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). The epitaxial structures 214 are formed by an epi-process. The epi-process may include a selective epitaxy growth (SEG) process, CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other applicable epi-processes. Similar to epitaxial structures 210 and 212, epitaxial structure 214 has a rhombus-like upper part and a columnar lower part. The rhombus-like upper part of epitaxial structure 214 has four facets 214A, 214B, 214C, and 214D. Each facet has a crystallographic orientation (111). It should be noted that, in comparison to Fig. 2G and Fig. 3C, no fin sidewall spacers are formed adjacent to the epitaxial structure 214 in Fig. 4E. Therefore, the volume and height of the epitaxial structure 214 are regulated by adjusting the depth of the trench 304 (shown in Fig. 4). Since there are no fin sidewall spacers to impede the growth of the epitaxial structure 214, the epitaxial structure 214 also tends to grow in the direction of the X-axis. Therefore, the width W3 of the epitaxial structure 214 is greater than the width W4 of the fin structure 104. Epitaxial structure 214 has a height Ht3 and a width W3. The height Ht3 of epitaxial structure 214 is less than the height Ht2 of epitaxial structure 212, and the width W2 of epitaxial structure 212 is greater than the width W3 of epitaxial structure 214. Furthermore, the height Ht3 of epitaxial structure 214 is less than the height Ht1 of epitaxial structure 210, and the width W1 of epitaxial structure 210 is greater than the width W3 of epitaxial structure 214. Referring again to Fig. 4D, the distance S between two adjacent epitaxial structures 214 ranges from approximately 0.1 nm to approximately 100 nm. In some embodiments, the width W3 of the epitaxial structure 214 ranges from approximately 10 nm to approximately 100 nm. In some embodiments, the height Ht3 of the epitaxial structure 214 ranges from approximately 10 nm to approximately 300 nm. In some embodiments, the ratio (Ht3 / W3) of the height to the width of the epitaxial structure 214 ranges from approximately 0.1 to approximately 10. The fin field-effect transistor (FIN) device structure can then be subjected to further processes to form other structures or components. In some embodiments, the metallization includes vertical connections, such as conventional vias or contacts, as well as horizontal connections, such as metal traces. The various connection features can be achieved using different conductive materials, including copper, tungsten, and / or silicide. Embodiments for forming a Fin field-effect transistor (FinFET) device structure are described. The FinFET device structure comprises a Fin structure extending over the substrate and an epitaxial structure formed on the Fin structure. In some embodiments, Fin sidewall spacers are formed adjacent to the epitaxial structure. These Fin sidewall spacers are configured to regulate the volume and height of the epitaxial structure. In other embodiments, no sidewall spacers are formed adjacent to the epitaxial structure; instead, the volume and height of the epitaxial structure are regulated by adjusting the depth of a trench formed by recessing a portion of the Fin structure. Once the volume and height of the epitaxial structure are adjusted, a further improvement in the performance of the FinFET device structure is achieved.

Claims

Fin field-effect transistor device structure comprising: a substrate (102); a fin structure (104) extending over the substrate (102); an epitaxial structure (210) formed on the fin structure (104), wherein the epitaxial structure (210) has a first height; fin sidewall spacers (105) formed adjacent to the epitaxial structure (210), wherein the fin sidewall spacers (105) have a second height and the first height is greater than the second height, and wherein the fin sidewall spacers (105) are arranged such that a volume and the first height of the epitaxial structure (210) are regulated;and an insulation structure (108), wherein the fin structure (104) is embedded in the insulation structure (108), wherein a bottom surface of the epitaxial structure (210) lies in a plane with the top surface of the insulation structure (108), wherein the epitaxial structure (210) has a rhombus-shaped upper part and a columnar lower part, and wherein the columnar lower part has a bottom surface and side walls adjoining the bottom surface, and wherein an angle between the bottom surface and the side walls is approximately 90 degrees. Fin field-effect transistor device structure according to claim 1, further comprising: a gate stack structure (15, 25) formed over a central part of the fin structure (104), wherein the epitaxial structure (210) is formed adjacent to the central part of the fin structure (104). Fin field-effect transistor device structure according to claim 1 or 2, wherein the second height is in a range of approximately 0.1 nm to approximately 100 nm. Fin field-effect transistor device structure according to one of the preceding claims, wherein the epitaxial structure (210) has a source / drain structure. Fin field-effect transistor device structure comprising: a substrate (102); a Fin structure (104) extending over the substrate (102); an isolation structure (108) formed on the substrate (102), wherein the Fin structure (104) is embedded in the isolation structure (108); and a first epitaxial structure (210) formed on the fin structure (104), wherein an interface of the first epitaxial structure (210) and the fin structure (104) lies below a cover surface of the insulation structure (108), and wherein no fin sidewall spacers are formed adjacent to the first epitaxial structure (210), wherein the epitaxial structure (210) has a rhombus-shaped upper part and a columnar lower part, and wherein the columnar lower part has a base surface and sidewalls adjoining the base surface, and wherein an angle between the base surface and the sidewalls is approximately 90 degrees. Fin field-effect transistor device structure according to claim 5, wherein the first epitaxial structure (210) extends from a cover surface of the insulation structure (108) to a depth in a range of approximately 0.1 nm to approximately 50 nm. Fin field-effect transistor device structure according to claim 5 or 6, further comprising: a gate stacking structure (15, 25) formed over a central part of the fin structure (104); and gate sidewall spacers (115) formed adjacent to the gate stacking structure (15, 25). Fin field-effect transistor device structure according to one of claims 5 to 7, further comprising: a second epitaxial structure (210) adjacent to the first epitaxial structure (210), wherein a distance between the first epitaxial structure and the second epitaxial structure is in a range of approximately 0.1 nm to approximately 100 nm. Fin field-effect transistor device structure according to one of claims 5 to 8, wherein the Fin structure (104) has a first width, wherein the first epitaxial structure (210) has a second width and wherein the second width is greater than the first width. Method for forming a Fin field-effect transistor device structure, comprising: providing a substrate (102); forming a Fin structure (104) over the substrate (102); forming a gate stack structure (15, 25) over a central part of the Fin structure (104); forming gate sidewall spacers (115) on a top face and sidewalls of the gate stack structure (15, 25) and forming Fin sidewall spacers (105) on a top face and sidewalls of the Fin structure (104); removing a head portion of the gate sidewall spacers (115) and a head portion of the Fin sidewall spacers (105) to expose a head portion of the gate stack structure (15, 25) and a head portion of the Fin structure (104); removing a portion of the Fin sidewall spacers (105), wherein the fin sidewall spacers (105) have a second height; Retracting part of the fin structure (104) to form a trench;epitaxial growth of an epitaxial structure (210) from the trench, wherein the epitaxial structure (210) is formed above the fin structure (104) and the epitaxial structure (210) has a first height and the first height is greater than the second height; and forming an isolation structure (108) on the substrate (102), wherein the removal of part of the fin structure (104) to form the recess between the fin sidewall spacers (105) further comprises: removing part of the fin structure (104) until a top surface of the fin structure (104) is on a plane with or below a top surface of the isolation structure (108). Method for forming the Fin field-effect transistor device structure according to claim 10, wherein forming the gate stack structure (15, 25) over the central part of the Fin structure (104) comprises: forming a gate electrode on the Fin structure (104); forming a first hard mask layer on the gate electrode; and forming a second hard mask layer on the first hard mask layer. Method for forming the Fin field-effect transistor device structure according to claim 10 or 11, wherein a bottom surface of the epitaxial structure (210) lies on a plane with or below a top surface of the insulation structure (108). Method for forming the Fin field-effect transistor device structure according to one of claims 10 to 12, further comprising, prior to the epitaxial growth of the epitaxial structure (210): removing the entire Fin sidewall spacer (105); and removing a part of the Fin structure (104) until a cover surface of the Fin structure (104) lies below a cover surface of the insulation structure (108).

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