Light-emitting semiconductor device

Abstract

Light-emitting semiconductor device comprising: a semiconductor layer structure (L) comprising a first surface and a second surface opposite each other, a semiconductor layer of a first conductivity type (14) and a semiconductor layer of a second conductivity type (16) forming the first surface and the second surface respectively, and an active layer (15) arranged between the semiconductor layer of the first conductivity type (14) and the semiconductor layer of the second conductivity type (16); a first electrode (17) which is arranged on the first surface of the semiconductor layer structure (L) and is connected to the semiconductor layer of the first conductivity type (14); a second electrode (18) which is arranged on the second surface of the semiconductor layer structure (L) and is connected to the semiconductor layer of the second conductivity type (16); a connecting electrode (48) which is connected to the second electrode (18) and which extends to the first surface of the semiconductor layer structure (L); a support substrate (45) arranged at the second electrode (18); and an insulating layer (46) arranged to insulate the connecting electrode (48) from the active layer (15) and the semiconductor layer of the first conductivity type (14), wherein the semiconductor layer structure (L) has a through hole (H) extending from the first surface to the second surface, and the connecting electrode (48) is electrically connected to the second electrode (18), is arranged on an inner side wall of the through hole (H) and extends to the first surface of the semiconductor layer structure (L), further comprising an etch stop layer (42; 102) which is arranged on a section of the second electrode (18) and connects the second electrode (18) to the connecting electrode (48), wherein the etch stop layer (42; 102) contains a conductive material and is arranged between the second electrode (18) and the support substrate (45, 105).

Description

GENERAL STATE OF THE ART

[0001] The present inventive concept relates to a light-emitting semiconductor device.

[0002] Light-emitting semiconductor diodes (LEDs) are widely used as light sources because they offer a variety of advantages, such as low power consumption and high brightness levels. More specifically, light-emitting semiconductor devices have been used for some time as illumination and backlighting devices in large liquid crystal displays (LCDs). Such light-emitting semiconductor devices can have a structure (e.g., a package structure) that allows them to be connected to an external circuit, enabling them to be installed in various devices, such as lighting fixtures.

[0003] A substrate used in an epitaxial growth process for a light-emitting semiconductor device (hereinafter referred to as the "growth substrate") can be removed after the light-emitting semiconductor device has grown. The substrate may be removed due to electrical connectivity issues or problems with optical losses. In this case, another method may be required to support epitaxial growth of a thin film. For example, an electrode structure of a certain thickness (e.g., 60 µm to 150 µm) or more, or a substrate incorporating the electrode structure, may be used in a light-emitting semiconductor device.

[0004] However, the method for distributing heat emitted from an active layer can be disadvantageous; more precisely, due to heat generated during operations involving high current flow, it can degrade the device's properties, leading to reduced reliability.

[0005] US 2014 / 0061700A1 discloses: A flip-chip light-emitting diode structure comprises a substrate, a light-emitting die structure, a reflective layer, an aperture, a dielectric layer, a first contact layer, and a second contact layer. The light-emitting die structure, located on the substrate, comprises a type-one semiconductor layer, a type-two semiconductor layer, and a light-emitting layer. The light-emitting layer is positioned between the type-one semiconductor layer and the type-two semiconductor layer. The reflective layer is located on top of the type-one semiconductor layer. The aperture penetrates the light-emitting die structure. The dielectric layer covers an inner sidewall of the aperture and extends to a portion of the surface of the reflective layer.The first contact layer is located on the portion of the reflective layer not covered by the dielectric layer. The second contact layer fills the aperture and is electrically connected to the second type of semiconductor layer.

[0006] WO 2014 / 007 479 A1 relates to a light-emitting diode (LED), in particular an LED module for surface mounting technology and a method for its manufacture.

[0007] US 2008 / 0031295A1 relates to a light-emitting semiconductor device and a method for its manufacture. SUMMARY

[0008] One aspect of the present disclosure relates to a light-emitting semiconductor device with a novel structure that addresses problems existing in current light-emitting devices. The invention is defined in the independent claims. Specific embodiments are defined in the dependent claims.

[0009] According to one embodiment, a light-emitting semiconductor device has a semiconductor layer structure comprising a first surface and a second surface that are opposite to each other, a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type forming the first surface and the second surface, respectively, and an active layer arranged between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type. A first electrode is arranged on the first surface of the semiconductor layer structure and connected to the semiconductor layer of the first conductivity type, and a second electrode is arranged on the second surface of the semiconductor layer structure and connected to the semiconductor layer of the second conductivity type.A connecting electrode is linked to the second electrode and extends to the first surface of the semiconductor layer structure. A support substrate is arranged on the second electrode, and an insulating layer is positioned to isolate the connecting electrode from the active layer and the first conductivity-type semiconductor layer. The semiconductor layer structure has a through-hole extending from the first surface to the second surface to expose a portion of the second electrode, and the connecting electrode is linked to the exposed portion of the second electrode, positioned on the inner sidewall of the through-hole, and extends to the first surface of the semiconductor layer structure. The light-emitting semiconductor device further includes an etch stop layer positioned on a portion of the second electrode connected to the through-hole.The etch stop layer contains a conductive material and is positioned between the second electrode and the substrate.

[0010] The semiconductor layer of the first conductivity type can be an n-type semiconductor layer, and the semiconductor layer of the second conductivity type can be a p-type semiconductor layer.

[0011] The second electrode can include a translucent electrode, and the support substrate can include a translucent substrate.

[0012] In this case, the second electrode can be located on a predominant portion of the second surface of the semiconductor layer structure. The first electrode can be a reflective electrode.

[0013] The light-emitting semiconductor device may further comprise first and second conductive contact protrusions arranged on sections of the first electrode and the connecting electrode on the first surface.

[0014] The first surface of the semiconductor layer structure can be provided as the main light-emitting surface, and the first electrode can be located on a section of the first surface of the semiconductor layer structure.

[0015] At least part of the section of the second electrode where the through-hole is formed can be removed to expose a section of the etch stop layer, and the connecting electrode can be connected to the exposed section of the etch stop layer. The light-emitting semiconductor device can further comprise at least one finger electrode connected to the etch stop layer and extending into a space between the second electrode and the support substrate.

[0016] According to one embodiment, a light-emitting semiconductor device has a semiconductor layer structure comprising a first surface and a second surface that are opposite to each other, a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type forming the first surface and the second surface, respectively, and an active layer arranged between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type. A first electrode is arranged on the first surface of the semiconductor layer structure and connected to the semiconductor layer of the first conductivity type, and a second electrode is arranged on the second surface of the semiconductor layer structure and connected to the semiconductor layer of the second conductivity type.A connecting electrode is linked to the second electrode and extends to the first surface of the semiconductor layer structure. A support substrate is arranged on the second electrode, and an insulating layer is positioned to isolate the connecting electrode from the active layer and the first conductivity-type semiconductor layer. The semiconductor layer structure has a through-hole extending from the first surface to the second surface to expose a portion of the second electrode, and the connecting electrode is linked to the exposed portion of the second electrode, positioned on the inner sidewall of the through-hole, and extends to the first surface of the semiconductor layer structure.The light-emitting semiconductor device further comprises an etch stop layer located between the semiconductor layer structure and the second electrode, with a section connected to the through-hole. The etch stop layer incorporates an insulating material and is positioned to surround the exposed portion of the second electrode.

[0017] The light-emitting semiconductor device may further include a planarization layer located between the second electrode and the support substrate, which has a planarized surface bonded to the support substrate.

[0018] The insulating layer can be located on the inner sidewall of the through-hole and can extend to the first surface of the semiconductor layer structure. In this case, the insulating layer can be extended to cover a portion of the first electrode, and the connecting electrode can extend to the extended portion of the insulating layer.

[0019] The light-emitting semiconductor device can further comprise an insulating element surrounding the side faces of the semiconductor layer structure. The connecting electrode can be arranged on the side faces of the semiconductor layer structure, and the insulating layer can be arranged between the connecting electrode and the side faces of the semiconductor layer structure.

[0020] The insulating element can contain a translucent adhesive material and can be positioned between the second surface of the semiconductor layer structure and the support structure to attach the semiconductor layer structure to the support substrate. The insulating element can be made of the same material as the support substrate.

[0021] The light-emitting semiconductor device may further comprise an electrode protection layer arranged between the second electrode and the support substrate, designed to protect the second electrode.

[0022] The support substrate can be made of glass or a polymer resin. The support substrate can contain a phosphor or a quantum dot.

[0023] According to an example to better understand the present invention, a light-emitting semiconductor device has a semiconductor layer structure comprising a first surface and a second surface that are opposite to each other, a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type forming the first surface and the second surface, respectively, and an active layer arranged between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type. A first electrode is arranged on the first surface of the semiconductor layer structure and is connected to the semiconductor layer of the first conductivity type. A second electrode is arranged on the second surface of the semiconductor layer structure and is connected to the semiconductor layer of the second conductivity type and is formed from a transparent electrode.A connecting electrode is connected to the second electrode such that it extends to the first surface of the semiconductor layer structure, and a portion of the connecting electrode located on the first surface serves as the contact area. A translucent substrate is placed on the second electrode, and an insulating layer is arranged to isolate the connecting electrode from the active layer and the semiconductor layer of the first conductivity type. The insulating layer extends to cover a portion of the first electrode, and the contact area of ​​the connecting electrode is located on this extended portion of the insulating layer.

[0024] In one example, a translucent adhesive layer is arranged between the translucent substrate and the second electrode. The connecting electrode can be located on side faces of the semiconductor layer structure, and the insulating layer can be located between the connecting electrode and the side faces of the semiconductor layer structure. The light-emitting semiconductor device can further include an insulating element surrounding the side faces of the first surface of the semiconductor layer structure, formed from a translucent adhesive material for bonding to the translucent substrate. The side faces of the semiconductor layer structure can have a surface inclined towards the second surface.

[0025] According to an example to better understand the present invention, a light-emitting semiconductor device has a support substrate with an upper surface divided into a first region and a second region, the first region being designated as a contact area. A semiconductor layer structure comprises a semiconductor layer of a second conductivity type, an active layer, and a semiconductor layer of a first conductivity type, arranged sequentially in the second region of the upper surface of the support substrate. A first electrode is arranged on the semiconductor layer of the first conductivity type, and a second electrode is arranged between the semiconductor layer of the second conductivity type and the support substrate and extends into the first region.

[0026] The support substrate can include a translucent substrate. The second electrode can include a translucent electrode positioned between the semiconductor layer of the second conductivity type and the support substrate, a metal electrode connected to the translucent electrode and located in the second region, and a contact electrode positioned on the metal electrode.

[0027] The metal electrode can have a first surface with a section connected to the translucent electrode and a second surface opposite the first surface. The second surface can be buried in the support substrate. The metal electrode can have at least one finger electrode extending into a space between the translucent electrode and the support substrate.

[0028] According to an example to better understand the present invention, a light-emitting semiconductor device has a semiconductor layer structure comprising a semiconductor layer of a second conductivity type, an active layer, and a semiconductor layer of a first conductivity type stacked one above the other. A first electrode is arranged on the semiconductor layer of the first conductivity type, and a second electrode is arranged on the semiconductor layer of the second conductivity type. An insulating layer is arranged at an exposed edge of the stack consisting of the semiconductor layer of the second conductivity type, the active layer, and the semiconductor layer of the first conductivity type. A connecting electrode is connected to a second electrode and extends along the insulating layer to a surface of the stacked semiconductor comprising the semiconductor layer of the first conductivity type.

[0029] The semiconductor layer structure can have a plurality of through-holes passing through the second-type semiconductor layer, the active layer, and the first-type semiconductor layer. The insulating layer can be arranged on an exposed edge of each of the plurality of through-holes. The connecting electrode can be positioned on the insulating layer of each through-hole such that it extends from the insulating layer to the surface of the layered semiconductor, which includes the first-type semiconductor layer.

[0030] The light-emitting semiconductor device can further comprise a light-emitting substrate arranged on the second electrode. Multiple etch stop contacts can be arranged between the light-transmitting substrate and the second electrode, each aligned with one of the multiple through-holes. Multiple finger electrodes can be arranged between the light-transmitting substrate and the second electrode, each extending from one of the multiple etch stop contacts.

[0031] The light-emitting semiconductor device can alternatively have a plurality of etch-stop contacts arranged between the semiconductor layer of the second conductivity type and the second electrode, and each of the etch-stop contacts can be aligned with a corresponding through-hole from the plurality of through-holes. The through-holes and the connecting electrode can extend through the etch-stop contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and further aspects, features and other advantages of the present disclosure will become clearer from the following detailed description in conjunction with the accompanying drawings, whereby: Fig. 1 a side view of a light-emitting semiconductor device according to an embodiment; Fig. 2A and Fig. 2B Plan views from below and from above are an example of an electrode layout of the in Fig. 1 shows the light-emitting semiconductor device shown; Fig. Figure 3 is a plan view from below, which is another example of an electrode layout of the in Fig. 1 shows a light-emitting semiconductor device; Fig. 4 shows an example in which the in Fig. 1 The light-emitting semiconductor device shown is attached to a circuit substrate by flip-chip mounting; Fig. Sections 5A to 10E are cross-sectional representations of the main process steps in a method for producing the in Fig. The light-emitting semiconductor device shown in the illustrations in 9 is shown; Fig. 6 is a cross-sectional view showing a flip-chip bonded light-emitting semiconductor device according to an embodiment; Fig. Figure 7 is a plan view from below, which is an example of an electrode layout shown in the Fig. 6 can be used in the light-emitting semiconductor device shown; Fig. Sections 8A to 8G are cross-sectional representations of the main process steps in a method for manufacturing the in Fig. The 6 shown light-emitting semiconductor device; Fig. 9 is a cross-sectional view showing a flip-chip bonded light-emitting semiconductor device according to an embodiment; Fig. Sections 10A to 10E are cross-sectional representations of the main process steps in a process for producing the in Fig. The light-emitting semiconductor device shown in the illustrations in 9 is shown; Fig. 11 is a cross-sectional view showing a flip-chip bonded light-emitting semiconductor device according to an embodiment; Fig. Sectional representations 12A to 12F show the main process steps for the production of the in Fig. 11 shows the light-emitting semiconductor device; Fig. 13 is a cross-sectional view showing a flip-chip bonded light-emitting semiconductor device according to an embodiment; Fig. Sections 14A to 14E show cross-sectional views of the main process steps for the production of the in Fig. 13 show the light-emitting semiconductor device shown; Fig. 15 is a cross-sectional representation, which is an improved example of the in Fig. Figure 13 shows a light-emitting semiconductor device; Fig. Figures 16A to 16C are cross-sectional representations showing flip-chip bonded light-emitting semiconductor devices with improved light extraction efficiency according to various embodiments; Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. 21 cross-sectional views are shown, illustrating light-emitting semiconductor devices according to various embodiments; Fig. Figures 22A to 22F are cross-sectional representations showing the main process steps in a method for manufacturing a light-emitting semiconductor device according to an exemplary embodiment; Fig. 23A to 23D plan views are those that show mask patterns which are in the Fig. The main process steps shown in 22A to 22F are used; Fig. Figures 24A to 24F are cross-sectional representations showing the main process steps in a method for manufacturing a light-emitting semiconductor device according to an exemplary embodiment; Fig. Figures 25A to 25D are cross-sectional views showing various examples of a buffer structure as illustrated in the embodiments; Fig. 26 and Fig. 27 cross-sectional views are shown, depicting packages of light-emitting semiconductor devices according to various embodiments; Fig. 28 is a CIE 1931 color coordinate system for describing a wavelength conversion material that can be used in an embodiment; Fig. 29 and Fig. 30 examples show how a light-emitting semiconductor device according to one embodiment is applied to a backlighting unit; Fig. 31 shows an example of a lighting apparatus comprising a light-emitting semiconductor device according to one embodiment; Fig. Figure 32 shows an example of a headlight which has a light-emitting semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0033] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0034] The disclosure can, however, be illustrated in many different forms and should not be considered limited to the embodiments specified herein. Instead, these embodiments are given to ensure that the disclosure is thorough and complete and that the scope of the disclosure is clearer to the person skilled in the art. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals are used throughout to denote identical or similar elements. Throughout the disclosure, directional terms such as "upper section," "top," "lower section," "bottom," or "side face" indicate positions relative to the respective orientations shown in the drawings.The terms should be understood as referring more broadly to the relative positions of different elements and thus may vary depending on the direction or orientation in which a light-emitting device is held or arranged.

[0035] When this disclosure refers to “an embodiment,” this is intended to emphasize certain features, structures, or properties and need not necessarily refer to one and the same embodiment. Furthermore, the respective features, structures, or properties may be combined in any suitable way in one or more embodiments. For example, a context described in a particular embodiment may be used in other embodiments, even if it is not described in the other embodiments, as long as it is not expressly stated that it contradicts or is inconsistent with the context in the other embodiments.

[0036] Fig. Figure 1 is a cross-sectional representation of a light-emitting semiconductor device according to an embodiment of the present disclosure.

[0037] It will be on Fig. Reference is made to Figure 1, which shows that a light-emitting semiconductor device 10 according to the embodiment of the present disclosure can have a semiconductor layer structure L comprising a semiconductor layer 14 of a first conductivity type, a semiconductor layer 16 of a second conductivity type, and an active layer 15 arranged between the semiconductor layer 14 of the first conductivity type and the semiconductor layer 16 of the second conductivity type. The light-emitting semiconductor device 10 can further comprise a first and a second electrode, 17 and 18, which are connected to the semiconductor layer of the first conductivity type, 14, and the semiconductor layer of the second conductivity type, 16, respectively.

[0038] In this embodiment, the first and second electrodes 17 and 18 can be arranged on a first surface and a second surface that are opposite each other in the semiconductor layer structure L. A support substrate 25 can be arranged on the second electrode 18 to support the semiconductor layer structure L.

[0039] The light-emitting semiconductor device 10 can further comprise a connecting electrode 28 as an electrode component, which is related to the second electrode 18. The connecting electrode 28 can be connected to the second electrode 18 and can extend to the first surface of the semiconductor layer structure L.

[0040] The connecting electrode 28 according to the exemplary embodiment can be formed using a through-hole H that passes through the semiconductor layer structure L and connects the first and second surfaces of the semiconductor layer structure L. A section of the second electrode 18 can be exposed through the through-hole H, and the exposed section can be provided as a contact area C that is connected to the connecting electrode 28. The connecting electrode 28 can be connected to the contact area C of the second electrode 18 and can be formed on an inner side wall of the through-hole H. A section 28a of the connecting electrode 28, which is arranged on the first surface of the semiconductor layer structure L, can be provided as a contact area.

[0041] In this way, the second electrode 18, which is located on the second surface of the semiconductor layer structure L, can be drawn through the connecting electrode 28 to the first surface, which is opposite the second surface, and thus a contact point area, which connects the second electrode 18 to an external circuit, can be provided on the first surface of the semiconductor layer structure L.

[0042] Such an electrode structure can be used to a greater advantage when the semiconductor layer 14 of the first conductivity type and the semiconductor layer 16 of the second conductivity type are n- and p-nitride semiconductor layers, respectively. Since the p-nitride semiconductor layer has a higher degree of contact resistance than the n-nitride semiconductor layer, it is difficult to implement an ohmic contact. In this embodiment, the second electrode 18 is arranged on the second surface of the semiconductor layer structure L, and therefore the contact area between the second electrode 18 and the semiconductor layer 16 of the second conductivity type can be increased, thus ensuring an ohmic contact with the p-nitride semiconductor layer.

[0043] The light-emitting semiconductor device 10 according to the embodiment can be a flip-chip structure in which light is emitted mainly in the direction of the support substrate 25.

[0044] The first electrode 17 can comprise an electrode material with high reflectivity and ohmic contact properties. For example, the first electrode 17 can comprise Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, or the like. Alternatively, the first electrode 17 can comprise a transparent conductive oxide, such as indium tin oxide (ITO), or a transparent conductive nitride. For example, the first electrode 17 can be implemented as a combination of the translucent electrode and a reflective electrode, or as a combination of the translucent electrode and an insulating material such as SiO2.

[0045] The second electrode 18 can be a translucent electrode, and the support substrate 25 can be a translucent substrate. The second electrode 18 can be a translucent metal such as Ni / Au, a transparent conductive oxide such as ITO, or a transparent conductive nitride. The support substrate 25 can be a glass substrate or a substrate formed from a translucent polymer resin.

[0046] The connecting electrode 28 can be electronically isolated from the semiconductor layer 14 of the first conductivity type and the active layer 15 by an insulating layer 26. As shown in Fig. As shown in Figure 1, the insulating layer 26 can be formed on the inner side wall of the through-hole H. The insulating layer 26 can be formed on side surfaces of the semiconductor layer structure L and provided as a passivation layer for the light-emitting semiconductor device 10. The insulating layer 26 can also be formed to extend over a surface of the first electrode 17. The insulating layer 26 can be silicon oxide or silicon nitride.

[0047] In this embodiment, the first electrode 17 can have an area sufficient to efficiently reflect light. The contact area 28a, located on the first surface of the semiconductor layer structure L, can now be extended to a section of an upper surface of the first electrode 17, so that the connecting electrode 28 has a sufficient contact area that is connected to (or available for connection to) the external circuit. The insulating layer 26 can have an additional extended section 26a (see “I” in Figure 1). Fig. 1) having a contact surface 28a and the first electrode 17 arranged between them, such that the contact surface 28a and the first electrode 17 are not electrically connected to each other.

[0048] A specific example of an electrode layout that can be used in the embodiment of the present disclosure is given in Fig. 2A and Fig. 2B is shown. Fig. 2A and Fig. Figure 2B shows an example of layouts of electrodes arranged on a second surface and a first surface of a semiconductor layer structure L.

[0049] As in Fig. As shown in Figure 2A, the second electrode 18 can be formed on a predominant part of the surface of the semiconductor layer 16 of the second conductivity type. As described above, the second electrode 18 is formed on a predominant part of the surface of the semiconductor layer 16 of the second conductivity type, and therefore contact resistance can be reduced. The second electrode 18 can be connected to a connecting electrode 28 via two contact areas C located at (or adjacent to or near) two corners of the second electrode 18.

[0050] As in Fig. As shown in Figure 2B, a contact area 28a of the connecting electrode 28 extends to a section of the upper surface of the first electrode 17, and therefore a relatively sufficient contact area can be ensured. The insulating layer 26 can also have an extended section 26a that extends to the section of the upper surface of the first electrode 17 in order to electrically insulate the first electrode 17 from the connecting electrode 28.

[0051] The electrode layout, which is in the Fig. The light-emitting semiconductor device shown in Figure 1 is not limited to the example described above and can be modified in many ways. For example, the electrode layout can be implemented in the same way as in Figure 1. Fig. 3 shown.

[0052] As in Fig. As shown in Figure 3, a contact region C can be provided in the form of a line located at or near an edge of the semiconductor layer structure L. Such a contact region C can be obtained by forming a through-hole H adjacent to the edge of the semiconductor layer structure L and connecting the connecting electrode 28 to a section of the second electrode 18 exposed through the through-hole H.

[0053] Fig. 4 shows an example in which the in Fig. 1 The light-emitting semiconductor device shown is attached to a circuit substrate by flip-chip mounting.

[0054] It will be on Fig. 4 Reference is made where a circuit substrate 31 is shown with the light-emitting semiconductor device 10 attached to it.

[0055] The light-emitting semiconductor device 10 can be a flip-chip structure, which also includes conductive contact protrusions 34 arranged at the first electrode 17 and the contact surface 28a of the connecting electrode 28, which lies on the first surface. The conductive contact protrusions 34 can consist of protrusions made of a conductive metal such as Au / Sn. The light-emitting semiconductor device 10 can be electrically connected via the conductive contact protrusions 34 to first and second circuit patterns 32a and 32b, which are arranged on the circuit substrate 31. In the exemplary embodiment, the second electrode 18, as described above, can be a transparent electrode such as ITO, and the support substrate 25 can be a transparent substrate, for example, a glass substrate, so that light is transmitted in the direction of the support substrate 25.

[0056] Fig. 5A to 5G are cross-sectional representations showing the main processes in a method for manufacturing the in Fig. Figure 1 shows a light-emitting semiconductor device. For the sake of simplicity and to make the description clearer, only a part corresponding to the two light-emitting semiconductor devices is shown in the drawings; the processes can be understood as processes at the wafer level, and a substrate 11 can be part of a wafer.

[0057] As in Fig. As shown in Figure 5A, a semiconductor layer structure L can be formed on a growth substrate 11 to form a plurality of light-emitting devices.

[0058] The semiconductor layer structure L can comprise a semiconductor layer 14 of a first conductivity type, an active layer 15, and a semiconductor layer 16 of a second conductivity type, which are grown sequentially on a surface of the substrate 11. The growth process can involve a process known in engineering, for example, metal-organic chemical vapor deposition (MOCVD), hydride gas phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0059] Depending on requirements, an insulating, conductive, or semiconductor substrate can be used as the growth substrate 11. For example, the growth substrate 11 can be sapphire, SiC, Si, MgAl2O4, MgO, LiAlO2, LiGaO2, or GaN.

[0060] The semiconductor layer structure L can be a nitride semiconductor material. For example, semiconductor layer 14 of the first conductivity type and semiconductor layer 16 of the second conductivity type can be a monocrystalline nitride with composition Al x In y Ga 1-x-yThe active layer 15 can be N (0≥x≥1, 0≥y≥1, and 0≥x+y≥1), but are not limited to these. An AlGaInP-based or an AlGaAs-based semiconductor material can be used as the first conductivity type semiconductor layer 14 and the second conductivity type semiconductor layer 16. The first conductivity type semiconductor layer 14 and the second conductivity type semiconductor layer 16 can contain n-type and p-type semiconductor materials, respectively. The active layer 15 can be a multi-quantum well (MQW) structure, in which quantum well layers and quantum barrier layers are stacked alternately. For example, in the case of a nitride semiconductor material, the active layer 15 can be a GaN / InGaN MQW structure. Alternatively, the active layer 15 can be a single quantum well (SQW) structure.

[0061] The semiconductor layer L can be formed (e.g., grown) on a buffer layer 12 arranged on the substrate 11. The buffer layer 12 can be used to reduce displacements caused by mismatches in lattice constants between the substrate 11 and the semiconductor layer L in a subsequent process, as well as deformation caused by differences in coefficients of thermal expansion and the formation of cracks. The buffer layer 12 can be formed as a single layer or as a multilayer layer with a plurality of layers on the surface of the substrate 11 before the semiconductor layer L is formed.

[0062] For example, if a silicon substrate is used as the growth substrate 11 for single-crystal nitride, a (111) plane of silicon can be used as the plane for crystal growth. In this case, the buffer layer 12 can include an AlN nucleation layer and a lattice buffer layer consisting of Al-containing nitride crystal. Various examples of the buffer layer 12 are given with reference to Fig. 25A to 25D described.

[0063] As in Fig. As shown in Figure 5B, a second electrode 18, which is connected to the semiconductor layer 16 of the second conductivity type, can then be formed on an upper surface (i.e. the second surface) of the semiconductor layer structure L.

[0064] The second electrode 18 can be configured to have a large contact area with the semiconductor layer 16 of the second conductivity type. In the exemplary embodiment, the second electrode 18 can be configured to cover the entire upper surface (or substantially the entire upper surface) of the semiconductor layer 16 of the second conductivity type.

[0065] The second electrode 18 can be a transparent conductive oxide or nitride layer. For example, the transparent conductive oxide layer can consist of at least one of the following: ITO, zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), In4Sn3O 12 and zinc magnesium oxide (Zn (1-x) Mg xO, 0≥x≥1). In some embodiments, the second electrode 18 can include a translucent metal layer such as Ni / Au or graphene. The process can be carried out in a thin-film formation process, for example by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0066] As in Fig. As shown in 5C, the carrier substrate 25 can then be bonded to the second electrode 18.

[0067] The carrier substrate 25 can be bonded to the second electrode 18 using an adhesive layer 21. In this embodiment, the carrier substrate 25 can be a translucent substrate, such as a glass substrate. The adhesive layer 21 can be a translucent adhesive material.

[0068] For example, the second process can be carried out by coating the second electrode 18 with an adhesive material such as benzocyclobutene (BCB) using a process such as spin coating, subsequently bonding the glass substrate to the second electrode 18, and then performing a heat treatment to cure the adhesive material. The adhesive layer 21 that can be used in the embodiment of the present invention need not be limited to BCB and can include various translucent adhesive materials. For example, other adhesive layers, such as a dry film resin (DFT), an epoxy resin, or a silicone resin, can be used.

[0069] The adhesive layer 21 can be used as an electrode protection layer to protect the second electrode 18. Alternatively, a separate electrode protection layer can be formed, and then a bonding process to the support substrate 25 using an adhesive material can be applied. Silicon oxide or silicon nitride can be used as the electrode protection layer.

[0070] As in Fig. As shown in 5D, the growth substrate 11 can then be removed from the semiconductor layer structure L.

[0071] The process of removing the growth substrate can be carried out using a process such as laser removal or a process in which the growth substrate 11 is directly removed, for example, by mechanical polishing or chemical etching. For example, if the growth substrate 11 is made of a transparent material such as sapphire, the sapphire substrate can be separated using the laser removal method, in which an interface between the semiconductor layer structure L and the growth substrate 11 is irradiated with a laser. If the growth substrate 11 is a silicon substrate with relatively low hardness, the silicon substrate can be removed by a process in which the growth substrate is directly removed, for example, by mechanical polishing or chemical etching.

[0072] If the buffer layer 12 has a high electrical resistance, the removal process can be carried out according to the embodiment of the present disclosure in order to expose a surface of the semiconductor layer 14 of the first conductivity type which is available for an electrical connection.

[0073] As in Fig. As shown in 5E, a through hole H can be formed in the semiconductor layer structure L to expose a section of the second electrode 18.

[0074] The process can be carried out by selectively removing the semiconductor layer structure L. Such a selective removal process can be performed by mechanical cutting, chemical etching, or dry plasma etching. The process can be carried out in conjunction with a fixture insulation process. A fixture insulation trench ISO can be formed together with the through-hole H. Alternatively, the through-hole H can be formed in a process that is different from that used for the fixture insulation trench ISO. For example, after forming the through-hole H, a necessary electrode formation process can be performed, and then a fixture insulation process, such as the process of forming the trench ISO, can be carried out.

[0075] As in Fig. As shown in 5F, a first electrode 17 and a connecting electrode 28 can then be formed in suitable areas.

[0076] Using this process, both contact surface areas, corresponding to the first and second electrodes 17 and 18, can be formed on the first surface of the semiconductor layer structure L. More precisely, after the formation of the first electrode 17, an insulating layer can be formed to cover the entire first surface of the semiconductor layer structure L. The insulating layer can then be selectively etched to reopen a contact area C, and the connecting electrode 28 can be formed to connect with the contact area C of the second electrode 18 and extend to the first surface. The insulating layer can then be selectively etched to expose the contact surface of the first electrode 17. Thus, the Fig. The resulting structure shown in 5F can be obtained.

[0077] The insulating layer 26 obtained can be formed on an inner side wall of the through-hole H such that the connecting electrode 28 is not connected to the active layer 15 and the semiconductor layer 14 of the first conductivity type. The insulating layer 26 can have an extended section 26a such that a section 28a of the connecting electrode 28, which is arranged on the first surface, is not connected to the first electrode 17.

[0078] The first electrode 17 can include a reflective electrode capable of forming an ohmic contact. For example, the first electrode 17 can contain Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, or Au. In some embodiments, the first electrode 17 can be a multilayer structure comprising the reflective electrode and an electrode forming an ohmic contact. For example, the first electrode 17 can have a structure such as Ni / Ag, Zn / Ag, Ni / Al, Zn / Al, Pd / Ag, Pd / Al, Ir / Ag, Ir / Au, Pt / Ag, Pt / Al, or Ni / Ag / Pt. The connecting electrode 28 can also be made of a similar material to the first electrode 17. The insulating layer 26 can be silicon dioxide or silicon nitride.

[0079] As described above, in some embodiments the first electrode 17 can have an electrode structure combining a transparent conductive oxide such as ITO or a transparent conductive nitride. For example, the first electrode 17 can be implemented as a combination of a translucent electrode and a reflective electrode, or as a combination of a translucent electrode and an insulating material such as SiO2.

[0080] As in Fig. As shown in the 5G diagram, a light-emitting semiconductor device 10 can be separated by separating the in Fig. The resulting structure shown in 5F can be obtained in individual device units.

[0081] In the exemplary embodiment, the semiconductor layer structure L was already separated into the fixture units in a previous process; therefore, the process can be easily implemented if the support substrate 25 is a substrate with a low degree of hardness, for example, a glass substrate. In contrast, if the fixture isolation trench ISO was not formed in the previous process, a fixture isolation process can be carried out in such a way that the support substrate 25 is separated together with the semiconductor layer structure L in this process.

[0082] The embodiment described above can be modified in various ways. For example, an etch stop layer can be formed to effectively control the etch depth when the through-hole H for the connecting electrode 28 is formed.

[0083] Fig. Figure 6 is a cross-sectional view showing a light-emitting flip-chip semiconductor device according to an embodiment of the present disclosure, which uses an etch stop layer formed from a conductive metal.

[0084] As in Fig. As shown in Figure 6, a light-emitting flip-chip semiconductor device 40 according to the embodiment of the present disclosure can have a semiconductor layer structure L, a first and a second electrode 17 and 18 and a support substrate 45.

[0085] In this embodiment, the first and second electrodes 17 and 18 can be connected, similarly to the one described in Fig. In the light-emitting semiconductor device shown in Figure 1, the electrodes are arranged on a first surface and a second surface, which are opposite to each other, in the semiconductor layer structure L. The support substrate 45 can be arranged on the second electrode 18. A connecting electrode 48 can be electrically connected to the second electrode 18 via a through-hole H and extends to the first surface of the semiconductor layer structure L.

[0086] In this way, the light-emitting semiconductor device 40 can have a flip-chip structure that includes contact surface areas on the first surface of the semiconductor layer structure L, so that the first and second electrodes 17 and 18 can be connected to an external circuit. A conductive contact bump 34 can be provided as a contact surface for both the first electrode 17 and the second electrode 48.

[0087] As in Fig. As shown in Figure 6, the light-emitting semiconductor device 40 can be connected to first and second circuit patterns 32a and 32b of a circuit substrate 31 using the conductive contact bumps 34.

[0088] In this embodiment, the first electrode 17 can have an electrode material with a high reflection rate, which also forms an ohmic contact with a semiconductor layer of a second conductivity type. The second electrode 18 can be a translucent metal such as Ni / Au, a transparent conductive oxide such as ITO, or a nitride. The support substrate 45 can be a glass substrate or a translucent polymer resin substrate.

[0089] The light-emitting semiconductor device 40 according to the embodiment of the present disclosure may, in contrast to the embodiments described above, have an etch stop layer 42 arranged between the second electrode 18 and the support substrate 45. The etch stop layer 42 according to the embodiment may be a conductive material. The etch stop layer 42 may be arranged on a section of the second electrode 18 in order to be directly connected to the second electrode 18.

[0090] As in Fig. As shown in Figure 6, a section of the etch stop layer 42 can be exposed by the through-hole H, and the connecting electrode 48 can be connected to the exposed section of the etch stop layer 42. Thus, the connecting electrode 48 can be electrically connected to the second electrode 18 through the etch stop layer 42. The connecting electrode 48 can be electrically insulated from a first-conductivity semiconductor layer 14 and an active layer 15 by an insulating layer 46 formed on an inner side wall of the through-hole H. The insulating layer 46 can be formed on the other surface of the light-emitting semiconductor device 40 to serve as a passivation layer.

[0091] The etch stop layer 42 can be made of a material with a lower etch rate than the second electrode 18. For example, if the second electrode 18 is an oxide such as ITO, the etch stop layer 42 can be a metal, such as Al, Au, Ag, Ti or TiW.

[0092] The etch stop layer 42 shown in the exemplary embodiment is formed between the second electrode 18 and the support substrate 45. However, if a compositional material of the etch stop layer 42 exhibits sufficient etch selectivity with respect to a compositional material of the semiconductor layer structure L, the etch stop layer 42 can be arranged between the second electrode 18 and the semiconductor layer structure L.

[0093] It is now shown that the second electrode 18 is completely removed in an area corresponding to the through-hole H. However, the second electrode 18 may remain partially in the area corresponding to the through-hole H. In some embodiments, the etch stop layer 42 may also be partially removed.

[0094] The light-emitting semiconductor device 40 can further comprise a planarization layer 43 to facilitate bonding to the support substrate 45. The planarization layer 43 can be formed on the second electrode 18, on which the etch stop layer 42 is located. If a bonding surface is uneven or rough, it is difficult to ensure robust bonding due to voids or the like that form during the bonding process. Therefore, if the etch stop layer 42 is arranged on the section of the second electrode 18, as in the embodiment of the present disclosure, the planarization layer 43 can be introduced to implement robust bonding to the support substrate 45.

[0095] The planarization layer 43 can provide a planar bonding surface using a transparent insulating material. For example, the planarization layer 43 can be formed using silicon dioxide, silicon nitride, or a curable resin. If required, an additional polishing process can be performed to provide a planarization layer 43 with a more advantageous bonding surface.

[0096] In the exemplary embodiment, the planarization layer 43 can also function as an electrode layer if a stable material is used that does not react with the second electrode 18.

[0097] The support substrate 45 can be bonded to the planarization layer 43 using an adhesive layer 41. Alternatively, the planarization layer 43 can be formed from an adhesive material, so that it can be bonded directly to the support substrate 45 without any separate adhesive layer.

[0098] If sufficient contact surface areas are ensured with respect to the first and second electrodes 17 and 18, the connecting electrode 48 does not need to overlap the first electrode 17, as in the first embodiment.

[0099] A more concrete example of an electrode layout that can be used in the embodiment is shown in Fig. 7 shown. Fig. Figure 7 is an example of an electrode layout which, according to the embodiment, is arranged on a second surface of a semiconductor layer structure L.

[0100] As in Fig. As shown in Figure 7, the second electrode can be formed on a predominant part of a surface of the semiconductor layer 16 of the second conductivity type, and two etch stop layers 42 can be arranged on areas corresponding to contact areas C located at (or near) both corners of the second electrode 18. The second electrode 18 can be connected to the connecting electrode 48 through the etch stop layer 42, which consists of a conductive material.

[0101] A plurality of finger electrodes 44 extending from the etch stop layer 42 can be formed on the second electrode 18. The plurality of finger electrodes 44 can distribute currents evenly through the second electrode 18. These finger electrodes 44 can be formed from the same material as the etch stop layer 42.

[0102] Fig. 8A to 8G are cross-sectional diagrams showing steps of main processes in a method for producing the in Fig. Figure 6 shows a light-emitting semiconductor device. The process can be considered a manufacturing process at the wafer stage, and a growth substrate 11 can be part of a wafer.

[0103] As in Fig. As shown in Figure 8A, an etch stop layer 42 can be formed on a second electrode 18 which is arranged on a semiconductor layer structure L.

[0104] The in Fig. The semiconductor layer structure shown in 8A can be compared to the one described in Fig. 5B corresponds to the semiconductor layer structure L shown, and the process can be described with reference to Fig. 5A and Fig. 5B and the associated descriptions must be understood. The etch stop layer 42 can be arranged in a region Ha of the second electrode 18 on which a through-hole H is to be formed. The etch stop layer 42 can have a larger area than the area exposed by the through-hole H. The etch stop layer 42 can be made of a material with high etch selectivity with respect to the second electrode 18. If the second electrode 18 is a transparent conductive oxide such as ITO, the etch stop layer 42 can be a metal, for example Al, Au, Ag, Ti, or TiW.

[0105] In this process, a plurality of finger electrodes 44, which are connected to the etch stop layer 42, can be formed on the second electrode 18, as shown in Fig. Figure 7 shows that these finger electrodes 44 can be formed from the same material as the etch stop layer 42. The majority of finger electrodes 44 can be formed during the same process step, which is shown in Fig. 8A is shown.

[0106] As in Fig. As shown in Figure 8B, a planarization layer 43 can then be formed on the second electrode 18, on which the etch stop layer 42 is arranged.

[0107] The planarization layer 43 can eliminate any unevenness caused by the etch stop layer 42 and provide a flat surface that is advantageous for the subsequent bonding process. In a flip-chip structure such as the embodiment, the planarization layer 43 can be formed from a translucent material, that is, from any of a variety of curable resins, as well as from silicon dioxide or silicon nitride. For example, tetraethyl orthosilane (TEOS), boron phosphosilicate glass (BPSG), spin-on glass (SOG), or spin-on dielectric (SOD) can be used as the planarization layer 43. Since such materials are fluid during processing, a layer with a relatively flat surface can be provided by a spin process or a reflow process.Alternatively, or in combination with this, after the formation of the material layer for planarization, a surface thereof can be planarized by means of a polishing process (for example, the surface roughness can be polished to a variation of less than 1 nm). Thus, a suitable planarization layer 43 can be formed.

[0108] As in Fig. As shown in 8C, a carrier substrate 45 can then be bonded to the planarization layer 43.

[0109] In this process, the support substrate 45 can be bonded to the planarization layer 43 using an adhesive layer 41. The support substrate 45 can be a translucent material such as a glass substrate. The adhesive layer 41 can be a translucent bonding material. For example, BCB, DFR, epoxy, or silicone resin can be used. Alternatively, the support substrate 45 can be bonded to the planarization layer 43 without any other adhesive layer.

[0110] As in Fig. As shown in 8D, the growth substrate 11 can then be removed from the semiconductor layer structure L.

[0111] In the removal process, a buffer layer 12 with high electrical resistance can be removed along with the growth substrate 11. This exposes an electrically connectable surface of a semiconductor layer 14 of a first conductivity type, and a process for forming an electrode contact point can be carried out on a first surface of the semiconductor layer structure L. The substrate removal process can be performed by separating the growth substrate, such as a laser removal process, or by directly removing the growth substrate 11, for example, by a mechanical polishing process or a chemical etching process.

[0112] Then, as in Fig. As shown in Figure 8E, a through hole H is formed in the semiconductor layer structure L.

[0113] The through-hole H can be formed to expose a section of the etch stop layer 42. Although the second electrode 18 is formed from a translucent material, its transmittance may decrease with increasing thickness. Therefore, the thickness of this second electrode 18 can be limited to ensure high transmittance. In this case, the second electrode 18 may be susceptible to damage while the through-hole H is being formed in the semiconductor layer structure L, and thus it may be difficult to ensure good contact with the connecting electrode 48.

[0114] For example, if the second electrode is 18 ITO, its thickness can range from 100 Å to 1000 Å. While the through-hole in the semiconductor layer L is formed with a thickness of 2 to 5 µm, the ITO can be damaged, resulting in a contact failure.

[0115] According to the embodiment shown, however, by using the etch stop layer 42 the etch depth can be easily controlled, and good contact with the second electrode 18 can be ensured.

[0116] The process can be divided into several etching processes according to the etching depth. For example, a first etching process can be performed to remove the semiconductor layer structure L, and then a second etching process can be performed to selectively remove the second electrode 18, for example ITO, to expose the etch stop layer 42.

[0117] In this process, during the formation of the through-hole H, a fixture insulation region can also be exposed to form a fixture insulation trench ISO.

[0118] Then, as in Fig. As shown in Figure 8F, the connecting electrode 48 is formed in a contact area C which is exposed by the through hole H.

[0119] This process allows both contact surfaces, which are associated with the first and second electrodes 17 and 18, to be formed on the first surface of the semiconductor layer structure L. An insulating layer 46 can be formed on an inner side wall of the through-hole H such that the connecting electrode 48 is not connected to the active layer 15 or the semiconductor layer 14 of the first conductivity type. The insulating layer 46 can have a section 46a extending to the first surface of the semiconductor layer structure L, such that a section 48a of the connecting electrode 48, located on the section 46a extending to the first surface, is not connected to the semiconductor layer 14 of the first conductivity type.Furthermore, the insulating layer 46 deposited in this process can be provided as a passivation layer on the other surface of the light-emitting semiconductor device 40.

[0120] As in Fig. 8G is shown, then by separating the in Fig. The resulting structure shown in 8F is obtained in individual device units, the light-emitting semiconductor device 40.

[0121] The etch stop layer used in the embodiment described above can be modified in various ways. For example, the material and / or position of the etch stop layer can be changed.

[0122] Fig. Figure 9 is a cross-sectional view showing a light-emitting flip-chip semiconductor device including an etch stop layer 52 formed from an insulating material, according to an exemplary embodiment.

[0123] As in Fig. As shown in Figure 9, a light-emitting flip-chip semiconductor device 50 according to the embodiment can have a semiconductor layer structure L, a first and a second electrode 17 and 18 and a support substrate 55.

[0124] In this embodiment, the light-emitting flip-chip semiconductor device 50 can have a similar flip-chip structure to that described above. More precisely, the first and second electrodes 17 and 18 can be arranged on a first surface and a second surface, respectively, which are opposite each other in the semiconductor layer structure L. The support substrate 55 can be arranged on the second electrode 18. The connecting electrode 58 can be electrically connected to the second electrode 18 through the through-hole H and extends to the first surface of the semiconductor layer structure L.

[0125] As in Fig. As shown in Figure 9, the semiconductor layer structure 50 can have conductive contact protrusions 34, each formed on the first electrode 17 and the connecting electrode 58, and provided as contact surface areas. The light-emitting semiconductor device 50 can be connected to the first and second circuit patterns 32a and 32b of a circuit substrate 31 using the conductive contact protrusions 34. The conductive contact protrusions 34 arranged on the connecting electrode 58 need not completely fill a section recessed by the through-hole H, as shown in Figure 9. Fig. 9 is shown. 9 is shown.

[0126] The in Fig. The light-emitting semiconductor device 50 shown in Figure 9 can have an etch stop layer 52. However, according to the embodiment of the present disclosure, the etch stop layer 52 can be arranged between the second electrode 18 and the semiconductor layer structure and can be formed from an electrically insulating material, unlike the one shown in Figure 9. Fig. 6 Etch stop layer shown 42.

[0127] In this embodiment, the second electrode 18 can have a region C exposed by the through-hole H, and the etch stop layer 52 can be arranged around the exposed region C. The connecting electrode 58 can be connected to the exposed region C of the second electrode 18. The connecting electrode 58 can be electrically insulated from the first-conductivity semiconductor layer 14 and the active layer 15 by an insulating layer 56 formed on the side faces of the through-hole H. The insulating layer 56 can be provided as a passivation layer on the other side of the light-emitting semiconductor device 50.

[0128] The etch stop layer 52 can, under certain circumstances, consist of a material with a higher etch rate than the second electrode 18. For example, if the second electrode 18 is a translucent oxide such as ITO, the etch stop layer 52 can be silicon oxide or silicon nitride.

[0129] Since the etch stop layer 52 is at least partially removed to provide (or ensure) a contact area C of the second electrode 18, it is possible that the etch stop layer 52 remains only around the contact area C of the second electrode 18, as shown in Fig. Figure 9 is shown. However, depending on wet etching conditions, the etch stop layer 52 may remain partially in the contact area C or be completely removed without leaving any residue around the contact area C. Unlike in the exemplary embodiment, even in the case where the etch stop layer 52 is almost completely removed without leaving any residue around the contact area C, it can be determined whether or not the etch stop layer 52 is used based on whether the contact area C of the second electrode 18 has irregularities or not.

[0130] The light-emitting semiconductor device 50 can further comprise a planarization layer 53 to facilitate bonding to the support substrate 55. The planarization layer 53 can be formed on the second electrode 18 to flatten the uneven surface created by the etch stop layer 52.

[0131] The planarization layer 53 can provide a uniform bonding surface using a transparent insulating material. For example, the planarization layer 53 can be silicon dioxide, silicon nitride, or a curable resin. If required, an additional polishing process can be introduced to provide the planarization layer 53 with a flatter and therefore more advantageous bonding surface. The substrate 55 can be bonded to the planarization layer 53 using an adhesive layer 51.

[0132] Fig. Figures 10A to 10E are cross-sectional diagrams showing the steps of main processes in a method for producing the in Fig. Figure 9 shows a light-emitting semiconductor device. The process can be considered a wafer-level process, and a substrate 11, which is in Fig. The part shown as 10A to 10E may be part of a wafer.

[0133] As in Fig. As shown in Figure 10A, an etch stop layer 52 is formed on a section of an upper surface of the semiconductor layer structure L, and then a second electrode 18 can be formed on a predominant part of the upper surface of the semiconductor layer structure L.

[0134] The etch stop layer 52 can be arranged on a region Ha of the semiconductor layer structure L in which a through hole H ( Fig. 10C) is to be formed before the second electrode 18 is formed. The etch stop layer 52 can have a larger area than the area exposed by the through-hole H. The etch stop layer 52 can be a material with high etch selectivity with respect to the second electrode 18. For example, if the second electrode 18 is ITO, the etch stop layer 52 can be SiO2.

[0135] As in Fig. As shown in Figure 10B, a planarization layer 53 can then be formed on the second electrode 18, and the support substrate 55 can be bonded to the planarization layer 53 using an adhesive layer 51.

[0136] The planarization layer 53 can provide a flat surface on the uneven surface of the second electrode 18 due to the etch stop layer 52, which is advantageous for the subsequent bonding process. In a flip-chip structure as in the exemplary embodiment, a translucent material, for example, various curable resins as well as silicon dioxide or silicon nitride, can be used as the planarization layer 53. After a material layer has been formed for planarization, a surface of the material layer can be planarized as required by performing a polishing process.

[0137] On the other hand, by selecting a material that can be bonded to the support substrate 55 as a component of the planarization layer 53, the support substrate 55 can be bonded directly to the planarization layer 53 without an additional adhesive layer.

[0138] As in Fig. As shown in 10C, the growth substrate 11 can be removed from the semiconductor layer structure L, and a through hole H can be formed in the semiconductor layer structure L.

[0139] In the substrate removal process, a high-resistance buffer layer 12 can be removed along with the substrate 11. During the through-hole formation process H, the etch depth can be properly controlled using the etch stop layer 52 to expose the second electrode 18 without significant damage. Given the variation in the etch depth of the semiconductor layer buildup L, the etch stop layer 52 can be provided with an appropriate thickness to protect the second electrode 18 while the semiconductor layer buildup L is being etched. After the semiconductor layer buildup L has been etched, the etch stop layer 52 (which is used to protect the second electrode 18 while the semiconductor layer buildup L is being etched) can be at least partially removed using a subsequent etching process. For example, if the second electrode 18 and the etch stop layer 52 are made of ITO and 52, respectively, the etch stop layer 52 can be removed using a subsequent etching process.SiO2 is formed, the second electrode 18, ITO, can have a thickness of 100 Å to 1000 Å, and the etch stop layer 52 can have a thickness of 100 Å to 1000 Å. The subsequent etching process to remove the etch stop layer 52 can be carried out using methods such as an etching process using a buffered oxide etch (BOE), in which high etch selectivity (e.g., 1:2) between two materials is ensured.

[0140] In the process, during the formation of the through-hole H, a device isolation device can also be exposed to form a device isolation trench ISO.

[0141] Then, as in Fig. As shown in Figure 10D, a connecting electrode 58 is formed in a contact area exposed by the through hole H, which is to be connected to the second electrode 18.

[0142] The connecting electrode 58 can be configured to extend to the first surface of the semiconductor layer structure L. A section of the connecting electrode 58 located on the first surface of the semiconductor layer structure L can be provided as a contact area. Using this process, both contact areas, relating to the first and second electrodes 17 and 18, can be formed on the first surface of the semiconductor layer structure L. More precisely, in this process, the insulating layer 56 can be formed on an inner sidewall of the through-hole H such that the connecting electrode 58 is not connected to the active layer 15 or the semiconductor layer 14 of the first conductivity type. Furthermore, the insulating layer 56 deposited in this process can be provided as a passivation layer on the other side of the light-emitting semiconductor device 50.

[0143] As in Fig. As shown in 10E, the light-emitting semiconductor device 50 can be separated by separating the in Fig. The resulting structure shown in 10D can be obtained in individual device units.

[0144] Fig. Figure 11 is a cross-sectional view showing a flip-chip mounted light-emitting semiconductor device according to an embodiment of the present disclosure.

[0145] As in Fig. As shown in Figure 11, a light-emitting flip-chip semiconductor device 60 according to the embodiment can have a semiconductor layer structure L, a first and a second electrode 17 and 18 and a support substrate 65.

[0146] In this embodiment, the first and second electrodes 17 and 18 can be arranged, similarly to the embodiments described above, on a first surface and a second surface that are opposite each other in the semiconductor layer structure L. The connecting electrode 68 can be electrically connected to the second electrode 18 via a through-hole H and extend to the first surface of the semiconductor layer structure L.

[0147] In this way, the light-emitting semiconductor device 60 can have a flip-chip structure that includes contact surface areas on the first surface of the semiconductor layer structure L, so that the first and second electrodes 17 and 18 can be connected to external circuits. Conductive contact bumps 34 can be provided as contact surface areas for the first electrode 17 and the connecting electrode 68, respectively. As shown in Fig. As shown in Figure 11, the light-emitting semiconductor device 60 can be connected to first and second circuit patterns 32a and 32b of a circuit substrate 31 using the conductive contact bumps 34.

[0148] In this embodiment, the first electrode 17 can have an electrode material with high reflectivity, which also forms an ohmic contact with a semiconductor layer 16 of a second conductivity type. In other embodiments, the first electrode 17 can have a structure that includes a translucent electrode. The second electrode 18 can be a translucent metal such as Ni / Au, or a transparent conductive oxide such as ITO, or a transparent conductive nitride. The support substrate 65 can be a glass substrate or a substrate formed from a translucent polymer resin.

[0149] The light-emitting semiconductor device 60 can further comprise an insulating element 63 surrounding the side surfaces S of the semiconductor layer structure L. The insulating element 63 can be provided on the second surface of the semiconductor layer structure L, that is, on the second electrode 18. According to the embodiment of this disclosure, the insulating element 63 can be a transparent material. The insulating element 63 can comprise a transparent material, for example, silicon dioxide, silicon nitride, or various curable resins. For example, the insulating element 63 can be TEOS, BPSG, SOG, or SOD. Such a material can be formed using a spin process or a reflow process to create a relatively flat top surface.An additional planarization process can be carried out such that the insulating element 63 has a planarized upper surface, which is advantageous for bonding to the support substrate, similar to the planarization layer described above. Furthermore, the insulating element 63 can serve as an electrode protection layer for the second electrode 18.

[0150] The insulating element 63 can be a material that can be bonded to the support substrate 65 to bond the semiconductor layer assembly L to the support substrate 65. For example, the insulating element 63 can be another translucent adhesive material, such as BCB, DFR, an epoxy, or a silicone resin. In some embodiments, the insulating element 63, which surrounds the side faces of the semiconductor layer assembly L, can be formed from a material that is used to form the support substrate 65 ( Fig. 15 and Fig. 16).

[0151] The insulating element 63 according to the exemplary embodiment can be provided as a passivation layer that protects the semiconductor layer structure L. In a subsequent process, a method for forming an additional passivation layer on the side surfaces of the semiconductor layer structure may be unnecessary in embodiments which include the insulating element 63.

[0152] To ensure a sufficient contact area for connecting the connecting electrode 68 to an external circuit, a contact area 68a, located on the first surface of the semiconductor layer structure L, can be extended to a section of the upper surface of the first electrode 17. An insulating layer 66 can have a section 66a that extends into a space between the extended contact area 68a and the first electrode 17, so that the extended contact area 68a and the first electrode 17 are not electrically connected to each other (see, for example, “I”).

[0153] The embodiment can be modified in various ways. For example, the light-emitting semiconductor device 60 can further have an etch stop layer on a section corresponding to the through-hole H, as described with reference to Fig. 6 or Fig. 9 has been described.

[0154] The in Fig. The light-emitting semiconductor device 60 shown in Figure 11 can be obtained by separating the semiconductor layer structure L into device units before removing a growth substrate and forming an insulating element 63 in a separate section. Processes are described in detail with reference to Fig. 12A to 12F described.

[0155] As in Fig. As shown in Figure 12A, a device isolation trench ISO can be formed in a semiconductor layer structure L that has been grown on a substrate 11.

[0156] As described in the above embodiments, a buffer layer 12 can be formed on the substrate 11, and the semiconductor layer structure L can be formed on the buffer layer 12. However, in this embodiment, unlike in the above embodiments, a process of separating the Fig. The devices shown in Figure 12A are used before the substrate 11 is removed. In this process, the device isolation trench ISO can be formed in the semiconductor layer structure L to separate the semiconductor layer structure L into individual device units. The process can be carried out by mechanical cutting, chemical etching, or dry etching using plasma. The semiconductor layer structure L can have an inclined side face, which depends on the type of crystal and the process (for example, the type of etching process) of the semiconductor layer structure L. For example, if the semiconductor layer structure L is a nitride semiconductor material, the side faces of the semiconductor layer structure L obtained after a dry etching process using plasma can be inclined sidewalls.

[0157] As in Fig. As shown in Figure 12B, a second electrode 18, which is connected to a semiconductor layer 16 of the second conductivity type, can then be formed on an upper surface (i.e. the second surface) of the semiconductor layer structure L.

[0158] The second electrode 18 can be configured to have a wide contact area with the semiconductor layer 16 of the second conductivity type. According to the exemplary embodiment, the second electrode 18 can be configured to cover the entire upper surface of the semiconductor layer 16 of the second conductivity type. The second electrode 18 can be a transparent conductive oxide or a transparent conductive nitride. For example, the transparent conductive oxide layer can be at least one of the following: ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In4Sn3O 12 , or Zn (1-x) Mg xO (0≥x≥1). In some embodiments, the second electrode 18 can include a translucent metal layer such as Ni / Au or graphene. In the exemplary embodiment, the process of forming the second electrode is carried out after the device insulation process. However, the process of forming the second electrode can be carried out before the device insulation process, and the second electrode 18 can be divided into device units during the device insulation process.

[0159] As in Fig. As shown in Figure 12C, an insulating element 63 can be applied to the semiconductor layer structure L, which has been divided into the device units, and a support substrate 65 can be applied to the insulating element 63.

[0160] The insulating element 63 can fill the device insulating trench ISO and cover the upper surface of the semiconductor layer structure L. According to the embodiment of this disclosure, the insulating element 63 can be a translucent material. For example, the insulating element 63 can be silicon dioxide, silicon nitride, or various curable resins. The process can be carried out using a spin process or a reflow process. For example, the insulating element 63 can be TEOS, BPSG, SOG, or SOD. If required, a process for planarizing the surface of the insulating element 63 can be additionally performed.

[0161] The support substrate 65 can be bonded to the planarization layer 63 using an additional adhesive layer. Alternatively, the insulating element 63 can be a material that can be bonded to the support substrate 65 to bond the semiconductor layer assembly L to the support substrate 65. For example, the insulating element 63 can be a different adhesive material, such as BCB, DFR, an epoxy, or a silicone resin.

[0162] As in Fig. As shown in Figure 12D, the growth substrate 11 can be removed from the semiconductor layer structure L, and a through hole H can be formed in the semiconductor layer structure L.

[0163] In this process, the buffer layer 12, which has a high electrical resistance, can be removed along with the substrate 11. The process of forming the through-hole H can be carried out by selectively removing the semiconductor layer structure L. This selective removal process can be performed by mechanical cutting, chemical etching, or dry etching using plasma. A section of the second electrode 18 can be exposed by the through-hole H formed in the process. The exposed section of the second electrode 18 can be designated as the contact area (region "C" in Figure 1). Fig. 12E) will be provided.

[0164] As in Fig. As shown in 12E, a connecting electrode 68 can then be formed in the contact area C, which is exposed by the through hole H in order to connect it to the second electrode 18.

[0165] The connecting electrode 68 can extend to the first surface of the semiconductor layer structure L. A section 68a of the connecting electrode 68, located on the first surface, can be provided as a contact area. The insulating layer 66 can be formed on an inner sidewall of the through-hole H and on a section of the first surface such that the connecting electrode 68 is not connected to the active layer 15 or the semiconductor layer 14 of the first conductivity type. By means of this process, both contact areas, relating to the first and second electrodes 17 and 18, can be formed on the first surface of the semiconductor layer structure L.

[0166] In this embodiment, the contact surface 68a of the connecting electrode 68 can extend to a section of the first electrode 17, and the insulating layer 66 can have a section 66a that extends to the first electrode 17, so that the contact surface 68a of the connecting electrode 68 is electrically isolated from the first electrode 17 (see region “I”). Furthermore, the insulating layer 66 deposited in this process can be provided on the other side of the light-emitting semiconductor device 60 as a passivation layer.

[0167] As in Fig. As shown in 12F, a preferred light-emitting semiconductor device 60 can be constructed by separating the components in Fig. The resulting structure shown in 12E can be obtained in individual device units.

[0168] Fig. Figure 13 is a cross-sectional view showing a flip-chip bonded light-emitting semiconductor device according to an embodiment of the present disclosure.

[0169] As in Fig. As shown in Figure 13, a light-emitting flip-chip semiconductor device 70 according to the embodiment of the present disclosure can have a semiconductor layer structure L, a first and a second electrode 17 and 18 and a support substrate 75.

[0170] In this embodiment, the first and second electrodes 17 and 18 can be arranged, similarly to the embodiments described above, on a first surface and a second surface that are opposite each other in the semiconductor layer structure L. The connecting electrode 78 can be connected to the second electrode 18, which is arranged on a second surface of the semiconductor layer structure L, such that it extends to the first electrode 17 of the semiconductor layer structure L. Unlike in the embodiments described above, the connecting electrode 78 according to this embodiment can be arranged on one (or more) side face(s) of the semiconductor layer structure L.The connecting electrode 78 can be divided into a first connecting electrode 78a, which is arranged on the side surface(s) and the second surface of the semiconductor layer structure L, and a second connecting electrode 78b, which is arranged on the first surface and serves as a contact point area. Thus, in the exemplary embodiment, a connecting electrode 78 can be formed using the side surfaces of the semiconductor layer structure L without the use of a through-hole.

[0171] To ensure a sufficient contact area for connecting the connection electrode 78 to an external circuit, the second connection electrode 78b, located on the first surface of the semiconductor layer structure L, can extend to a section of the upper / outer surface of the first electrode 17. The insulating layer 76 can be divided into a first insulating layer 76a, located on the side faces of the semiconductor material, and a second insulating layer 76b, located on the first surface of the semiconductor layer structure L. The first insulating layer 76a can prevent an unwanted connection between the first connection electrode 78a and the semiconductor layer structure L, and the second insulating layer 76b can prevent the second connection electrode 78b from being electrically connected to the first electrode 17 and to the semiconductor layer 14 of the first conductivity type (see region “I”).

[0172] In this way, the semiconductor layer structure 70 can have a flip-chip structure including contact surface areas for connecting the first and second electrodes 17 and 18 to external circuits on the first surface of the semiconductor layer structure L. Conductive contact bumps 34 can be provided as contact surface areas for the first electrode 17 and the connecting electrode 78, respectively. As shown in Fig. As shown in Figure 13, the light-emitting semiconductor device 70 can be connected to first and second circuit patterns 32a and 32b of a circuit substrate 31 using the conductive contact bumps 34.

[0173] The light-emitting semiconductor device 70 can further comprise an insulating element 73 that surrounds the side surface S of the semiconductor layer structure L. The insulating element 73 can also be provided for covering the second surface of the semiconductor layer structure L, i.e., the second electrode 18. The insulating element 73 according to the exemplary embodiment can be compared to the insulating element 63, which in the above embodiment is referred to in Fig. 11, as described, be the same or similar.

[0174] A method for producing the in Fig. The light-emitting semiconductor device 70 shown in 13 can be described with reference to Fig. 14A and Fig. 14E will be described.

[0175] As in Fig. As shown in Figure 14A, a first insulating layer 76a can be formed on side surfaces of a semiconductor layer structure L, which is divided into device units (e.g. divided by a device insulating trench ISO).

[0176] A process for forming the first insulating layer 76a can be understood as one that follows a device isolation process of the semiconductor layer build-up L (see Fig. 12A) and a process for forming the second electrode (see Fig. 12B). The first insulating layer 76a can be applied to an entire first surface of the semiconductor layer structure L, which has been divided into the device units, and then selectively removed from an upper surface of the second electrode 18 and a contact area C' of a device insulating region.

[0177] As in Fig. As shown in 14B, a first connecting electrode 78a can then be formed on the side surfaces of the semiconductor layer structure L.

[0178] The first connecting electrode 78a can be connected to the second electrode 18, which is arranged on a second surface of the semiconductor layer structure L, and can extend along the side faces of the semiconductor layer structure L to the contact area C' located between the semiconductor layer structures L. The first connecting electrode 78a can be formed on the first insulating layer 76 to cover at least a portion of the first insulating layer 76, as shown in Fig. 14B is shown.

[0179] As in Fig. As shown in Figure 14C, an insulating element 73 can be formed on the semiconductor layer structure L, which has been divided into the device units, and a support substrate 75 can be formed on the insulating element 73.

[0180] Similar to the embodiment described above, the insulating element 73 can fill a device insulating trench ISO and cover an upper surface of the semiconductor layer structure L. A process for bonding the support substrate 75 can be carried out using an additional adhesive layer. However, the insulating element 73 itself can be formed from a material that can be bonded to the support substrate 75, if necessary.

[0181] Then, as in Fig. As shown in Figure 14D, a growth substrate 11 is removed from the semiconductor layer structure L, and a first electrode 17 and a second connecting electrode 78b can be formed on the first surface of the semiconductor layer structure L.

[0182] In this process, a high-resistance buffer layer 12 can be removed along with the growth substrate 11 to expose the second surface (i.e., a first-conductivity semiconductor layer 14) of the semiconductor layer structure L. The first electrode 17 can be positioned on the second surface of the semiconductor layer structure L to be connected to the first-conductivity semiconductor layer 14. In the flip-chip structure according to the embodiment of the present disclosure, the first electrode 17 can have a high-reflectivity structure that establishes an ohmic contact. After forming the first electrode 17, the second insulating layer 76b and the second connecting electrode 78b can then be formed. During the removal of the growth substrate 11, a section of the first connecting electrode 78b, located in the contact region C', can be exposed.Although it is possible that only the exposed portion of the first connecting electrode 78a is provided as the contact area, a second connecting electrode 78b can additionally be formed to ensure a sufficient contact area, as in the exemplary embodiment. The second connecting electrode 78b can be arranged on the first surface of the semiconductor layer structure L to be connected to the exposed portion of the first connecting electrode 78a; as shown in the exemplary embodiment, the second connecting electrode 78b can also extend so far as to overlap a portion of the first electrode 17 to further enlarge the contact area.

[0183] As in Fig. As shown in 14E, it can then be separated by separating the parts in Fig. The resulting structure shown in 14D is obtained in individual device units, the light-emitting semiconductor device 70.

[0184] Fig. Figure 15 is a cross-sectional view showing a flip-chip bonded light-emitting semiconductor device according to an embodiment of the present disclosure.

[0185] A light-emitting semiconductor device 80, which is in Fig. Figure 15 shows that it can have the same electrode structure as the one shown in Fig. Figure 13 shows a light-emitting semiconductor device 70. Unlike the embodiments described above, however, a support substrate according to the exemplary embodiment can be a support substrate 85 formed from a light-transmitting resin containing a wavelength conversion material P, for example, a phosphor or a quantum dot. A curable resin such as a silicone resin or an epoxy resin can be used as the light-transmitting resin. In the embodiments described above, the process of Fig. 14C is replaced by a process in which a translucent liquid resin mixed with the wavelength conversion material P is applied to the semiconductor layer structure L and cured to achieve the in Fig. Figure 15 shows the light-emitting semiconductor device 80. The support 85 according to the exemplary embodiment can replace other support substrates described in the embodiments described above. Such a support 85 can be bonded to the second electrode 18 without an additional adhesive layer.

[0186] Furthermore, the carrier 85 can be pre-shaped and applied to the semiconductor layer structure L in a hardened or semi-hardened state, instead of applying the liquid resin to the semiconductor layer structure L, as in this embodiment.

[0187] The support 85 is shown as a polymer-based resin, but another translucent material such as glass can also be used. For example, in the case of a glass substrate, a glass substrate containing a phosphor can be manufactured by mixing a wavelength conversion material P, for example a phosphor, into a glass composition and sintering it at a low temperature.

[0188] The phosphor or quantum dot (QD) used in the exemplary embodiment can have various compositions and wavelength properties. A ceramic phosphor, for example an oxide group, a silicate group, a nitride group, or a fluoride group, can be used. - Oxide group yellow and green: Y3Al5O 12 :Ce, Tb3Al5O 12 :Ce, Lu3Al5O 12 :Ce - Silicate group yellow and green: (Ba,Sr)2SiO4:Eu, yellow and orange: (Ba,Sr)3SiO5:Ce - Nitride group green: β-SiAlON:Eu, yellow: La3Si6N 11 :Ce, orange: α-SiAlON:Eu, red CaAlSiN3:Eu, Sr2Si5N8:Eu, SrSiAl4N7:Eu, SrLiAl3N4:Eu, Ln 4-x (eu z M 1-z ) x Si 12- y Al y O 3+x+y N 18-x-y (0.5≥x≥3, 0 <z<0,3 und 0<y≥4) (Ln ist hierbei mindestens ein Element, das ausgewählt ist aus der Gruppe bestehend aus einem Element der Gruppe IIIa und einem Seltenerdelement, und M ist mindestens ein Element, das ausgewählt ist aus der Gruppe bestehend aus Ca, Ba, Sr und Mg). - Fluoride group: KSF-based, red: K2SiF6:Mn 4+ , K2TiF6:Mn 4+ , NaYF4:Mn 4+ , NaGdF4:Mn 4+

[0189] The composition of the phosphor can be stoichiometric, and each element can be replaced by another element within a corresponding group of the periodic table. For example, Sr can be replaced by Ba, Ca, or Mg in the alkaline earth (II) group, and Y can be replaced by Tb, Lu, Sc, or Gd in the lanthanide group. Furthermore, an activator, Eu, can be replaced by Ce, Tb, Pr, Er, or Yb, depending on a preferred energy level. The activator can be used alone, or a coactivator can be added to modify its properties.

[0190] Furthermore, a quantum dot can replace the phosphor, or the phosphor and the quantum dot can be used alone or as a mixture.

[0191] The quantum dot can have a structure consisting of a core, such as CdSe or InP (3 to 10 nm), a shell, such as ZnS or ZnSe (0.5 to 2 nm), and a ligand to stabilize the core and shell. Furthermore, the quantum dot can implement different colors depending on its size.

[0192] Table 1 below shows different types of phosphors for a white light emitting device using a UV LED chip (200 to 440 nm) or a blue LED chip (440 to 480 nm), listed by application. [Table 1] Zweck Leuchtstoff LED TV BLU β-SiAlON:Eu 2+ , (Ca,Sr)AlSiN3:Eu 2+ , La3Si6N 11 :Ce 3+ ,K2SiF6:Mn 4+ , SrLiAl3N4:Eu, Ln 4-x (Eu z M 1-z ) x Si 12-y Al y ABOUT 3+x+y N 18-x-y (0.5≥x≥3, 0 <z<0,3 und 0<y≥4), K2TiF6:Mn 4+ , NaYF4:Mn 4+ ,NaGdF4:Mn 4+ Beleuchtung Lu3Al5O 12 :What 3+ , Ca-α-SiAlON:Iu 2+ , La3Si6N 11 :What 3+ , (Ca,Sr)AlSiN3:I 2+ , Y3Al5O 12 :What 3+ , K2SiF6:Mn 4+ , SrLiAl3N4:Iu, Ln 4- x (Eu z M 1-z ) x Si 12-y Al y O 3+x+y N 18-x-y (0.5≥x≥3, 0 <z<0,3, and 0<y≥4),K2TiF6:Mn 4+ , NaYF4:Mn 4+ , NaGdF4:Mn 4+ Seitenansicht(Mobiltelefon,Notebook) Lu3Al5O 12 :What 3+ , Ca-α-SiAlON:Iu 2+ , La3Si6N 11 :What 3+ , (Ca,Sr)AlSiN3:I 2+ , Y3Al5O 12 :What 3+ , (Sr, Ba, Ca, Mg)2SiO4:Iu 2+ ,K2SiF6:Mn 4+ , SrLiAl3N4:Iu, Ln 4-x (I z M 1-z ) x And 12-y the y A 3+x+y N 18-x-y (0.5≥x≥3, 0 <z<0,3 und 0<y≥4), K2TiF6:Mn 4+ , NaYF4:Mn 4+ ,NaGdF4:Mn 4+ Elektronik(Scheinwerferusw.) Lu3Al5O 12 :What 3+ , Ca-α-SiAlON:Iu 2+ , La3Si6N 11 :What 3+ , (Ca,Sr)AlSiN3:I 2+ , Y3Al5O 12 :What 3+ , K2SiF6:Mn 4+ , SrLiAl3N4:Iu, Ln 4-x (I z M 1-z ) x And 12-y the y A 3+x+y N 18-x-y (0.5≥x≥3, 0 <z<0,3 und 0<y≥4),K2TiF6:Mn 4+ , NaYF4:Mn 4+ , NaGdF4:Mn 4+

[0193] Thus, various types of wavelength conversion materials, such as phosphors or quantum dots, can be used to convert light emitted from the active layer. Furthermore, white light can be implemented as the ultimately emitted light using the wavelength conversion material. The embodiment is shown in a chip-based implementation, but can also be implemented at a package level including the chip (see Fig. 26 and Fig. 27).

[0194] Fig. Figures 16A to 16C are cross-sectional views illustrating flip-chip bonded light-emitting semiconductor devices according to various embodiments of the present disclosure.

[0195] Light-emitting semiconductor devices (10a, 10b and 10c) that are in Fig. Figures 16A to 16C are examples where textured structures are introduced at various locations in interfaces to improve light extraction efficiency. Note that some designs of the light-emitting semiconductor devices differ from those shown in Fig. The light-emitting semiconductor device shown in section 4 has been modified.

[0196] A light-emitting semiconductor device 10a, which is in Fig. As shown in Figure 16A, a support substrate 25' can have a light-emitting surface on which a texture T1 is formed. The texture T1 of the support substrate 25' can be formed before or after bonding the support substrate 25' to a semiconductor layer structure L.

[0197] A light-emitting semiconductor device 10b, which is in Fig. As shown in Figure 16B, a support substrate 25'' and an adhesive layer 21' that bonds to the support substrate 25'' can be included. A texture T2 to improve light extraction efficiency can be provided for an interface between the support substrate 25'' and the adhesive layer 21'. That is, the texture T2 can be pre-formed on a bonding surface of the support substrate 25'', and then the support substrate 25'' is bonded to the adhesive layer 21' before the adhesive layer 21' is cured.

[0198] A light-emitting semiconductor device 10c, which is in Fig. As shown in Figure 16C, a texture T3 can be present on an interface between a first electrode 17c, which is designated as a reflective electrode, and the semiconductor layer 14 of the first conductivity type. Such a structure can be formed by forming the texture T3 on a surface of the semiconductor layer 14' of the first conductivity type and depositing the first electrode 17c thereon. The texture T3 of the semiconductor layer 14' of the first conductivity type can be formed during a process of separating a growth substrate or by an additional etching process after the separation of the growth substrate.

[0199] In addition to the textures described in the embodiments described above, a texture can be introduced into an interface between the two layers, which have different refractive indices. If, for example, the second electrode 18 is a transparent electrode, such as ITO, the texture can additionally be introduced into a surface of the transparent electrode (e.g., a surface common to the second electrode 18 and the semiconductor layer 16 of the second conductivity type).

[0200] Although the embodiments described above describe light-emitting flip-chip semiconductor devices, the concept of the invention can be implemented in a chip structure (with wire bonding structure) in which a support substrate provides a mounting surface. Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. Figure 21 are cross-sectional views illustrating light-emitting semiconductor devices according to various embodiments of the present disclosure.

[0201] As in Fig. As shown in Figure 17, a light-emitting semiconductor device 10' can have a similar structure to that shown in Figure 17. Fig. 1. Light-emitting semiconductor device 10 shown, except that an electrode arrangement on a first surface of the semiconductor layer structure L is different. The electrode arrangement according to the embodiment of the present disclosure can be modified to couple light out easily through the first surface. The first electrode 17' can be formed on a section of the first surface of the semiconductor layer structure L, and a section of the connecting electrode 28' arranged on the first surface can be smaller than the contact area of ​​the electrode 10 shown in the illustration. Fig. 1 shown connection electrode 28.

[0202] In this embodiment, the second electrode 18 can be a translucent electrode such as ITO, and the support substrate 25 can be a translucent substrate, for example, a glass substrate. In this case, light emitted by the light-emitting semiconductor device 10' can be coupled out from side surfaces of the device as well as from a top surface of the device (i.e., from the first surface of the semiconductor layer structure L). Alternatively, the second electrode 18 can be designed with a high reflectivity electrode. For example, the second electrode 18 can contain Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, or Au. In this case, an opaque substrate can be used as the support substrate 25.

[0203] A method for manufacturing a light-emitting semiconductor device according to the embodiment of the present disclosure can be described with reference to Fig. 5A to 5G can be described as above. However, the process can be described with respect to the electrode arrangement on the first surface (see Fig. 5F) into a process of implementing the in Fig. The electrode arrangement shown in 17 can be modified.

[0204] Light-emitting semiconductor devices 40' and 50', which are in Fig. 18 and Fig. Figure 19 shows examples in which an etch stop layer is used and exhibits similar structures to the light-emitting semiconductor devices 40 and 50, respectively, which are shown in Figure 19. Fig. 6 and Fig. 9 are shown, except that the electrode arrangement on the first surface of the semiconductor layer structure L is different.

[0205] Similarly, light-emitting semiconductor devices 60' and 70', which are in Fig. 20 and Fig. Figure 21 shows examples in which a device isolation process is applied before the substrate is removed, and they have a similar structure to the light-emitting semiconductor devices 60 and 70, respectively, shown in Figure 21. Fig. 11 and Fig. Figure 13 are shown, except that the electrode arrangement on the first surface of the semiconductor layer structure L is different.

[0206] The electrode arrangement, which is in the Fig. 18, Fig. 19, Fig. 20 to Fig. 21 light-emitting semiconductor devices are used, which in the embodiment described above with reference to Fig. The devices described in section 17 can be modified so that light is readily coupled through the first surface. The first electrode 17' can be formed on only a portion of the first surface of the semiconductor layer structure L, and a portion of the connecting electrode located on the first surface can have a relatively smaller area. Processes for fabricating the light-emitting semiconductor devices according to the devices described with reference to Fig. 17, Fig. 18, Fig. 19, Fig. 20 to Fig. The exemplary embodiments described in 21 can be used to describe the processes for manufacturing the corresponding products, with reference to Fig. 1, Fig. 6, Fig. 9, Fig. 11 and Fig. 13 described light-emitting semiconductor devices, with the exception of the process with respect to the electrode arrangement on the first surface.

[0207] Fig. Figures 22A to 22F are cross-sectional views showing the main processes in a method for manufacturing a light-emitting semiconductor device, and Fig. 23A to 23D are top views showing mask patterns used in the respective processes.

[0208] As in Fig. As shown in Figure 22A, a metal electrode 102 can first be formed on a second electrode 18, which is arranged on a semiconductor layer structure L. In this process, the metal electrode 102 can be formed such that it is deposited in an area from which the semiconductor layer structure L is to be removed in the subsequent process. The etch stop layer 102 can be a material with high etch selectivity with respect to the second electrode 18. For example, the second electrode 18 can be a transparent electrode, such as ITO. The metal electrode 102 can be a metallic material such as Al, Au, Ag, Ti, or TiW.

[0209] An M1 mask, which is in Fig. Figure 23A is an example of a mask available for use in the electrode training process. As shown in Fig. As shown in Figure 23A, the mask M1 can have not only a pattern 102' for the metal electrode 102, but also a pattern 104' for a plurality of finger electrodes extending from the metal electrode pattern 102'. The plurality of finger electrodes can ensure a uniform current distribution in the device. The plurality of finger electrodes can be deposited using the same material used to form the metal electrode 102.

[0210] As in Fig. As shown in 22B, a support substrate 105 can then be formed on the second electrode 18, on which the metal electrode 102 is arranged.

[0211] The process can involve forming a planarization layer 103 on the second electrode 18 and bonding the support substrate 105 to the planarization layer 103.

[0212] As illustrated in the exemplary embodiment, the planarization layer 103 can eliminate any unevenness caused by the metal electrode 102 and provide a flat surface, which is advantageous for a subsequent bonding process. The planarization layer 103 can be a translucent material, such as silicon dioxide, silicon nitride, or various curable resins. For example, the planarization layer 103 can be TEOS, BPSG, SOG, or SOD. Since such a material is fluid during processing, a relatively flat surface can be provided by means of a spin process or a reflow process. Alternatively, or in combination with these methods, the planarization layer 103 can be obtained by forming a material layer for planarization and then planarizing a surface on it using a polishing process.

[0213] The carrier substrate 105 shown in this process is bonded directly to the planarization layer 103 without an additional adhesive layer. However, the carrier substrate 105 can be bonded to the planarization layer 103 using an additional adhesive layer if required.

[0214] As in Fig. As shown in 22C, the growth substrate 11 can then be removed from the semiconductor layer structure L, and a texture T can be formed on the first surface of the semiconductor layer structure L.

[0215] The process of removing the growth substrate 11 can be carried out using a laser removal process, a mechanical polishing process, or a chemical etching process. In this process, a buffer layer 12 with high electrical resistance can be removed along with the growth substrate 11. The removal process exposes the first surface of the semiconductor layer structure L, that is, a surface of the semiconductor layer 14 of the first conductivity type. The texture T can be formed on the surface of the semiconductor layer 14 of the first conductivity type.

[0216] An M2 mask, which is in Fig. Figure 23B is an example of a mask that can be used in the texture formation process. Reference is made to Figure 22C, which shows that a mask M2 can have a pattern for removing the texture from electrode formation areas P1 and P1' after forming the texture T on the first surface of the semiconductor layer buildup L. Furthermore, in this process, the mask M2 can have an additional pattern for removing the texture from a boundary region P2. The mask M2 can have electrode formation areas P1 and P1', and the electrode formation areas P1 and P1' can have a contact point formation area P1 and two finger electrode formation areas P1' extending from it. As in the exemplary embodiment, the two finger electrode formation areas P1' can be arranged such that they form the Fig. The finger electrode pattern shown in Figure 23A should not overlap 102' to avoid current compression.

[0217] As in Fig. As shown in 22D, a fixture isolation trench ISO can then be formed to divide the semiconductor layer structure L into individual fixture units.

[0218] Through this process, a section of the semiconductor layer structure L can be removed to expose a section of the metal electrode 102. That is, one section of the metal electrode 102 can be exposed, and another section of the metal electrode 102 can maintain the state of connection (and direct contact) with the second electrode 18. One section of the metal electrode 102 can be provided as a contact point training area. A mask M3, which is in Fig. As shown in Figure 23C, it can have open areas P2' for forming the device insulating trench ISO and contact areas at both corners.

[0219] In this embodiment, the metal electrode 102 has a lower etch rate compared to the second electrode 18, and therefore the metal electrode 102 can be stably and reliably provided for the area where the semiconductor layer structure L is removed, even if the second electrode 18 has a small thickness. One surface of the metal electrode 102 can have a section that is connected to the second electrode, and the other surface of the metal electrode 102 can be in a state where it is buried in the support substrate (in this embodiment, in the planarization layer 103).

[0220] As in Fig. As shown in Figure 22E, a first and a second contact point 107 and 108 can each be formed on a section of the semiconductor layer 14 of the first conductivity type and on the metal electrode 102, which is arranged (and exposed) in the contact area where a contact point is to be formed.

[0221] The M4 mask, which is available in the process of forming an electrode contact point, is in Fig. The mask M4 is shown in 23D. It can have a pattern P1 for the first electrode contact point 107 and pattern P1 for the second electrode contact point 108. Furthermore, the mask M4 can have the finger electrode patterns P1' extending from the contact point pattern P1 of the first electrode. The first electrode contact point 107 and the finger electrodes extending from it can be formed on sections of the semiconductor layer 14 of the first conductivity type using the mask M4, and the second electrode contact point 108 can be formed in a region of the metal electrode 102 that lies within the contact area.

[0222] As in Fig. As shown in 22F, a preferred light-emitting semiconductor device 100 can be formed by dividing the Fig. The structure shown in 22E can be obtained in individual device units.

[0223] In the Fig. In the light-emitting semiconductor device 100 shown in Figure 22F, the upper surface of the support substrate 105 (and / or an upper surface provided by the planarization layer 103) can be divided into a first region, which provides the contact area C, and a second region, in which the semiconductor layer structure L is located. The first electrode contact point 107 can be arranged on the semiconductor layer of the first conductivity type (14). The second electrode 18, which is arranged between the semiconductor layer 16 of the second conductivity type and the support substrate 105, can extend into the first region to provide an electrode contact point. In the exemplary embodiment, the second electrode 18 can be removed in the first region to expose the metal electrode 102, but this is not a limitation. Sections of the second electrode 18 may remain in the first region depending on the progress of the etching process.

[0224] In this embodiment, the support substrate 105 can comprise a translucent substrate, and the second electrode 18 can comprise a translucent electrode. The second electrode 18 can have a translucent electrode arranged between the semiconductor layer 16 of the second conductivity type and the support substrate 105, a metal electrode 102 arranged in the first region and connected to the translucent electrode, and a second electrode contact point 108 arranged on the metal electrode 102.

[0225] The present invention can be applied not only to a light-emitting semiconductor device with a flip-chip structure, but also to a light-emitting semiconductor device with a structure having a mounting direction opposite to the flip-chip structure, i.e., a structure in which the semiconductor layer structure L is oriented upwards.

[0226] Fig. Figures 24A to 24F are cross-sectional views showing the main processes in a method for manufacturing a light-emitting semiconductor device, and Fig. Figures 25A to 25D are cross-sectional views showing various examples of a buffer structure that can be used in an embodiment of the present disclosure.

[0227] As in Fig. As shown in Figure 24A, a semiconductor layer structure L can be formed for a plurality of light-emitting devices on a growth substrate 11.

[0228] The semiconductor layer structure L can comprise a semiconductor layer 14 of a first conductivity type, an active layer 15, and a semiconductor layer 16 of a second conductivity type. The growth substrate 11 can be sapphire, SiC, Si, MgAl₂O₄, MgO, LiAlO₂, LiGaO₂, or GaN. The semiconductor layer structure L can be a nitride semiconductor material. The semiconductor layer structure L can be formed on a buffer layer 12 arranged on the substrate 11.

[0229] As in Fig. As shown in Figure 24B, an upper surface of the semiconductor layer structure L (i.e., a second surface) can then be bonded to a temporary substrate 111, and the growth substrate 11 can be removed.

[0230] Various types of supports can be used as the temporary substrate 111, and the semiconductor layer assembly L can be bonded to the temporary substrate 111 using an adhesive material. A process for removing the growth substrate 11 can be carried out in the state where bonding to the temporary substrate 111 has occurred (e.g., after the semiconductor layer assembly L has been bonded to the temporary substrate 111). Various methods can be used with reference to Fig. The removal processes described in 5D can be used.

[0231] As in Fig. As shown in 24C, a support substrate 115 can then be bonded to a lower surface of the semiconductor layer structure L (i.e., a first surface), and the temporary substrate 11 can be removed from the semiconductor layer structure L.

[0232] The support substrate 115 can comprise a glass substrate. As in the exemplary embodiment, the support substrate can be bonded using an adhesive layer 113. For example, the bonding process can be carried out by coating the lower surface of the semiconductor layer structure L with an adhesive material such as BCB using a process such as spin coating, bonding the glass substrate, and performing a heat treatment. Various forms of the Fig. The bonding processes described in Section 5C can be used. If required, a planarization process can be additionally introduced on the lower surface of the semiconductor layer assembly L before the adhesive layer 113 is applied. The temporary substrate 111 can be removed in a state where the semiconductor layer assembly L has already been bonded to the support substrate 115. As described above, if the semiconductor layer assembly L is bonded to the temporary substrate 111 using adhesive, the temporary substrate 111 can be removed from the semiconductor layer assembly L by a simple heat treatment process.

[0233] As in Fig. As shown in 24D, a second electrode 118, which is connected to the semiconductor layer 16 of the second conductivity type, can then be formed on the upper surface of the semiconductor layer structure L (i.e. the second surface).

[0234] The second electrode 118 can be a translucent electrode, such as ITO. The second electrode 118 can be formed on the entire upper surface of the semiconductor layer 16 of the second conductivity type to obtain a wide contact area with the semiconductor layer 16 of the second conductivity type.

[0235] As in Fig. As shown in 24E, sections of the semiconductor layer 16 of the second conductivity type and the active layer 15 can then be removed to expose a section ME of the semiconductor layer 14 of the first conductivity type.

[0236] The process can be carried out by selectively removing sections of the semiconductor layer structure L. This selective removal can be performed using mechanical cutting, chemical etching, or dry etching with plasma.

[0237] As in Fig. As shown in Figure 24F, a first and a second electrode contact point 119a and 119b can each be formed on the exposed section ME of the semiconductor layer 14 of the first conductivity type and on the semiconductor layer 16 of the second conductivity type.

[0238] The growth substrate used in the embodiments described above can be a silicon substrate. In the case of the silicon substrate, the buffer layer 12 can have various structures. If the silicon substrate is used as the growth substrate 11 for a single-crystal nitride, a (111) plane of silicon can be used as the crystal growth plane, and the buffer layer 12 can have an AlN nucleation layer and a lattice buffer layer formed from an Al-containing nitride crystal. In addition to the buffer layer 12, an additional stress-equalizing layer can be used to compensate for stresses caused by a difference in the coefficient of thermal expansion between the silicon substrate and the single-crystal nitride.

[0239] Fig. Figures 25A to 25D are cross-sectional views showing various examples of a buffer layer and a voltage equalization layer that can be used in a process of growing a nitride semiconductor material using a silicon substrate.

[0240] As in Fig. As shown in Figure 25A, a buffer layer 210, a voltage equalization layer 220 and a nitride semiconductor layer structure L can be arranged successively on a silicon substrate 201.

[0241] The silicon substrate 201 can be a substrate composed entirely of silicon material, or a substrate that partially contains silicon material. For example, a silicon-on-insulator (SOI) substrate can be used. An upper surface of the silicon substrate 201 can be a (111) plane.

[0242] The buffer layer 210 can include a nucleation layer 212 arranged on the silicon substrate 201 and a lattice buffer layer 214 arranged on the nucleation layer 212. The nucleation layer 212 can be AlN. The nucleation layer 212 can be designed to prevent remelting. Furthermore, the nucleation layer 212 can provide a growth plane with improved wettability to promote crystal growth. For example, the nucleation layer 212 can have a size ranging from a few dozen nanometers to several hundred nanometers (e.g., 10⁻⁹ nm).

[0243] The lattice buffer layer 214 can bend dislocation lines to reduce defects. Increasing the thickness of the lattice buffer layer 214 can reduce pressure stress relaxation in a first nitride semiconductor layer 221, which is grown in a subsequent process, and also reduce defects. The thickness of the lattice buffer layer 214 can range from several hundred nanometers to several micrometers.

[0244] The grid buffer layer 214 can have the same composition across its entire thickness. As in Fig. As shown in 25A, the grid buffer layer 214 can, however, be a graded layer of Al x In y Ga 1-x-yN (0≥x, y≥1 and x+y≥1). The graded structure according to the embodiment of the present disclosure can have a plurality of layers 214-1, 214-2, ... and 214-n, and the plurality of layers 214-1, 214-2, ... and 214-n can have a stepwise graded structure in which the Al composition gradually decreases from layer 214-1 to layer 214-n. In some embodiments, the lattice buffer layer 214 with the graded structure can be implemented in a ternary AlGaN in which the Al composition is controlled. In other embodiments, the lattice buffer layer 214 need not have a stepwise graded structure, but can instead have a linearly graded structure in which the Al composition is gradually (e.g., linearly) decreased by the thickness of the layer 214.

[0245] Such a lattice buffer layer 214 can gradually reduce a lattice mismatch between the AlN nucleation layer 212 and the first nitride semiconductor layer 221. In particular, by efficiently generating compressive stress during grain growth, the lattice buffer layer 214 can reduce tensile stress generated during cooling.

[0246] The voltage-equalizing layer 220 can comprise a first nitride semiconductor layer 221, an intermediate layer 222, and a second nitride semiconductor layer 223, which are stacked sequentially onto the lattice buffer layer 214. The first nitride semiconductor layer 221 can be a nitride crystal with a larger lattice constant than the lattice buffer layer 214. The first nitride semiconductor layer 221 can be Al x In y Ga 1-x-yN (0≥x, y≥1 and x+y<1), for example GaN. The first nitride semiconductor layer 221 can withstand a compressive stress at an interface with the lattice buffer layer 214.

[0247] The compressive stress can be reduced as the thickness of the first nitride semiconductor layer 221 increases. However, if the thickness of the first nitride semiconductor layer 221 exceeds a threshold value (e.g., greater than approximately 2 µm), it becomes difficult to suppress the tensile stress generated by the difference in the coefficient of thermal expansion between the substrate 201 and the first nitride semiconductor layer 221 as it cools to room temperature after the growth process is complete, and cracking may even occur.

[0248] The intermediate layer 222 can be arranged on the first nitride semiconductor layer 221 to compensate for the tensile stress generated during cooling. The intermediate layer 222 can be a nitride crystal with a smaller lattice constant than the first nitride semiconductor layer 221. For example, the intermediate layer 222 can be Al x G a1-x N (0.4 <x<1) sein.

[0249] The second nitride semiconductor layer 223 can be arranged on the intermediate layer 222. The second nitride semiconductor layer 223 can exhibit compressive stress. The compressive stress of the second nitride semiconductor layer 223 can compensate for a relatively weak compressive or tensile stress applied to the first nitride semiconductor layer 221 to suppress cracking. The second nitride semiconductor layer 223 can be Al x In y Ga 1-x-yN (0≥x, y≥1 and x+y<1) include, similar to the first nitride semiconductor layer 221. For example, the second nitride semiconductor layer 223 can be GaN. At least one of the first and second nitride semiconductor layers 221 and 223 can be an undoped nitride layer, but this is not a restriction. The nitride semiconductor layer structure L can be the semiconductor layer structure L described in the embodiments above.

[0250] It will be on Fig. Reference is made to Figure 25B, which shows a buffer layer 210, a voltage equalization layer 220 and a nitride semiconductor layer structure L arranged sequentially on a silicon substrate 201, similar to the figure shown in Figure 25B. Fig. 25A.

[0251] The buffer layer 210 can have an AlN nucleation layer 212 and a lattice buffer layer 214', similar to the buffer layer 210 described in Fig. 25A. However, according to this embodiment, the grid buffer layer 214' can have a different structure than the grid buffer layer 214 of the buffer layer 210 shown in Fig. 25A is shown.

[0252] The lattice buffer layer 214' can have a superlattice structure in which two or more layers 214a and 214b, having different compositions, are stacked alternately. For example, the lattice buffer layer 214' can be a superlattice layer made of Al x1 In y1 Ga 1-x1-y1 N / Al x2 In y2 Ga 1-x2-y2 N (0≥x1, x2, y1, y2≥1, x1≠x2 or y1≠y2, x1+y1≥1 and x2+y2≥1). As in the exemplary embodiment, the lattice buffer layer 214', which has the superlattice structure, can also cancel the stress between the silicon substrate 201 and the first nitride semiconductor layer 221.

[0253] The voltage equalization layer 220 according to the embodiment of the present disclosure can further be added to the first and second nitride semiconductor layers 221 and 223 and the first intermediate layer 222 arranged between them, as with reference to Fig. 25A shows a second intermediate layer 224 and a third nitride semiconductor layer 225.

[0254] The second interlayer 224 and the third nitride semiconductor layer 225 can perform a similar function to the first interlayer 222 and the second nitride semiconductor layer 223. That is, the second interlayer 224 can be placed on top of the second nitride semiconductor layer 223 to compensate for tensile stress during cooling. The second interlayer 224 can be a nitride crystal with a smaller lattice constant than the second nitride semiconductor layer 223. For example, the second interlayer 224 can be Al x Ga 1-xN (0.4 <x<1) sein, ähnlich wie die erste Zwischenschicht 222.

[0255] The third nitride semiconductor layer 225 can be arranged on the second intermediate layer 224. The third nitride semiconductor layer 225 can exhibit compressive stress, and such compressive stress of the third nitride semiconductor layer 225 can compensate for a relatively weak compressive or tensile stress applied to the first and second nitride semiconductor layers 221 and 223 (especially to 223) in order to suppress cracking.

[0256] The third nitride semiconductor layer 225 can Al x In y Ga 1-x-y N (0≥x, y≥1 and x+y<1) include, similar to the second nitride semiconductor layer 223. For example, the third nitride semiconductor layer can be 225 GaN.

[0257] It will be on Fig. Reference is made to Figure 25C, which shows that a buffer layer 210, a voltage equalization layer 220 and a nitride semiconductor layer structure L are arranged sequentially on a silicon substrate 201, similar to the figure shown in Figure 25C. Fig. 25A. However, unlike in the one in Fig. The example shown in Figure 25A further includes a mask layer 226 and a coalesced nitride layer 227 formed on the mask layer 226.

[0258] The mask layer 226 can be arranged on the first nitride semiconductor layer 221.

[0259] Most of the dislocation lines in the first nitride semiconductor layer 221 can be blocked by the mask layer 226, and the remaining dislocation lines can be bent by the subsequently grown, coalesced nitride layer 227. As a result, the defect density of the subsequently grown coalesced nitride layer 227 can be significantly reduced. The thickness and defect density of the coalesced nitride layer 227 can vary depending on the growth conditions, such as temperature, pressure, and the molar composition ratio of V / III sources.

[0260] The mask layer 226 can be made of silicon nitride (SiN₂). x ) or titanium nitride (TiN). For example, a SiN xA mask layer is formed using silane (SiH4) and ammonia gas. The mask layer 226 does not need to completely cover the surface of the first nitride semiconductor layer 221. Thus, depending on the degree of coverage of the first nitride semiconductor layer 221 by the mask layer 226, an exposed area of ​​the first nitride semiconductor layer 221 can be determined, and the morphology of the initially existing islands of the nitride crystal grown on it can change. If the exposed area of ​​the nitride semiconductor layer is increased by enlarging a region of the SiN x If the mask layer is reduced, the density of the initially present islands of the coalesced nitride layer 227, which is grown on the mask layer 226, can be reduced, but the size of the coalesced islands can increase relatively. Thus, the thickness of the coalesced nitride layer 227 can also increase.

[0261] Furthermore, if the mask layer 226 is included, stresses between the nitride semiconductor layer and the mask layer 226 can be decoupled, and thus a compressive stress transferred to the coalesced nitride layer 227 can be partially blocked. As growing islands coalesce, a relative tensile stress can also be generated in the coalesced nitride layer 227. As a result, the first nitride semiconductor layer 221 can withstand a strong compressive stress, while, conversely, the coalesced nitride layer 227 deposited on the mask layer 226 can withstand a relatively weak compressive or tensile stress due to the stress decoupling and island coalescence.Since cracks are generated during a cooling process when the thickness of a layer with a relatively lower compressive stress exceeds a critical point, the thickness of the coalesced nitride layer 227 can be appropriately selected to meet the conditions under which no cracks are generated and the defect density is reduced.

[0262] It will be on Fig. Reference is made to Figure 25D, which shows a buffer layer 210, a voltage equalization layer 220 and a nitride semiconductor layer structure L arranged sequentially on a silicon substrate 201.

[0263] The stress-equalizing layer 220 according to the embodiment of the present disclosure can comprise a first and a second nitride semiconductor layer 220a and 220b, which have been grown under different growth conditions. By growing the first nitride semiconductor layer 220a in a two-dimensional mode, so that the increase in surface roughness is limited, the generation of twisted grain boundaries at the interface with the second nitride semiconductor layer 220b can be reduced.

[0264] The first nitride semiconductor layer 220a can be formed under a first growth condition such that it has a surface roughness ratio of 3 or less with respect to the surface roughness of the buffer layer 210, and the second nitride semiconductor layer 220b can be formed on the first nitride semiconductor layer 220a under a second growth condition. The second growth condition differs from the first growth condition in that it has a larger three-dimensional growth mode. That is, at least one of the conditions—temperature, pressure, and molar composition ratio of V / III sources—of the second growth condition can differ from those of the first growth condition.

[0265] Regarding temperature, the growth temperature for the first nitride semiconductor layer 220a can be set lower than the growth temperature for the second nitride semiconductor layer 220b. For example, the growth temperature of the first nitride semiconductor layer 220a can be in the range of above 900 °C and below 1040 °C, preferably in the range of 930 °C to 1030 °C. Under these growth temperature conditions, it is possible to increase the crystallinity and effectively reduce the twisted grain boundaries in the first nitride semiconductor layer 220.

[0266] The second nitride semiconductor layer 220b can then be grown under a second growth condition, which differs from the first growth condition, to enhance the three-dimensional growth mode. For example, the temperature range of the second growth condition can be set higher than that of the first growth condition for the second nitride semiconductor layer 220b. As described above, the second nitride semiconductor layer 220b can be grown by controlling a volume fraction of hydrogen in a nitrogen source gas to 40% or less at a temperature of 1040 °C or less. The first nitride semiconductor layer 220a can also be grown at a temperature below 1040 °C by controlling a volume fraction of hydrogen, similar to the growth condition of the second nitride semiconductor layer 220b.

[0267] Meanwhile, the first growth condition of the first nitride semiconductor layer 220a can be adjusted by controlling the pressure or the molar composition ratio of V / III sources. Generally, the crystallinity and pressure stress can be higher the lower the pressure. Furthermore, the crystallinity and pressure stress can be higher the larger the molar composition ratio of the V / III sources. For example, the pressure of the first growth condition can be in the range of 20 to 500 Torr. The pressure of the second growth condition can be in the range of 50 to 300 Torr.

[0268] The thickness of the first nitride semiconductor layer 220a can range from 2 to 1000 nm. Increasing the thickness of the first nitride semiconductor layer 220a can reduce the formation of twisted grain boundaries at the interface between the first nitride semiconductor layer 220a and the second nitride semiconductor layer 220b. However, if the first nitride semiconductor layer 220a is thin, the crystallinity of the entire thin film may be reduced. This is because the first nitride semiconductor layer 220a is grown at a relatively lower temperature than the second nitride semiconductor layer 220b and therefore has more defects. Therefore, reducing the thickness of the first nitride semiconductor layer 220a can be advantageous in minimizing the formation of twisted grain boundaries.

[0269] By reducing the twisted grain boundaries, the defects of the second nitride semiconductor layer 220b, which is stacked on top of the first nitride semiconductor layer 220a, can be reduced. Specifically, if the first nitride semiconductor layer 220a has a thickness of 2 to 1000 nm and a surface roughness ratio of 3 or less relative to the surface roughness of the buffer layer 210, the defects of the second nitride semiconductor layer 220b, which is stacked on top of the first nitride semiconductor layer 220a, can be reduced. Since the same degree of crystallinity can be achieved with a small thickness, the entire structure can be made thin. For example, the combined thickness of the buffer layer 210 and the stress-equalizing layer 220 can be 6 µm or less, even without the use of a mask layer. This reduces the process time and the cost associated with grain growth.

[0270] The second nitride semiconductor layer 220b can be made of Al x In y Ga 1-x-y N (0≥x,y≥1, and x+y<1). The second nitride semiconductor layer 220b can be grown continuously (or directly) on the first nitride semiconductor layer 220a without additionally growing a layer with a different composition. The second nitride semiconductor layer 220b can have the same composition as the first nitride semiconductor layer 220a. For example, the first and second nitride semiconductor layers 220a and 220b can be GaN. In some embodiments, the first nitride semiconductor layer 220a can be undoped GaN and the second nitride semiconductor layer 220b can be n-GaN.

[0271] The buffer layer and voltage-equalizing layer described above can be removed together during the substrate removal process or after substrate removal. In some embodiments, if the voltage-equalizing layer is sufficiently conductive, it does not need to be removed and can be provided as a contact area. In other embodiments, the buffer layer and the voltage-equalizing layer can be selectively removed to expose the contact area of ​​the semiconductor layer of the first conductivity type.

[0272] Fig. 26 and Fig. Figure 27 are cross-sectional views representing packages of light-emitting semiconductor devices according to embodiments of the present disclosure.

[0273] A in Fig. Package 500 of a light-emitting device shown in 26 can be used in Fig. Figure 26 shows a light-emitting semiconductor device 10, a package housing 502 and two conductor frames 503.

[0274] The light-emitting semiconductor device 10 can be mounted on a conductor frame 503, and each of its electrodes can be electrically connected to the conductor frame 503. If required, the light-emitting semiconductor device 10 can be mounted in a different area than the conductor frame 503, for example, on the package housing 502. Furthermore, the package housing 502 can have a cup (U) shape to enhance light reflection, and an encapsulation 505, formed from a translucent material, can be provided within the reflective cup to encapsulate the light-emitting semiconductor device 10.

[0275] The light-emitting semiconductor device used in the present embodiment can advantageously include another light-emitting semiconductor device with a flip-chip structure in addition to the one described in Fig. Use the light-emitting semiconductor device 10 shown in Figure 1. Each of the light-emitting semiconductor devices (except for the design with respect to the circuit substrate) shown in Figure 10 may be used. Fig. Figures 6, 9, 11, 13, 15 and 16A to 16C are shown in the following. Fig. Package 500 of a light-emitting semiconductor device is used as shown in Figure 26.

[0276] A in Fig. Package 600 of a light-emitting device shown in 27 can be used in Fig. Figure 17 shows a light-emitting semiconductor device 10', a mounting plate 610 and an encapsulation 603.

[0277] The light-emitting semiconductor device 10' can be mounted on the mounting plate 610 and electrically connected to the mounting plate 610 via one or more wires W.

[0278] The mounting plate 610 can comprise a substrate body 611, one or more upper electrodes 613, one or more lower electrodes 614, and one or more through electrodes 612, each connecting one upper electrode 613 to one lower electrode 614. The mounting plate 610 can be a PCB, MCPCB, MPCB, FPCB, or the like, and the structure of the mounting plate 610 can be implemented in various forms.

[0279] The encapsulation 603 can have a dome-shaped lens structure with a convex upper surface. In some embodiments, the encapsulation 603 can have a convex or concave lens structure to adjust the angle of light emitted through the upper surface of the encapsulation.

[0280] If required, a wavelength conversion material such as a phosphor or a quantum dot can be arranged in the encapsulations 505 and 603 or on a surface of the light-emitting semiconductor devices 10 and 10'.

[0281] The phosphor or quantum dot can be suitably selected from the phosphors and quantum dots described above.

[0282] For example, the phosphor can be at least one of phosphors that are excited by light emitted from the light-emitting semiconductor device 10 and 10', and can emit light with a different wavelength than the light emitted by the devices 10 and 10'. Light with different wavelengths can be emitted by the phosphors.

[0283] If the light-emitting semiconductor devices 10 and 10' emit blue light, a package of a light-emitting device containing at least one yellow, green, and / or red phosphor can emit light with different color temperatures depending on the mixing ratio of the phosphors. Alternatively, a package of a light-emitting device containing the light-emitting semiconductor devices 10 and 10' with a green or red phosphor can emit green or red light. By combining the package of a light-emitting device that emits white light with the package of a light-emitting device that emits green or red light, the color temperature and color rendering index (CRI) of white light can also be controlled.Furthermore, the package of a light-emitting device can be designed to include at least one light-emitting device that emits at least one type of violet, blue, green, red, or infrared light. In this case, the package of a light-emitting device, or a module product containing the package of a light-emitting device, can be controlled to have a CRI level ranging from that of a sodium (Na) lamp (CRI: 40) to that of sunlight (CRI: 100) and to produce white light with different color temperatures ranging from 2000 K to 20,000 K. Additionally, the package of a light-emitting device can, as required, produce visible light with violet, blue, green, red, orange, or infrared light to adjust the lighting color according to an ambient atmosphere or mood.Furthermore, the light source device can generate light with a specific wavelength to stimulate plant growth.

[0284] Reference is made to the CIE 1931 chromaticity coordinate system, which is in Fig. Figure 28 shows that white light produced by combining yellow, green, and red phosphors, and / or green and red LEDs with UV or blue LEDs, can have two or more peak wavelengths and can be arranged in a segment with (x,y) coordinates (0.4476, 0.4074), (0.3484, 0.3516), (0.3101, 0.3162), (0.3128, 0.3292), and (0.3333, 0.3333) of the CIE 1931 chromaticity coordinate system, which is shown in Fig. Figure 28 shows the white light. Alternatively, the white light can be arranged in a region surrounded by the spectrum of the segment and the blackbody radiation spectrum. The color temperature of the white light corresponds to 2000 K to 20,000 K.

[0285] In some embodiments, a package of a white light-emitting device with a color temperature of 4000 K, a package of a white light-emitting device with a color temperature of 3000 K, and a package of a red light-emitting device can be arranged in a white light-emitting package module. The color temperature of the white light-emitting package module can be controlled to the range of 2000 K to 4000 K by combining the packages of light-emitting devices. Furthermore, a white light-emitting package module with a CRI Ra of 85 to 99 can be manufactured. Such a light source module can advantageously be used in a bulb-like lighting device that is in Fig. 31 is shown.

[0286] In other embodiments, a package of a white light-emitting device with a color temperature of 5000K and a package of a white light-emitting device with a color temperature of 2700K can be arranged in a white light-emitting package module. The color temperature of the white light-emitting package module can be controlled to the range of 2700K to 5000K by combining the packages of light-emitting devices. Furthermore, a white light-emitting package module with a CRI Ra of 85 to 99 can be produced. Such a light source module can advantageously be used in a bulb-like lighting device that is located in Fig. 31 is shown.

[0287] The number of packages of light-emitting devices can vary depending on the base color temperature settings. If the base color temperature settings are around 4000 K, the number of packages of white light-emitting devices corresponding to a color temperature of 4000 K may be higher than the number of packages of white light-emitting devices corresponding to a color temperature of 3000 K, or higher than the number of packages of red light-emitting devices.

[0288] In this way, one or more light-emitting semiconductor devices according to the embodiment described above and a package containing one or more of these devices can advantageously be used in different applications.

[0289] Fig. 29 and Fig. Figure 30 shows examples in which a light-emitting semiconductor device according to an embodiment of the present disclosure is incorporated into a backlighting unit.

[0290] It will be on Fig. Reference is made to Figure 29, which shows that a backlighting unit 1000 may comprise a light source 1001 mounted on a substrate 1002 and one or more optical surfaces 1003 arranged on the light source 1001. The light source 1001 may include the light-emitting semiconductor device described above or a package containing the light-emitting semiconductor device.

[0291] The light source 1001 in the in Fig. The backlight unit 29 shown emits light towards an upper surface where a liquid crystal display (LCD) is located. In contrast, another backlight unit 2000, which is shown in Fig. Figure 30 shows a light source 2001 mounted on a substrate 2002, emitting light in a lateral direction. The emitted light can fall onto a light guide plate 2003 and be converted into surface light. Light passing through the light guide plate 2003 is emitted upwards, and a reflective layer 2004 can be arranged on a lower surface of the light guide plate 2003 to improve the light extraction efficiency.

[0292] Fig. Figure 31 is a perspective exploded view showing a lighting apparatus comprising a light-emitting semiconductor device according to an embodiment of the present disclosure.

[0293] The lighting apparatus 3000 from Fig. Figure 31 is shown as a pear-shaped lamp as an example and includes a light-emitting module 3003, a driver unit 3008 and an external connection section 3010.

[0294] Furthermore, external structures such as external and internal housings 3006 and 3009 and a cover 3007 may also be included. The light-emitting module 3003 may comprise a light source 3001, that is, one or more of the light-emitting semiconductor devices described above, or a package containing the light-emitting semiconductor device, and a printed circuit board 3002 on which the light source 3001 is mounted. For example, a first and a second electrode of the light-emitting semiconductor device may be electrically connected to an electrode pattern of the printed circuit board 3002. In this embodiment, a single light source 3001 is mounted on the printed circuit board 3002, but a plurality of light sources 3001 may be mounted as required.

[0295] The external housing 3006 can serve as a heat dissipation unit and includes a heat dissipation plate 3004, which is in direct contact with the light-emitting module 3003 to enhance heat dissipation, and a heat-radiating fin 3005, which surrounds the side surfaces of the lighting apparatus 3000. The cover 3007 can be mounted on the light-emitting module 3003 and has a convex lens shape. The driver unit 3008 can be installed in the internal housing 3009 and connected to the external connection section 3010, for example a socket structure, to receive power from an external power source.

[0296] Furthermore, the driver unit 3008 can be used to convert the power into a suitable current source capable of driving the light source 3001 of the light-emitting module 3003. For example, a driver unit 3008 can be designed as an AC-DC converter, as a rectifier circuit component, or the like.

[0297] Fig. Figure 32 shows an example in which a light-emitting semiconductor device according to an embodiment of the present disclosure is used for a headlight.

[0298] It will be on Fig.Reference is made to Figure 32, which shows that a headlight 4000, used as a vehicle lamp or the like, may comprise a light source 4001, a reflecting unit 4005, and a lens cover unit 4004. The lens cover unit 4004 may comprise a waveguide 4003 and a lens 4002. The light source 4001 may include the light-emitting semiconductor device described above or a package containing the light-emitting semiconductor device.

[0299] The headlight 4000 can further comprise a heat dissipation unit 4012, which conducts heat generated by the light source 4001 to the outside. To dissipate heat effectively, the heat dissipation unit 4012 can include a heat sink 4010 and a cooling fan 4011. The headlight 4000 can also further comprise a housing 4009, which supports the heat dissipation unit 4012 and the reflecting unit 4005 in a fixed manner. The housing 4009 can include a body 4006 and a central opening 4008 formed in one of its surfaces, in which the heat dissipation unit 4012 is coupled and installed.

[0300] The housing 4009 can have a front opening 4007 formed on the outer surface, which is integrally connected to one surface and bent at a right angle. The front opening 4007 can fix the reflecting unit 4005 so that it is positioned above the light source 4001. Thus, one front of the housing 4009 can be open through the reflecting unit 4005. The reflecting unit 4005 is fixed to the housing 4009 in such a way that the open front corresponds to the front opening 4007, allowing light reflected by the reflecting unit 4005 to pass through the front opening 4007 and be emitted to the outside.

[0301] As explained above, according to the embodiments of this disclosure, a light-emitting chip-on-board (COB) semiconductor device with different structures can be created using a simple support substrate other than a support substrate having an electrode structure. More precisely, in a flip-chip structure, superior heat dissipation performance can be achieved because the light-emitting semiconductor device has a heat dissipation path that does not pass through the support substrate. In particular, the structure can be advantageously applied to a process for fabricating the light-emitting nitride semiconductor layer using a silicon substrate.

Claims

[1] Light-emitting semiconductor device comprising: a semiconductor layer structure (L) comprising a first surface and a second surface opposite each other, a semiconductor layer of a first conductivity type (14) and a semiconductor layer of a second conductivity type (16) forming the first surface and the second surface respectively, and an active layer (15) arranged between the semiconductor layer of the first conductivity type (14) and the semiconductor layer of the second conductivity type (16); a first electrode (17) which is arranged on the first surface of the semiconductor layer structure (L) and is connected to the semiconductor layer of the first conductivity type (14); a second electrode (18) which is arranged on the second surface of the semiconductor layer structure (L) and is connected to the semiconductor layer of the second conductivity type (16); a connecting electrode (48) which is connected to the second electrode (18) and which extends to the first surface of the semiconductor layer structure (L); a support substrate (45) arranged at the second electrode (18); and an insulating layer (46) arranged to insulate the connecting electrode (48) from the active layer (15) and the semiconductor layer of the first conductivity type (14), wherein the semiconductor layer structure (L) has a through hole (H) extending from the first surface to the second surface, and the connecting electrode (48) is electrically connected to the second electrode (18), is arranged on an inner side wall of the through hole (H) and extends to the first surface of the semiconductor layer structure (L), further comprising an etch stop layer (42; 102) which is arranged on a section of the second electrode (18) and connects the second electrode (18) to the connecting electrode (48), wherein the etch stop layer (42; 102) contains a conductive material and is arranged between the second electrode (18) and the support substrate (45, 105). [2] Light-emitting semiconductor device according to claim 1, wherein the second electrode (18) includes a light-transmitting electrode and the support substrate (45) includes a light-transmitting substrate. [3] Light-emitting semiconductor device according to claim 2, wherein the first electrode (17) includes a reflective electrode. [4] Light-emitting semiconductor device according to claim 3, further comprising first and second conductive contact protrusions (34) arranged on sections of the first electrode (17) and the connecting electrode (48) respectively on the first surface. [5] Light-emitting semiconductor device according to claims 1 to 4, wherein the second electrode (18) leaves a section of the etch stop layer (42) exposed and the connecting electrode (48) is connected to the exposed section of the etch stop layer (42). [6] Light-emitting semiconductor device according to any one of claims 1 to 5, further comprising at least one finger electrode (44) which is connected to the etch stop layer (42) and which extends into a space between the second electrode (18) and the support substrate (45). [7] Light-emitting semiconductor device comprising: a semiconductor layer structure (L) comprising a first surface and a second surface opposite each other, a semiconductor layer of a first conductivity type (14) and a semiconductor layer of a second conductivity type (16) forming the first surface and the second surface respectively, and an active layer (15) arranged between the semiconductor layer of the first conductivity type (14) and the semiconductor layer of the second conductivity type (16); a first electrode (17) which is arranged on the first surface of the semiconductor layer structure (L) and is connected to the semiconductor layer of the first conductivity type (14); a second electrode (18) which is arranged on the second surface of the semiconductor layer structure (L) and is connected to the semiconductor layer of the second conductivity type (16); a connecting electrode (58) which is connected to the second electrode (18) and which extends to the first surface of the semiconductor layer structure (L); a support substrate (55) arranged at the second electrode (18); and an insulating layer (56) arranged to insulate the connecting electrode (58) from the active layer (15) and the semiconductor layer of the first conductivity type (14), wherein the semiconductor layer structure (L) has a through hole (H) extending from the first surface to the second surface, and the connecting electrode (58) is electrically connected to the second electrode (18), is arranged on an inner side wall of the through hole (H) and extends to the first surface of the semiconductor layer structure (L), wherein the light-emitting semiconductor device further comprises an etch stop layer (42) arranged between the semiconductor layer structure (L) and the second electrode (18) and having a section connected to the through-hole (H), wherein the etch stop layer (52) includes an insulating material and is arranged on a section of the second electrode (18) such that it surrounds and leaves open an exposed section (C) of the second electrode (18) which is connected to the connecting electrode (58). [8] Light-emitting semiconductor device according to any one of claims 1 to 7, further comprising a planarization layer (43; 53) located between the second electrode (18) and the support substrate (45; 55) and having a planarized surface which is attached to the support substrate (45; 55). [9] Light-emitting semiconductor device according to any one of claims 1 to 8, wherein the insulating layer (46; 56) is arranged on the inner side wall of the through hole (H) and extends to the first surface of the semiconductor layer structure (L). [10] Light-emitting semiconductor device according to any one of claims 1 to 9, wherein the insulating layer (26; 66) has an extended section (26a; 66a) which covers a section of the first electrode (17) and the connecting electrode (28; 68) extends onto the extended section (26a; 66a) of the insulating layer (26; 66). [11] Light-emitting semiconductor device according to any one of claims 1 to 10, further comprising an insulating element (63; 73) surrounding side surfaces of the semiconductor layer structure (L). [12] Light-emitting semiconductor device according to any one of claims 1 to 11, further comprising an electrode protection layer arranged between the second electrode (18) and the support substrate (45; 55) and designed to protect the second electrode (18). [13] Light-emitting semiconductor device according to any one of claims 1 to 12, wherein the support substrate (55; 65) is made of glass or a polymer resin. [14] Light-emitting semiconductor device according to claim 13, wherein the support substrate (55; 65) includes a phosphor or a quantum dot. [15] Light-emitting semiconductor device according to any one of claims 1 to 14, wherein the semiconductor layer of the first conductivity type (14) is an n-type semiconductor layer and the semiconductor layer of the second conductivity type (16) is a p-type semiconductor layer. [16] Light-emitting semiconductor device according to claim 1, wherein the second electrode (18) is a translucent electrode; wherein a section (28a; 68a) of the connecting electrode (28; 68) which is arranged on the first surface is provided as a contact point area; wherein the support substrate (25; 65) is a translucent substrate; and wherein the insulating layer (26) has an extended section (26a; 66a) which covers a section of the first electrode (17), and the contact surface of the connecting electrode (28; 68) is arranged on the extended section (26a; 66a) of the insulating layer (26; 66). [17] Light-emitting semiconductor device according to claim 16, further comprising a light-transmitting adhesive layer (21) arranged between the light-transmitting substrate (25) and the second electrode (18). [18] Light-emitting semiconductor device according to claim 16, further comprising an insulating element (63) which surrounds the side faces and the first surface of the semiconductor layer structure (L) and is formed from a translucent adhesive material in order to be attached to the translucent substrate (65). [19] Light-emitting semiconductor device according to claim 18, wherein the side surfaces of the semiconductor layer structure (L) include a surface which slopes towards the second surface.

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