Method for fabricating superjunction semiconductor devices with a superstructure aligned with a basis

Abstract

A method for manufacturing a semiconductor device, comprising: Forming a trench mask (410) by forming mask openings (418, 419) in a trench mask layer on a semiconductor layer (100a); Forming, by using the trench mask (410), first and second trenches (181, 182) extending in a vertical projection of the mask openings (418, 419) from a main surface (101a) into the semiconductor layer (100a); Forming a base comprising first areas (191) in and / or directly adjacent to the first trenches (181), wherein a fill material forming structures in the first and second trenches (181, 182) fills the mask openings (418, 419); Performing a selective etching process with respect to the filler material to form at least steps (203) on the first grooves (181) in a device area (610) or steps (201) on the second grooves (182) in a kerf area (690); and Forming a superstructure in alignment with the base by using positional information obtained directly from the stages (201, 203).

Description

BACKGROUND

[0001] In superjunction semiconductor devices, complementary doped first and second semiconductor regions alternate along at least one horizontal direction in a drift layer. The doping concentrations in the first and second semiconductor regions are adjusted relative to each other such that, even at comparatively high dopant concentrations in the superjunction structure, a part or section of the drift layer containing the superjunction structure can be completely depleted in an off-state of the semiconductor device. A semiconductor device with high dopant concentrations in sections of the drift layer exhibits a comparatively low on-state or on-state resistance.

[0002] Superjunction structures can be formed by etching trenches into a semiconductor layer of a first conductivity type and filling the trenches with semiconductor material of the complementary second conductivity type. After the superjunction structure has been formed, a superstructure comprising transistor cells can be created in a semiconductor layer above the superjunction structure. To align the transistor cells with the superjunction structure, an alignment mark is created before or after the formation of the superjunction structure.

[0003] In US 2015 / 0 044 854 A1, a trench for an alignment mark is formed in the scribe lane of an epitaxial layer. A stop layer is deposited on the epitaxial layer, lined with the stop layer, and finally filled with an alignment mark material. A photoresist layer is deposited onto the stop layer and patterned with a photomask aligned to the alignment mark material. Hole trenches are etched into the epitaxial layer through openings in the patterned photoresist layer. After the stop layer is removed from the epitaxial layer, a portion of the alignment mark material remains in the trench in the scribe lane. Subsequent processes can be aligned to the remaining portion of the alignment mark material.

[0004] CN 104 658 889 A forms narrow, shallow trenches in an active region and a wide, deep trench in an alignment mark region of a first epitaxial layer. Epitaxial material is then grown in all trenches until the trenches in the active region are completely filled, while the wider, deeper trench in the alignment mark region is only partially filled. A second epitaxial layer is deposited on the first epitaxial layer with the completely filled trenches in the active region and the only partially filled trench in the alignment mark region. The partially filled trench in the alignment mark region forms a depression on the surface of the second epitaxial layer. Varying trench dimensions and specific control of the epitaxial deposition thus create an alignment mark on the surface of an epitaxial layer.

[0005] The document US 2011 / 0 294 278 A1 describes the simultaneous formation of trenches for p-doped pillars in a component region and of trenches for a temporary alignment mark in a region of temporary alignment marks using a hard mask. The trenches are filled epitaxially, with p-doped pillars of a superjunction structure being formed in the trenches in the component region. Subsequently, epitaxially deposited material outside the trenches is planarized up to the upper edge of the hard mask. A photoresist is deposited and patterned, with the structure of the photoresist being aligned to the epitaxially filled trenches in the region of the temporary alignment marks using an optical method. Using the photolithographically patterned photoresist, final alignment marks are formed in a region of non-temporary alignment marks, based on which structures in later deposited layers are aligned to the p-doped pillars.

[0006] It is desirable to align a superstructure to a base containing a superjunction structure in a reliable and economical manner. SUMMARY

[0007] The object is achieved by the subject matter of the independent claims. The dependent claims relate to further embodiments.

[0008] According to one embodiment, a method of manufacturing a semiconductor device comprises forming first and second trenches extending from a main surface into a semiconductor layer, wherein a single trench mask is used to form both the first and second trenches. A base comprising first regions in and / or directly adjacent to the first trenches is formed. A superstructure is created in alignment with the base, wherein position information is obtained directly from structures formed in at least one of the first and second trenches.

[0009] According to another embodiment, a semiconductor substrate comprises a superjunction structure in a device region of a semiconductor layer, the superjunction structure comprising first regions and second regions of an opposite conductivity type, the first and second regions alternating along at least one horizontal direction. An alignment mark in a kerf region of the semiconductor layer includes vertical steps formed by a portion of an alignment structure that protrudes or is recessed from a main surface of the semiconductor layer. The alignment structure is made of the material of the first regions of the superjunction structure.

[0010] According to another embodiment, a semiconductor device comprises a superjunction structure in an active region of a semiconductor section, wherein the superjunction structure comprises first regions and second regions of an opposite conductivity type, and wherein the first and second regions alternate along at least one horizontal direction. An alignment mark in an inactive region of the semiconductor section comprises vertical steps formed by a portion of an alignment structure that protrudes or is recessed from a first surface of the semiconductor section. The alignment structure is made of the material of the first regions of the superjunction structure.

[0011] According to another embodiment, a method for manufacturing a semiconductor device comprises forming, by using a single trench mask, first and second trenches extending from a main surface into a semiconductor layer. A base is provided that includes a superjunction structure. The superjunction structure comprises doped first regions in and / or directly adjacent to the first trenches and oppositely doped second regions. The first and second regions alternate along at least one horizontal direction parallel to the main surface. A superstructure is formed that is aligned with the base, utilizing position information obtained directly from structures formed in at least one of the first and second trenches.

[0012] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain principles of the invention. Other embodiments and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. Fig. 1 is a schematic flow diagram of a method for manufacturing a superjunction semiconductor device according to an embodiment using position information derived directly from structures formed in the trenches intended for creating the superjunction structure or formed simultaneously with trenches intended for creating the superjunction structure. Fig. 2A is a schematic vertical cross-sectional view of a portion of a semiconductor substrate for illustrating a method of manufacturing a superjunction semiconductor device according to an embodiment using an alignment mark with enhanced contrast based on second trenches formed simultaneously with first trenches intended for creating a superjunction structure after forming a trench mask. Fig. Figure 2B is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2A after etching both first and second trenches using the trench mask. Fig. Figure 2C is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2B after filling the first and second trenches with a filling material. Fig. Figure 2D is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2C after planarization of the filling material. Fig. Figure 2E is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2D after formation of a device mask exposing a second part or section of the trench mask around the second trenches. Fig. Figure 2F is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2E after forming an alignment mark with increased contrast by selectively removing the second portion of the trench mask around the second trenches. Fig. Figure 2G is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2F after a complete, non-selective removal of a first section of the trench mask. Fig. Figure 2H is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2G after forming a gate mask, wherein position information obtained from the alignment mark with increased contrast is used to align an exposure mask for the gate mask. Fig. Figure 2I is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 2H after forming gate structures using the gate mask. Fig. 3A is a schematic vertical cross-sectional view of a portion of a semiconductor substrate for illustrating a method of fabricating a superjunction semiconductor device by using an alignment mark with enhanced contrast based on second trenches formed simultaneously with first trenches intended to create a superjunction structure, after recessing fill material in the second trenches with respect to a trench mask. Fig. Figure 3B is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 3A after a complete, non-selective removal of the trench mask. Fig. 4A is a schematic vertical cross-sectional view of a portion of a semiconductor substrate for illustrating a method of fabricating a superjunction semiconductor device using position information directly derived from a material-selective etching process effective on structures in first trenches intended for creating a superjunction structure after forming a transistor cell region mask. Fig. Figure 4B is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4A after removing a second portion of a trench mask exposed by the transistor cell region mask. Fig. Figure 4C is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4B after a complete, non-selective removal of the trench mask. Fig. Figure 4D is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4C after deposition of a conformal mask layer. Fig. Figure 4E is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4D after forming an auxiliary mask. Fig. Figure 4F is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4E after forming, using the auxiliary mask, a spacer mask from the conformal mask layer. Fig. 4G is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4F after forming gate trenches that are self-aligned to first regions formed in the first trenches. Fig. 4H is a schematic vertical cross-sectional view of the semiconductor substrate portion of Fig. 4G after forming gate structures in the gate trenches. Fig. Figure 5A is a diagram showing orientation dependencies for the Fig. 2A to 3B, according to one embodiment. Fig. Figure 5B is a diagram showing orientation dependencies for the Fig. 4A to 4H schematically illustrates the method according to another embodiment. Fig. 6 is a schematic vertical cross-sectional view of a semiconductor substrate having a plurality of device regions for superjunction semiconductor devices according to an embodiment with an alignment mark with increased contrast in a kerf region. Fig. 7 is a schematic vertical cross-sectional view of a semiconductor device according to an embodiment having an alignment mark with increased contrast in an inactive region. Fig. 8A is a schematic top view of an alignment mark with parallel alignment structures according to an embodiment. Fig. 8B is a schematic top view of a cross-shaped alignment mark according to one embodiment. Fig. 8C is a schematic top view of a box-shaped alignment mark according to one embodiment. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which is shown, for purposes of illustration, specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used in or in connection with other embodiments to arrive at yet another embodiment. It is intended that the present invention encompass such modifications and changes. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements are designated by corresponding reference numerals in the various drawings, unless otherwise noted.

[0015] The terms "have," "contain," "comprise," "have," and similar terms are open terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not exclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0016] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p." For example, "n-" indicates a doping concentration lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions can have the same or different absolute doping concentrations.

[0017] Fig. 1 illustrates a method of manufacturing a superjunction semiconductor device according to embodiments.

[0018] The superjunction semiconductor device may be or include a power semiconductor diode, an IGFET (insulated gate field effect transistor), for example a MOSFET (metal oxide semiconductor field effect transistor) in the usual sense, including FETs with metal gates and FETs with semiconducting gates, or an IGBT (insulated gate bipolar transistor).

[0019] Using a single trench mask, trenches are formed that extend from a main surface into a semiconductor layer of a crystalline semiconductor material such as silicon (Si) (710). First regions are formed in and / or directly adjacent to the first trenches (720). The first regions may be or comprise insulating, semiconducting, or highly conductive structures. According to one embodiment, the first regions may be or comprise semiconducting sections of the semiconductor layer 100a that are temporarily accessible through the trenches. According to other embodiments, the first regions may be or comprise semiconducting structures formed by filling the trenches with doped or intrinsic semiconductor material.

[0020] The first regions are part of a foundation. By using positional information derived directly from structures formed in the trenches, a superstructure, which may include transistor cells, is created in alignment with the foundation (730).

[0021] Every photolithography process defines functional structures such as insulator structures, conductive structures, or semiconducting regions of semiconductor elements, either in the base or in the superstructure. Critical or crucial photolithography processes that define alignment marks not only define an alignment mark but also functional structures. The process eliminates any critical lithography process that exclusively defines a nonfunctional structure such as an alignment mark.

[0022] According to one embodiment, an optical response of a structure formed in at least a second of the trenches can be evaluated to align the superstructure with the base. In this way, the position information about a placement of the base is derived directly from the structure in the at least one second trench. According to another embodiment, the position information can be derived directly from steps formed along sidewalls of structures formed in at least some of the first trenches intended for creating the superjunction structure.

[0023] The first regions formed in the first trenches may form or be part of a superjunction structure. Unlike approaches that provide an alignment mark prior to creating the superjunction structure and align both the base containing the superjunction structure and the superstructure comprising the transistor cells with the alignment mark, the position information signal is not attenuated by planarizing processes acting on the semiconductor layer containing the superjunction structure, for example, to remove or ablate excess trench fill material. Instead, the present embodiments utilize a high-contrast signal based directly on the superjunction structure or on an alignment mark that may be formed as an extension of the superjunction structure.

[0024] Unlike a process that uses alignment markers created after the creation of the superjunction structure and in alignment with the superjunction structure, the process for forming the superstructure is directly aligned with the superjunction structure and therefore an inherent statistical misalignment by a factor 2 reduced.

[0025] Fig. 2A to 2I relate to a method of manufacturing a superjunction semiconductor device by aligning a superstructure comprising transistor cells to an alignment mark 200 formed simultaneously with a superjunction structure 190 in a base in a semiconductor substrate 500a.

[0026] The semiconductor substrate 500a has a main surface 101a on a front side. The distance between the main surface 101a and a back surface 102a on the back side of the semiconductor substrate 500a can reach several hundred µm. Directions parallel to the main surface 101a are horizontal directions, and a direction perpendicular to the main surface 101a is a vertical direction.

[0027] The semiconductor substrate 500a may be formed of a semiconductor layer 100a of a crystalline semiconductor material such as single-crystal silicon (Si), germanium (Ge), a silicon-germanium (SiGe) crystal, silicon carbide (SiC), or an A III B V-semiconductor or comprise such a semiconductor. The semiconductor substrate 500a may further comprise conductive, dielectric, or semiconducting sections. For example, the semiconductor layer 100a is an n-doped epitaxial layer formed on a substrate section 105a obtained from a semiconductor ingot, wherein the substrate section 105a may form a homojunction, for example, a unipolar homojunction or a pn junction, with the semiconductor layer 100a.

[0028] The semiconductor layer 100a may be homogeneously doped with dopants of the same type or with complementary dopants, or it may comprise sections of different dopant concentrations for at least one dopant type. For example, the semiconductor layer 100a may contain sections in which the net dopant concentration increases or decreases with decreasing distance from the main surface 101a.

[0029] A trench mask layer is formed on the main surface 101a. The trench mask layer may consist of a single homogeneous layer or may be a layer stack comprising two or more layers of different materials.

[0030] The trench mask layer is patterned by photolithography to form a trench mask 410 with first mask openings 418 in a device region 610 and second mask openings 419 in a scribe line or kerf region 690. The device region 610 corresponds to portions of the semiconductor substrate 500a from which semiconductor dies for semiconductor devices are obtained. The kerf region 690 forms a grid, with the device regions 610 forming the meshes. The kerf region 690 may be partially or completely discarded during a separation process that separates the semiconductor dies from the semiconductor substrate 500a.

[0031] Fig. 2A shows the trench mask 410 with the first mask openings 418 in the device region 610 and the second mask openings 419 in the kerf region 690. The trench mask 410 may include a first mask layer 411, which may be a silicon oxide layer. For example, the first mask layer 411 may contain or consist of thermally grown silicon oxide, deposited silicon oxide, for example, silicon oxide deposited by LPCVD (low pressure chemical vapor deposition) using TEOS (tetraethyl orthosilicate) as a precursor material and densified in a heat treatment. A second mask layer 412 may be formed of a material with a high etch selectivity compared to the material of the first mask layer 411. According to one embodiment, the second mask layer 412 contains or consists of silicon nitride. A third mask layer 413 may, for example,contain or consist of a further silicon oxide layer or a silicate glass layer, for example BSG (borosilicate glass), PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass).

[0032] The first mask openings 418 may form a regular pattern of stripes or dots, wherein a first width of the dots in the horizontal plane is at most three times the second width of the dots, orthogonal to the first width, and wherein horizontal cross-sections of the dots may be circles, ellipses, ovals, distorted polygons, or regular polygons such as octagons, hexagons, or squares.

[0033] A center-to-center distance between adjacent first mask openings 418 may be in a range from 1 µm to 20 µm, for example, in a range from 2 µm to 10 µm. A width of the first and second mask openings 418, 419 may be in a range from 500 nm to 10 µm, for example, from 1 µm to 5 µm. A center-to-center distance between a pair of adjacent first and second mask openings 418, 419 may be at least five times a center-to-center distance between adjacent first mask openings 418.

[0034] The second mask openings 419 may have the same horizontal cross-sectional shape as the first mask openings 418. According to other embodiments, the second mask openings 419 may have different dimensions, and the horizontal cross-sections may correspond to the cross-sections of conventional alignment marks. For example, the second mask openings 419 form a pattern comprising rectangular stripes with rounded and / or partially beveled strip ends, and without cuts and branches. The pattern may, for example, comprise two or more stripes arranged parallel to each other, like a cross, or along the outline of a rectangle.

[0035] An etching process, for example, reactive ion beam etching, utilizes the trench mask 410 to form first trenches 181 in a vertical projection of the first mask openings 418 in the device region 610 and second trenches 182 in the vertical projection of the second mask openings 419 in the kerf region 690. Etching the first and second trenches 181, 182 may partially consume the third mask layer 419.

[0036] Fig. 2B shows the first and second trenches 181, 182, wherein, in the device region 610, mesa portions 172 of the semiconductor substrate 100a separate the first trenches 181 from each other. A vertical extension of the first and second trenches 181, 182 may be in a range of 5 µm to 100 µm, for example, in a range of 20 µm to 50 µm.

[0037] First regions 191 may be formed in at least some of the first trenches 181 and / or in parts or portions of the semiconductor layer 100a that are temporarily accessible through at least some of the first trenches 181. Second regions 192 may be formed in the mesa portions 172, in other of the first trenches 181, and / or in further portions of the semiconductor layer 100a that are accessible through other of the first trenches 181.

[0038] The first and second regions 191, 192 may consist of or contain insulating, semiconducting, or highly conductive materials. According to one embodiment, the first and second regions 192 are complementarily doped semiconducting regions and form a superjunction structure 190 in which charges contained in the first and second regions 191, 192 approximately cancel each other out.

[0039] For example, complementary doped layers may be formed, for example, deposited along sidewalls of the first trenches 181. The complementary doped layers may completely fill the first trenches 181 or may leave a void in the center of each first trench 181, wherein the void may be filled with an intrinsic semiconductor material and / or insulating material, or wherein a cap may seal the void.

[0040] Alternatively, a section of the semiconductor layer 100a having a thickness corresponding to a vertical extension of the first trenches 181 may contain complementary dopants, and the first and second regions 191, 192 are formed by a heat treatment after filling the trenches with, for example, lightly doped or intrinsic semiconductor material, wherein different diffusion properties of the complementary dopants in the semiconductor layer 100a result in a partial separation of the complementary dopants.

[0041] According to a further embodiment, the first regions 191 may be formed by filling adjacent first trenches 181 with complementarily doped semiconducting material.

[0042] According to the illustrated embodiment, a superjunction structure 190 is formed by first regions 191 formed primarily in the first trenches 181 and by second regions 192 formed in the mesa portions 172 of the semiconductor layer 100a between the first trenches 181. Initially, at least a portion of the trench mask 410 may be removed. For example, a wet etch may remove a remaining portion of the third mask layer 413 and the second mask layer 412. At least a portion of the first mask layer 411 may form an epitaxial mask 450 covering surfaces of the mesa portions 172 in the main surface 101a. A selective epitaxial process may fill the first and second trenches 181, 182 and the first and second mask openings 418, 419 in the epitaxial mask 450 with a fill material, which may be a doped, crystalline semiconductor material.

[0043] In Fig. 2C form structures in the filled first trenches 181 of Fig. 2B shows first regions 191 of a superjunction structure 190, and the mesa parts or sections 172 form second regions 192 of the superjunction structure 190. The first and second regions 191, 192 are oppositely doped. The dopant concentrations in the first and second regions 191, 192 and their dimensions are selected such that the charge carriers in the superjunction structure 190 approximately compensate for one another and the superjunction structure 190 is completely depleted at voltages below the maximum reverse voltage of a semiconductor device obtained from the semiconductor substrate 500a.

[0044] Interfaces between the first and second regions 191, 192 in the device region 610 form compensation pn junctions pnx. In the kerf region 690, the selective epitaxy forms an alignment structure 202 in one or more second trenches 182 of Fig. 2B. The epitaxy also fills the first and second mask openings 418, 419 in the epitaxial mask 450 and may overgrow the epitaxial mask 450 to some extent.

[0045] A planarization process stopping at the epitaxial mask 450 can remove or ablate portions or parts of the filling material that lie outside the first and second trenches 181, 182 and outside the first and second mask openings 418, 419 of the epitaxial mask 450 of Fig. 2C. The planarization process may include CMP (chemical mechanical polishing).

[0046] Fig. 2D shows the planarized surface of the semiconductor substrate 500a, with top surfaces of the first regions 191 aligned with the exposed surface of the epitaxial mask 450. The top surfaces of the first regions 191 and the exposed surface of the epitaxial mask 450 form a continuous plane.

[0047] A resist layer may be deposited and patterned by photolithography to form a device mask 420 covering at least the device region 610. A mask opening 429 in the device mask 420 exposes a portion of the kerf region 690 around the alignment structure 202, including a second portion of the epitaxial mask 450. Since a distance between the superjunction structure 190 and the alignment structure 202 is significantly greater than a distance between adjacent first regions 191 of the superjunction structure 190, an acceptable misalignment of the mask opening 429 in the device mask 420 is comparatively large, and the lithography processes involved are uncritical.

[0048] Using the device mask 420 as an etch mask, either the exposed second portion of the epitaxial mask 450 may be selectively removed with respect to the fill material of the alignment structure 202 or the fill material of the alignment structure 202 may be excluded with respect to an epitaxial mask 450.

[0049] Fig. 2F relates to the local removal of the second portion of the epitaxial mask 450 in the kerf region 690, exposing steps 201 between the main surface 101a and the alignment structure 202. The steps 201 are approximately vertical and have a vertical extension or height hs corresponding to the layer thickness of the epitaxial mask 450, which may be in a range from 50 nm to 2 µm, for example, in a range from 100 nm to 500 nm. The structured surface around the protruding alignment structure 202, and including the steps 201, forms an alignment mark 200 with increased contrast. Due to the sharp-edged steps 201 and the significant height of the steps 201, the alignment mark 200 provides high optical contrast.

[0050] In the device region 610, a remaining first portion of the epitaxial mask 450 is removed along with portions of the fill material in the same horizontal plane, so that (i) a resulting surface in the device region 610 remains planar and (ii) the steps 201 of the alignment mark 200 are preserved with increased contrast. For example, a plasma etching process may uniformly depress the planar surface in the device region 610 and the stepped surface in the kerf region 690 regardless of the different materials of the epitaxial layer 450 and the first regions 191. For example, the plasma process may etch an epitaxial mask 450 made of silicon oxide and crystalline silicon of the first regions 191 at the same rate.

[0051] Fig. 2G shows the planar surface of the superjunction structure 190 forming part of a foundation in the device region 610, as well as the preserved steps 201 of the alignment mark 200 with increased contrast in the kerf region 690.

[0052] An optical method may capture position information based on the enhanced-contrast alignment mark 200. For example, the optical method captures an image of the enhanced-contrast alignment mark 200 and may align the image with predefined position information to align the semiconductor substrate 500a with an exposure instrument used to pattern a superstructure based on the superjunction structure 190.

[0053] One or more opaque layers that map the contour of the alignment mark 200 in an exposed surface of the one or more opaque layers may cover the alignment mark 200, wherein a surface relief of the one or more opaque layers may distort and / or shift the contour of the alignment mark 200 in a reproducible and predictable manner.

[0054] Alternatively or additionally, layers that are transparent in an inspection wavelength range used by exposure instruments for evaluating alignment marks may cover the alignment mark 200. The transparent layers may be gap-filling layers that do not map the shape of the alignment mark at all into a surface relief in the exposed surface of the one or more transparent layers, or that map the shape of the alignment mark only in a non-reproducible and unpredictable manner.

[0055] For example, an epitaxial layer 100b may be formed on the main surface 101a and reproducibly maps the alignment mark 200 onto an exposed epitaxial layer 101b. A conformal gate dielectric layer 151a may be formed on the exposed epitaxial layer 101b by thermal oxidation, and a conformal conductive layer 155a, for example, a doped polycrystalline silicon layer, may be formed on the conformal gate dielectric layer 151a.

[0056] Fig. 2H shows the epitaxial layer 100b with a thickness less than 5 µm, for example less than 3 µm, the conformal gate dielectric layer 151a and the conformal conductive layer 155a, which map the alignment mark 200 into an exposed surface of the conformal conductive layer 155a.

[0057] By using the optical response from the enhanced contrast alignment mark 200 imaged into the exposed surface of the conformal conductive layer 155a, masks for creating the superstructure, e.g., for patterning elements of transistor cells TC, can be precisely aligned to the base.

[0058] For example, after deposition of a gate mask layer on the uniform or conformal conductive layer 155a, a photolithography process may evaluate the optical response of the alignment mark 200 with enhanced contrast to form a gate mask 430 with gate mask openings 439 in the vertical projection of the first regions 191 of the superjunction structure 190. By using the gate mask 430 as an etch mask for anisotropic etching, gate structures 150 may be formed from the conformal conductive layer 155a.

[0059] Fig. Figure 2I shows the gate structures 150 formed from the conformal conductive layer 155a. Due to the strong, high-contrast signal from the enhanced-contrast alignment mark 200, the gate mask 430 can be reliably aligned to the second regions 192, such that distances between the gate structures 150 and the adjacent first regions 191 of the superjunction structure 190 deviate only slightly from a mean value. Before or after formation of the gate structure 150, the enhanced-contrast alignment mark 200 can also be used for implantations to create doped regions of the transistor cells.

[0060] Fig. 3A to 3B refer to a selective recess or regression of a second portion of the epitaxial mask 450 in the cut edge region 690 as in Fig. 2F. Instead of removing the epitaxial mask 450, the masked etch selectively removes or ablates the alignment structure 202 with respect to the epitaxial mask 450. After removing the device mask 420, a plasma etch process or a planarization process may remove the epitaxial mask 450 non-selectively relative to the fill material in both the device region 610 and the kerf region 690.

[0061] Fig. 3B shows the resulting alignment mark 200 with increased contrast in the kerf area 690 with vertical steps 201 between the recessed alignment structure 202 and the surrounding portion of the semiconductor layer 100a.

[0062] The Fig. 4A to 4H utilizes different etching properties of the different materials that are deposited in the device region 610 after the planarization process of Fig. 2D are exposed for narrowly defined patterning processes, whereas alignment of less narrowly defined patterning processes for the superstructure can be based on conventional alignment marks or an alignment mark 200 with increased contrast as described above.

[0063] Narrowly defined patterning processes may directly align portions of the superstructure to individual first and second regions 191, 192, for example, individual gate structures to individual second regions 192. Less narrowly defined patterning processes may, for example, distinguish within each device region 610 between a transistor cell region comprising active transistor cells through which a load current flows in an on-state, on the one hand, and a termination region without active transistor cells, on the other hand. Less narrowly defined patterning processing may also be processed using intermediate structures to increase the allowable range for horizontal deviations.

[0064] A superjunction structure 190 may be formed in the semiconductor layer 100a of a semiconductor substrate 500a as described with reference to Fig. 2A to 2D. An auxiliary mask layer, for example, a resist layer, may be deposited and patterned by photolithography to form a mask 460 for a transistor cell region.

[0065] As in Fig. As illustrated in FIG. 4A, the transistor cell region mask 460 may cover a termination region 619 of a device portion 610, wherein the termination region 619 may directly adjoin a kerf region, and wherein the superjunction structure 190 extends into a portion of the termination region 619. A mask opening 461 of the transistor cell region mask 460 exposes a transistor cell region 611.

[0066] Using the mask 460 for a transistor cell region as an etch mask, different etch properties of the epitaxial mask 450 and the crystalline semiconductor material of the first regions 191 are utilized to create steps 203 in the transistor cell region 611. For example, a portion of the epitaxial mask 450 in the transistor cell region 611 may be locally removed with respect to the crystalline semiconductor material of the first regions 191, or the crystalline semiconductor material of the first regions 191 may be selectively excluded with respect to the epitaxial mask 450.

[0067] According to the Fig. 4B, the portion of the epitaxial mask 450 in the transistor cell region 611 is removed to form steps 203 between the first regions 191 and the second regions 192 of the superjunction structure 190.

[0068] A plasma etch may remove a portion of the epitaxial mask 450 in the termination region 619 and uniformly lower the surface in the termination region 619 and the transistor cell region 611 without planarizing the steps 203 in the transistor cell region 611.

[0069] Fig. 4C shows the preserved steps 203 in the transistor cell region 611 and the planar termination region 619 from which a part of the epitaxial mask 450 in the termination region 619 has been removed.

[0070] A conformal mask layer 470a may be deposited, lining the steps 203 between the first and second regions 191, 192 of the superjunction structure 190. The conformal mask layer 470a may be an oxide layer, for example, a silicon oxide layer formed using TEOS as a precursor material.

[0071] Fig. 4D shows the conformal mask layer 470a covering the main surface 101a and lining the steps 203 in the transistor cell region 611 at a uniform layer thickness. A layer thickness of the conformal mask layer 470 may be in a range of 5% to 45% of the width of the second regions 192, for example, in a range of 50 nm to 1 µm. In the transistor cell region 611, the conformal mask layer 470a lines notches 473 in the vertical projection of the second regions 192, wherein a width of the notches 473 is equal to the width of the second regions 192, reduced by twice the layer thickness of the conformal mask layer 470a.

[0072] An auxiliary mask layer may be deposited and patterned by photolithography to form an auxiliary hard mask 480 covering at least complete portions of the conformal mask layer 470a in the vertical projection of the first regions 191. Mask openings 481 in the auxiliary hard mask 480 expose at least the notches 473 lined by the conformal mask layer 470a. Alignment of the auxiliary hard mask 480 allows comparatively high deviations in a range of half the thickness of the conformal mask layer 470a and is a less tightly defined patterning process.

[0073] Patterning the auxiliary hard mask 480 may utilize (i) a conventional alignment mark formed before or after creation of the superjunction structure 190, (ii) an alignment mark as described with reference to Fig. 2E or Fig. 3B or may (iii) use a signal from the depicted stages 203 in the transistor cell region 611 to adjust the mask openings 481 to the superjunction structure 190.

[0074] As in Fig. As illustrated in Figure 4E, mask openings 481 in the auxiliary hard mask 480 expose the notches 473 lined by the conformal mask layer 470a. The auxiliary hard mask 480 may be made of or include a silicon nitride layer.

[0075] A highly anisotropic etch of the material of the conformal mask layer 470a with a high etch selectivity against the material of the auxiliary hard mask 480 forms a spacer mask 470 from the conformal mask layer 470a.

[0076] According to Fig. 4F, the spacer mask 470 comprises spacer mask openings 471 which are self-aligned or self-aligned to adjacent first regions 191 according to sufficiently aligned mask openings 481 in the auxiliary hard mask 480.

[0077] Gate trenches 150a may be etched into the semiconductor layer 100a, with the spacer mask 470 effective as an etch mask.

[0078] Fig. 4G shows the gate trenches 150a formed in the second regions 192 in a vertical projection of the spacer mask openings 471. The gate trenches 150a have the same distance from both adjacent first regions 191.

[0079] Fig. 4H shows gate structures 150 formed in gate trenches 150a and comprising a conductive gate electrode 155 and a gate dielectric 151 separating gate electrode 155 from semiconductor layer 100a. Based on gate trenches 150a or based on structures derived from spacer mask 470 or gate trenches 150a, doped regions and contacts for transistor cells may be created before or after formation of gate structures 150.

[0080] Although the embodiment may utilize an alignment mark for the formation of the auxiliary hard mask 480, the gate trenches 150a are self-aligned to the superjunction structure 190, and tight alignment tolerances can be met as long as the relatively uncritical tolerance condition for the mask openings 481 in the auxiliary hard mask 480 is met, that is, as long as the misalignment is considerably less than the thickness of the conformal mask layer 470a.

[0081] Fig. 5A and Fig. 5B show alignment dependencies for first patterning processes I for creating a base containing a superjunction structure and second patterning processes II for creating a superstructure that may include transistor cells, wherein the superstructure may be created at least partially in an epitaxial layer grown on the base after creation of the superjunction structure.

[0082] A first lithography process 750 defines, in a base I, a superjunction structure FSJ and an alignment mark FAlgn, which are formed simultaneously. The superjunction structure FSJ and the alignment mark FAlgn result from the same exposure process. From the alignment mark FAlgn, a contrast enhancement process 760 forms an alignment mark EnhAlgn with increased contrast, using non-critical or only slightly critical lithography processes. Second lithography processes 770 form termination structures Trm, e.g., JTEs (junction termination extensions), using exposure masks aligned to the alignment mark EnhAlgn with increased contrast.Alternatively, the termination structures Trm may be aligned with the original alignment mark FAlgn, and the enhanced contrast alignment mark EnhAlgn is formed only at the end of the patterning processes concerning the base I. Third lithography processes 780 may, among other things, define transistor cells TC in a superstructure II by utilizing exposure masks brought into alignment with the enhanced contrast alignment mark EnhAlgn.

[0083] In Fig. 5A, all third lithography processes 780 operating on superstructure II can be aligned to the alignment mark EnhAlgn with increased contrast.

[0084] In Fig. 5B, a first subset 782 of the third lithography processes 780 may be aligned to the superjunction structure FSJ itself and formed without utilizing a further exposure process. A second subset 784 of the third lithography processes 780 with relaxed tolerance constraints may be based on any of the previously formed alignment marks, for example, on the enhanced-contrast alignment mark EnhAlgn.

[0085] Fig. 6 shows a semiconductor substrate 500a for the fabrication of superjunction semiconductor devices, which may be or include IGFETs, IGBTs, or power semiconductor diodes. The semiconductor substrate 500a may be a semiconductor wafer at any processing stage after creating (i) superjunction structures 190 in a plurality of device regions 610 and (ii) at least one alignment mark 200 with enhanced contrast in a kerf region 690, wherein the kerf region 690 forms a grid enclosing individual device regions 610 in the mesh.

[0086] The semiconductor substrate 500a may consist of or include a semiconductor layer 100a of a semiconductor material, such as crystalline silicon. The semiconductor substrate 500a may further comprise conductive, dielectric, or semiconducting portions. For example, the semiconductor layer 100a is an n-doped epitaxial layer formed on a substrate portion 105a obtained from a semiconductor ingot. The substrate portion 105a may be thinned or completely removed or ablated during processing.

[0087] The semiconductor layer 100a may include a drift structure 120 of a first conductivity type. A dopant concentration in the drift structure 120 may gradually increase or decrease in steps with increasing distance from a main surface 101a of the semiconductor layer 100a on a front side of the semiconductor substrate 500a, at least in sections of its vertical extent. According to other embodiments, the dopant concentration in the drift structure 120 may be approximately uniform. An average dopant concentration in the drift structure 120 may be between 5E12 cm -3 and 1E15 cm -3 , for example in a range of 5E13 cm -3 up to 5E14 cm -3 , lay.

[0088] In the device regions 610, the drift structure 120 contains superjunction structures 190, which are effective as compensation structures and comprise first regions 191 of a first conductivity type and second regions 192 of a complementary second conductivity type. The first regions 191 may be formed by depositing a suitable dopant-containing fill material into trenches temporarily formed in the drift structure 120, for example, by depositing a doped semiconductor layer along sidewalls of temporary trenches or by diffusing dopants from the semiconductor layer 100a into a lightly doped or intrinsic semiconductor material that fills temporary trenches. The second regions 192 may consist of more highly doped sections orPortions of the drift structure 120 between the trenches can be formed, for example, by depositing a doped semiconductor layer along the sidewalls of temporary trenches, by diffusing dopants from the semiconductor layer 100a into lightly doped or intrinsic semiconductor material that fills temporary trenches, or by depositing fill material containing suitable dopants into temporary trenches. The fill material can be, for example, doped single-crystal semiconductor material.

[0089] The first and second regions 191, 192 alternate along at least one horizontal direction. According to one embodiment, surfaces connecting points of the same dopant concentration in the first and second regions 191, 192 are not corrugated and do not exhibit concave sections or notches, as do surfaces connecting points of the same dopant concentration in the semiconductor regions of superjunction structures resulting from a multiple epitaxy / multiple implantation process.

[0090] The integrated spatial dopant concentrations across the first and second regions 191, 192 are approximately equal, so that the effects of complementary charge carriers cancel each other out to a large extent and a portion of the drift structure 120 containing the superjunction structure 190 can be completely depleted in a blocking state of the semiconductor devices obtained from the semiconductor substrate 500a.

[0091] Portions of transistor cells or complete transistor cells may be formed in portions of the device regions 610 along the main surface 101a. The illustrated embodiment refers to a process stage of the semiconductor substrate 500a after formation of gate structures 150 in the device regions 610.

[0092] The gate structures 150 may be lateral gates formed outside the semiconductor layer 100a along the main surface 101a, as illustrated. According to another embodiment, the gate structures 150 may be trench gates extending from the first surface 101 into the semiconductor layer 100a.

[0093] The gate structures 150 may include a conductive gate electrode 155, which may include or consist of a highly doped polycrystalline silicon layer or a metal-containing layer. The gate structures 150 further include a gate dielectric 151 that separates the gate electrode 155 from the semiconductor portion 100. The gate dielectric 151 may include or consist of a semiconductor oxide, for example, thermally grown or deposited silicon oxide, a semiconductor nitride, for example, deposited or thermally grown silicon nitride, a semiconductor oxynitride, for example, silicon oxynitride, or a combination thereof.

[0094] The kerf region 690 includes an alignment mark 200 with increased contrast having vertical or nearly vertical steps 201. The steps 201 are formed along sidewalls of an alignment structure 202 that protrudes from a directly adjacent portion of the semiconductor layer 100a.

[0095] The portion of the semiconductor layer 100a directly adjacent to the alignment structure 202 may be exempted from a portion of the semiconductor layer 100a comprising the superjunction structure 190. A surface of the alignment structure 202 may be aligned with the corresponding surface of the superjunction structure 190. A vertical extension hs of the step 201 is at least 50 nm, for example, at least 200 nm.

[0096] The material of the alignment structure 202 is the same as that of the first regions 191 of the superjunction structures 190 in the device regions 610, for example, a doped crystalline semiconductor material such as single-crystalline silicon, which may be p-doped and which may result from an epitaxial process.

[0097] The dimensions of the alignment structure 202 may be the same as or different from those of the first regions 191 in the superjunction structures 190. A horizontal cross-section of the alignment structure 202, parallel to the first surface 101, may be a rectangle.

[0098] The alignment mark 200 may comprise a plurality of separate alignment structures 202, which may be arranged, for example, parallel to one another, like a cross or like a rectangle.

[0099] The alignment mark 200 may be exposed, may be covered by one or more opaque layers that image the step 201 into the exposed surface of the one or more opaque layers, and / or may be covered by a gap-filling layer that is transparent at an inspection wavelength or in an inspection wavelength range used by an exposure instrument to obtain position information about the alignment mark 200.

[0100] In the illustrated embodiment, an epitaxial layer 100b having a thickness of less than 10 µm and formed on the main surface 101a maps the original alignment mark 200 into an epitaxial surface 101b, and a conformal and transparent silicon oxide layer forming the gate dielectric in the device region 610 covers the alignment mark 200 mapped into the epitaxial surface 101b. Further dielectric layers, for example, an interlayer dielectric comprising layers of silicon oxide and / or silicate glasses, may cover the gate structures 150 and the alignment mark 200 mapped into the epitaxial surface 101b.

[0101] Fig. 7 shows a semiconductor device 500, which may be or comprise an IGFET, an IGBT, or a power semiconductor diode. In an active region 614 of the semiconductor device 500, functional transistor cells TC or an anode zone of a power semiconductor diode are formed, through which a load current flows directly in an on-state or forward mode of the semiconductor device 500. An inactive region 615 is free of functional transistor cells and free of an anode zone of a power semiconductor diode, and in an on-state or forward mode, no load current flows directly through the inactive region 615. The inactive region 615 may be a portion of the semiconductor device 500, for example, in or beyond a termination region or beneath gate conductors. According to one embodiment, the inactive region 615 may be a remnant of a kerf region.The inactive area 615 contains an alignment mark 200 with increased contrast as discussed above.

[0102] The semiconductor device 500 may include a semiconductor portion 100 made of a semiconductor material such as crystalline silicon. The semiconductor portion 100 may include a drift structure 120 with a superjunction structure 190 having first and second regions 191, 192 as described with reference to Fig. 6, and may contain further conductive, dielectric or semiconducting sections.

[0103] Transistor cells TC may be formed in the semiconductor section 100 along the first surface 101. The transistor cells TC may be formed on trench gates or planar gates with gate structures 150 as described with reference to Fig. 6 described.

[0104] The transistor cells TC comprise body zones 115 of the second conductivity type. The body zones 115 form first pn junctions pn1 with the second regions 192 of the superjunction structure 190 and second pn junctions pn2 with source zones 110. The body zones 115 may be wells that extend from the first surface 101 into the semiconductor section 100. The source zones 110 may be wells that extend from the first surface 101 into the body zones 115. The source zones 110 and the body zones 115 may be electrically connected to a first load electrode L1. The gate dielectric 151 capacitively couples the gate electrode 155 to channel sections of the body zones 115.

[0105] Along a second surface 102 opposite the first surface 101, the semiconductor section 100 may include a highly doped contact layer 129 electrically connected to a second load electrode L2. A field stop layer 128 with a lower dopant concentration than the contact layer 129 may be sandwiched between the contact layer 129 and a lightly doped drift zone 121.

[0106] The inactive area 615 includes an alignment mark 200, as described with reference to Fig. 6. An interlayer dielectric 210 may cover the alignment mark 200 and the gate structures 150.

[0107] Fig. 8A shows an alignment mark 200 with multiple parallel alignment structures 202.

[0108] In Fig. 8B, the alignment mark 200 comprises four separate alignment structures 202 arranged in a cross shape.

[0109] In Fig. 8C, the four separate alignment structures 202 form a rectangular frame.

[0110] Although specific embodiments are illustrated and described herein, it will be understood by those skilled in the art that a variety of alternative and / or equivalent designs may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is therefore intended to cover any adaptations or modifications of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Forming a trench mask (410) by forming mask openings (418, 419) in a trench mask layer on a semiconductor layer (100a); Forming, by using the trench mask (410), first and second trenches (181, 182) extending in a vertical projection of the mask openings (418, 419) from a main surface (101a) into the semiconductor layer (100a); Forming a base comprising first regions (191) in and / or directly adjacent to the first trenches (181), wherein a fill material forming structures in the first and second trenches (181, 182) fills the mask openings (418, 419); Performing an etching process selective with respect to the fill material to form at least steps (203) on the first trenches (181) in a device region (610) or steps (201) on the second trenches (182) in a kerf region (690); and Forming a superstructure in alignment with the base by using positional information obtained directly from steps (201, 203). [2] The method of claim 1, further comprising: selectively removing the trench mask (410) with respect to the fill material in the mask openings (418, 419) to form the steps (201, 203) exposing sidewalls of the fill material. [3] The method of claim 1, further comprising: selectively forming back the fill material with respect to the trench mask (410) to form the steps (201, 203) exposing sidewalls of the semiconductor layer (100a). [4] A method according to any one of claims 1 to 3, further comprising: Forming a spacer mask (470) with mask spacers along side walls of the steps (203) and a spacer mask opening (471) between the steps (203). [5] The method of claim 4, further comprising: Forming a gate trench (150a) in the semiconductor layer (100a) in a vertical projection of the spacer mask opening (471). [6] The method according to any one of claims 1 to 3, wherein the position information is derived by using an optical method from alignment structures (202) formed by filling the second trenches (182), the alignment structure (202) being part of an alignment mark (200). [7] The method of claim 6, further comprising: Determining position information from the alignment structure (202) to align a photomask for patterning gate structures (150) in alignment with the alignment mark (200). [8] The method of claim 6 or 7, wherein forming the alignment structure (202) comprises selectively removing a second portion of the trench mask (410), the second portion of the trench mask (410) directly adjacent to the alignment structure (202), with respect to a first portion of the trench mask (410) directly adjacent to the first regions (191). [9] The method of claim 8, wherein selectively removing the second portion of the trench mask (410) comprises depositing a device mask (420) on the trench mask (410) and patterning the device mask (420) by photolithography, wherein a minimum distance between adjacent first and second trenches (181, 182) is greater than a distance between adjacent first trenches (181). [10] A method according to any one of claims 8 or 9, further comprising: uniformly stripping or removing the first part of the trench mask (410) and the exposed sections of the first regions (191) at an equal removal rate. [11] The method of claim 10, wherein the trench mask (410) contains silicon oxide, the fill material forming the first region (191) is crystalline silicon, and a uniform removal of the trench mask (410) and the fill material comprises plasma etching. [12] The method of any one of claims 1 to 11, wherein the first regions (191) are doped regions of a first conductivity type. [13] The method of claim 12, further comprising: Forming doped second regions (192) in the semiconductor layer (100a). [14] The method of claim 13, wherein the first and second regions (191, 192) form a superjunction structure (190). [15] Semiconductor substrate comprising: a superjunction structure (190) in a device region (610) of a semiconductor layer (100a), wherein the superjunction structure (190) comprises first regions (191) and second regions (192) of an opposite conductivity type, wherein the first and second regions (191, 192) alternate along at least one horizontal direction, and wherein the first regions (191) are formed from trench-deposited fill material containing dopants; and an alignment mark (200) in a kerf region (690) of the semiconductor layer (100a), wherein the alignment mark (200) comprises vertical steps (201) formed by an alignment structure (202) protruding or recessed from a main surface (101a) of the semiconductor layer (100a), and wherein the alignment structure (202) consists of the material of the first regions (191) of the superjunction structure (190). [16] The semiconductor substrate of claim 15, wherein a vertical extent of the alignment structure (202) is equal to a vertical extent of the first regions (191). [17] A semiconductor substrate according to any one of claims 15 or 16, wherein the alignment structure (202) comprises separate strip-shaped parts. [18] Semiconductor substrate according to one of claims 15 to 17, wherein a vertical extension of the step (201) is at least 50 nm. [19] A semiconductor device comprising: a superjunction structure (190) in an active region (614) of a semiconductor section (100), wherein the superjunction structure (190) comprises first regions (191) and second regions (192) of an opposite conductivity type, wherein the first and second regions (191, 192) alternate along at least one horizontal direction, and wherein the first regions (191) are formed from trench-deposited fill material containing dopants; and an alignment mark (200) in an inactive region (615) of the semiconductor section (100), wherein the alignment mark (200) has vertical steps (201) formed by an alignment structure (202) that protrudes or is recessed from a first surface (101) of the semiconductor section (100), and wherein the alignment structure (202) consists of the material of the first regions (191) of the superjunction structure (190). [20] The semiconductor device of claim 19, wherein a vertical extent of the alignment structure (202) is equal to a vertical extent of the first regions (191). [21] A semiconductor device according to any one of claims 19 or 20, wherein a vertical extension of the step (201) is at least 50 nm. [22] A method of manufacturing a semiconductor device, the method comprising: Forming a trench mask (410) by forming mask openings (418, 419) in a trench mask layer on a semiconductor layer (100a); Forming, by using the trench mask (410), first and second trenches (181, 182) extending in a vertical projection of the mask openings (418, 419) from a main surface (101a) into the semiconductor layer (100a), wherein the first trenches (181) are formed in a device region (610) and the second trenches (182) are formed in a kerf region (690); Forming a base with a superjunction structure (190), wherein the superjunction structure (190) comprises doped first regions (191) in and / or directly adjacent to the first trenches (181) and oppositely doped second regions (192), wherein the first and second regions (191, 192) alternate along at least one horizontal direction parallel to the main surface (101a), wherein a fill material forming structures in the first and second trenches (181, 182) fills the mask openings (418, 419); in at least the device region (610) or the kerf region (690) (i) removing the trench mask (410) with respect to the filler material in the mask openings (418, 419) to form steps (201, 203) exposing sidewalls of the filler material or (ii) regressing the filler material with respect to the trench mask (410) to form steps (201, 203) exposing sidewalls of the semiconductor layer (100a); and Forming a superstructure in alignment with the base by utilizing position information directly obtained from structures formed in at least one of the first and second trenches (181, 182).

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