CONTROLLING MULTIPLE LIGHT SOURCES

Abstract

A device for controlling a plurality of light sources (206) arranged in a matrix structure (101, 201), the device being a semiconductor device (102, 205) comprising: - a shift register having at least two cells, an output of each cell controlling one of the plurality of light sources (206); - wherein the at least two cells are connected in series and controlled by a clock signal; - wherein each cell of the shift register comprises a flip-flop and a register; - where the output of the flip-flop is connected to the input of the register; - wherein the register is arranged to store the output of the register based on an update signal and wherein the output of the register controls one of the light sources (206); - wherein the flip-flops of the at least two cells are filled with a data signal on the basis of the clock signal; - wherein after a predetermined number of cycles of the clock signal, the update signal is supplied to the registers which control the light sources (206) according to the values ​​stored in the flip-flops of the cells; - in which the cells of the shift registers are part of a semiconductor device (102, 205), wherein a matrix structure (101, 201) with the plurality of light sources (206) is arranged above the semiconductor device (102, 205); - wherein the semiconductor device (102, 205) comprises a driver for each light source of the matrix structure (101, 201); - in which the driver for each light source of the matrix structure (101, 201) comprises a current mirror to which at least one reference current is supplied; - in which the at least one reference current is generated in a common region of the semiconductor device (102, 205) and is supplied to all drivers for the light sources (206) of the matrix structure (101, 201); - in which the cell of the shift register and the driver associated with an individual light source of the matrix (101, 201) are arranged on an area having a size corresponding to the size of the area of ​​the individual light source of the matrix (101, 201).

Description

[0001] Embodiments of the present invention relate to a device for controlling multiple light sources. The light sources can, in particular, be LEDs arranged in a matrix structure (LED array).

[0002] US 8,692,758 B2 relates to a time signal used for a display operation of a display device.

[0003] US 7,372,440 B2 relates to an active matrix display device that performs signal writing via current signals.

[0004] US 6,380,687 B1 relates to an electroluminescent display consisting of a semiconductor element incorporated in a substrate and an electronic device having the electroluminescent display.

[0005] One particular task is to improve the control of a large number of light sources.

[0006] This object is achieved according to the features of the independent claims. Preferred embodiments can be found in particular in the dependent claims.

[0007] These examples proposed herein may, in particular, be based on at least one of the following solutions. In particular, combinations of the following features may be used to achieve a desired result. The features of the method may be combined with any feature(s) of the device, apparatus, or system, or vice versa.

[0008] A device for controlling a plurality of light sources arranged in a matrix structure is proposed, the device being a semiconductor device comprising: - a shift register having at least two cells, an output of each cell controlling one of the plurality of light sources; - wherein the at least two cells are connected in series and controlled by a clock signal; - wherein each cell of the shift register comprises a flip-flop and a register; - where the output of the flip-flop is connected to the input of the register; - wherein the register is arranged to store the output of the register based on an update signal and wherein the output of the register controls one of the light sources; - wherein the flip-flops of the at least two cells are filled with a data signal on the basis of the clock signal; - wherein after a predetermined number of cycles of the clock signal, the update signal is supplied to the registers which control the light sources according to the values ​​stored in the flip-flops of the cells; - in which the cells of the shift registers are part of a semiconductor device, wherein a matrix structure with the plurality of light sources is arranged above the semiconductor device; - wherein the semiconductor device comprises a driver for each light source of the matrix structure; - in which the driver comprises a current mirror for each light source of the matrix structure to which at least one reference current is supplied; - in which the at least one reference current is generated in a common region of the semiconductor device and is supplied to all drivers for the light sources of the matrix structure; - in which the cell of the shift register and the driver associated with an individual light source of the matrix are arranged on an area having a size corresponding to the size of the area of ​​the individual light source of the matrix.

[0009] A flip-flop (also called a latch) is a two-state stable circuit that can be used to store state information. Signals applied to one or more control inputs can cause the circuit to change state, and it can have at least one output.

[0010] The flip-flop is a simple storage element that can be used in sequential logic.

[0011] It should be noted that the register can be implemented as a flip-flop. The register can be any means for storing information; in particular, the stored information can be used (only) to control the light source, where the light source can be directly or indirectly coupled to the register's output. For such purposes, the register can include an input to which the update signal can be applied; an active update signal can then cause the register's input to be routed to its output to appropriately control the light source connected to the register's output.Applying the update signal to multiple registers simultaneously results in the control of multiple light sources, each supplied via an output of a separate register at such a time; the output for controlling the respective light sources comes from the flip-flops to which the data signal was supplied over several cycles of the clock signal.

[0012] It is further noted that the flip-flops of the shift register are filled with the data signal based on the clock signal as follows: the data signal comprises a stream of values ​​"0" and "1", which are passed sequentially into the shift register: a first clock signal allows a first value of the data signal to enter the first flip-flop of the shift register. With a second clock signal, the first value of the data signal is transmitted from the first flip-flop to the second flip-flop of the shift register, and the second value of the data signal is stored in the first flip-flop. The stream of values ​​"0" or "1" is therefore subsequently passed through the at least two flip-flops of the shift registers, with each clock cycle, e.g. a rising edge of the clock signal, triggering the shift operation.

[0013] Therefore, the approach allows for a matrix device with a (shift) register functionality for individually accessing pixels of a matrix, where each pixel includes a light source. This shift register allows serial-to-parallel conversion when addressing the pixels based on the clock signal.

[0014] It is a further development that the flip-flop is a D flip-flop and the register is an additional D flip-flop, with the update signal being fed to the clock terminal of the additional D flip-flop.

[0015] It is a further development that the matrix contains at least two rows and at least two columns.

[0016] It is a further development that each light source of the matrix is ​​assigned a cell of the shift registers.

[0017] It is a further development that the cells of the shift register are part of a semiconductor device, wherein the matrix structure comprising the plurality of light sources is arranged next to the semiconductor device.

[0018] Therefore, the matrix structure and the semiconductor device can be located side by side, side by side, or close to each other.

[0019] Therefore, the driver and shift register cell configured for the individual light source can be located on the semiconductor device below the light source, but require no more than the area of ​​the semiconductor device corresponding to the area of ​​that light source. This allows the array of light sources (e.g., LED array) to be deployed on the semiconductor device and the light sources of the array structure to be connected to their respective cells.

[0020] The solution presented here allows an area-efficient implementation of the components on the semiconductor device required to operate the single light source of the matrix structure.

[0021] The driver may comprise a current source and / or a current mirror for driving a single light source.

[0022] The shift register cell can be part of a pixel addressing block as described here.

[0023] It is a further development that the semiconductor device comprises a common circuit for the light sources of the matrix structure.

[0024] It is a further development that the common circuit is arranged in an area next to the shift register.

[0025] It is a further development that each light source comprises at least one semiconductor light source, in particular at least one LED.

[0026] It is a further development that the device is an integrated circuit, which is realized in particular as a single chip.

[0027] Also provided is a system comprising a matrix structure having a matrix of light sources and a device as described herein, such device being a semiconductor device comprising: - a pixel cell circuit on a first region over which a matrix structure comprising a matrix of light sources is connected, and - a common circuit on a second region arranged adjacent to the first region, the common circuit being configured to operate and / or power the pixel cell circuit.

[0028] Embodiments are shown and illustrated with reference to the drawings. The drawings serve to illustrate the basic principle, so only aspects necessary for understanding the basic principle are shown. The drawings are not to scale. In the drawings, the same reference numerals designate the same features. Fig. 1 shows an exemplary arrangement with an LED array placed over a semiconductor device; Fig. 2 shows an exemplary block diagram with a matrix of LEDs and a semiconductor device with an LED driver matrix and a common circuit; Fig. 3 shows high-side current sources, each arranged on the LED driver matrix, on which LEDs are mounted; Fig. 4 shows an exemplary pixel addressing circuit that may be arranged on the semiconductor device for two pixel cells n and n+1; Fig. 5 shows a schematic block diagram of a pixel cell with a pixel addressing block, a driver and a comparator; Fig. 6 shows an exemplary block diagram of a pixel cell that is based on the Fig. 5, but does not include any diagnostic functionality; Fig. Figure 7 shows an exemplary implementation of the pixel addressing block; Fig. 8 shows an example implementation of the driver; Fig. 9 shows an example implementation of the comparator.

[0029] Light sources, e.g., semiconductor light sources or LEDs (light-emitting diodes), can be arranged together as an array. The array of light sources can be arranged above a semiconductor device (array) designed as a control circuit for the light sources. The light sources can be mounted on the semiconductor device. If the semiconductor device provides a current source for each light source, such a current source can be individually controlled to enable control of the respective light source.

[0030] Fig. 1 shows an exemplary arrangement with an LED array 101 placed over a semiconductor device 102. The semiconductor device 102 may be arranged on a printed circuit board (PCB) 104; it may be electronically connected via bond wires 103. The LED array 101 mounted on the semiconductor device 102 is also referred to as a chip-on-chip assembly.

[0031] The semiconductor device 102 may include at least one of the following alternatives: - current sources for the individual LEDs arranged on the LED array 101, in particular at least one current source for each LED; - a communication interface for controlling the LEDs and for management purposes; - generation of at least one reference current; and - Diagnostic and protection functionality.

[0032] For this purpose, semiconductor device 102 may comprise an array of silicon cells, where each silicon cell (also referred to as a pixel cell) may comprise a current source that may be directly connected to an LED of LED array 101. Additionally, semiconductor device 102 may comprise a common circuit.

[0033] Fig. 2 shows an exemplary representation with a matrix 201 of LEDs 206 (each pixel of the matrix can be represented by at least one LED) and a semiconductor device 205, which includes an LED driver matrix 202 (i.e., a part of the semiconductor device associated with a pixel of the LED array 101) and a common circuit 203. The semiconductor device 205 can be connected to a serial interface 204. The respective LEDs 206 of the matrix 201 can be controlled via the serial interface 204. The matrix 201 can be arranged above the LED driver matrix 202. The LED driver matrix 202 can be part of the Fig. 1 and may include a pixel cell area (also referred to as a "pixel cell") for each LED 206 of the matrix 201. It is possible for the LED driver matrix 202 to have (e.g., substantially) the same area as the matrix 201. In particular, the pixel cell area of ​​the LED driver matrix 202 may have (substantially) the same area as the LED 206. The LEDs 206 of the matrix 201 may be directly connected to the pixel cells of the LED driver matrix 202. In particular, the matrix 201 may be arranged above the LED driver matrix 202.

[0034] The common circuit 203 may in particular comprise a serial interface for accessing the LEDs of the matrix 201, e.g. a register for configuration purposes, a reference current generator, a reference voltage generator and a temperature sensor.

[0035] The matrix 201 may comprise any number of LEDs (pixels) arranged in columns and rows. The matrix 201 may, for example, comprise 256 or 1024 LEDs. In the Fig. In the example shown in Figure 2, the matrix 201 comprises 16 rows and 16 columns of LEDs 206, for a total of 256 LEDs.

[0036] It should be noted that LED is mentioned as an example of a light source. It is possible to use any type of light source, especially a semiconductor light source. Another possibility is that each light source can be a module comprising at least two semiconductor light sources.

[0037] The common circuit 203 may be located in an area adjacent to or remote from the LED driver matrix 202.

[0038] In an exemplary application, each pixel of the LED array 101 may consume an area of, for example, less than 150 µm 2This value is only an example value for an area. Any area suitable for a predetermined resolution of the LED array 101 can be selected. The semiconductor light source can be arranged in the center of each pixel cell. Adjacent pixel cells can have a gap between light sources that is less than 150 µm. Each LED can have one contact connected to the LED driver matrix 202 and one contact connected to a common contact, e.g., GND. This is an example scenario; other dimensions, distances, and connections may apply accordingly.

[0039] If each LED is mounted directly above the semiconductor device, each current source is defined in an area defined by the area of ​​the pixel cell. In the example given above, the area is 150 μm⋅150 μm=0.022500 mm2.

[0040] To increase the resolution in the x and y dimensions (e.g., 0.5°) of the light at large distances and to avoid additional mechanical components for beam leveling adjustment, a short pitch between pixel cells is advantageous. In the example given above, the pitch between pixel cells can be less than 150 µm.

[0041] Due to the compact arrangement, a high amount of heat sources can generate different temperatures, which can affect temperature gradients and therefore lead to mismatch between pixels.

[0042] Additionally, the output of each current source per pixel cell may not be directly accessible because the LED driver matrix is ​​directly connected to the LEDs.

[0043] A solution is therefore required that provides at least one of the following alternatives: - a current source that supplies current to the individual LED, allowing the LED to be switched on or off with high precision, providing overcurrent protection where necessary; - a diagnostic functionality that can detect an open load and a short circuit to ground of the output channel; - a slight mismatch between different pixels, i.e. between different current sources.

[0044] Fig. Figure 3 shows high-side current sources 301 to 303, each arranged on the LED driver matrix, upon which LEDs 304 to 306 are mounted. In this scenario, LED 304 is arranged above current source 301, LED 305 is arranged above current source 302, and LED 306 is arranged above current source 303.

[0045] Each current source 301 to 303 may be an NMOS power stage whose drain is connected to a supply voltage Vcc and whose source is connected to the respective LED 304 to 306. The gate of each NMOS power stage may be controlled by an error amplifier 307 to 309.

[0046] The respective error amplifiers 307 to 309 can be used to control the output current using an internal reference current. The error amplifiers 307 to 309 can be enabled by a digital or analog signal.

[0047] An LED driver matrix can thus comprise an enormous number of current sources and / or switches within the area available for a pixel cell (if the LED driver matrix is ​​located below the LED array).

[0048] The examples provided here demonstrate, in particular, how an efficient solution for the LED array and the underlying LED driver matrix can be realized even when the LED driver matrix is ​​arranged on a silicon semiconductor device (e.g., a single chip). The examples provided specifically address a large number of heat sources as well as thermal gradients between current sources of the pixel cells.

[0049] Examples given here allow the provision of an LED driver matrix which in particular comprises at least one of the following alternatives: - a communication interface to control the drivers for each pixel cell; - an output current control with self-protection against overcurrent; - a diagnostic functionality for open loads and short circuit to ground; and - low temperature sensitivity.

[0050] In particular, this can be achieved by distributing control logic between a common circuit and the LED driver matrix, both integrated on a semiconductor device. The common circuit can be arranged adjacent to the LED driver matrix, and the LED driver matrix can occupy the same surface area as the LED array, which can be arranged above the LED driver matrix as explained above.

[0051] As one possibility, the common circuit can be located in an area adjacent to or remote from the LED driver matrix.

[0052] One issue is how to efficiently drive the current sources, placing (or assigning) one current source to a pixel cell. As shown in the example described above, the distance between two pixel cells (e.g., less than 150 µm) can pose limiting constraints that can make it difficult to electrically connect all current sources located beneath their associated light sources so that they can be driven by the common circuitry of the semiconductor device.

[0053] Fig. Figure 4 shows an exemplary circuit that can be arranged on the semiconductor device for two pixel cells n and n+1. This example suggests that the common circuit provides an update signal UPD, a data signal Data_i, and a clock signal CLK. In the example, pixel cell n provides a data signal Data_i+1 to pixel cell n+1, and pixel cell n+1 provides a data signal Data_i+2 to a subsequent pixel cell (not shown).

[0054] The data signal Data_i is a sequence of binary signals (e.g., "0" and "1") fed to a shift register. Each cell of the shift register can comprise a D flip-flop, i.e., a D flip-flop 401 for pixel n and a D flip-flop 402 for pixel n+1. The data signal Data_i is connected to the D input of D flip-flop 401, and the Q output of D flip-flop 401 is connected to the D input of D flip-flop 402. Both D flip-flops 401 and 402 are also controlled by the clock signal CLK.

[0055] Therefore, a sequence of values ​​"0" and "1" can be supplied to the D flip-flops 401, 402, wherein at each clock cycle (rising edge) of the clock signal CLK, the actual value stored in the D flip-flop 401 is shifted to the subsequent D flip-flop 402 and the next value provided by the data signal Data_i is stored in the D flip-flop 401.

[0056] According to the Fig. In the example shown in Figure 4, a bit sequence of first 0 and then 1 - after two clock cycles - is stored in the D flip-flops 401, 402, so that the D flip-flop 401 has a value "1" and the D flip-flop 402 has the value "0".

[0057] A light source, e.g., LED, for pixel n is controlled via a terminal 404 of a register, e.g., a D flip-flop 403, and a light source, e.g., LED, for pixel n+1 is controlled via a terminal 406 of a register, e.g., a D flip-flop 405. The D input of D flip-flop 403 is connected to the Q output of D flip-flop 401, and the D input of D flip-flop 405 is connected to the Q output of D flip-flop 402. The enable (or clock) inputs of both D flip-flops 403, 405 are connected to the update signal UPD. When the update signal UPD becomes "1," the value stored in D flip-flop 401 becomes visible at the Q output of D flip-flop 403 and is therefore used to control the light source for this pixel n. Accordingly, the value stored in D flip-flop 402 becomes visible at the Q output of D flip-flop 405 and is therefore used to control the light source of pixel n+1.

[0058] Therefore, the exemplary in Fig. The shift register shown in Figure 4 comprises two cells, where the cell for pixel n comprises the D flip-flop 401 and the register 403, and the cell for pixel n+1 comprises the D flip-flop 402 and the register 405. The register can be implemented as a flip-flop, in particular as a D flip-flop.

[0059] Fig. Figure 4 shows only an example excerpt of a sequence of two pixel cells. However, this approach can be applied to a sequence of more than two pixel cells, e.g., a column or a row of a matrix of pixels. Furthermore, multiple rows or columns can be connected and represented by an even longer shift register. In this respect, the shift register can be used to supply a data signal to all pixels in a column, row, or even a matrix, updating the column, row, or matrix at once.

[0060] The frequency of the clock signal CLK can advantageously be high enough to fill the shift registers for such a sequence of pixels before the update signal UPD is activated and before the values ​​stored in the respective shift register at that time are used to control the pixels of that sequence, e.g., column or row of the pixel matrix. Therefore, a high refresh rate for each pixel can result in high resolution PWM dimming. Therefore, a high clock frequency can be advantageous for storing the information in the flip-flop of the shift register before the update signal is triggered.

[0061] By providing registers (e.g. D flip-flops according to Fig. 4) By arranging these registers in a cascaded manner (with one pixel controlling the next) and arranging them together with the respective pixel cells, a single line is advantageously sufficient to supply the data signal Data_i to a sequence of pixels, whereas otherwise each pixel would require a separate connection for supplying the data signal controlling that pixel.

[0062] Note that any type of register or memory can be used to achieve the result described above. The register can be a flip-flop, a latch, a register, or any other element with memory functionality.

[0063] Fig. Figure 5 shows a schematic block diagram of a pixel cell 501 with a pixel addressing block 502, a driver 503, and a comparator 504. The comparator 504 may be used for diagnostic purposes if necessary.

[0064] The pixel cell 501 may correspond to a part of the semiconductor device with the area of ​​a pixel of the LED array. The pixel cell 501 may provide an Out terminal that can be connected to the light source, e.g., an LED 505 of the LED array. The light source may be mounted directly on the semiconductor device, e.g., above the pixel cell 501. The LED mounted on the semiconductor device may therefore be considered an integral part of the pixel cell. As one possibility, the term pixel cell may refer to the element of the semiconductor device associated with a single LED that can be mounted on this element of the semiconductor device. It is noted that the pixel cell 501 may be part of the semiconductor device 102, in particular the LED driver matrix 202. In one embodiment, the pixel cell 501 may be part of the LED driver matrix 202 according to Fig. 2 correspond.

[0065] Driver 503 receives a voltage Vcp and a voltage Vcc. A reference current Iref is also supplied to driver 503. Reference current Iref can be supplied by common circuit 203, e.g., via a current source connected to this common circuit 203. Driver 503 is connected to ground (also referred to as Vss).

[0066] In addition, the driver 503 receives a signal 506 from the pixel addressing block 502 and provides its output signal for controlling the respective light source via a node 508. The node 508 is connected to the Out terminal.

[0067] Pixel addressing block 502 receives the update signal UPD, the data signal Data_i, and the clock signal CLK. It provides the data signal Data_i+1 to a subsequent pixel cell (or to the common circuit if there is no subsequent pixel cell).

[0068] Furthermore, the pixel addressing block 502 provides the signal 506 to the driver 503. The basic functionality of the pixel addressing block 502 is described with reference to Fig. 4 and Fig. 7 explained.

[0069] If pixel cell 501 is equipped with diagnostic functionality, a diagnostic signal Diag can be provided to pixel addressing block 502 of pixel cell 501. In such a scenario, node 508 is also connected to comparator 504, and a result processed by comparator 504 is provided as signal 507 to pixel addressing block 502. Comparator 504 is also connected to voltage Vcc and to ground Vss.

[0070] As one possibility, all connections to / from the pixel cell 501 may be on the common circuit, except for the Out terminal, which is connected to the LED 505, which may be mounted above the pixel cell 501.

[0071] Fig. 6 shows an exemplary pixel cell 601 based on pixel cell 501, but not including the above-mentioned diagnostic functionality. Thus, pixel cell 601 does not have a comparator 504, and no diagnostic signal Diag is applied to pixel addressing block 502.

[0072] The pixel addressing block 502, the driver 503 and the comparator 504 are explained in more detail below.

[0073] Fig. Figure 7 shows an exemplary implementation of the pixel addressing block 502. In addition, reference is made to the above Fig. 4, which explains the shift registers that operate between multiple pixel cells in more detail.

[0074] In addition to Fig. 4 includes the pixel addressing block of Fig. 7 a diagnostic functionality. The signal 507 from the comparator 504 is fed to an input "1" of a multiplexer 702, while the signal Data_i is fed to an input "0" of the multiplexer 702. Either the input "0" or "1" of the multiplexer 702 is selected via an input 703 of the multiplexer. The output of the multiplexer 702 is connected to the D input of the D flip-flop 401. Depending on a digital value fed to the input 703, one of the multiplexer inputs is connected to the D input of the D flip-flop 401.

[0075] When the value supplied to input 703 is "0", the signal Data_i is supplied to the D input of the D flip-flop 401, and when the value is "1", the signal 507 is supplied to the D input of the D flip-flop 401.

[0076] The diagnostic signal Diag is applied to the first input of an AND gate 701 (also referred to as an AND gate), and the second input of the AND gate 701 is connected to the Q output of the D flip-flop 403. The output of the AND gate 701 is connected to the input 703 of the multiplexer 702.

[0077] According to this example, if the Diag signal is "1" and the Q output of the D flip-flop 403 is "1", the signal 507 is selected by the multiplexer 703 for connection to the D input of the D flip-flop 401. Otherwise, that is, if at least one of the inputs of the AND gate 701 is "0", the Data_i signal is selected by the multiplexer 703 for connection to the D input of the D flip-flop 401.

[0078] The Q output of D flip-flop 403 supplies signal 506 to driver 503. The Q output of D flip-flop 401 supplies the subsequent data signal Data_i+1.

[0079] Fig. Figure 8 shows an exemplary implementation of driver 503. Signal 506 from pixel addressing block 502 is fed to the gate of an n-channel MOSFET 805. The drain terminal of MOSFET 805 is connected to the gate of an n-channel MOSFET 806 and to the gate of an n-channel MOSFET 807. MOSFET 806 corresponds to a read stage, and MOSFET 807 corresponds to a power stage of driver 503.

[0080] The source terminal of MOSFET 805 is connected to ground Vss. The voltage Vcp is supplied to a terminal 808 of a current mirror 804 via a current source 801. Furthermore, the voltage Vcp is connected to a terminal 810 of the current mirror 804 via a current source 803. The terminal 810 is connected to the gate of MOSFET 806. A terminal 809 of the current mirror 804 is connected to ground Vss via a current source 802. A terminal 811 of the current mirror 804 is connected to node 508, which is also connected to the Out terminal.

[0081] Current sources 801 to 803 each reflect a bias current.

[0082] Current mirror 804 includes two NPN transistors 812 and 813. The collector of transistor 812 is connected to terminal 808 and to the base of transistor 812 and to the base of transistor 813. The emitter of transistor 812 is connected to terminal 809. The collector of transistor 813 is connected to terminal 810, and the emitter of transistor 813 is connected to terminal 811.

[0083] The voltage Vcc is connected to the drain terminal of MOSFET 806 and to the drain terminal of MOSFET 807. The reference current Iref is supplied to the source terminal of MOSFET 806 and to terminal 809 of current mirror 804. The source terminal of MOSFET 807 is connected to node 508.

[0084] MOSFET 807 acts as an NMOS power stage, and MOSFET 806 acts as an NMOS read cell. The gate-source voltage of MOSFET 807 is regulated via current mirror 804 based on the reference current Iref and a predetermined KILIS factor (e.g., 50).

[0085] The KILIS factor refers to the ratio between a load current and a read current. The load current is KILIS times the read current.

[0086] The driver topology can be useful to reduce cell power dissipation by providing a small voltage drop across the power stage at high current.

[0087] The reference current Iref can be provided by the common circuit for all pixel cells. Therefore, the reference current Iref is generated away from the heat sources of the pixel cells. The current can be mirrored per pixel cell, per row of pixel cells, and / or per column of pixel cells.

[0088] Generating the reference current Iref for the current mirror 804 outside of the driver 503 thus has the particular advantage that the area required on the semiconductor device for the pixel cell can be further reduced. A further advantage is that the reference current Iref is essentially identical for all pixel cells.

[0089] Therefore, any influence of the pixel cell power dissipation has a limited effect on adjacent pixel cells, resulting in high accuracy of the output current per pixel cell.

[0090] One possibility is for the power stage to be designed with a KILIS factor of 4:200, meaning the NMOS read stage comprises 4 cells, each of which is mirrored by 50 cells of the power stage. These 4 cells can be arranged in a cross-connected configuration in the layout to reduce the effect of different temperature gradients.

[0091] The Fig. The driver shown in Figure 8 also provides high accuracy with low offset. It occupies only a small area on the chip and provides overcurrent protection in the event of a short circuit to ground Vss. Therefore, if a short circuit occurs at the Out terminal, the current mirror 804, which provides the reference current, cannot operate, and the MOSFET 807 (power stage) is pulled down.

[0092] Fig. 9 shows an example implementation of the comparator 504. The comparator 504 also provides an EXCLUSIVE-OR functionality.

[0093] Node 508 is also connected to comparator 504, i.e., to the gate of an n-channel MOSFET 905 and to the gate of a p-channel MOSFET 906 (both gates are connected together). Signal 507 is supplied via the drain terminal of MOSFET 905. The drain terminal of MOSFET 905 is connected to voltage Vcc via a current source 901. The drain terminal of MOSFET 906 is connected to voltage Vcc via a current source 903. The source terminal of MOSFET 905 is connected to the drain terminal of an n-channel MOSFET 907. The source terminal of MOSFET 907 is connected to ground Vss via a current source 902. The source terminal of MOSFET 906 is connected to the gate of MOSFET 907. In addition, the source terminal of the MOSFET 906 is connected to ground Vss via a current source 904.

[0094] Current sources 901 to 904 each reflect bias currents.

[0095] The pixel addressing block 502 according to Fig. 7 in combination with the comparator of Fig. The diagnostic functionality shown in Figure 9 allows to determine for each pixel cell whether an open load or short circuit to ground situation exists.

[0096] Comparator 504 can be designed as a window comparator capable of detecting both conditions, e.g., open load and short circuit. Advantageously, comparator 504 requires only a small area on the chip. Pixel addressing block 502 is configured to select the output 507 of comparator 504 instead of the data signal Data_i via multiplexer 702.

[0097] The status of output 507 (which indicates whether the pixel cell is operating within predefined parameters or exhibits an open load or short circuit condition) is loaded into the shift register and can be read from the shift register (after a predetermined number of clock cycles).

[0098] For example, a 256-bit data frame containing only the pixel to be tested is fed into the shift register, and the diagnostic signal Diag is enabled (i.e., set to "1") for this pixel cell to be tested. The multiplexer 702 of this pixel cell does not transmit the data signal Data_i of a previous pixel cell, but rather the output 507 of comparator 504. Another 256-bit data frame is provided to feed the diagnostic information from the shift register 401 to the common circuit and a microcontroller capable of processing this diagnostic information.

[0099] Therefore, it can be determined whether the pixel cell to be diagnosed is operating within predefined parameters (indicated by logic "0") or is suffering from open load or short to ground problems (indicated by logic "1").

[0100] This routine can be repeated 256 times to check all pixel cells.

[0101] The comparator 504 provides a digital logic “high” information if the output voltage is too high (open load) or too low (short to ground).

[0102] The reference voltages used are the threshold voltage of the MOSFET 905 and the MOSFET 906.

[0103] Once the voltage at node 508 (which corresponds to the voltage at LED 505) is less than a predetermined threshold, MOSFET 905 is turned off and the current supplied by current source 901 pulls up signal 507, resulting in a logic "1" being stored in D flip-flop 401.

[0104] Once the voltage at node 508 is higher than a voltage Vcc-Vth (where Vth is the threshold voltage in this example of the MOFSET), MOSFET 906 is turned off, and the current supplied by current source 904 pulls the gate of MOSFET 907 low (thus turning it off), and therefore the current from current sources 901 pulls signal 507 high, resulting in a logic "1" being stored in D flip-flop 401.

[0105] During normal operation (i.e., the voltage at node 508 is non-zero or too high), MOSFET 905 is on and MOSFET 906 is on, causing MOSFET 907 to be on. The current supplied by current source 902 is higher than the current supplied by current source 901 to pull signal 507 down to logic "0." Furthermore, the current through current source 903 is higher than the current supplied by current source 904, so MOSFET 907 is on and to allow enablement of the left branch (pulling down signal 507). Therefore, the logic "0" signal is stored in D flip-flop 401.

[0106] Therefore, with only a few MOSFETs, the comparator 504 is able to generate the signal 507 which is logic "1" if the voltage at the node 508 is less than the predetermined threshold (thus allowing detection of a short circuit to ground) or if the voltage at the node 508 is higher than the voltage Vcc-Vth (thus allowing detection of an open load condition).

[0107] Therefore, each pixel of the matrix of LEDs (see Fig. 2) be checked quickly and efficiently.

[0108] Although various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications may be made which achieve some of the advantages of the invention without departing from the spirit and scope of the invention. Furthermore, it will be apparent to those of ordinary skill in the art that other components performing the same functions may be suitably substituted. It should be noted that features explained with reference to a specific figure may be combined with features of other figures, even where not expressly stated. Furthermore, the methods of the invention may be achieved either in pure software implementations using corresponding processor instructions, or in hybrid implementations utilizing a combination of hardware logic and software logic to achieve the same results.Such modifications of the inventive concept are intended to be covered by the appended claims.

Claims

[1] A device for driving a plurality of light sources (206) arranged in a matrix structure (101, 201), the device being a semiconductor device (102, 205) comprising: - a shift register having at least two cells, an output of each cell controlling one of the plurality of light sources (206); - wherein the at least two cells are connected in series and controlled by a clock signal; - wherein each cell of the shift register comprises a flip-flop and a register; - where the output of the flip-flop is connected to the input of the register; - wherein the register is arranged to store the output of the register based on an update signal and wherein the output of the register controls one of the light sources (206); - wherein the flip-flops of the at least two cells are filled with a data signal on the basis of the clock signal; - wherein after a predetermined number of cycles of the clock signal, the update signal is supplied to the registers which control the light sources (206) according to the values ​​stored in the flip-flops of the cells; - in which the cells of the shift registers are part of a semiconductor device (102, 205), wherein a matrix structure (101, 201) with the plurality of light sources (206) is arranged above the semiconductor device (102, 205); - wherein the semiconductor device (102, 205) comprises a driver for each light source of the matrix structure (101, 201); - in which the driver for each light source of the matrix structure (101, 201) comprises a current mirror to which at least one reference current is supplied; - in which the at least one reference current is generated in a common region of the semiconductor device (102, 205) and is supplied to all drivers for the light sources (206) of the matrix structure (101, 201); - in which the cell of the shift register and the driver associated with an individual light source of the matrix (101, 201) are arranged on an area having a size corresponding to the size of the area of ​​the individual light source of the matrix (101, 201). [2] The device of claim 1, wherein the flip-flop is a D flip-flop and the register is an additional D flip-flop, the update signal being supplied to the clock terminal of the additional D flip-flop. [3] Device according to one of the preceding claims, wherein the matrix (101, 201) comprises at least two rows and at least two columns. [4] Device according to one of the preceding claims, in which each light source of the matrix (101, 201) is assigned a cell of the shift registers. [5] Device according to one of claims 3 or 4, wherein the cells of the shift register are part of a semiconductor device (102, 205), wherein the matrix structure (101, 201) comprising the plurality of light sources (206) is arranged adjacent to the semiconductor device (102, 205). [6] Device according to one of the preceding claims, wherein the semiconductor device (102, 205) comprises a common circuit for the light sources (206) of the matrix structure (101, 201). [7] The apparatus of claim 5, wherein the common circuit is arranged in an area adjacent to the shift register. [8] Device according to one of the preceding claims, wherein each light source comprises at least one semiconductor light source, in particular at least one LED. [9] Device according to one of the preceding claims, in which the device is an integrated circuit, which is realized in particular as a single chip. [10] A system comprising a matrix structure having a matrix (101, 201) of light sources (206) and the device according to any one of the preceding claims, such device being a semiconductor device (102, 205), the system comprising: - a pixel cell circuit on a first region over which a matrix structure comprising a matrix (101, 201) of light sources (206) is connected, and - a common circuit on a second region arranged adjacent to the first region, the common circuit being configured to operate and / or power the pixel cell circuit.

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