Embedded logic analyzer and integrated circuit with the same

Abstract

Embedded logic analyzer (50) of an integrated circuit (10) with: a comparator block (100) configured to generate a comparator data signal (CPDT) and a plurality of comparator enable signals (CMPEN) based on an input data signal (INDT) from one of the function blocks (11-17) contained in the integrated circuit (10), such that the comparator enable signals (CMPEN) are each activated based on different comparator conditions; an operation block (200) configured to perform a logic operation on the comparison enable signals (CMPEN) to generate a data enable signal (DTEN) indicating a data acquisition time; and a packer circuit (300) configured to generate a packer data signal (PCKDT) with acquisition data and acquisition time information, based on the acquisition data signal (CPDT), the data release signal (DTEN) and a time information signal (TMINF), where the comparison block (100) contains: a plurality of comparator circuits (COMP1-COMP8), each comparator circuit (COMP1-COMP8) being configured to generate a enable signal (CMPEN1-CMPEN8) from the comparator enable signals (CMPEN) based on the input data signal (INDT) and a control signal from the comparator control signals (CMPCON) specifying the comparator control conditions, where at least one first comparator circuit of the majority of comparators (COMP1-COMP8) is configured to: Shifting of one of the input data signal (INDT) and a first shifted data signal from a second comparator circuit of the plurality of comparators (COMP1-COMP8) to generate a second shifted data signal and Comparing the second shifted data signal with a reference data signal and a third shifted data signal from a third comparator circuit of the plurality of comparators to generate the enable signal generated by the first comparator circuit.

Description

BACKGROUND 1. Technical field

[0001] Exemplary embodiments generally relate to integrated semiconductor circuits and in particular to an embedded logic analyzer and an integrated circuit with the embedded logic analyzer. 2. Discussion of related techniques

[0002] When a developed integrated circuit malfunctions, a debugging procedure is performed to locate and resolve the problem. Functional blocks, such as a central processing unit (CPU), a digital signal processor (DSP), etc., connected to a main bus, can be debugged using a Joint Test Action Group (JTAG) architecture, etc. To debug circuits, such as the internal logic of a modem block not directly connected to the main bus, internal signals must be extracted to an external device for analysis. This increases the chip size and reduces productivity because many input / output contacts are occupied for extracting the internal signals.

[0003] US 2006 / 0 156 290 A1 and US 2014 / 0 053 026 A1 concern integrated circuits. SUMMARY

[0004] The invention is set out in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The above and further features and advantages of exemplary embodiments of the inventive concepts will be more clearly illustrated by describing exemplary embodiments of the inventive concepts in detail with reference to the accompanying drawings. The accompanying drawings are intended to illustrate exemplary embodiments of the inventive concepts and should not be interpreted as limiting the intended scope of the claims. The accompanying drawings should not be considered to be to scale unless explicitly stated otherwise. Fig. Figure 1 is a block diagram representing an integrated circuit according to at least some exemplary embodiments of the inventive concepts. Fig. Figure 2 is a block diagram representing an embedded logic analyzer according to at least some exemplary embodiments of the inventive concepts. Fig. Figure 3 is a block diagram showing one of the embedded logic analyzers. Fig. 2 containing comparison block according to at least some exemplary embodiments of the inventive concepts. Fig. 4 is a diagram which shows one in the comparison block from Fig. 3. The comparison unit contained in the document represents at least some exemplary embodiments of the inventive concepts. Fig. 5 is a diagram to describe an operation of the comparison unit from Fig. 4. Fig. Figure 6 is a diagram that represents a data selector for outputting a capture data signal according to at least some exemplary embodiments of the inventive concepts. Fig. 7 is a block diagram showing one of the embedded logic analyzers. Fig. 2 contains an operational block according to at least some exemplary embodiments of the inventive concepts. Fig. 8 is a timing diagram showing the operations of a time controller and a logic gate, which are contained in the operation block. Fig. 7 are included. Fig. 9 is a diagram that shows one in the operation block from Fig. 7 contains the first operational unit according to at least some exemplary embodiments of the inventive concepts. Fig. 10 is a diagram that shows a time controller located in the operation block. Fig. 7 is included, according to at least some exemplary embodiments of the inventive concepts. Fig. 11A to 11F are diagrams illustrating exemplary operations of the time controller. Fig. Represent 10. Fig. Figure 12 is a diagram that represents a control signal selector for varying a trigger control signal according to at least some exemplary embodiments of the inventive concepts. Fig. 13 is a diagram showing an operation of the control signal selector from Fig. 12 represents. Fig. 14 is a block diagram showing one of the embedded logic analyzers. Fig. 2 containing packers according to at least some exemplary embodiments of the inventive concepts. Fig. 15 is a diagram generated by the packer from Fig. 14 generated combined data signals. Fig. 16 is a block diagram that shows one of the embedded logic analyzers. Fig. 2 containing packers according to at least some exemplary embodiments of the inventive concepts. Fig. 17A, Fig. 17B and Fig. 17C are diagrams that show examples of packer data signals that originate from the packer. Fig. 16 were generated, represent. Fig. 18 is a diagram that shows one in the packer from Fig. 16 contained data extractors according to at least some exemplary embodiments of the inventive concepts. Fig. 19 is a chart generated by the data extractor of Fig. 18 generated data signals according to at least some exemplary embodiments of the inventive concepts. Fig. Figure 20 is a block diagram representing an embedded logic analyzer according to at least some exemplary embodiments of the inventive concepts. Fig. 21A and Fig. 21B are diagrams that represent a provision of logic signals according to at least some exemplary embodiments of the inventive concepts. Fig. Figure 22 is a block diagram representing an integrated circuit according to at least some exemplary embodiments of the inventive concepts. Fig. Figure 23 is a block diagram illustrating a computer system with a video encoder according to at least some exemplary embodiments of the inventive concepts. Fig. 24 is a block diagram that represents a computer system consisting of Fig. 23 usable interfaces according to at least some exemplary embodiments of the inventive concepts. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0006] Detailed exemplary embodiments of the inventive concepts are disclosed herein. However, certain structural and functional details are only reproduced here for the purpose of describing exemplary embodiments of the inventive concepts. Exemplary embodiments of the inventive concepts can, however, take many alternative forms and should not be interpreted as being limited to the embodiments described here.

[0007] Accordingly, while various modifications and alternative forms are possible in exemplary embodiments of the inventive concepts, these embodiments are shown in the drawings only as examples and will be described in detail here. It should be understood, however, that there is no intention to limit exemplary embodiments of the inventive concepts to the specific disclosed forms; on the contrary, exemplary embodiments of the inventive concepts are intended to cover all modifications, equivalents, and alternatives that fall within the scope of the exemplary embodiments and inventive concepts. Throughout the description of the figures, identical numbers refer to the same elements.

[0008] It will be understood that although the terms first / first / first, second / second / second, etc., are used here to describe different elements, these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be called a second element, and likewise a second element could be called a first element, without departing from the scope of the exemplary embodiments of the inventive concepts. As used here, the term "and / or" includes any and all combinations of one or more of the linked items listed.

[0009] It will be understood that when an element is described as "connected" or "coupled" with another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is described as "directly connected" or "directly coupled" with another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in the same way (e.g., "between" as opposed to "directly intervening," "adjacent," "opposite," "directly adjacent," etc.).

[0010] The terminology used here is solely for the purpose of describing certain embodiments and is not intended to limit exemplary embodiments of the inventive concepts. As used here, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "has," "having," "contains," and / or "containing," when used here, will be understood to indicate the presence of specified features, integers, steps, operations, elements, and / or components, but will not exclude the presence or addition of one or more features, integers, steps, operations, elements, components, and / or groups thereof.

[0011] It should also be noted that in some alternative implementations, the functions / effects shown may occur in a different order than depicted in the figures. For example, two figures shown consecutively may actually be executed essentially simultaneously or in reverse order, depending on the functionalities / effects involved.

[0012] Exemplary embodiments of the inventive concepts are described here with reference to schematic representations of idealized embodiments (and intermediate structures) of the inventive concepts. As such, variations in the shape of the representations are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments of the inventive concepts should not be interpreted as being limited to specific shapes of the areas shown here, but should include deviations in shapes that are a result of, for example, a manufacturing process.

[0013] Although corresponding top and / or perspective views of some cross-sectional views may not be shown, the cross-sectional views of device structures presented here support a plurality of device structures extending along two different directions, as would be shown in a top view, and / or extending in three different directions, as would be shown in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction, which may be orthogonal to the two different directions. The plurality of device structures may be integrated into the same electronic device. For example, if a device structure (e.g.,An electronic device, such as a memory cell structure or a transistor structure, can contain a plurality of device structures (e.g., memory cell structures or transistor structures) as would be shown in a top view of the electronic device. The plurality of device structures can be arranged in a matrix and / or a two-dimensional pattern.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as they are commonly understood by an average person of knowledge in the field to which this disclosure belongs. It will further be understood that terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with their meaning in the context of the related technology and will not be interpreted in an idealized or overly formal manner, unless expressly defined herein.

[0015] Fig. Figure 1 is a block diagram representing an integrated circuit according to at least some exemplary embodiments of the inventive concepts.

[0016] Referring to Fig. 1. An integrated circuit IC 10 can include a connection device 20, a plurality of functional blocks FB 11-17 connected to the connection device 20, and an embedded logic analyzer ELA 50 directly connected to at least one of the functional blocks 11-17. The embedded logic analyzer 50 can also be connected to the connection device 20. The embedded logic analyzer 50 can be integrated together with the functional blocks 11-17 and the connection device 20 in the same semiconductor chip. The total number of functional blocks 11-17 and the number of functional blocks directly connected to the embedded logic analyzer 50 in Fig. The configuration of one connected function block can be modified in various ways.

[0017] The connection device 20 can be implemented by a circuit. For example, the connection device 20 can be implemented with various bus systems, including a main bus, a bridge, a peripheral bus, etc. The functional blocks 11-17 can all be formed by circuits or integrated circuits. For example, the functional blocks 11-17 can include a memory controller, a display controller, a file system block, a graphics processing unit, an image signal processor, a multi-format codec block, a modem block, etc. Some of the functional blocks 11-17 can be slave devices, such as a memory controller, and other parts of the functional blocks 11-17 can be master devices that issue requests to request services from the slave devices.

[0018] The following describes configurations and operations of the embedded logic analyzer 50 according to at least some exemplary embodiments of the inventive concepts with reference to Fig. 2 to 22 will be described.

[0019] Fig. Figure 2 is a block diagram representing an embedded logic analyzer according to at least some exemplary embodiments of the inventive concepts.

[0020] The embedded logic analyzer 50 can be configured using circuits or a single circuit. For example, with reference to Fig. 2 an embedded logic analyzer 50 a comparator block 100, an operation block 200, a packer 300 and a main controller 400, all of which may be formed by circuits or a circuit.

[0021] The comparator block 100 can generate one acquisition data signal CPDT and a plurality of comparator enable signals CMPEN based on an input data signal INDT. The comparator enable signals CMPEN can each be activated under different comparator conditions. The input data signal INDT can be provided by at least one of the function blocks connected to the logic analyzer 50, as shown in Fig. The input data signal INDT, shown in Figure 1, is directly connected. It can be a parallel signal with multiple bits. The main controller 400 can generate comparator control signals CMPCON, which represent the comparator conditions for controlling the comparator block 100. The comparator control signals CMPCON can include various shift control signals SFT, reference data signals CMPVL, and selection signals CMPMX, as shown below with reference to... Fig. 3 to 6 are described.

[0022] Operation block 200 can receive the comparison enable signals CMPEN and perform a logic operation on these signals to generate a data enable signal DTEN, which indicates the data acquisition time. The main controller 400 can generate operation control signals OPTCON, which represent the logic operation for controlling operation block 200. The OPTCON operation control signals can include a start trigger signal STROP, an end trigger signal ETROP, a write enable signal WENOP, a time control signal TMCON, and a selection signal CNTOPT, as described in [reference to...]. Fig. 7 to 13 will be described.

[0023] The Packer 300, which can also be referred to as a Packer Circuit 300, can receive the acquisition data signal CPDT from the comparator block 100 and the data release signal DTEN from the operation block 200. The Packer 300 can generate a Packer Data Signal PCKDT containing acquisition data and acquisition time information based on the acquisition data signal CPDT, the data release signal DTEN, and a time information signal TMINF. The main controller 400 can generate Packer Control Signals PCKCON to control the operation of the Packer 300. The Packer Control Signals PCKCON can contain a time-domain signal TMSZ, a period-domain signal TMPD, and a bit-width signal BTWD, as shown below. Fig. 14 to 19 will be described. The time information signal TMINF can represent an absolute time and / or a relative time of data acquisition. The time information signal TMINF can be a system time SYSTM provided by a system timer in the integrated circuit 10 and / or an internal time ELATM provided by an internal timer 253, as described with reference to Fig. 10 will be described. The information contained in the packer data signal PCKDT can be used as error correction information for error correction operations of the integrated circuit 10. For example, according to at least one exemplary embodiment, the packer data signal PCKDT can be provided to an external device or system outside the integrated circuit 10, and the external device or system can perform error correction operations with respect to the integrated circuit 10 (or one or more elements) based on the error correction information contained in the packer data signal PCKDT.

[0024] The main controller 400 can contain a register REG 450 that stores control values ​​and generates the signals CMPCON, OTPCON, and PCKCON based on the values ​​stored in register 450. If a problem occurs in the integrated circuit 10, the control values ​​can be appropriately set for necessary troubleshooting. By setting the control values, the start and end times of the data acquisition period, the data acquisition time, the selection of acquisition data, the combination of acquisition time information, etc., can be efficiently controlled. For the sake of simplicity, Fig. 2 are described with reference to an example in which the main controller 400 is contained in the embedded logic analyzer 50. However, some exemplary embodiments of the inventive concepts are not limited to the one described in Section 2. Fig. The example shown is limited and the main controller 400 may be contained in another functional block, such as a processor.

[0025] Therefore, the embedded logic analyzer 50 and the integrated circuit 10 containing the embedded logic analyzer 50 can efficiently control a collection of data required for fault correction according to at least some exemplary embodiments of the inventive concepts, and thus fault correction of the integrated circuit 10 can be carried out efficiently by overcoming limitations on internal resources of the integrated circuit 10, such as the data throughput of a main bus, internal memory capacity, etc.

[0026] Fig. Figure 3 is a block diagram showing one of the embedded logic analyzers. Fig. 2 containing comparison block according to at least some exemplary embodiments of the inventive concepts.

[0027] Referring to Fig. 3. A comparator block 100 can contain a plurality of comparator units COMP1-COMP8, each of which can be formed by circuits or a single circuit. Furthermore, each of the comparator units COMP1-COMP8 can generate each of the comparator enable signals CMPEN1-CMPEN8, based on the input data signal INDT, each of the shift control signals SFT1-SFT8, and reference data signals CMPVL1-CMPVL8, which represent the aforementioned comparator conditions. The shift control signals SFT1-SFT8 and the reference data signals CMPVL1-CMPVL8 can be included in the comparator control signals CMPCON, which are provided by the main controller 400, as shown in Fig. 2 is shown. Fig. Figure 3 represents the eight comparison units COMP1-COMP8 for the purpose of illustration and description, and the number of comparison units can be changed in various ways.

[0028] One or more comparator units COMPi (i=1-8) of the comparator units COMP1-COMP8 can shift the input data signal INDT to generate a shifted data signal CMPDTi and can compare the shifted data signal CMPDTi with the reference data signal CMPVLi to generate the comparator enable signal CMPENi. For example, as in Fig. Figure 3 shows the first comparison unit COMP1, the second comparison unit COMP2, the fourth comparison unit COMP4, the fifth comparison unit COMP5, the seventh comparison unit COMP7 and the eighth comparison unit COMP8 corresponding to the one or more comparison units COMPi mentioned above.

[0029] In contrast, one or more comparator units COMPk (k=1-8) of comparator units COMP1-COMP8 can shift one of the input data signal INDT and a first shifted data signal CMPDTm from another comparator unit COMPm to generate a second shifted data signal CMPDTk, and can compare the second shifted data signal CMPDTk with one of the reference data signal CMPVLk and a third shifted data signal CMPDTn from yet another comparator unit COMPn to generate the comparator enable signal CMPENk. For example, as in Fig. Figure 3 shows the third comparator COMP3 and the sixth comparator COMP6 corresponding to the one or more comparators COMPk mentioned above. Multiplexers MX1, MX2, MX3, and MX4 can be placed before the third comparator COMP3 and the sixth comparator COMP6 to selectively output the data signal in response to the selection signals CMPMX1 and CMPMX2, respectively.

[0030] Therefore, through configuration such as in Fig. 3 shown and defining the shift control signals SFT1-SFT8 and the reference data signals CMPVL1-CMPVL8 the comparison conditions for collecting data for necessary troubleshooting can be efficiently determined.

[0031] Fig. 4 is a diagram which shows one in the comparison block from Fig. 3 included comparison unit and Fig. 5 is a diagram to describe an operation of the comparison unit from Fig. 4 according to at least some exemplary embodiments of the inventive concepts.

[0032] Referring to Fig. 4. A comparator unit can contain a first shift register RSR, a second shift register RSR, and a comparator CMP. For the sake of simplicity, Fig. 4 described with reference to an example where the input data signal INDT contains 64 bits INDT[63:0], the reference data signal CMPVL contains 32 bits CMPVL[31:0], and the shift control signal SFT contains 16 bits SFT[15:0]. However, at least some exemplary embodiments of the inventive concepts are not related to the one described in Fig. The example shown is limited and the number of bits in the signals can be changed in various ways according to the requirements and / or wishes of a user or manufacturer of the ELA 50.

[0033] The first shift register LSR can shift the input data signal INDT left in response to the first bits SFT[5:0] of the shift control signal SFT, where the first bits SFT[5:0] represent a shift number to the left. The second shift register RSR can shift an output signal SFDT of the first shift register LSR right in response to the second bits SFT[11:6] of the shift control signal SFT, where the second bits SFT[11:6] represent a shift number to the right. The comparator CMP can compare an output signal of the second shift register RSR, i.e., the shifted data signal CMPDT, with the reference data signal CMPVL[31:0] in response to the third bits SFT[15:12] of the shift control signal SFT to generate the comparison enable signal CMPEN, where the third bits SFT[15:12] represent a comparison bit number.The comparator CMP can activate the comparison enable signal CMPEN on a first logic level if the portion of the shifted data signal CMPDT corresponding to the comparison bit is equal to that of the reference data signal CMPVL, and can deactivate the comparison enable signal CMPEN on a second logic level if the portion of the shifted data signal CMPDT corresponding to the comparison bit is not equal to that of the reference data signal CMPVL. The comparison enable signal CMPEN can be a pulse signal with pulses that are activated as soon as the comparison condition is met.

[0034] For example, as in Fig. Figure 5 shows the second to seventh data bits A1-A6 of the first to sixty-fourth data bits A0-A63 of the input data signal INDT, which are the bits to be compared with the reference data signal CMPVL. In this case, the first bits SFT[5:0] of the shift control signal SFT can be set to 57, the second bits SFT[11:6] of the shift control signal SFT can be set to 58, and the first bits SFT[15:12] of the shift control signal SFT can be set to 6. Referring to the configuration from Fig. 4. The input data signal INDT is shifted left by a left shift of 57 and then shifted right by a right shift of 58. Finally, the low-order 6 bits A1-A6 of the shifted data signal CMPDT can be compared with the low-order 6 bits B0-B5 of the reference data signal CMPVL.

[0035] Fig. Figure 6 is a diagram that represents a data selector for outputting a capture data signal according to at least some exemplary embodiments of the inventive concepts.

[0036] Referring to Fig. 6. A data extractor 150 can be implemented with a multiplexer MUX configured to select one of the input data signal INDT and the shifted data signals CMPDT4, CMPDT5, and CMPDT6 from the comparators and to output the one selected signal as the acquisition data signal CPDT in response to, for example, a selection signal CPMX3. The data extractor 150 can also be referred to as a data selector 150 or a data selection circuit 150. In at least some exemplary embodiments of the inventive concepts, the data selector 150 can be located in the comparator block 100 in Fig. 2 must be included.

[0037] The comparison data bits used to determine whether the condition for data acquisition is met can be different from the acquired data bits. Each of the comparison units COMP1-COMP8 in Fig. 3 can be used to determine whether the condition for data acquisition is met or to shift and provide the data bits to be acquired.

[0038] Fig. 7 is a block diagram that shows one of the embedded logic analyzers. Fig. 2 contains an operational block according to at least some exemplary embodiments of the inventive concepts.

[0039] Referring to Fig. 7. An operation block 200 can contain a first operation unit 210, a second operation unit 220, a third operation unit 230, a time controller 250 and a logic gate 260, each of which can be implemented by circuits or a circuit.

[0040] The first operating unit 210 can generate a start release signal STREN, based on the comparison release signals CMPEN and a start release control signal STROP. The second operating unit 220 can generate an end release signal ETREN, based on the comparison release signals CMPEN and an end release control signal ETROP. The third operating unit 230 can generate a write release signal WREN, based on the comparison release signals CMPEN and a write release control signal WENOP. The start release signal STREN can be used to determine a start time for the data acquisition period, the end release signal ETREN can be used to determine an end time for the data acquisition period, and the write release signal WREN can be used to determine the data acquisition time.The first, second and third operational units 210, 220 and 230 can also be referred to as first, second and third operational circuits 210, 220 and 230 respectively.

[0041] The time controller 250 can generate a write-enable signal WRON, which indicates a start and end time of the data acquisition duration, in response to the start-trigger enable signal STREN, the end-trigger enable signal ETREN, and a timing control signal TMCON. The logic gate 260 can generate the data-enable signal DTEN, which indicates the data acquisition time, based on the write-enable signal WRON and the write-enable signal WREN. According to at least some exemplary embodiments, the logic gate 260 can, for example, be an AND gate.

[0042] The start trigger control signal STROP, the end trigger control signal ETROP, the write enable control signal WENOP, and the time control signal TMCON can be contained in the operation control signals OPTCON, which are described in Fig. 2 shown, from which the main controller 400 is provided.

[0043] Fig. Figure 8 is a timing diagram that represents the operations of a time controller and a logic gate, which are contained in the operation block consisting of Fig. 7 are included.

[0044] In Fig. 8. A write start signal WSTT indicates the start time ts of the data acquisition period, and a write end signal WEND indicates the end time te of the data acquisition period. The write start signal WSTT and the write signal WEND can be generated in the time controller 250, and the time controller can generate the write enable signal WRON based on the write start signal WSTT and the write signal WEND. Data acquisition can be enabled when the write enable signal WRON is activated at a first logic level (e.g., a logic high level), and data acquisition can be prevented when the write enable signal WRON is deactivated at a second logic level (e.g., a logic low level). As described in Fig. Figure 8 shows that although the write enable signal WREN is enabled in a pulse shape, the data enable signal DTEN, which represents the data acquisition time, can maintain the disabled state while the write enable signal WRON is disabled. While the write enable signal WRON is enabled between the data acquisition duration ts~te, the data enable signal DTEN can be enabled synchronously with the write enable signal WREN.

[0045] Fig. 9 is a diagram that shows one in the operation block from Fig. 7 contains the first operational unit, according to at least some exemplary embodiments of the inventive concepts.

[0046] Referring to Fig. 9 The first operating unit 210 can contain a plurality of multiplexers 211-215 and an operator 216, which can be formed by a circuit or a switching circuit. The operator 216 can also be referred to as an operator switching circuit 216. The multiplexers 211-215 can output selected comparator enable signals SCMPEN1-SCMPEN5, which correspond to a section of the comparator enable signals CMPEN1-CMPEN8, in response to the start trigger control signal STROP. For example, as in Fig. Figure 9 shows that the first multiplexer 211 selects one of the comparison signals CMPEN1-CMPEN8 in response to the first bits STROP[2:0] of the start trigger control signal STROP to output the first selected comparison enable signal SCMPEN1. The second multiplexer 212 can select one of the comparison signals CMPEN1-CMPEN8 in response to the second bits STROP[5:3] of the start trigger control signal STROP to output the second selected comparison enable signal SCMPEN2. The third multiplexer 213 can select one of the comparison signals CMPEN1-CMPEN8 in response to the third bits STROP[8:6] of the start trigger control signal STROP to output the third selected comparison enable signal SCMPEN3. The fourth multiplexer can select one of the comparison signals CMPEN1-CMPEN8 in response to the fourth bits STROP[11:9] of the start trigger control signal. STROP to output the fourth selected comparison release signal SCMPEN4,and the fifth multiplexer 215 can select one of the comparison signals CMPEN1-CMPEN8 in response to fifth bits STROP[14:12] of the start trigger control signal STROP to output the fifth selected comparison enable signal SCMPEN5. The number of comparison enable signals, the number of multiplexers and the number of bits of the start trigger control signal STROP can be varied in many ways.

[0047] Operator 216 can perform a logic operation on the selected comparator enable signals SCMPEN1-SCMPEN5 in response to the start trigger control signal STROP to generate the start trigger enable signal STREN. Operator 216 can perform various logic operations on the selected comparator enable signals SCMPEN1-SCMPEN5 to provide different results of the logic operations. Operator 216 can select one of the results of the logic operations in response to the sixth bit STROP[18:15] of the start trigger enable signal STREN, as shown in Fig. Figure 9 shows how to output the selected signal as the start trigger enable signal STREN. The logic operations can be implemented as various combinations of an AND logic operation, an OR logic operation, a NOT logic operation, etc.

[0048] Fig. Figure 9 represents an exemplary embodiment of the first operating unit 210. Furthermore, the second operating unit 220 and the third operating unit 230 can be described in Fig. 7 configurations that are the same as or similar to the configuration from Fig. 9 are. For example, the second operating unit 220 can contain a plurality of multiplexers configured to output selected comparator enable signals corresponding to a section of the comparator enable signals CMPEN1-CMPEN8 in response to the end-release control signal ETROP, and can contain an operator configured to perform a logic operation on the selected comparator enable signals in response to the end-release control signal ETROP to generate the end-release enable signal ETREN.The third operating unit 230 can include a plurality of multiplexers configured to output selected comparator enable signals corresponding to a section of the comparator enable signals CMPEN1-CMPEN8 in response to the write enable control signal WENOP, and an operator configured to perform a logic operation on the selected comparator enable signals in response to the write enable control signal WENOP to generate the write enable signal WREN.

[0049] Fig. 10 is a diagram representing a time controller located in the operation block consisting of Fig. 7 is included, according to at least some exemplary embodiments of the inventive concepts.

[0050] Referring to Fig. 10. A time controller 250 can contain a first logic circuit SLOG 251, a second logic circuit ELOG 252, an internal timer 253 and a counter 254.

[0051] The first logic circuit 251 can generate a write start signal WSTT, which indicates the start time of the data acquisition period. The second logic circuit 252 can generate a write end signal WEND, which indicates the end time of the data acquisition period. The internal timer 253 can provide a relative time for the data acquisition. The counter 254 can count the activation counts of the start trigger enable signal STREN and the end trigger enable signal ETREN.

[0052] The time controller 250 can receive the start trigger enable signal STREN and the end trigger enable signal ETREN from the first and second operating units 210 and 220. Fig. 7, a system time SYSTM from a system timer in the integrated circuit 10, a start control signal STRECON, an end control signal ETRCON, a reference start time STM, a reference end time ETM and a reference count signal CNTVL, and generate an internal time ELATM, a trigger count signal TRCNT and a write-on signal WRON. The start control signal STRCON, the end control signal ETRCON, the reference start time STM, the reference end time ETM and the reference count signal CNTVL can be used in the time control signal TMCON in Fig. 7 are included and can be accessed from the main controller 400 in Fig. 2 will be provided.

[0053] Fig. 11A to 11F are diagrams illustrating exemplary operations of the time controller. Fig. 10 represent. That in Fig. The signal shown in 11A to 11F can be one of two signals. For example, it can Fig. 11A represents a temporal relationship between the start control signal STRCON and the write start signal WSTT or a temporal relationship between the end control signal ETRCON and the write end signal WEND.

[0054] Referring to Fig. 11A The time controller 250 can activate each of the write start signal WSTT and the write end signal WEND in response to each of the start control signal STRCON and an end control signal ETRCON, respectively. According to at least some exemplary embodiments of the inventive concepts, the start control signal STRCON and an end control signal ETRCON can be provided by an external circuit outside the time controller 250, e.g., by the main controller 400 in Fig. 2.

[0055] Referring to Fig. 11B The time controller 250 can activate each of the write start signal WSTT and the write end signal WEND if a system time SYSTM from a system timer matches each of the reference start time STM or the reference end time ETM.

[0056] Referring to Fig. The 11C time controller 250 can count each of the activation counts (e.g., counting a number of activations) of the start trigger enable signal STREN and the end trigger enable signal ETREN after each one has been activated by the start control signal STRCON and the end control signal ETRCON, and can activate each of the write start signal WSTT and the write end signal WEND, based on each of the activation counts. For example, the reference count signal CNTVL is set to a value of "3" and each of the write start signal WSTT and the write signal WEND can be activated when the trigger count signal TRCNT has the value "3".

[0057] Referring to Fig. 11D The time controller 250 can count each of the activation counts (e.g., counting a number of activations) of the start trigger enable signal STREN and the end trigger enable signal ETREN after the system time SYSTM matches each of the reference start time STM and reference end time ETM, and can activate each of the write start signal WSTT and the write end signal WEND based on each of the activation counts. For example, the reference count signal CNTVL is set to a value of "3" and each of the write start signal WSTT and the write signal WEND can be activated when the trigger count signal TRCNT has the value "3".

[0058] Referring to Fig. The time controller 250 can buffer (or latch) the internal time ELATM at a time point t1 after the start control signal STRCON has been activated, when the start trigger enable signal STREN is activated. Additionally, the time controller 250 can buffer the internal time ELATM at a time point (also represented as t1) after the end control signal ETRCON has been activated, when the end trigger enable signal ETREN is activated. The time controller 250 can activate each of the write start signal WSTT and the write end signal WEND, based on a difference DIFFTM between the buffered time LTM and the internal time ELATM. For example, if the reference start time STM and the reference end time ETM are set to a value of "5", each of the write start signal WSTT and the write signal WEND can be activated when the time difference DIFFTM reaches the value "5".

[0059] Referring to Fig. According to section 11F, the time controller 250 can buffer the internal time ELATM at a time point t1 after the start control signal STRCON has been activated, when the release trigger signal STREN is activated. Additionally, the time controller 250 can buffer the internal time ELATM at a time point (also represented as t1) after the end control signal ETRCON has been activated, when the end release trigger signal ETREN is activated. The time controller 250 can activate each of the write start signal WSTT and the write end signal WEND, based on a difference DIFFTM between the buffered time LTM and the internal time ELATM.For example, each reference start time STM and reference end time ETM is set to a value of “5” and each can be activated by the write start signal WSTT and the write end signal WEND when each is activated by the start trigger enable signal STREN and the end trigger enable signal ETREN after the time difference DIFFTM reaches the value of “5”.

[0060] Fig. Figure 12 is a diagram representing a control signal selector for varying a trigger control signal according to at least some exemplary embodiments of the inventive concepts, and Fig. 13 is a diagram showing an operation of the control signal selector from Fig. 12 represents at least some exemplary embodiments of the inventive concepts.

[0061] Referring to Fig. 12 and Fig. 13. A control signal selector 218 can contain a first multiplexer 218a and a second multiplexer 218b. The first multiplexer 218a can select one of input start-trigger control signals iSTROP0-iSTROP7 and output it in response to a trigger count signal TRCNT. The second multiplexer 218b can select one of the fixed input start-trigger control signal iSTROP0 and the output of the first multiplexer 218a and output it in response to a selection signal CNTOPT. As in Fig. As shown in Figure 13, the value of the trigger count signal TRCNT can be increased stepwise when the start trigger enable signal STREN is activated, and thus the value of the start trigger control signal STROP can be changed stepwise.

[0062] Fig. 12 and Fig. 13 represent a change to the start trigger control signal STROP, and the end trigger control signal ETROP can be varied using the same method. Therefore, each of the first operating unit 210 and the second operating unit 220 can be used in Fig. 7 each of the start trigger control signal STROP and the end trigger control signal ETROP vary, based on each of the activation counts of the start trigger enable signal STREN and the end trigger enable signal ETREN.

[0063] Fig. 14 is a block diagram representing a packer that is part of the embedded logic analyzer. Fig. 2 is included, according to at least some exemplary embodiments of the inventive concepts and Fig. 15 is a diagram that represents combined data signals generated by the packer. Fig. 14 are produced, according to at least some exemplary embodiments of the inventive concepts.

[0064] Referring to Fig. Figure 14 can be a packer 301, which can also be called a packer circuit 301, a data extractor DEXT 311, a time information extractor TIEXT 312, a synthesizer (or summarizer) SYN 313, and a multiplexer MUX 314. The data extractor DEXT 311, the time information extractor TIEXT 312, and the synthesizer SYN 313 can all be formed by circuits or a single circuit. The data extractor DEXT 311, the time information extractor TIEXT 312, and the synthesizer SYN 313 can also be referred to as a data extraction circuit, a time information circuit, and a synthesizer circuit. Although not in Fig. As shown in Figure 14, the Packer 301 can receive the data release signal DTEN, which represents the data acquisition time as described above. The Packer 301 can generate the Packer data signal PCKDT synchronously with the data release signal DTEN.

[0065] The data extractor 311 can generate data bit signals DB1-DB4 of various bit counts (e.g., 32 bits, 40 bits, 48 ​​bits, 56 bits, etc.) based on the acquisition data signal CPDT. The time information extractor 312 can generate time information bit signals TIB1-TIB4 of various bit counts (e.g., 32 bits, 24 bits, 16 bits, 18 bits, etc.) based on the time information signal TMINF. The example bit count of the signals is shown in parentheses. The synthesizer 313 can combine the data bit signals DB1-DB4 and the time information bit signals TIB1-TIB4 to generate combined data signals SYND1-SYND4 of the same total number of bits (e.g. combined data signals with 32+32=40+24=48+16=56+8=64 bits), so that the combined data signals SYND1-SYND4 contain the acquisition time information of different bit numbers.

[0066] Fig. Figure 15 presents an example of the combined data signals SYND1-SYND4. Fig. In section 15, "D" represents the captured data, and "T" represents the time information of the captured data. The first combined data signal, SYND1, contains the time information of 8 bits and the captured data of 56 bits; the second combined data signal, SYND2, contains the time information of 16 bits and the captured data of 48 bits; the third combined data signal, SYND3, contains the time information of 24 bits and the captured data of 40 bits; and the fourth combined data signal, SYND4, contains the time information of 32 bits and the captured data of 32 bits.

[0067] The multiplexer 314 can select one of the combined data signals SYND1-SYND4, based on a time-variable signal TMSZ from the main controller 400. Fig. 2 to output the selected one as the Packer data signal PCKDT.

[0068] Therefore, the number of bits of time information contained in the packer data signal PCKDT can be efficiently controlled by changing the value of the time parameter signal TMSZ.

[0069] Fig. Figure 16 is a block diagram representing a packer that is part of the embedded logic analyzer. Fig. 2 is included, according to at least some exemplary embodiments of the inventive concepts.

[0070] Referring to Fig. 16. A packer 302, which can also be called a packer circuit 302, can contain a data extractor DEXT 321, a time information extractor TIEXT 322, and a multiplexer MUX 323. The data extractor DEXT 321 and the time information extractor TIEXT 322 can each be formed by circuits or a single circuit. Although not in Fig. As shown in Figure 16, the Packer 302 can receive the data release signal DTEN, which represents the data acquisition time, as described above. The Packer 302 can generate the Packer data signal PCKDT synchronously with the data release signal DTEN.

[0071] The data extractor 321 can generate a data bit signal DB of a fixed number of bits (e.g., a specified number of bits) based on the acquisition data signal CPDT. The time information extractor 322 can generate a time information bit signal TIB of a specified number of bits based on the time information signal TMINF. Example bit counts for the signals are shown in parentheses (e.g., 64 bits). The number of bits in the data bit signal DB can be equal to the number of bits in the time information bit signal TIB.

[0072] The multiplexer 323 can select one of the data bit signal DB and the time information bit signal TIB, based on a period signal TMPD from the main controller 400. Fig. 2 to output the selected one as the Packer data signal PCKDT.

[0073] Fig. 17A, Fig. 17B and Fig. 17C are diagrams that represent examples of packer data signals generated by the packer. Fig. 16 have been generated.

[0074] Referring to Fig. 17A The 64-bit acquisition data D0 can be output as the packer data signal PCKDT at time t1, the 64-bit acquisition data D1 can be output as the packer data signal PCKDT at time t2, and then the time information T0 and T1 can be output as the packer data signal PCKDT at time t3. Similarly, the acquisition data D2 and D3 can be output as the packer data signal at times t4 and t5, and then the time information T2 and T3 can be output as the packer data signal PCKDT at time t6. As a result, the 32-bit time information can be mapped to the 64-bit acquisition data.

[0075] Referring to Fig. 17B, ​​the acquisition data D0 of 64 bits can be output as the packer data signal PCKDT at time t1, the acquisition data D1 of 64 bits can be output as the packer data signal PCKDT at time t2, the acquisition data D2 of 64 bits can be output as the packer data signal PCKDT at time t3, the acquisition data D3 of 64 bits can be output as the packer data signal PCKDT at time t4, and then the time information T0, T1, T2, and T3 can be output as the packer data signal PCKDT at time t5. Similarly, the acquisition data D4, D5, D6, and D7 can be output as the packer data signal at times t6, t7, t8, and t9, and the time information T4, T5, T6, and T7 can then be output as the packer data signal PCKDT at time t10. As a result, the 16-bit time information can be mapped to the 64-bit acquisition data.

[0076] Referring to Fig. 17C, the acquisition data D0 of 64 bits can be output as the packer data signal PCKDT at time t1, the acquisition data D1 of 64 bits can be output as the packer data signal PCKDT at time t2, the acquisition data D2 of 64 bits can be output as the packer data signal PCKDT at time t3, the acquisition data D3 of 64 bits can be output as the packer data signal PCKDT at time t4, the acquisition data D4 of 64 bits can be output as the packer data signal PCKDT at time t5, the acquisition data D5 of 64 bits can be output as the packer data signal PCKDT at time t6, the acquisition data D6 of 64 bits can be output as the packer data signal PCKDT at time t7, the acquisition data D7 of 64 bits can be output as the Packer data signal PCKDT at time t8 and can then contain the time information T0, T1, T2, T3, T4, T5,T6 and T7 are output as the packer data signal PCKDT at time t9. As a result, the 8-bit time information can be mapped to the 64-bit acquisition data.

[0077] Therefore, the number of bits of time information contained in the packer data signal PCKDT can be efficiently controlled, as shown in Fig. 17A, Fig. 17B and Fig. 17C is represented by changing the value of the period signal TMPD.

[0078] Fig. 18 is a diagram which shows one in the packer from Fig. 16 contained data extractors according to at least some exemplary embodiments of the inventive concepts, and Fig. 19 is a diagram generated by the data extractor from Fig. 18 generated data signals according to at least some exemplary embodiments of the inventive concepts.

[0079] Referring to Fig. 18 A data extractor 340 can contain a plurality of flip-flop devices 341-348 and a multiplexer 349. Fig. Figure 18 presents an example for processing the 64-bit CPDT acquisition data signal. However, at least some embodiments of the inventive concepts are not based on the one described in Figure 18. Fig. The example shown is limited to 18, and the configuration of the data extractor 340 can be changed in many ways, e.g., depending on the number of bits of the CPDT acquisition data signal. Fig. 18 represents “FF” eight flip-flops, which correspond to one-byte data.

[0080] The acquisition data in the acquisition data signal CPDT can initially be stored in the first flip-flop device 341. When new acquisition data is entered by the acquisition data signal CPDT, a portion of the data stored in the first flip-flop device 341 is shifted and stored in the second flip-flop device 342, and the new acquisition data is stored in the first flip-flop device 341. In this way, the oldest acquisition data is stored in the eighth flip-flop device 348, and the most recent acquisition data is stored in the first flip-flop device 341. The shift operation between flip-flop devices 341-348 can be performed synchronously with the data release signal DTEN, which represents the data acquisition time.

[0081] The 64 bits D00-D07 of the first flip-flop device 341 can form a first data bit signal DBa, the 64 bits D00-D03 and D10-D13 of the first and second flip-flop devices 341 and 342 can form a second data bit signal DBb, the 64 bits D00, D01, D10, D11, D20, D21, D30 and D31 of the first to fourth flip-flop devices 341-344 can form a third data bit signal DBc, and the 64 bits D00, D10, D20, D30, D40, D50, D60 and D70 of the first to eighth flip-flop devices 341-348 can form a fourth data bit signal DBd. The first to eighth data bit signals DBa, DBb, DBc and DBd thus formed are in Fig. 19 shown.

[0082] The multiplexer 349 can output one of the first to fourth data bit signals DBa, DBb, DBc and DBd in response to a bit width signal BTWD from the main controller 400. Fig. Select 2 and output the selected one as the data bit signal DB.

[0083] Therefore, the Packer 340 can set a number of bits to be captured in the acquisition data from the total number of bits in the CPDT acquisition data signal, in response to the BTWD bit width signal. For example, as in Fig. 18 and Fig. Figure 19 shows the total number of bits of the CPDT acquisition data signal to be 64. All 64 bits can be acquired when the first data bit signal DBa is selected, 32 bits of the total 64 bits can be acquired when the second data bit signal DBb is selected, 16 bits of the total 64 bits can be acquired when the third data bit signal DBc is selected, and 8 bits of the total 64 bits can be acquired when the fourth data bit signal DBd is selected.

[0084] If a portion of the total bits in the CPDT acquisition data signal is significant and required for error correction, only that portion of the total bits needs to be acquired. This reduces the amount of data in the integrated circuit and allows for efficient use of the limited memory capacity.

[0085] Therefore, the embedded logic analyzer and the integrated circuit with the embedded logic analyzer, according to at least some exemplary embodiments of the inventive concepts, can efficiently control a collection of data required for fault correction, and thus fault correction of the integrated circuit can be efficiently carried out by overcoming limitations of internal resources of the integrated circuit, such as the data throughput of a main bus, internal memory capacity, etc.

[0086] Fig. Figure 20 is a block diagram representing an embedded logic analyzer according to at least some exemplary embodiments of the inventive concepts.

[0087] Referring to Fig. 20 An embedded logic analyzer 51 can contain the comparator block 100, the operation block 200, the packer 300, the main controller 400 and an input selector 500.

[0088] The input selector 500 can select one of the logic signals INLOG1-INLOGn from the integrated circuit 10. Fig. Select one of the contained function blocks to provide the selected input data signal INDT. The input selector 500 can be implemented by a multiplexer MUX, which performs a selection operation in response to a selection control signal MXCON from the main controller 400.

[0089] The comparator block 100 can generate one acquisition data signal CPDT and a plurality of comparator enable signals CMPEN based on an input data signal INDT. The comparator enable signals CMPEN can each be activated under different comparator conditions. The input data signal INDT can be received from the single function block that is directly connected to the embedded logic analyzer 50, as shown in Fig. Figure 1 is shown. The input data signal INDT can be a parallel signal with multiple bits. The main controller 400 can generate comparator control signals CMPCON, which represent the comparator conditions, for controlling the comparator block 100. The comparator control signals CMPCON can be the shift control signals SFT, the reference data signals CMPVL, and the selection signals CMPMX as shown above. Fig. 3 to 6 described, included.

[0090] Operation block 200 can receive the comparison enable signals CMPEN and perform a logic operation on these signals to generate a data enable signal DTEN, which indicates the data acquisition time. The main controller 400 can generate operation control signals OPTCON, which represent the logic operation for controlling operation block 200. The OPTCON operation control signals can include the start trigger signal STROP, the end trigger signal ETROP, the write enable signal WENOP, the time control signal TMCON, and the selection signal CNTOPT, as specified in the following diagram: Fig. 7 to 13 described, contained.

[0091] The Packer 300 can receive the acquisition data signal CPDT from the comparator block 100 and the data release signal DTEN from the operation block 200. The Packer 300 can generate a Packer data signal PCKDT containing acquisition data and acquisition time information based on the acquisition data signal CTDT, the data release signal DTEN, and a time information signal TMINF. The main controller 400 can generate Packer control signals PCKCON to control the operation of the Packer 300. The Packer control signals PCKCON can include the time-domain signal TMSZ, the period-domain signal TMPD, and the bit-width signal BTWD, as described above. Fig. Contains 14 to 19.

[0092] The main controller 400 can contain a register REG 450, which stores control values ​​and generates the signals CMPCON, OPTCON, and PCKCON based on the values ​​stored in register 450. If a problem occurs in the integrated circuit 10, the control values ​​can be set to facilitate troubleshooting. By setting the control values, the start and end times of the data acquisition period, the data acquisition time itself, the selection of acquisition data, combinations of acquisition time information, and so on, can be efficiently controlled. For the sake of simplicity, Fig. 2 explained with reference to an example in which the main controller 400 is contained in the embedded logic analyzer 50. However, some exemplary embodiments of the inventive concepts are not limited to those in Fig. The two examples shown are limited, and the main controller 400 can be contained in other functional blocks, including, for example, a processor.

[0093] Therefore, the embedded logic analyzer 51 and the integrated circuit with the embedded logic analyzer 51 can efficiently control a collection of data required for fault correction according to at least some exemplary embodiments of the inventive concepts, and thus fault correction of the integrated circuit can be carried out efficiently by overcoming limitations of the internal resources of the integrated circuit, such as the data volume of a main bus, an internal memory capacity, etc.

[0094] Fig. 21A and Fig. 21B are diagrams which represent a provision of logic signals according to at least some exemplary embodiments of the inventive concepts.

[0095] In at least some exemplary embodiments of the inventive concepts, as shown in Fig. As shown in Figure 21A, an input selector 501 receives logic signals INLOG1 and INLOG2 from the same function block FB and provides one of the logic signals INLOG1 and INLOG2 as the input data signal INDT. In at least some further exemplary embodiments of the inventive concepts, as shown in Fig. As shown in Figure 21B, an input selector 502 receives logic signals INLOG1 and INLOG2 from different function blocks FB1 and FB2 and provides one of the logic signals INLOG1 and INLOG2 as the input data signal INDT. Therefore, data acquisition can be performed selectively for one of a plurality of logic signals using the common embedded logic analyzer, thus making data acquisition and error correction even more efficient. The in Fig. 21A and Fig. The functional blocks FB shown in 21B can all be formed by circuits or a switching circuit.

[0096] Fig. Figure 22 is a block diagram which represents an integrated circuit according to at least some exemplary embodiments of the inventive concepts.

[0097] Referring to Fig. Figure 22 shows that an integrated circuit IC 60 can include a connecting device 20, a plurality of functional blocks FB 61, 62, and 63 connected to the connecting device 20, and an embedded logic analyzer ELA 52 directly connected to at least one of the functional blocks 61, 62, and 63. The connecting device 20, the plurality of functional blocks FB 61, 62, and 63, and the embedded logic analyzer ELA 52 can all be formed by circuits or a single integrated circuit. Furthermore, the logic analyzer 52 can be connected to the connecting device 20. The embedded logic analyzer 52 can be integrated together with the functional blocks 61, 62, and 63, as well as the connecting device 20, on the same semiconductor chip. As in Fig. As shown in Figure 22, the functional blocks 61, 62 and 63 can contain a processor 62 and an embedded memory MEM1 63.

[0098] The embedded logic analyzer 52 can include a comparator block CBK, an operation block OBK, a packer PKR, a buffer FIFO, and a direct memory access controller DMA, each of which can be implemented by circuits or a single integrated circuit. Compared to the configuration from Fig. 2. The embedded logic analyzer 52 can further include the FIFO buffer and the DMA direct memory access controller. Accordingly, the embedded logic analyzer 52 can have the same structure as the embedded logic analyzer 50, except that the embedded logic analyzer 52 additionally includes the FIFO buffer and the DMA direct memory access controller. The FIFO buffer can store data from the packer data signal from the packer PKR. The DMA direct memory access controller can transfer the data stored in the buffer to the embedded memory 63 contained in the integrated circuit 60. Additionally, the DMA direct memory access controller can transfer the data stored in the FIFO buffer to an external memory MEM2 70 outside the integrated circuit 60. Furthermore, the DMA direct memory access controller can transfer the data stored in the FIFO buffer to an external device, such as...A personal computer PC 80, through an external high-speed interface I / F 65, such as a Universal Serial Bus (USB), a PCI Express, etc. The Direct Memory Access Controller DMA can be connected to the embedded memory 63, a memory controller 64, and / or the external high-speed interface 65 through the connection device 20. As shown in . Fig. As shown in figure 22, the memory controller 64 can be contained in the processor 62.

[0099] Fig. Figure 23 is a block diagram representing a computer system with a video encoder according to at least some exemplary embodiments of the inventive concepts.

[0100] Referring to Fig. 23. A computing system 1000 can contain a processor 1010, a storage device 1020, a memory device 1030, an input / output device 1040, a power supply 1050, and an image sensor 900. Although it is not in Fig. As shown in Figure 23, the computing system can contain 1000 additional ports that communicate with a video card, a sound card, a memory card, a Universal Serial Bus (USB) device and / or other electronic devices.

[0101] The 1010 processor can perform various calculations or tasks. The 1010 processor can include an embedded logic analyzer, the ELA 1011. The embedded logic analyzer, the ELA 1011, can have a configuration for efficiently controlling the collection of data required for troubleshooting, such as with regard to... Fig. as described in sections 1 to 22. For example, the ELA 1011 can have the same structure and function as described above with reference to the ELA 50, the ELA 51, or the ELA 52. According to some embodiments, the processor 1010 can, for example, be a microprocessor or a central processing unit (CPU). The processor 1010 can communicate with the storage device 1020, the storage device 1030, and the input / output device 1040 via an address bus, a control bus, and / or a data bus. In at least some exemplary embodiments of the inventive concepts, the processor 1010 can be coupled to an extended bus, such as a peripheral component interconnection (PCI) bus. The storage device 1020 can store data for the operation of the computer system 1000.For example, the storage device 1020 can be implemented using a dynamic random access memory (DRAM) device, a mobile DRAM device, a static random access memory (SRAM) device, a phase-change random access memory (PRAM) device, a ferroelectric random access memory (FRAM) device, a resistive random access memory (RRAM) device, and / or a magnetic random access memory (MRAM) device. The storage device can include a solid-state drive (SSD), a hard disk drive (HDD), a read-only compact disc (CD-ROM), etc. The input / output device 1040 can include an input device (e.g., a keyboard, a keypad, a mouse, etc.) and an output device (e.g., a printer, a display device, etc.). The power supply 1050 provides operating voltages for the computer system 1000.

[0102] The image sensor 900 can communicate with the processor 1010 via buses or other communication links. The image sensor 900 and the processor 1010 can be integrated into a single chip, or they can be implemented as separate chips.

[0103] The Computing System 1000 can be packaged according to one or more of a wide range of package technologies, such as Package-on-Package (PoP), Ball Grid Arrays (BGAs), Chip-Scale Packages (CSPs), Plastic-Leaded Chip Carriers (PLCCs), Plastic Dual In-Line Packages (PDIPs), Die-In-Waffle Packs, Die-In-Wafer Forms, Chip-On-Board (COBs), Ceramic Dual In-Line Packages (CERDIPs), Plastic Metric Quad Flat Packs (MQFPs), Thin Quad Flat Packs (TQFPs), Small Outline Integrated Circuits (SOICs), Shrink Small Outline Packages (SSOPs), Thin Small Outline Packages (TSOPs), System-In-Packages (SIPs), and Multi-Chip Packages (MCPs). Wafer-Level Fabricated Package (WFP) or Wafer-Level Processed Stack Package (WSP).

[0104] The computing system 1000 can be any computer system from a wide variety of different computing systems and can include an embedded logic analyzer according to at least some exemplary embodiments of the inventive concepts. For example, the computing system 1000 can include a digital camera, a mobile phone, a smartphone, a portable multimedia player (PMP), a personal digital assistant (PDA), etc.

[0105] Fig. 24 is a block diagram representing an interface in the computing system. Fig. 23 can be used according to at least some exemplary embodiments of the inventive concepts.

[0106] Referring to Fig. 24. A computing system 1100 can be implemented by a data processing device that uses a Mobile Industry Processor Interface (MIPI®). The computing system 1100 can include an application processor 1110, an image sensor 1140, a display device 1150, etc. A CSI host 1112 of the application processor 1110 can perform serial communication with a CSI device 1141 of the image sensor 1140 via a Camera Serial Interface (CSI) interface. In at least some exemplary embodiments of the inventive concepts, the CSI host 1112 can include a deserializer (DES) and the CSI device 1141 can include a serializer (SER). A DSI host 1111 of the application processor 1110 can perform serial communication with a DSI device 1151 of the display device 1150 via a Display Serial Interface (DSI) interface.

[0107] In at least some exemplary embodiments of the inventive concepts, the DSI host 1111 can include a serializer (SER), and the DSI device 1151 can include a deserializer (DES). The computing system 1100 can further include a radio frequency (RF) chip 1160, which performs communication with the application processor 1110. A physical layer (PHY) 1113 of the computing system 1100 and a physical layer (PHY) 1161 of the RF chip 1160 can perform data communication based on a MIPI® DigRFSM standard. The application processor 1110 can further include a DigRFSM master 1114, which controls the data communication of the PHY 1161.

[0108] The 1010 processor can include an embedded logic analyzer ELA 1115. The embedded logic analyzer 1115 can be configured for efficient control of the collection of data required for troubleshooting, as described above. Fig.exhibiting 1 to 22. For example, the ELA 1115 may have the same structure and function as described above with reference to the ELA 50, the ELA 51 or the ELA 52.

[0109] The 1100 computer system can further include a global positioning system (GPS) 1120, a memory 1170, a microphone 1180, a DRAM device 1185, and a speaker 1190. Additionally, the 1100 computer system can perform communication using ultra-wideband (UWB) 1210, wireless local area network (WLAN) 1220, worldwide interoperability for microwave access (WiMAX) 1230, etc. However, the architecture and interface of the 1100 computer system are not limited to these.

[0110] As will be recognized by those skilled in the art, exemplary embodiments of the inventive concepts may be a system, a method, a computer program product, and / or a computer program product formed on one or more computer-readable media with computer-readable program code formed thereon. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device. The computer-readable medium may be a computer-readable signaling medium or a computer-readable storage medium. The computer-readable storage medium may be any physical medium capable of containing or storing a program for the purpose of using, or in conjunction with, an instruction execution system, device, or apparatus.

[0111] The present disclosure can be applied to any devices and systems with an embedded logic analyzer for error correction of any integrated circuits. For example, the present disclosure can be applied to systems such as a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital television, a set-top box, a portable game console, a navigation system, etc.

Claims

[1] Embedded logic analyzer (50) of an integrated circuit (10) comprising: a comparator block (100) configured to generate a comparator data signal (CPDT) and a plurality of comparator enable signals (CMPEN) based on an input data signal (INDT) from one of the function blocks (11-17) contained in the integrated circuit (10), such that the comparator enable signals (CMPEN) are each activated based on different comparator conditions; an operation block (200) configured to perform a logic operation on the comparison enable signals (CMPEN) to generate a data enable signal (DTEN) indicating a data acquisition time; and a packer circuit (300) configured to generate a packer data signal (PCKDT) with acquisition data and acquisition time information, based on the acquisition data signal (CPDT), the data release signal (DTEN) and a time information signal (TMINF), where the comparison block (100) contains: a plurality of comparator circuits (COMP1-COMP8), each comparator circuit (COMP1-COMP8) being configured to generate a enable signal (CMPEN1-CMPEN8) from the comparator enable signals (CMPEN) based on the input data signal (INDT) and a control signal from the comparator control signals (CMPCON) specifying the comparator control conditions, where at least one first comparator circuit of the majority of comparators (COMP1-COMP8) is configured to: Shifting of one of the input data signal (INDT) and a first shifted data signal from a second comparator circuit of the plurality of comparators (COMP1-COMP8) to generate a second shifted data signal and Comparing the second shifted data signal with a reference data signal and a third shifted data signal from a third comparator circuit of the plurality of comparators to generate the enable signal generated by the first comparator circuit. [2] Embedded logic analyzer (50) according to claim 1, further comprising: a main controller (400) configured to generate comparison control signals (CMPCON) indicating the comparison conditions, operation control signals (OPTCON) controlling the logic operation of the operation block (200), and packer control signals (PCKCON) controlling an operation of the packer circuit (300). [3] Embedded logic analyzer (50) according to claim 1, wherein at least one first comparator circuit of the plurality of comparators (COMP1-COMP8) is configured to shift the input data signal (INDT) to generate a shifted data signal (CMPDT1-CMPDT8) and is configured to compare the shifted data signal (CMPDT1-CMPDT8) with a reference data signal (CMPVL) to generate the enable signal (CMPEN1-CMPEN8) generated by the first comparator circuit. [4] Embedded logic analyzer according to claim 1, wherein at least one first comparator circuit contains the plurality of comparators: a first shift register (LSR) configured to shift the input data signal left in response to the first bits of a shift control signal (SFT), where the first bits represent a shift number to the left; a second shift register (RSR) configured to shift an output signal (SFDT) of the first shift register (LSR) to the right in response to second bits of the shift control signal (SFT), where the second bits represent a shift number to the right; and a comparator (CMP) configured to compare an output signal (CMPDT) of the second shift register (RSR) with a reference data signal (CMPVL) in response to third bits of the shift control signal (SFT) to generate the enable signal (CMPEN) generated by the first comparator circuit, where the third bits represent a number of comparator bits. [5] Embedded logic analyzer according to claim 3, wherein the comparison block further comprises: a multiplexer (MX2) configured to select a signal from the input data signal (INDT) and shift data signals (CMPDT1) generated by the plurality of comparator circuits (COMP1-COMP8) and to output the selected signal as the acquisition data signal (CPDT). [6] Embedded logic analyzer according to claim 1, wherein the operation block (200) contains: a first operational circuit (210) configured to generate a start trigger enable signal (STREN) based on the comparison enable signals (CMPEN) and a start trigger control signal (STROP); a second operational circuit (220) configured to generate an end-of-life release signal (ETREN) based on the comparison release signals (CMPEN) and an end-of-life control signal (ETROP); and a third operational circuit (230) configured to generate a write enable signal (WREN) based on the compare enable signals (CMPEN) and a compare enable control signal (WENOP). [7] Embedded logic analyzer according to claim 6, wherein each comprises the first operational circuit (210), the second operational circuit (220) and the third operational circuit (230): a plurality of multiplexers (211-215) configured to output first selected signals (SCMPEN1-SCMPEN4) selected from the comparison enable signals (CMPEN1-CMPEN8), such that the first selected signals (SCMPEN1-SCMPEN5) correspond to a portion of the comparison enable signals in response to each of the start release control signal (STROP), end release control signal (ETROP), and write enable control signal (WNOP); and an operator circuit (216) configured to perform a logic operation on the first selected signals (SCMPEN1-SCMPEN6) in response to each of the start release control signal (STROP), the end release control signal (ETROP) and the write enable control signal (WNOP) to generate each of the start release enable signal (STREN), the end release enable signal (ETREN) and the write enable signal (WREN). [8] Embedded logic analyzer according to claim 6, wherein the operation block (200) further comprises: a time controller (250) configured to generate the write-on signal (WRON), which indicates the start and end times of the data acquisition period, in response to the start trigger enable signal (STREN), the end trigger enable signal (ETREN), and a time control signal (TMCON); and a logic gate (260) configured to generate the data release signal (DTEN) based on the write enable signal (WRON) and the write enable signal (WREN). [9] Embedded logic analyzer according to claim 8, wherein the time controller (250) comprises: a first logic circuit (251) configured to generate a write start signal (WSTT) indicating the start time of the data acquisition period; a second logic circuit (252) configured to generate a write signal (WEND) indicating the end time of the data acquisition period; an internal timer (253) configured to provide a relative time of data acquisition; and a counter (254) configured to count activation counts of the start trigger enable signal (STREN) and the end trigger enable signal (ETREN). [10] Embedded logic analyzer according to claim 6, wherein the first operational circuit (210) is configured to vary the start trigger control signal (STROP) based on a number of activations of the start trigger enable signal (STREN) and The second operational circuit is configured to vary the end-of-travel control signal (ETROP) based on a number of activations of the end-of-travel release signal (ETREN). [11] Embedded logic analyzer according to claim 1, wherein the packer circuit (300) comprises: a data extraction circuit (311) configured to generate data bit signals (DB1-DB4) based on the acquisition data signal (CPDT), wherein the data bit signals (DB1-DB4) all have different numbers of bits; a time information extraction circuit (312) configured to generate time information bit signals (TIB1-TIB4) based on the time information signal (TMINF), wherein the time information bit signals (TIB1-TIB4) all have different numbers of bits; a synthesis circuit (313) configured to combine the data bit signals (DB1-DB4) and the time information bit signals (TIB1-TIB4) to generate combined data signals (SYND1-SYND4) that all have the same number of bits; and a multiplexer (314) configured to selectively output one of the combined data signals (SYND1-SYND4) as the packer data signal (PCKDT), based on a time-variable signal (TMSZ). [12] Embedded logic analyzer according to claim 1, wherein the packer circuit (302) comprises: a data extraction circuit (321) configured to generate a data bit signal (DB) of a fixed number of bits, based on the acquisition data signal (CPDT); a time information extraction circuit (322) configured to generate a time information bit signal (TIB) of a fixed number of bits, based on the time information signal (TMINF); and a multiplexer (323) configured to selectively output one of the data bit signal (DB) and the time information bit signal (TIB) as the packer data signal (PCKDT) based on a time span signal (TMPD). [13] Embedded logic analyzer according to claim 1, wherein the packer circuit (300; 301; 302) is configured to set a number of bits that have been captured for the capture data from an aggregate of bits of the capture data signal (CPDT) in response to a bit width signal (BTWD). [14] Embedded logic analyzer (50) according to claim 1, further comprising: an input selection circuit configured to select one of the logic signals from the function blocks (11-17) as the input data signal (INDT). [15] Integrated circuit (10) with: the embedded logic analyzer (50) according to claim 1; a connecting circuit (20); and the functional blocks (11-17), wherein the functional blocks (11-17) are connected to the connecting circuit (20) and wherein the embedded logic analyzer (50) is directly connected to at least one of the functional blocks (11-17). [16] Embedded logic analyzer (50) comprising an integrated circuit (10): an input selection circuit (500) configured to select one of the logic signals (INLOG1-INLOGn) of functional blocks (11-17) contained in the integrated circuit (10) as an input data signal (INDT) and to provide the input data signal (INDT); a comparison block (100) configured to generate a capture data signal (CPDT) and a plurality of comparison enable signals (CMPEN) based on the input data signal (INDT), such that the comparison enable signals (CMPEN) are activated based on different comparison conditions; an operation block (200) configured to perform a logic operation on the comparison enable signals (CMPEN) to generate a data enable signal (DTEN) indicating a data acquisition time; a packer circuit (300) configured to generate a packer data signal (PCKDT) containing acquisition data and acquisition time information, based on the acquisition data signal (CPDT), the data release signal (DTEN), and a time information signal (TMINF); and a main controller (400) configured to control operations of the input selection circuit (500), the comparator block (100), the operation block (200) and the packer circuit (300), the packer circuit (300) contains: a data extraction circuit (311) configured to generate data bit signals (DB1-DB4) based on the acquisition data signal (CPDT), wherein the data bit signals (DB1-DB4) all have different numbers of bits; a time information extraction circuit (312) configured to generate time information bit signals (TIB1-TIB4) based on the time information signal (TMINF), wherein the time information bit signals (TIB1-TIB4) all have different numbers of bits; a synthesis circuit (313) configured to combine the data bit signals (DB1-DB4) and the time information bit signals (TIB1-TIB4) to generate combined data signals (SYND1-SYND4) that all have the same number of bits; and a multiplexer (314) configured to selectively output one of the combined data signals (SYND1-SYND4) as the packer data signal (PCKDT), based on a time-variable signal (TMSZ). [17] Embedded logic analyzer with: a first circuit that is configured to: Receiving input data generated by at least one functional block of an integrated circuit, and Generating acquisition data based on reference data signals and the input data; and a second circuit configured to generate a packer data signal with fault correction information from the integrated circuit by combining acquisition data and acquisition time information, based on the acquisition data signal, the second circuit contains: a data extraction circuit (321) configured to generate a data bit signal (DB) of a fixed number of bits, based on the acquisition data signal (CPDT); a time information extraction circuit (322) configured to generate a time information bit signal (TIB) of a fixed number of bits, based on the time information signal (TMINF); and a multiplexer (323) configured to selectively output one of the data bit signal (DB) and the time information bit signal (TIB) as the packer data signal (PCKDT) based on a time span signal (TMPD). [18] Embedded logic analyzer according to claim 17, further comprising: an operating block where the first circuit is further configured to generate initial enable signals, where the operation block is configured to perform a logic operation based on the initial enable signals to generate a data enable signal indicating a data acquisition time, and the second circuit is configured to generate the packer data signal, based on the data release signal, the acquisition data signal and a time information signal.

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