Integrated circuit with amplifier MOSFET and method for its manufacture as well as analog output stage

Abstract

Integrated circuit (200) comprising: - a substrate (106), - an amplifier MOSFET (100), and - a bias terminal (110) configured to generate a potential difference of the substrate (106) relative to at least one load terminal (101, 102) of the amplifier MOSFET (100), wherein the resistivity of the substrate (106) is not less than 0.3 kΩ cm, and the potential difference is -3 volts or more negative, and - at least one input terminal (221, 222) connected to a control terminal (103) of the amplifier MOSFET (100) and configured to receive at least one input signal, and - an output terminal (231) configured to output a signal, and - at least one switch (302, 303, 401, 402) arranged adjacent to the at least one input terminal (221, 222). is and has a series connection of switch MOSFETs (431) to ground (217),wherein the switch MOSFETs (431) and the amplifier MOSFET (100) have the same gate length (103A), wherein the at least one switch (302, 303, 401, 402) is arranged in a bypass branch (301) which connects the at least one input terminal (221, 222) to the output terminal (231) bypassing the amplifier MOSFET (100), wherein the integrated circuit (200) comprises several switches (302, 303, 401, 402) and several input terminals (221, 222), wherein at least some of the several switches (302, 303, 401, 402) are each associated with a corresponding one of the several input terminals (221, 222), and at least one overvoltage protection element (601, 602) comprising at least one ESD MOSFET (611, 831) wherein the at least one ESD MOSFET (611, 831) and the amplifier MOSFET (100) have the same gate length (103A), wherein the at least one overvoltage protection element (601, 602) is located between the at least one input terminal (221,222) and the control terminal (103) of the amplifier MOSFET (100), and / or wherein the at least one overvoltage protection element (601, 602) is arranged between the at least one load terminal (101, 102) of the amplifier MOSFET (100) and the output terminal (231), wherein the at least one overvoltage protection element (601, 602) is implemented by the at least one switch (302, 303, 401, 402).

Description

TECHNICAL AREA Various embodiments involve an integrated circuit with an amplifier MOSFET and a substrate. The potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET is -3 V or less. The resistivity of the substrate is not less than 0.3 kΩ·cm. BACKGROUND In many applications, amplifying a signal with low noise is desirable. This is particularly true for high-frequency signals, where low noise amplification can be highly advantageous. Silicon-germanium (SiGe) technology is often used to implement such low-noise amplifiers (LNAs). SiGe transistors can exhibit a relatively high threshold voltage (typically 0.7V) coupled with relatively high current consumption due to the base-emitter diode, as well as temperature dependence (typically 2mV / K) for switching from a non-conducting to a conducting state. Furthermore, SiGe transistors can offer high robustness against electrostatic discharge. On the other hand, the complexity of manufacturing components using SiGe technology can be comparatively high. Furthermore, the linearity and efficiency of switches based on SiGe technology can often be severely limited. This can be particularly true compared to complementary metal-oxide semiconductor (CMOS) technology. CMOS technology uses metal oxide field-effect transistors (MOSFETs). US 2014 / 0042545A1 discloses a MOS transistor with a substrate comprising a semiconductor area. The semiconductor area is doped with a first dopant type. The first dopant type has a reference doping level. A well is formed in the semiconductor surface, the well being doped with a second dopant type. An implantation dose can be selected to reduce leakage within the boundary condition; the boundary condition concerns the increase in the electric field of the depletion region, which arises from the migration of dopants from the high-energy implantation region into the depletion region in the well. For example, a 3 V reverse bias across the well-substrate junction results in at least 90% of the total dose of the reverse doping region being located between the bottom of the depletion region of the well and a diffusion length below the bottom of the depletion region of the well. JP H09-270515A discloses a semiconductor thin-film layer deposited on a high-resistance substrate with an insulating separator layer placed between them. The high-resistance substrate is a semiconductor exhibiting a substrate resistance of 1 kΩ cm or greater. US 2009 / 0159968A1 discloses a double-defused MOS transistor with an extended drain region. US 5 923 067 A discloses an SOI substrate with a silicon thin-film layer separated from bulk silicon by an insulator. US 6 300 649 B1 discloses a SOI MOSFET with improved electrical characteristics, including a low-threshold bulk contact below the source region. However, conventional CMOS amplifier implementations exhibit disadvantages regarding signal-to-noise ratio compared to similar silicon-germanium implementations. The signal-to-noise ratio can be significant. SUMMARY Therefore, there is a need for improved amplifier circuit techniques. In particular, there is a need for techniques that alleviate or eliminate at least some of the aforementioned disadvantages and limitations. This task is solved by the features of the independent patent claims. The dependent patent claims define embodiments. According to an example according to claim 1, an integrated circuit comprises, in particular, a substrate and an amplifier MOSFET. The integrated circuit also includes a bias terminal. The bias terminal is configured to generate a potential difference between the substrate and at least one load terminal of the amplifier MOSFET. The resistivity of the substrate is not less than 0.3 kΩ·cm. The potential difference is -3 V or negative. The integrated circuit further comprises at least one input terminal connected to a control terminal of the amplifier MOSFET and configured to receive at least one input signal, and one output terminal configured to output a signal.The integrated circuit further comprises at least one switch located adjacent to the at least one input terminal and having a series connection of switch MOSFETs to ground, wherein the switch MOSFETs and the amplifier MOSFET have the same gate length, wherein the at least one switch is located in a bypass branch connecting the at least one input terminal to the output terminal bypassing the amplifier MOSFET, wherein the integrated circuit comprises multiple switches and multiple input terminals, wherein at least some of the multiple switches are each associated with a corresponding input terminal.The integrated circuit further comprises at least one overvoltage protection element, which includes at least one ESD MOSFET, wherein the at least one ESD MOSFET and the amplifier MOSFET have the same gate length, wherein the at least one overvoltage protection element is arranged between the at least one input terminal and the control terminal of the amplifier MOSFET, and / or wherein the at least one overvoltage protection element is arranged between the at least one load terminal of the amplifier MOSFET and the output terminal, wherein the at least one overvoltage protection element is implemented by the at least one switch. In a further example according to claim 12, a method comprises processing a substrate such that the substrate has a specific resistance of not less than 0.3 kΩ cm. The method also comprises providing an integrated circuit on the substrate, comprising an amplifier MOSFET and a bias terminal. The bias terminal is configured to generate, during amplifier operation of the amplifier MOSFET, a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET that is -3 V or more negative. The features set out above and those described below can be used not only in the corresponding explicitly set out combinations, but also in further combinations or in isolation, without leaving the scope of protection of the present invention. BRIEF DESCRIPTION OF THE FIGURES Fig. 1A schematically illustrates an N-channel MOSFET according to various embodiments. Fig. 1B schematically illustrates a P-channel MOSFET according to various embodiments. Fig. 2 schematically illustrates an integrated circuit with a MOSFET and a cascode MOSFET according to various embodiments. Fig. 3 schematically illustrates an integrated circuit with a MOSFET and a bypass branch according to various embodiments. Fig. 4 schematically illustrates an integrated circuit with a MOSFET, several input terminals, and several switches associated with the input terminals according to various embodiments. Fig. 5 schematically illustrates the switches of Fig. 4 in greater detail according to various embodiments. Fig. 6 schematically illustrates an integrated circuit with a MOSFET and overvoltage protection elements according to various embodiments. Fig. 7 schematically illustrates the overvoltage protection elements of Fig.Figure 6 shows in greater detail various embodiments. Figure 8 schematically illustrates an integrated circuit with a MOSFET according to various embodiments. Figure 9 is a flowchart of a method according to various embodiments. DETAILED DESCRIPTION OF EXECUTION FORMS The properties, features and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more easily understood in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the drawings. The present invention is explained in more detail below with reference to preferred embodiments and the drawings. In the figures, identical reference numerals denote identical or similar elements. The figures are schematic representations of various embodiments of the invention. Elements depicted in the figures are not necessarily shown to scale. Rather, the various elements depicted in the figures are represented in such a way that their function and general purpose are understandable to a person skilled in the art. Connections and couplings between functional units and elements shown in the figures can also be implemented as indirect connections or couplings. Functional units can be implemented as hardware, software, or a combination of hardware and software. The following describes techniques for providing integrated circuits configured to amplify an input signal with a gain factor and output a corresponding signal. These techniques are particularly suitable for amplifying a high-frequency input signal. Signal components of the high-frequency input signal can have frequencies above 1 GHz, above 3 GHz, or above 10 GHz. The techniques described herein can, for example, provide an integrated circuit with a MOSFET. The MOSFET typically includes a control terminal, also known as the gate terminal. It also typically includes two load terminals, also known as the drain and source terminals. A control voltage applied to the control terminal switches the conductivity between the load terminals. The MOSFET can amplify the input signal and can therefore also be called an amplifier MOSFET. The MOSFET can be manufactured using CMOS technology. This means that the MOSFET can be, for example, a P-channel or an N-channel MOSFET. Silicon can be used as the substrate. It is not necessary for the MOSFET to be manufactured using silicon-on-insulator (SOI) technology. In various examples, the substrate may have a particularly low phosphorus doping concentration. This can mean that the substrate has a comparatively high resistivity. For example, the resistivity of the substrate could be 0.3 kΩ·cm or greater. In other examples, the substrate might have a negative bias relative to a reference potential. For instance, this potential difference between the substrate and the MOSFET's source terminal could be -3 V or less. Similarly, this potential difference between the substrate and the MOSFET's drain terminal could be -3 V or less. Using such techniques, parasitic capacitances can be significantly reduced, thereby gaining additional degrees of freedom regarding transistor geometry. This allows for optimization towards exceptionally low signal noise during amplification. This can be achieved, for example, by specifically improving the conductivity of the gate polysilicon. As a result, amplification with high Qts can be implemented. Simultaneously, it may be possible to implement the integrated circuit using the established and well-controlled CMOS technology, further leveraging the advantages of logic integration. Furthermore, by using a MOSFET it may be possible to provide the amplification with high linearity. Figure 1A illustrates aspects relating to a MOSFET 100. For example, the MOSFET 100 could be used to amplify an input signal, i.e., as an amplifier MOSFET. In the example shown in Figure 1A, the MOSFET 100 is implemented as an N-channel MOSFET (often also referred to as NMOS). This means that by applying a control voltage to the control terminal 103, a channel with negative charge carriers forms between the load terminals 101 and 102 in the otherwise p-doped substrate 106, e.g., silicon. A load current can then flow between the load terminals 101 and 102 via these negative charge carriers (conducting state of the MOSFET 100). The control terminal 103 is separated from the substrate 106 by an insulating layer 105. Fig. 1A further illustrates aspects relating to a bias voltage between the substrate 106 and a reference potential. A bias terminal 110 is shown in Fig. 1A. This terminal is configured to generate a potential difference between the substrate 106 and at least one of the load terminals 101, 102 – for example, relative to the source terminal 101. The potential difference can be defined as: ΔU = Usubstrate - Usource, where Usubstrate denotes the electrical potential of the substrate and Usource denotes the electrical potential of the source terminal 101. For example, the bias terminal 110 could be configured as a contact pad so that an external voltage source can be connected to the integrated circuit 100 to generate the potential difference. It would also be possible for the bias terminal 110 to be connected to a voltage source integrated on the integrated circuit 100, for example, a supply terminal. For example, the potential difference could be -3 volts or negative. It would also be possible for the potential difference to be -4 volts or negative, preferably -6 volts or negative, and most preferably -8 volts or negative. Fig. 1A further illustrates aspects relating to the doping of the substrate 106. In the example shown in Fig. 1A, the substrate 106 has a doping 195 with few acceptors (not shown in Fig. 1A). Therefore, the substrate 106 is weakly P-doped. The doping 195 can be carried out such that the substrate 106 has a specific resistivity. For example, the resistivity could be 0.3 kΩ cm or greater. It would also be possible for the resistivity to be 0.5 kΩ cm or greater, preferably 1 kΩ cm or greater, and most preferably 5 kΩ cm or greater. Fig. 1B illustrates aspects relating to a MOSFET 100. Again, the MOSFET 100, as shown in Fig. 1B, could be used to amplify an input signal, i.e., as an amplifier MOSFET. In the example of Fig. 1B, the MOSFET 100 is implemented as a P-channel MOSFET. The P-channel MOSFET 100 in Fig. 1B is essentially equivalent to the N-channel MOSFET 100 in Fig. 1A. The P-channel MOSFET 100 in Fig. 1B has an N-doped well 104 surrounding the load terminals 101 and 102. Applying a control voltage to the control contact 103 allows a channel with positive charge carriers to form within the N-doped well. Figures 1A and 1B also show a gate length 103A of the control pin 103. The gate length 103A is typically defined by the CMOS technology used. Typical gate lengths 103A are, for example, in the range of 14 nm to 1000 nm.In Figures 1A and 1B, parasitic capacitances 120 are shown between the load terminals 101 and 102 and the substrate 106. These capacitances 106 arise due to charge carrier depletion in the area of ​​a space charge region, where a separation of positive and negative charge carriers occurs. Due to the low doping 195, only a few free charge carriers are available in the region of the substrate 106. In other words, the comparatively high resistivity of the substrate 106 results in few free charge carriers being present in this region. Therefore, a particularly large space charge region is achieved. Consequently, the capacitances 106 are comparatively small. This allows for larger, lower-impedance geometries, which can be used to reduce signal noise.Furthermore, the low capacitance can reduce the requirements for the high-frequency matching circuit and, for example, allow for smaller inductance values: this also reduces losses. Reducing losses, in turn, further reduces signal noise. In most examples, the use of an N-channel MOSFET 100 is preferred over the use of a P-channel MOSFET 100 due to its significantly slower switching times and operating frequencies 106. A P-channel MOSFET typically has a significantly lower gain. It is often desirable to implement a particularly large gate width for the MOSFET 100. The gate width refers to the extent of the MOSFET 100 perpendicular to the line connecting the load terminals 101 and 102. The gate width can be adjusted, for example, by connecting several finger structures in parallel, each comprising a transistor element of the MOSFET 100. By using a comparatively large gate width for the MOSFET 100, a particularly low signal noise can be achieved during amplification. For example, the gate width of the MOSFET 100 could be > 100 µm, preferably > 200 µm, and most preferably > 500 µm. For instance, the gate width of the MOSFET 100 could be in the range of 280–580 µm. The various examples described herein are based on the understanding that the high resistivity of substrate 106 reduces the influence of the capacitors 120. This, in turn, makes it possible to use a larger gate width for MOSFET 100 without achieving unacceptably high absolute values ​​for the capacitors 120. This, in turn, allows the channel resistance between load terminals 101 and 102 to be reduced. This, in turn, results in lower signal noise during amplification. The following describes various examples relating to P-channel MOSFETs 100. However, corresponding techniques could also be implemented with N-channel MOSFETs 100. Fig. 2 illustrates aspects relating to an integrated circuit 200. The circuit 200 comprises the MOSFET 100, e.g., according to one of the examples in Fig. 1A, Fig. 1B. The MOSFET 100 is connected with its load terminals 101, 102 between a supply terminal 216 and ground 217. A corresponding current flow can be switched between the load terminals of the MOSFET 100 as a function of the input signal at the control terminal 103 of the MOSFET 100. The circuit 200 implements an LNA based on the MOSFET 100. For simplification, the bias setting for the MOSFET 100 is not shown in Fig. 2. Circuit 200 also includes an input terminal 221 which is configured to receive an input signal, for example, a high-frequency input signal. Input terminal 221 is connected to the control terminal 103 of MOSFET 100. An inductor 221 is located adjacent to the input terminal 221. This inductor filters the input signal. The inductance 221 depends on the source impedance as well as the operating frequency and can therefore be omitted in some examples. Circuit 200 also includes an output terminal 231, which is configured to output a signal, for example, a high-frequency output signal. The output terminal 231 is located on the side of the MOSFET 100 facing the load terminals 101 and 102. The output signal can correspond to the input signal but have a larger amplitude. Such amplification of the input signal can be achieved by the MOSFET 100. The ratio of the output signal amplitude to the input signal amplitude defines a gain factor. The circuit 200 also includes an inductor 212. The inductor 212 is arranged on the side of the MOSFET 100 facing the load terminals 101, 102. In the example shown in Fig. 2, the inductor 212 is arranged between the source terminal 101 of the MOSFET 100 and ground 217. The MOSFET 100 and the inductor 212 determine the gain factor. For example, the gain factor can be 10 dB or greater, preferably 15 dB or greater, and most preferably 18 dB or greater. In various examples described herein, the MOSFET 100 is not manufactured using SOI technology. The load terminals 101, 102 of the MOSFET 100 are therefore not separated from the substrate 106 by an insulating layer, i.e., they are arranged in bulk technology with respect to the substrate 106. This means that the potential difference and the resistivity can be implemented as bulk properties of the circuit 200. This means that the potential difference and resistivity can be present across the entire circuit 200. Multiple bias terminals 100 are not required; a single bias terminal 100 can serve the entire circuit 200. In particular, it may be unnecessary to implement individual parameters for the doping 195 and the potential difference in each of the transistors of the integrated circuit 200.This allows for a particularly low level of complexity in the manufacturing technology used. Circuit 200 also includes a cascode MOSFET 213, which is arranged between the drain terminal 102 of MOSFET 100 and the output terminal 231. The cascode MOSFET 213 is switched by a supply voltage provided via a supply terminal 215 (for clarity, Fig. 2 does not show a circuit for providing the cascode voltage to the cascode MOSFET 213). The cascode MOSFET 213 can be used to suppress the Miller effect. It is possible for the cascode MOSFET 213 and the MOSFET 100 to be manufactured using the same technology. In particular, the cascode MOSFET 213 and the MOSFET 100 can have identical structural parameters. For example, it would be possible for the cascode MOSFET 213 and the MOSFET 100 to have the same gate length 103A. This would enable particularly simple manufacturing of the circuit 200. In particular, it would eliminate the need to implement the separate manufacturing of the MOSFET 100 and the cascode MOSFET 213. The MOSFET 100 and the cascode MOSFET 213 can have the same potential difference between their respective load terminals 101, 102 and the substrate 106. The same bias terminal 110 can be used for this purpose. In some examples, it would be possible for the cascode MOSFET 213 and the MOSFET 100 to have different gate widths. An inductor 214 is further provided to increase the impedance towards the supply terminal 216 for the high-frequency output signal. Fig. 3 illustrates aspects relating to an integrated circuit 200. The circuit 200 comprises the MOSFET 100, for example, according to one of the examples in Fig. 1A or Fig. 1B. The circuit 200 according to the example in Fig. 3 is fundamentally the same as the circuit 200 according to the example in Fig. 2. In particular, various aspects described above with regard to the circuit 200 according to the example in Fig. 2 can also be applied to the circuit 200 according to the example in Fig. 3. The circuit 200 implements an LNA based on the MOSFET 100. In the example shown in Fig. 3, the circuit 200 comprises two switches 302 and 303. Switches 302 and 303 are arranged adjacent to the input terminal 221. Switch 302 is located between the input terminal 221 and the control terminal 103 of the MOSFET 100. Switch 302 is arranged in a bypass branch 301 that connects the input terminal 221 to the output terminal 231, bypassing the MOSFET 100. Depending on the amplitude of the input signal at input terminal 221, it would be possible to selectively activate the bypass branch 301 by actuating switches 302 and 303 accordingly, thus enabling or suppressing the amplification of the input signal. This allows, for example, power amplifiers, the energy consumption of MOSFET 100 to be reduced by bypassing it when the input signal amplitude is sufficiently large. Furthermore, input-side compression / saturation of MOSFET 100 can be avoided. Fig. 4 illustrates aspects relating to an integrated circuit 200. The circuit 200 comprises the MOSFET 100, for example, according to one of the examples in Fig. 1A or Fig. 1B. The circuit 200 according to the example in Fig. 4 is fundamentally the same as the circuit 200 according to the examples in Fig. 2 and Fig. 3. In particular, various aspects described above with regard to the circuit 200 according to the examples in Fig. 2 and Fig. 3 can also be applied to the circuit 200 according to the example in Fig. 4. The circuit 200 implements an LNA based on the MOSFET 100. In the example shown in Fig. 4, the circuit 200 comprises several switches 401, 402 and several input terminals 221, 222. Switches 401, 402 are each associated with one of the input terminals 221, 222. For example, switch 401 is located adjacent to input terminal 221. Specifically, switch 401 is located between the control terminal 103 of the MOSFET 100 and input terminal 221. Switch 402 is also located adjacent to input terminal 222. Specifically, switch 402 is located between the control terminal 103 of the MOSFET 100 and input terminal 222. By appropriately actuating switches 401, 402, it is possible to select between different input signals at input terminals 221, 222 for amplification using MOSFET 100. Fig. 5 illustrates details of switches 302, 303, 401, and 402. Switches 302, 303, 401, and 402 are each implemented by a series connection of switch MOSFETs to ground 217. The switch MOSFETs can have the same gate length 103A as MOSFET 100. This allows for particularly simple fabrication of circuit 200. In particular, it eliminates the need to fabricate MOSFET 100 and the switch MOSFETs separately. In the example shown in Fig. 5, the respective switches 302, 303, 401, 402 are implemented by several switch MOSFETs 431 with associated control resistors 441 and supply terminals 450. By stacking switch MOSFETs 431 in this way, the comparatively low breakdown voltage of the individual switch MOSFETs 431 can be compensated for by a uniform distribution of the voltage drop across the various switch MOSFETs 431 in the stack. The MOSFET 100 and the switching MOSFETs 431 can have the same potential difference between their respective load terminals 101 and 102 and the substrate 106. The same bias terminal 110 can be used for this purpose. The negative bias of the substrate 106 reduces parasitic substrate diodes in the switching MOSFETs 431. This results in a particularly linear voltage distribution for the "OFF" state within the stack 431 for switches 302, 303, 401, and 402. Fig. 6 illustrates aspects relating to an integrated circuit 200. The circuit 200 comprises the MOSFET 100, for example, according to one of the examples in Fig. 1A or Fig. 1B. The circuit 200 according to the example in Fig. 6 is fundamentally equivalent to the circuit 200 according to the example in Figs. 2-4. In particular, various aspects described above with regard to the circuit 200 according to the example in Figs. 2-4 can also be applied to the circuit 200 according to the example in Fig. 6. The circuit 200 implements an LNA based on the MOSFET 100. The circuit 200 in the example shown in Fig. 6 further includes an overvoltage protection element 601, which is arranged between the input terminal 221 and the MOSFET 100. The overvoltage protection element 601 is thus located on the side of the MOSFET 100 facing its control terminal 101. The overvoltage protection element 601 can be configured to dissipate overvoltages of the input signal—for example, due to electrostatic discharges during manual handling of the circuit 200—to ground 217. In this way, damage to the MOSFET 100 can be prevented. The circuit 200 in the example of Fig. 6 further comprises an overvoltage protection element 602, which is arranged between the output terminal 231 and the MOSFET 100. The overvoltage protection element 602 is thus arranged on a side of the MOSFET 100 facing the load terminals 101, 102 of the MOSFET 100. In particular, the overvoltage protection element 602 is arranged between the drain terminal 102 of the MOSFET 100 and the output terminal 231. Fig. 7 illustrates aspects relating to the surge protection elements 601, 602. In particular, Fig. 7 illustrates the surge protection elements 601, 602 according to an exemplary implementation in greater detail. The overvoltage protection elements 601, 602 comprise a capacitor 612, an ESD MOSFET 611, a resistor 613, and a supply terminal 614. In the example shown in Fig. 7, the overvoltage protection elements 601, 602 comprise only a single ESD MOSFET 611. In other examples, however, it would also be possible for the overvoltage protection elements 601, 602 to comprise a series connection of several ESD MOSFETs 611 – comparable to the implementation of switches 202, 303, 401, 402 according to the example shown in Fig. 5. It is possible that at least one ESD MOSFET 611 has the same gate length of 103A as MOSFET 100. This would, in turn, enable particularly simple manufacturing of circuit 200. In particular, it may be unnecessary to implement the separate manufacturing of MOSFET 100 and ESD MOSFET 611. In some examples, the functionality of switches 302, 303, 411, 412 and the functionality of surge protection elements 601, 602 could be implemented by corresponding structures with stacked MOSFETs 431, 611. In such examples, for instance, the surge protection element 601, which is located adjacent to input terminal 221, could be implemented by the corresponding switch 303. This would allow for a particularly high level of integration of the circuit 200. The MOSFET 100 and the at least one ESD MOSFET 611 can have the same potential difference between their respective load terminals 101, 102 and the substrate 106. The same bias terminal 110 can be used for this purpose. Fig. 8 illustrates aspects relating to an integrated circuit 200. The circuit 200 comprises the MOSFET 100, for example, according to one of the examples in Fig. 1A or Fig. 1B. The circuit 200 according to the example in Fig. 8 is fundamentally equivalent to the circuit 200 according to the examples in Figs. 2-4 and 6. In particular, various aspects described above with regard to the circuit 200 according to the examples in Figs. 2-4 and 6 can also be applied to the circuit 200 according to the example in Fig. 8. The circuit 200 implements an LNA based on the MOSFET 100. The example of circuit 200 according to Fig. 8 again includes overvoltage protection elements 601, 602, which are arranged adjacent to the input terminal 221 and the output terminal 231, respectively. The overvoltage protection element 602 comprises a series connection of ESD MOSFETs 831 with corresponding gate resistors 613, 833. In addition, resistors 832 are connected in parallel to the load terminals 101, 102 of the ESD MOSFETs 832. These serve to set a quiescent potential so that the ESD MOSFET 831 can be switched in a defined manner. The MOSFET 100 and the ESD MOSFETs 832 can have the same potential difference between their respective load terminals 101, 102 and the substrate 106. The same bias terminal 110 can be used for this purpose. Circuit 200 comprises two cascode MOSFETs 213-1, 213-2. The cascode MOSFET 213-2 is controlled via a voltage divider 811, 812, 813. Capacitors 821 and 822 are located adjacent to the output terminal 231. A current mirror 801, 802 is provided for controlling the MOSFET 100, which provides a current 215 for recharging the control terminal 101 of the MOSFET 100. The circuit 200 with amplifier functionality, as described in the various examples herein, could be used in different applications. For example, the input terminal 221 could be connected to one or more antennas, such as those of a mobile phone device. Fig. 9 is a flowchart of a process according to various embodiments. In block 1001, a substrate is processed. This can be achieved, for example, by doping the substrate. The substrate is processed such that it has a specific resistance of not less than 0.3 kΩ·cm. Block 1002 involves the fabrication of an integrated circuit on the substrate. Block 1002 can include one or more lithography steps. These lithography steps might include, for example, coating the substrate with a photoresist, exposing the photoresist, developing the photoresist, depositing material, and removing the photoresist. Block 1002 could also include one or more etching steps. For example, the integrated circuit in block 1002 can be implemented using CMOS technology. Specifically, the integrated circuit could include an amplifier MOSFET and a bias terminal. The bias terminal can be configured to create a potential difference between the substrate and at least one load terminal of the amplifier MOSFET. This potential difference could be, for example, -3 V or lower. Various effects can therefore be achieved using the techniques described herein. As a first effect, the capacitances between the load terminals and the substrate of a MOSFET can be reduced due to the low conductivity or high resistivity of the substrate. This reduces the signal noise of the amplifier. For example, using the techniques described herein, amplifiers with signal noise in the range of 0.2–1.2 dB can be achieved as the minimum achievable signal noise for a given gain and frequency. Secondly, the negative bias of the substrate can reduce parasitic substrate diodes. This allows for particularly good linearity for switches implemented by a series connection of switch MOSFETs. As a third effect, due to small capacitances to the substrate, unwanted modes in high-frequency signals can also be located outside the relevant spectrum in passive components such as capacitors or inductors. Naturally, the features of the embodiments and aspects of the invention described above can be combined with one another. In particular, the features can be used not only in the combinations described, but also in other combinations or individually, without leaving the scope of the invention. While the preceding section primarily described exemplary circuits and switching elements in connection with LNAs, it would also be possible to apply corresponding techniques to power amplifiers. Power amplifiers typically switch high current flows in the range of >200 mA, or >1 A, or >50 A. The following examples are preferred embodiments of the invention. Example 1. Integrated circuit (200) comprising: - a substrate (106), - an amplifier MOSFET (100), and - a bias terminal (110) configured to generate a potential difference of the substrate (106) relative to at least one load terminal (101, 102) of the amplifier MOSFET (100), wherein the resistivity of the substrate (106) is not less than 0.3 kΩ cm, and the potential difference is -3 volts or more negative. Example 2. Integrated circuit (200) according to Integrated circuit with example 1, wherein the gate width of the amplifier MOSFET (100) is greater than 100 µm, optionally greater than 200 µm, further optionally greater than 500 µm. Example 3. Integrated circuit (200) according to Example 1 or 2, wherein the specific resistance and the potential difference are bulk properties of the substrate (106) in the area of ​​the integrated circuit (200). Example 4. Integrated circuit (200) according to one of the preceding examples, further comprising: - at least one input terminal (221, 222) connected to a control terminal (103) of the amplifier MOSFET (100) and configured to receive at least one input signal, and - an output terminal (231) located on a side facing the at least one load terminal (101, 102) of the amplifier MOSFET (100) and configured to output a signal. Example 5. Integrated circuit (200) according to Example 4, further comprising: - an inductor (212) arranged on the side facing the load terminal (101, 102) of the amplifier MOSFET (100), wherein the amplifier MOSFET (100) and the inductor (212) are configured to implement a gain of the output signal over the at least one input signal of not less than 10 dB, preferably not less than 15 dB, and most preferably not less than 18 dB. Example 6. Integrated circuit (200) according to Example 4 or 5, further comprising: - at least one cascode MOSFET (213, 213-1, 213-2) arranged between the at least one load terminal (101, 102) of the amplifier MOSFET (100) and the output terminal (231), wherein the at least one cascode MOSFET (213, 213-1, 213-2) and the amplifier MOSFET (100) have the same gate length (103A). Example 7. Integrated circuit (200) according to one of Examples 4 - 6, further comprising: - at least one switch (302, 303, 401, 402) located adjacent to the at least one input terminal (221, 222) and comprising a series connection of switch MOSFETs (431) to ground (217), wherein the switch MOSFETs (431) and the amplifier MOSFET (100) have the same gate length (103A). Example 8. Integrated circuit (200) according to Example 7, wherein the at least switch (302, 303, 401, 402) is arranged in a bypass branch (301) which connects the at least one input terminal (221, 222) to the output terminal (231) bypassing the amplifier MOSFET (100). Example 9. Integrated circuit (200) according to Example 7 or 8, wherein the integrated circuit (200) comprises several switches (302, 303, 401, 402) and several input terminals (221, 222), wherein at least some of the several switches (302, 303, 401, 402) are each associated with a corresponding one of the several input terminals (221, 222). Example 10. Integrated circuit (200) according to one of the preceding examples, further comprising: - at least one overvoltage protection element (601, 602) comprising at least one ESD MOSFET (611, 831), wherein the at least one ESD MOSFET (611, 831) and the amplifier MOSFET (100) have the same gate length (103A). Example 11. Integrated circuit (200) according to one of Examples 4-9, and according to claim 10, wherein the at least one overvoltage protection element (601, 602) is arranged between the at least one input terminal (221, 222) and the control terminal (103) of the amplifier MOSFET (100), and / or wherein the at least one overvoltage protection element (601, 602) is arranged between the at least one load terminal (101, 102) of the amplifier MOSFET (100) and the output terminal (231). Example 12. Integrated circuit (200) according to one of Examples 7 - 9, as well as according to Example 10 or 11, wherein the at least one surge protection element (601, 602) is implemented by the at least one switch (302, 303, 401, 402). Example 13. Integrated circuit (200) according to one of the preceding examples, wherein the specific resistance of the substrate (106) is not less than 0.5 kOhm cm, preferably not less than 1 kOhm cm, particularly preferably not less than 5 kOhm cm. Example 14. Integrated circuit (200) according to any of the preceding examples, wherein the potential difference is -4 volts or negative, preferably -6 volts or negative, particularly preferably -8 volts or negative. Example 15. Integrated circuit according to one of the preceding examples, wherein the at least one load terminal (101, 102) of the amplifier MOSFET (100) are arranged in bulk technology with respect to the substrate (106). Example 16. Integrated circuit according to one of the preceding examples, wherein the substrate (106) is silicon. Example 17. Integrated circuit according to one of the preceding examples, wherein the amplifier MOSFET (100) implements a low-noise amplifier or a power amplifier. Example 18. Analog output stage of a high-frequency transceiver comprising: - an antenna, and - the integrated circuit (200) according to one of the preceding claims, wherein the antenna is connected to an input terminal (221, 222) of the integrated circuit (200). Example 19. Method comprising: - processing a substrate (106) such that it has a resistivity of not less than 0.3 kOhm cm, and - providing an integrated circuit (200) on the substrate (106) comprising an amplifier MOSFET (100) and a bias terminal (110), wherein the bias terminal (110) is configured to generate a potential difference of the substrate (106) relative to at least one load terminal (101, 102) of the amplifier MOSFET (100) that is -3 volts or more negative. Example 20. Method according to Example 19, wherein the method for manufacturing an integrated circuit (200) according to one of Examples 1 - 17 is used.

Claims

Integrated circuit (200) comprising: - a substrate (106), - an amplifier MOSFET (100), and - a bias terminal (110) configured to generate a potential difference of the substrate (106) relative to at least one load terminal (101, 102) of the amplifier MOSFET (100), wherein the resistivity of the substrate (106) is not less than 0.3 kΩ cm, and the potential difference is -3 volts or more negative, and - at least one input terminal (221, 222) connected to a control terminal (103) of the amplifier MOSFET (100) and configured to receive at least one input signal, and - an output terminal (231) configured to output a signal, and - at least one switch (302, 303, 401, 402) arranged adjacent to the at least one input terminal (221, 222). is and has a series connection of switch MOSFETs (431) to ground (217),wherein the switch MOSFETs (431) and the amplifier MOSFET (100) have the same gate length (103A), wherein the at least one switch (302, 303, 401, 402) is arranged in a bypass branch (301) which connects the at least one input terminal (221, 222) to the output terminal (231) bypassing the amplifier MOSFET (100), wherein the integrated circuit (200) comprises several switches (302, 303, 401, 402) and several input terminals (221, 222), wherein at least some of the several switches (302, 303, 401, 402) are each associated with a corresponding one of the several input terminals (221, 222), and at least one overvoltage protection element (601, 602) comprising at least one ESD MOSFET (611, 831) wherein the at least one ESD MOSFET (611, 831) and the amplifier MOSFET (100) have the same gate length (103A), wherein the at least one overvoltage protection element (601, 602) is located between the at least one input terminal (221,222) and the control terminal (103) of the amplifier MOSFET (100), and / or wherein the at least one overvoltage protection element (601, 602) is arranged between the at least one load terminal (101, 102) of the amplifier MOSFET (100) and the output terminal (231), wherein the at least one overvoltage protection element (601, 602) is implemented by the at least one switch (302, 303, 401, 402). Integrated circuit (200) according to claim 1, wherein the gate width of the amplifier MOSFET (100) is greater than 100 µm. Integrated circuit (200) according to claim 1 or 2, wherein the specific resistance and the potential difference are bulk properties of the substrate (106) in the region of the integrated circuit (200). Integrated circuit (200) according to one of the preceding claims, further comprising: - an inductor (212), wherein the amplifier MOSFET (100) and the inductor (212) are configured to implement a gain factor of the output signal relative to the at least one input signal of not less than 10 dB. Integrated circuit (200) according to one of the preceding claims, further comprising: - at least one cascode MOSFET (213, 213-1, 213-2) arranged between the at least one load terminal (101, 102) of the amplifier MOSFET (100) and the output terminal (231), wherein the at least one cascode MOSFET (213, 213-1, 213-2) and the amplifier MOSFET (100) have the same gate length (103A). Integrated circuit (200) according to one of the preceding claims, wherein the specific resistance of the substrate (106) is not less than 0.5 kOhm cm. Integrated circuit (200) according to one of the preceding claims, wherein the potential difference is -4 volts or more negative. Integrated circuit according to one of the preceding claims, wherein the at least one load terminal (101, 102) of the amplifier MOSFET (100) are arranged in bulk technology with respect to the substrate (106). Integrated circuit according to one of the preceding claims, wherein the substrate (106) is silicon. Integrated circuit according to one of the preceding claims, wherein the amplifier MOSFET (100) implements a low-noise amplifier or a power amplifier. Analog output stage of a high-frequency transceiver comprising: - an antenna, and - the integrated circuit (200) according to one of the preceding claims, wherein the antenna is connected to an input terminal (221, 222) of the integrated circuit (200). A method comprising: - processing a substrate (106) such that it has a resistivity of not less than 0.3 kΩ cm, and - providing an integrated circuit (200) on the substrate (106) comprising an amplifier MOSFET (100) and a bias terminal (110), wherein the bias terminal (110) is configured to generate a potential difference of the substrate (106) relative to at least one load terminal (101, 102) of the amplifier MOSFET (100) that is -3 volts or more negative, wherein the integrated circuit (200) further comprises: - at least one input terminal (221, 222) connected to a control terminal (103) of the amplifier MOSFET (100) and configured to receive at least one input signal, and - an output terminal (231) configured to output a signal, and - at least one switch (302, 303, 401, 402), adjacent to at least one input connection (221,222) and which has a series connection of switch MOSFETs (431) to ground (217), wherein the switch MOSFETs (431) and the amplifier MOSFET (100) have the same gate length (103A), wherein the at least one switch (302, 303, 401, 402) is arranged in a bypass branch (301) which connects the at least one input terminal (221, 222) to the output terminal (231) bypassing the amplifier MOSFET (100), wherein the integrated circuit (200) comprises several switches (302, 303, 401, 402) and several input terminals (221, 222), wherein at least some of the several switches (302, 303, 401, 402) are each connected to a corresponding one of the several input terminals (221, 222) are associated, and- at least one overvoltage protection element (601, 602) comprising at least one ESD MOSFET (611, 831), wherein the at least one ESD MOSFET (611, 831) and the amplifier MOSFET (100) have the same gate length (103A),wherein the at least one overvoltage protection element (601, 602) is arranged between the at least one input terminal (221, 222) and the control terminal (103) of the amplifier MOSFET (100), and / or wherein the at least one overvoltage protection element (601, 602) is arranged between the at least one load terminal (101, 102) of the amplifier MOSFET (100) and the output terminal (231), wherein the at least one overvoltage protection element (601, 602) is implemented by the at least one switch (302, 303, 401, 402). Method according to claim 12, wherein the method for manufacturing an integrated circuit (200) according to one of claims 2 – 10 is used.

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