Interconnect setup and method

Abstract

Procedure, comprehensive: Deposition of a first dielectric layer (16) over a substrate (10); Forming a second dielectric layer (18, 26) on the first dielectric layer (16), wherein the second dielectric layer (18, 26) has a hardness greater than that of the first dielectric layer (16) and a k-value higher than that of the first dielectric layer (16); Deposition of a third dielectric layer (20) over the second dielectric layer (18, 26), wherein the third dielectric layer (20) has a hardness that is lower than that of the second dielectric layer (18, 26) and has a k-value that is lower than that of the second dielectric layer (18, 26); Etching the third dielectric layer (20), the second dielectric layer (18, 26), and the first dielectric layer (16) to form a first opening (22) exposing a first region (12) above the substrate (10), wherein the first opening (22) has a via opening with a first width and a trench opening with a second width, the trench opening overlapping the via opening, the second width being greater than the first width, and a bottom surface of the trench opening being separated by a first section of the first dielectric layer (16) or a first section of the third dielectric layer (20) from a surface of the second dielectric layer (18, 26); and Filling the first opening (22) with a conductive material to form a first conductive intermediate connection (24) which is in contact with the first region (12) of the substrate (10), wherein the first conductive intermediate connection (24) has a via section (24b) in the via opening and a trench section (24a) in the trench opening, the formation of the second dielectric layer (18, 26) on the first dielectric layer (16) comprises the following: Performing a plasma treatment process on the first dielectric layer (16) to form the second dielectric layer (18, 26) on the first dielectric layer (16), wherein the first dielectric layer (16) after the plasma treatment process has a thickness that is less than the thickness of the first dielectric layer (16) before the plasma treatment process, wherein the plasma treatment process converts an upper section of the first dielectric layer (16) into the second dielectric layer (18, 26).

Description

GENERAL STATE OF THE ART

[0001] In the current miniaturization process of semiconductor devices, low-k dielectric materials are desirable as intermetal and / or interlayer dielectrics between conductive connections to reduce the resistive-capacitive (RC) delay in signal propagation due to capacitive effects. The lower the dielectric constant of the dielectric layer, the lower the parasitic capacitance of the adjacent conductors and the lower the RC delay of the integrated circuit.

[0002] However, the materials currently considered or used as low-k dielectric materials are not ideal. In particular, when choosing a material based on its k-value, and especially its low-k-value, other properties such as the material's hardness or strength may not be ideal for use in a semiconductor manufacturing process. Therefore, improvements to processes that utilize low-k dielectric materials are desirable.

[0003] For the state of the art, reference is made to the publications US 6 362 091 B1, US 2010 / 0 028 695 A1, US 7 638 859 B2, US 2005 / 0 110 153 A1 and US 2006 / 0 199 373 A1.

[0004] The invention provides for a method according to claim 1, a method according to claim 9, and a structure according to claim 15. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of this disclosure are best understood from the following detailed description, when read in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as appropriate for the clarity of the discussion. Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. Figure 9 shows sectional views of intermediate stages in the production of an intermediate connection assembly according to some embodiments. Fig. Figure 7 is a sectional view of an intermediate connection assembly according to some embodiments. Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 shows sectional views of intermediate stages in the production of an intermediate connection assembly according to some embodiments. Fig. Figure 12 is a sectional view of an intermediate connection assembly according to some embodiments. Fig. Figure 13 is an example of a Fin field-effect transistor (FinFET) in a three-dimensional view. Fig. Figures 14 to 18, 19A to 19C, 20A to 20C, 21A to 21C, 22A to 22C, 23A to 23C, 24A to 24C, 25A to 25C, 26A to 26C and 27A to 27C are sectional views of intermediate stages in the production of FinFETS with intermediate structures according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples of the implementation of various features of the invention. Certain examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not itself prescribe any relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially related terms such as "under," "below," "below," "above," "above," and the like may be used here to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially related terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially related terms used here may be interpreted accordingly.

[0008] Intermediate compound setups and methods for their formation according to various embodiments are provided. Intermediate stages in the formation of intermediate compound setups are illustrated. Some embodiments discussed here are presented in the context of intermediate compounds formed using a dual-damascene process. In other embodiments, a single-damascene process may be used. Several modifications to the embodiments are discussed. A person skilled in the art will readily recognize other feasible modifications envisaged within the scope of other embodiments. Although method implementations are discussed in a particular order, various other method implementations may be carried out in any logical order and may include fewer or more steps than described here.

[0009] With reference to Fig. 1 illustrates Fig. 1 A substrate 10 with active devices (not shown), metallization layers (not shown) in the substrate 10, a conductive element 12 coupled to the metallization layers, an optional etch stop layer 14, and a first dielectric layer 16. The substrate 10 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 10 can be a wafer such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate.Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of substrate 10 can comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0010] The active devices can comprise a wide variety of active devices such as transistors and the like, and passive devices such as capacitors, resistors, inductors and the like, which can be used to create the desired structural and functional parts of the concept. The active and passive devices can be formed in or on the substrate 10 using any suitable method.

[0011] The metallization layers are formed over active devices and designed to connect the various active devices to form a functional circuit structure for the design. In one embodiment, the metallization layers are formed from alternating layers of dielectric and conductive materials and can be formed by any suitable process (such as deposition, damascene, dual-damascene, etc.). In one embodiment, one to four layers of metallization can be separated from each other by at least one interlayer dielectric (ILD), but the exact number of metallization layers depends on the design.

[0012] The conductive element 12 can be formed in or above the metallization layers and is an area with which an intermediate compound 24 (in Fig. 1 not illustrated, but below in Fig. (6 illustrated and described) will establish a physical and electrical connection. In one embodiment, the conductive element 12 can be a material such as copper formed using, for example, a Damascene or dual-Damascene process, wherein an opening is formed in the metallization layers, the opening is filled or overfilled with a conductive material such as copper, and a planarization process is performed to embed the conductive material in the metallization layers. However, any suitable material and any suitable process can be used to form the conductive element 12.

[0013] The etch stop layer 14 can be formed over the substrate 10, any metallization layers, and the conductive elements 12. In some embodiments, the etch stop layer 14 can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, the like, or a combination thereof, and can be deposited by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof.

[0014] The first dielectric layer 16 can be formed to help insulate the intermediate connection 24 from other adjacent electrical routing lines. In one embodiment, the first dielectric layer 16 can, for example, be a low-k dielectric film to help insulate the intermediate connection 24 from other structures. By insulating the intermediate connection 24, the resistance-capacitance (RC) delay of the intermediate connection 24 can be reduced, thereby increasing the overall efficiency and speed of electricity through the intermediate connection.

[0015] In one embodiment, the first dielectric layer 16 can be a porous material such as SiOCN, SiCN, SiOCN, SiOCH, or the like, and can be formed by initially forming a precursor layer over the etch stop layer 14, if one is present. The precursor layer can comprise both a matrix material and a pore-forming agent incorporated into the matrix material, or alternatively, the matrix material without the pore-forming agent. In one embodiment, the precursor layer can be formed, for example, by co-depositing the matrix and the pore-forming agent using a process such as plasma-enhanced chemical vapor deposition (PECVD), wherein the matrix material is deposited at the same time as the pore-forming agent, thereby forming the precursor layer with the mixed matrix material and pore-forming agent.However, as any average professional will recognize, co-deposition using a simultaneous PECVD process is not the only process that can be used to form the precursor layer. Any process can be used, such as premixing the matrix material and the pore-forming agent as a liquid and then spin-applying the mixture onto the etch-stop layer 14.

[0016] The precursor layer can be made to a thickness sufficient to provide the insulation and routing properties desired by the first dielectric layer 16. In one embodiment, the precursor layer can be made to a first thickness T1 in a range of about 10 Å to about 1000 Å, such as about 300 Å. However, these thicknesses are only meant to be illustrative and are not intended to limit the scope of the embodiments, since the exact thickness of the precursor layer can be any suitable desired thickness (1 Å = 0.1 nm).

[0017] The matrix material, or the basic dielectric material, can be formed using a process such as PECVD, although alternatively any suitable process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or even spin coating can be used. The PECVD process can use precursors such as methyl diethoxysilane (DEMS), although alternatively other precursors such as other silanes, alkylsilanes (e.g., trimethylsilane and tetramethylsilane), alkoxysilanes (e.g., methyltriethoxysilane (MTEOS), methyltrimethoxysilane (MTMOS), methyldimethoxysilane (MDMOS), trimethylmethoxysilane (TMMOS), and dimethyldimethoxysilane (DMDMOS)), linear siloxanes, and cyclic siloxanes (e.g., octamethylcyclotetrasiloxane (OMCTS) and tetramethylcyclotetrasiloxane (TMCTS)), combinations thereof, and the like can be used.However, as the average expert will recognize, the materials and processes mentioned here are merely illustrative and are not intended to limit the embodiments, since any other suitable matrix precursors can be used alternatively.

[0018] The pore-forming agent can be a molecule that can be removed from the matrix material after the matrix material has cured to form pores in the matrix, thereby reducing the overall value of the dielectric constant of the first dielectric layer. The pore-forming agent can be a material large enough to form the pores while remaining small enough that the size of the individual pores does not displace the matrix material too much. Therefore, the pore-forming agent can be an organic molecule such as alpha-terpinene (ATRP) (1-isopropyl-4-methyl-1,3-cyclohexadiene), cyclooctane (boat-shaped), or 1,2-bis(triethoxysilyl)ethanesilicium.

[0019] After the formation of the precursor layer with the pore-forming agent dispersed in the matrix material, the pore-forming agent is removed from the matrix material to form the pores in the matrix material. In one embodiment, the removal of the pore-forming agent is carried out by an annealing process that can decompose and vaporize the pore-forming agent material, thereby allowing the pore-forming agent to diffuse and leave the matrix material, leaving behind a structurally intact porous dielectric material as the first dielectric layer 16. For example, an annealing process in a range of about 200 °C to about 500 °C, such as about 400 °C, can be used for a range of about 10 seconds to about 600 seconds, such as about 200 seconds.

[0020] However, as an average person will recognize, the thermal process described above is not the only method that can be used to remove the pore-forming agent from the matrix material to form the first dielectric layer 16. Alternatively, other suitable processes can be used, such as irradiating the pore-forming agent with UV radiation to decompose it, or using microwaves to decompose it. These and any other suitable processes for removing all or part of the pore-forming agent are intended to be included in the scope of the embodiments.

[0021] However, the first dielectric layer 16, as described above, does not possess the desired resistance to withstand unbalanced stresses that can occur during a structuring process. For example, trenches located next to a via hole may deform to a different extent than a trench located further away from the via hole, such as the third furthest trench from the via hole.In a specific example, each of the trench openings can be structured by a process that attempts to form them so that they have a uniform width. However, this desired width might be reduced by 4 nm, 5 nm, or 6 nm for a trench opening located adjacent to the via, due to unbalanced forces in each opening, compared to the thickness achieved by a trench opening furthest from the via. These reductions and differences between the various trench openings could cause gap-filling problems in subsequent metallization processes (discussed below).

[0022] Fig. Figure 2 illustrates the formation of an insert layer 18 over the first dielectric layer 16 to provide a framework for additional structural support, thereby increasing the robustness of the first dielectric layer 16 and other subsequently deposited layers. Furthermore, the inclusion of the insert layer 18 affects the capacitance less than simply modifying the bulk film from a low-k dielectric film. In one embodiment, the insert layer 18 is a material with greater hardness and a higher k-value than the first dielectric layer 16. For example, in an embodiment where the first dielectric layer 16 has a hardness in the range of about 1.5 GPa to about 3.0 GPa, such as about 2 GPa, the insert layer 18 can have a hardness greater than about 8 GPa, such as in the range of about 10 GPa to about 13 GPa, such as about 12 GPa.In other words, the insert layer 18 can have a hardness that is at least 5 GPa higher than that of the first dielectric layer 16. Similarly, in an embodiment where the first dielectric layer has a k-value in the range of about 2.3 to about 2.9, the insert layer 18 can have a k-value greater than about 3.0.

[0023] In some embodiments, the insert layer 18 can be a material such as Si x O y (e.g. SiO2), Si x C y (e.g. SiC), Si x O y C z (e.g. SiOC), and Si x C y N z (e.g., SiCN), combinations thereof, or the like. However, any suitable material can be used to provide the additional structural support to the first dielectric layer 16.

[0024] In one embodiment, the insert layer 18 can be formed using a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced electrochemical vapor deposition (PECVD), spin coating, or the like. In other embodiments, such as one in which SiO₂ is formed, an initial layer of a first material, such as silicon, can be deposited or formed, and the layer can then be treated with, for example, oxygen to form the final material for the insert layer 18. Any suitable process can be used to form the insert layer 18. The insert layer 18 can be produced to a second thickness T₂ in a range of about 10 Å to about 100 Å, such as about 50 Å (1 Å = 0.1 nm).

[0025] Fig. Figure 3 illustrates the formation of a second dielectric layer 20 above the insert layer 18. In one embodiment, the second dielectric layer 20 can be formed from a similar material and in a similar manner to the first dielectric layer 16. For example, the second dielectric layer 20 can comprise a porous material such as ATRP (1-isopropyl-4-methyl-1,3-cyclohexadiene) or cyclooctane (boat-shaped) or 1,2-bis(triethoxysilyl)ethane silicon, formed by initially arranging a matrix material and a pore-forming agent and then removing the pore-forming agent. However, in other embodiments, the second dielectric layer 20 can be a different material than the first dielectric layer 16. Any suitable combination of materials can be formed.In one embodiment, the second dielectric layer 20 can be made to a third thickness T3 in a range of about 10 Å to about 1000 Å, such as about 600 Å (1Å = 0.1 nm).

[0026] Fig. Figure 4 illustrates the structuring of the second dielectric layer 20, the insert layer 18, the first dielectric layer 146, and the etch stop layer 14, if present, to form openings 22 for exposing portions of the conductive elements 12. The openings 22 allow some of the intermediate connections 24 to make physical and electrical contact with the conductive elements 12. In some embodiments, the openings 22 are dual damascene openings comprising upper trench sections 22A and lower via opening sections 22B. Although the embodiments illustrate dual damascene openings in layers 16, 18, and 20, the method disclosed in the present application is applicable to an embodiment with single damascene openings in the layers.In dual damascene technologies that incorporate a "via first" structuring process or a "trench first" structuring process, the upper trench section 22A and the lower via opening section 22B can be formed using photolithography with masking technologies and anisotropic etching activities (e.g. plasma etching or reactive ion etching).

[0027] For example, in one embodiment for "via first," a first photoresist (not shown) is formed and patterned over the second dielectric layer 20 to expose a portion of the second dielectric layer 20. The first photoresist can be formed using a spin-depositing technique and can be patterned using acceptable photolithography techniques. Once the first photoresist is patterned, a first anisotropic etching process is performed to form the via openings to the conductive elements 12, and the first photoresist can serve as a mask for the etching process. After the first anisotropic etching process, the first photoresist is removed, for example, by an acceptable ashing process. After the removal of the first photoresist, a second photoresist is formed and patterned over the second dielectric layer 20 to expose a portion of the second dielectric layer 20.The second photoresist can be formed using a spin-coating technique and can be structured using acceptable photolithography techniques. Once the second photoresist is structured, a second anisotropic etching process is performed to form the trench portion of the openings, and the second photoresist can act as a mask for the etching process. After the second anisotropic etching process, the second photoresist is removed, for example, by an acceptable ashing process.

[0028] While previous processes (which did not use insert layer 18) led to unbalanced stresses from nearby via etching processes, causing bending of the top opening of trenches adjacent to the vias and resulting in problems of critical dimensional variations in a range of trench openings at different locations around the device, the presence of insert layer 18 will help prevent the first dielectric layer 16 and the second dielectric layer 20 from bending or collapsing. Therefore, the top of the openings 22 will better retain the desired shape, and the openings 22 may exhibit less variation across the device.While, for example, previous processes without the insert layer 18 could lead to bending that could cause width variations in an area of ​​different openings 22 in a range of about 5 nm to about 6 nm, such as about 5.5 nm (or more than 10% of the desired structure), the inclusion of the insert layer 18 can reduce the extent of bending at the top of the openings 22.

[0029] Fig. Figure 5 illustrates filling the openings 2 with a conductive material 24. In one embodiment, the openings 22 can be filled with a barrier layer 23 and a conductive material 24. The barrier layer 23 can comprise a conductive material such as titanium nitride, although alternatively other materials such as tantalum nitride, titanium, a dielectric, or the like can be used. The barrier layer 23 can be formed using a CVD process such as PECVD. In some embodiments, the barrier layer 23 is designed to have a thickness in the range of about 10 Å to about 1000 Å. However, other processes such as sputtering or metal-organic chemical deposition from the gas phase (MOCVD) can be used. The barrier layer 23 is formed to conform precisely to the shape of the underlying openings 22 (1 Å = 0.1 nm).

[0030] The conductive material 24 can comprise copper, although alternatively other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like may be used. The conductive material can be formed by first creating a seed layer (in Fig. 5 not shown separately) is formed and then copper is electrically plated onto the seed layer, thereby filling and overfilling the openings 22.

[0031] Once the openings 22 are filled, it illustrates Fig. 6. The removal of the excess barrier layer 23 and the excess conductive material 24 outside the openings 22 to form intermediate connections 24. In some embodiments, the removal of the excess barrier layer 23 and the excess conductive material 24 is carried out by a grinding process such as chemical-mechanical polishing (CMP), although any suitable removal process may be used. In some embodiments, the intermediate connections 24 are dual-Damascene intermediate connections comprising a trench section 24A and a via section 24B. In some embodiments, the via sections 24B of the intermediate connections 24 have heights D1 measured from a surface of the substrate 10, the heights D1 being in a range of about 400 Å to about 450 Å.In some embodiments, the trench sections 24A have heights D2 measured from their upper surfaces to their bottom surfaces, with heights D2 ranging from approximately 410 Å to approximately 460 Å. In some embodiments, the bottom surfaces of the trench sections 24A of the intermediate connections 24 are separated from an upper surface of the insert layer 18 by a distance D3, with the distance D3 ranging from approximately 20 Å to approximately 130 Å (1 Å = 0.1 nm).

[0032] By forming the insert layer 18 to provide additional support to both the first and second dielectric layers, the distortion and bending that would normally occur during the structuring process can be mitigated or prevented. This prevents the adverse effects of these undesirable distortions, such as variable reduced widths along the top surface of the openings 22. Such prevention results in fewer defects during the subsequent filling process.

[0033] Fig. Figure 7 illustrates a sectional view of an intermediate connection assembly according to another embodiment. The embodiment in Fig. 7 is the embodiment described in Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. Figure 6 illustrates similar embodiments, except that in this embodiment, unlike the via section in the previous embodiment, the insert layer 18 is formed in the trench section of the intermediate connections 24. The materials and formation processes of the first dielectric layer 16, the insert layer 18, and the second dielectric layer 20 can be similar to those in the previously described embodiment, except that the relative thicknesses of the layers can be changed, and therefore the description of these layers is not repeated here. Details regarding this embodiment, which are similar to those for the previously described embodiment, are not repeated here.

[0034] In this embodiment, the first dielectric layer 16 can have a fourth thickness T4 in a range of about 10 Å to about 1000 Å, such as about 600 Å, the insert layer 18 can have a second thickness T2, and the second dielectric layer 20 can have a fifth thickness T5 in a range of about 10 Å to about 1000 Å, such as about 300 Å. In this embodiment, the bottom surfaces of the trench sections 24A of the intermediate connections 24 are separated from a bottom surface of the insert layer 18 by a distance D4, wherein the distance D4 is in a range of about 30 Å to about 150 Å (1 Å = 0.1 nm).

[0035] Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 shows sectional views of intermediate stages in the production of an intermediate connection assembly according to another embodiment. This embodiment is the one described in Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. The embodiment illustrated in Figure 6 is similar, except that in this embodiment, unlike the deposition process in the previous embodiment, the insert layer is formed by a plasma treatment process. Details regarding this embodiment, which are identical to those for the previously described embodiment, will not be repeated here.

[0036] Fig. 8 is located at the same processing point as the one described above. Fig. 1, and the description of the processes and steps carried out up to this point will not be repeated here. Fig. 8 contains the substrate 10, the conductive elements 12, the optional etch stop layer 14 and the first dielectric layer 16.

[0037] Fig. Figure 9 illustrates the formation of the insert layer 26 over the first dielectric layer 16 to provide a framework for additional structural support, thereby increasing the robustness of the first dielectric layer 16 and other subsequently deposited layers. Furthermore, the inclusion of the insert layer 26 affects the capacitance less than simply modifying the bulk film from a low-k dielectric film. In one embodiment, the insert layer 26 is a material with greater hardness and a higher k-value than the first dielectric layer 16. For example, in some embodiments, the first dielectric layer 16 has a k-value of about 2.6 or less, and the insert layer 26 has a k-value greater than 2.8, such as about 3.0.

[0038] In some embodiments, the insert layer 26 is formed by performing a plasma treatment process on the first dielectric layer 16. The plasma treatment process may involve plasma reaction gases such as He, Ar, NH3, CO2, N2, O2, the like, or a combination thereof. In some embodiments, the plasma treatment process may be performed at a temperature in the range of about 200 °C to about 400 °C, at a pressure in the range of about 66.7 Pa to about 1333.2 Pa, and at a treatment power (sometimes referred to as discharge power and / or bombardment intensity) in the range of about 100 watts (W) to about 500 watts. In some embodiments, the plasma system is a direct plasma system, and in other embodiments, the plasma system is a remote plasma system.The plasma treatment process can convert at least an upper section of the first dielectric layer 16 into the insert layer 26, thus reducing the thickness of the first dielectric layer 16. In some embodiments, the insert layer 26 is formed at least partially from the plasma-treated first dielectric layer 16, while in other embodiments, the insert layer 26 consists mainly of the plasma-treated first dielectric layer 26.

[0039] Fig. Figure 10 illustrates the formation of the second dielectric layer 20 over the insert layer 26. In one embodiment, the second dielectric layer 20 can be formed from a similar material and in a similar manner to the first dielectric layer 16. However, in other embodiments, the second dielectric layer 20 can be a different material than the first dielectric layer 16. Any suitable combination of materials can be formed. In one embodiment, the second dielectric layer 20 can be made to a thickness T8 in a range of about 10 Å to about 1000 Å, such as about 600 Å. The insert layer 26 can be made to a thickness T7 in a range of about 10 Å to about 100 Å, such as about 50 Å. The first dielectric layer 16 can be made to a thickness T6 in a range of about 10 Å to about 1000 Å, such as about 300 Ä (1 Å = 0.1 nm).

[0040] After the second dielectric layer 20 has been formed, a processing step is performed, which is described above. Fig. 4, Fig. 5 and Fig. The same as described in section 6 was done to facilitate the construction of Fig. 11, which is located at the same processing point as Fig. 6 is located, to form. The processes and steps of Fig. 4, Fig. 5 and Fig. The six points described above are not repeated here.

[0041] Fig. Figure 12 is a sectional view of an intermediate connection assembly according to another embodiment. The embodiment in Fig. 12 is the one in Fig. 8, Fig. 9, Fig. 10 to Fig. The embodiment illustrated in Figure 11 is similar, except that in this embodiment, unlike the via section in the previous embodiment, the insert layer 26 is formed in the trench section of the intermediate connections 24. The materials and formation processes of the first dielectric layer 16, the insert layer 26, and the second dielectric layer 20 can be similar to those in the previously described embodiment, except that the relative thicknesses of the layers can be changed, and therefore the description of these layers is not repeated here. Details regarding this embodiment, which are similar to those for the previously described embodiment, are not repeated here.

[0042] In this embodiment, the first dielectric layer 16 can have a thickness T9 in a range of approximately 10 Å to approximately 1000 Å, such as approximately 600 Å, the insert layer 26 can have a thickness T7, and the second dielectric layer 20 can have a thickness T10 in a range of approximately 10 Å to approximately 1000 Å, such as approximately 300 Å. In this embodiment, the bottom surfaces of the trench sections 24A of the intermediate connections 24 are separated from a bottom surface of the insert layer 26 by a distance D4 (1 Å = 0.1 nm).

[0043] By providing the insert layer as a frame for additional structural support, the normally weaker porous material of the first dielectric layer 16 and the second dielectric layer 20 can be supported. This additional support helps to reduce variations between different openings caused by their proximity (or lack thereof) to adjacent openings. This prevents complications that could arise during subsequent gap-filling processes.

[0044] Fig. Figures 14 to 18, 19A to 19C, 20A to 20C, 21A to 21C, 22A to 22C, 23A to 23C, 24A to 24C, 25A to 25C, 26A to 26C and 27A to 27C are sectional views of intermediate stages in the production of FinFETS with intermediate structures according to some embodiments.

[0045] Fig. Figure 13 illustrates an example of a fin field-effect transistor (FinFET) 30 in a three-dimensional view. The FinFET 30 comprises a fin 36 on a substrate 32. The substrate 32 includes insulating regions 34, and the fin 36 projects upwards and from the region between adjacent insulating regions 34. A gate dielectric 38 is located along side walls and over a top surface of the fin 36, and a gate electrode 40 is located above the gate dielectric 38. Source / drain regions 42 and 44 are located on opposite sides of the fin 36 with respect to the gate dielectric 38 and the gate electrode 40. Fig. Figure 13 further illustrates reference cross-sections used in later figures. Cross-section AA extends across a channel, the gate dielectric 38, and the gate electrode 40 of the FinFET 30. Cross-section B / CB / C extends perpendicular to cross-section AA and along a longitudinal axis of the fin 36 and, for example, in a direction of current flow between the source / drain regions 42 and 44. For clarity, subsequent figures refer to these reference cross-sections.

[0046] Some embodiments discussed here are in the context of FinFETs formed using a "gate-last" process. Other embodiments may employ a "gate-first" process. Additionally, some embodiments consider aspects relevant to flat devices such as flat FETs.

[0047] Fig. Figures 14 to 27C are cross-sections of intermediate stages in the fabrication of FinFETs according to an exemplary embodiment. Fig. 14, Fig. 15, Fig. 16, Fig. 17 to Fig. Figure 18 illustrates, except for multiple FinFETs, the reference cross-section AA, which is shown in Fig. Figure 13 illustrates this. Fig. Figures 19A to 27C are figures ending with an “A” illustrated along a similar cross-section AA; figures ending with a “B” illustrated along a similar cross-section B / CB / C and in a first area on a substrate; and figures ending with a “C” illustrated along a similar cross-section B / CB / C and in a second area on a substrate.

[0048] Fig. Figure 14 illustrates a substrate 50. The substrate 50 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0049] The substrate 50 has a first region 50B and a second region 50C. The first region 50B (corresponding to the following figures ending with "B") can be used to form n-type devices such as NMOS transistors like n-type FinFETs. The second region 50C (corresponding to the following figures ending with "C") can be used to form p-type devices such as PMOS transistors like p-type FinFETs.

[0050] Fig. 15 and Fig. Figure 16 illustrates the formation of fins 52 and isolation areas 54 between adjacent fins 52. In Fig. 15 fins 52 are formed in the substrate 50. In some embodiments, the fins 52 can be formed by etching grooves into the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic.

[0051] In Fig. In this embodiment, an insulating material 54 is formed between adjacent fins 52 to form the insulating areas 54. The insulating material 54 can be an oxide such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma vapor deposition (HDP-CVD), flowable fluid vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into another material such as an oxide), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. Once the insulating material is formed, an annealing process can be performed. In the illustrated embodiment, the insulating material 54 is silicon dioxide formed by an FCVD process. The insulating material 54 can be referred to as the insulating areas 54.Furthermore, in . Fig. 5 and in step 504 a planarization process such as chemical-mechanical polishing (CMP) removes any excess insulation material 54 and forms upper surfaces of the insulation areas 54 and upper surfaces of the fins 52 that are coplanar.

[0052] Fig. Figure 17 illustrates the deepening of the insulation regions 54 to form trench insulation (STI) regions 54. The insulation regions 54 are deepened such that fins 56 protrude from the first region 50B and the second region 50C of regions between adjacent insulation regions 54. Furthermore, the upper surfaces of the insulation regions 54 can be flat, convex, concave (such as bowl-shaped), or a combination thereof, as illustrated. The upper surfaces of the insulation regions 54 can be made flat, convex, and / or concave by appropriate etching. The insulation regions 54 can be deepened using an acceptable etching process, such as one that is selective with respect to the material of the insulation regions 54.For example, chemical oxide removal can be performed using a CERTAS® etching or SICONI tool from Applied Materials, or dilute hydrofluoric acid (dHF).

[0053] An average expert will easily understand that, with reference to Fig. 15, Fig. 16 to Fig. The process described in Section 17 is only one example of how fins 56 can be formed. In other embodiments, a dielectric layer can be formed over a top surface of the substrate 50; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still other embodiments, heteroepitaxial structures can be used for the fins. For example, the semiconductor strips 52 in Fig. 16 can be deepened and a material different from the semiconductor strips 52 can be epitaxially grown in their place. In yet another embodiment, a dielectric layer can be formed over a top surface of the substrate 50; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate 50; and the dielectric layer can be deepened so that the heteroepitaxial structures protrude from the dielectric layer to form fins 56.In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials can be doped in place during growth, thus avoiding prior and subsequent implantations, although doping in place and by implantation can be used together. Furthermore, it can be advantageous to epitaxially grow a material different from the material in a PMOS region within an NMOS region. In various embodiments, the fins can comprise silicon germanium (SixGe1-x, where x can be between approximately 0 and 100), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like.For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AIP, GaP and the like.

[0054] In Fig. 17 Suitable basins can be formed in the fins 56, the fins 52 and / or the substrate 50. For example, a P basin can be formed in the first area 50B, and an N basin can be formed in the second area 50C.

[0055] The various implantation steps for the different regions 50B and 50C can be achieved using a photoresist or other masks (not shown). For example, a photoresist is formed over the fins 56 and the isolation regions 54 in the first region 50B. The photoresist is then patterned to expose the second region 50C of the substrate, such as a PMOS region. The photoresist can be formed using a spin-coating technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the second region 50C, and the photoresist can act as a mask to essentially prevent n-type impurities, such as an NMOS region, from being implanted into the first region 50B.The n-type impurities can be phosphorus, arsenic, or the like, and are present up to a concentration of 10 or less. 18 cm -3 , such as an area of ​​about 10 17 cm -3 up to about 10 18 cm -3 , implanted in the first area. After implantation, the photoresist is removed, for example by an acceptable ashing process.

[0056] Following implantation in the second region 50C, a photoresist is formed over the fins 56 and the isolation regions 54 in the second region 50C. The photoresist is structured to expose the first region 50B of the substrate, such as the NMOS region. The photoresist can be formed by spin-casting and structured using acceptable photolithography techniques. Once the photoresist is structured, p-type impurity implantation can be performed in the first region 50B, and the photoresist can serve as a mask to essentially prevent p-type impurities from being implanted into the second region, such as the PMOS region. The p-type impurities can be boron, FB2, or the like, and are implanted at concentrations of 10 or less. 18 cm -3 , such as in an area of ​​about 10 17 cm -3 up to about 10 18 cm-3 , implanted in the first area. After implantation, the photoresist can be removed, for example by an acceptable ashing process.

[0057] Following implantation in the first region 50B and the second region 50C, annealing can be performed to activate the implanted p-type and n-type impurities. The implantations can form a p-type well in the first region 50B, e.g., the NMOS region, and an n-type well in the second region 50C, e.g., the PMOS region. In some embodiments, the grown materials of the epitaxial fins can be doped in place during growth, thus avoiding implantation, although doping in place and by implantation can be used together.

[0058] In Fig. 18 A dummy dielectric layer 58 is formed on the fins 56. The dummy dielectric layer 58 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 60 is formed over the dummy dielectric layer 58, and a mask layer 62 is formed over the dummy gate layer 60. The dummy gate layer 60 can be deposited over the dummy dielectric layer 58 and then planarized, for example by CMP. The mask layer 62 can be deposited over the dummy gate layer 60. The dummy gate layer 60 can be formed, for example, from polysilicon, although other materials exhibiting high etch selectivity for etching the insulating regions 50 can also be used. The mask layer 62 can, for example, comprise silicon nitride or the like.In this example, a single dummy gate layer 60 and a single mask layer 62 are formed over the first region 50B and the second region 50C. In other embodiments, separate dummy gate layers and separate mask layers can be formed in the first region 50B and the second region 50C.

[0059] In Fig. 19A, Fig. 19B and Fig. 19C, the mask layer 62 can be structured using acceptable photolithography and etching techniques to create masks 72 in the first area 50B (as in Fig. 19B illustrated) and in the second area 50C masks 78 (as in Fig. (19C illustrated). The structure of masks 72 and 78 can then be transferred to the dummy gate layer 60 and the dummy dielectric layer 58 by an acceptable etching technique to form dummy gates 70 in the first region 50B and dummy gates 76 in the second region 50C. The dummy gates 70 and 76 cover respective channel regions of the fins 56. The dummy gates 70 and 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the epitaxial fins.

[0060] In Fig. 20a, Fig. 20B and Fig. 20C can be formed on exposed surfaces of the respective dummy gates 70 and 76 and / or fins 56 gate sealing spacers 80. The gate sealing spacers 80 can be formed by thermal oxidation followed by anisotropic etching.

[0061] After the formation of the gate sealing spacers 80, implantations can be performed for lightly doped source / drain (LDD) regions. Similar to the above in Fig. In the 17 discussed implantations, a mask such as a photoresist can be formed over the first region 50B, e.g., the NMOS region, while the second region 50C, e.g., the PMOS region, is exposed, and p-type impurities can be implanted into the exposed fins 56 in the second region 50C. Then the mask can be removed. Subsequently, a mask such as a photoresist can be formed over the second region 50C while the first region 50B is exposed, and n-type impurities can be implanted into the exposed fins 56 in the first region 50B. Then the mask can be removed. The n-type impurities can be any of the previously discussed n-type impurities, and the p-type impurities can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have an impurity concentration of approximately 10 15 cm -3 up to about 10 16cm -3 exhibit. An annealing process can be used to activate the implanted impurities.

[0062] Furthermore, in Fig. 20A, Fig. 20B and Fig. In the first region 50B, epitaxial source / drain regions 82 and 84 are formed in the fins 56 such that each dummy gate 70 is arranged between adjacent pairs of epitaxial source / drain regions 82. In some embodiments, these epitaxial source / drain regions 82 may extend into the fins 52. In the second region 50C, epitaxial source / drain regions 84 are formed in the fins 56 such that each dummy gate 76 is arranged between adjacent pairs of epitaxial source / drain regions 84. In some embodiments, these epitaxial source / drain regions 84 may extend into the fins 52.

[0063] Epitaxial source / drain regions 82 in the first region 50B, e.g., the NMOS region, can be formed by masking the second region 50C, e.g., the PMOS region, and depositing a dummy spacer layer in the first region 50B with a surface-accurate finish. This is followed by anisotropic etching to form dummy gate spacers (not shown) along the sidewalls of the dummy gates 70 and / or the dummy sealing spacers 80 in the first region 50B. The source / drain regions of the epitaxial fins in the first region 50B are then etched to form depressions. The epitaxial source / drain regions 82 in the first region 50B are epitaxially grown in these depressions. The epitaxial source / drain regions 82 can comprise any acceptable material suitable for n-type FinFETs. If the fin 56 is silicon, the epitaxial source / drain regions 82 can, for example, comprise silicon, SiC, SiCP, SiP, or the like.The epitaxial source / drain areas 82 may have surfaces that are raised above the respective surfaces of the fins 56 and may have facets. Subsequently, the dummy gate spacers in the first area 50B are removed, for example by etching, as is the mask on the second area 50C.

[0064] Epitaxial source / drain regions 84 in the second region 50C, e.g., the PMOS region, can be formed by masking the first region 50B, e.g., the NMOS region, and depositing a dummy spacer layer in the second region 50C with surface fidelity, followed by anisotropic etching to form dummy gate spacers (not shown) along the sidewalls of the dummy gates 76 and / or the dummy sealing spacers 80 in the second region 50C. The source / drain regions of the epitaxial fins in the second region 50C are then etched to form depressions. The epitaxial source / drain regions 84 in the second region 50C are epitaxially grown in the depressions. The epitaxial source / drain regions 84 can comprise any acceptable material suitable for p-type FinFETs. If the fin 56 is silicon, the epitaxial source / drain regions 84 can, for example, comprise SiGe, SiGeB, Ge, GeSn, or the like.The epitaxial source / drain areas 84 may have surfaces that are raised above the respective surfaces of the fins 56 and may have facets. Subsequently, the dummy gate spacers in the second area 50C are removed, for example by etching, as is the mask on the first area 50B.

[0065] In Fig. 21A, Fig. 21B and Fig. 21C are formed at the gate sealing spacers 80 along the sidewalls of the dummy gates 70 and 76. The gate spacers 86 can be formed by surface-accurate deposition of a material and subsequent anisotropic etching of the material. The material of the gate spacers 86 can be silicon nitride, SiCN, a combination thereof, or the like.

[0066] Similar to the process previously discussed for the formation of lightly doped source / drain regions, dopants can be implanted into the epitaxial source / drain regions 82 and 84 and / or the epitaxial fins to form source / drain regions, followed by annealing. The source / drain regions can contain an impurity concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 The n-type impurities for source / drain regions in the first region 50B, e.g., the NMOS region, can be any of the previously discussed n-type impurities, and the p-type impurities for source / drain regions in the second region 50C, e.g., the PMOS region, can be any of the previously discussed p-type impurities. In other embodiments, the epitaxial source / drain regions 82 and 84 can be doped locally during growth.

[0067] In Fig. 22A, Fig. 22B and Fig. 22°C will be above the in Fig. 21A, Fig. 21B and Fig. Figure 21C illustrates the setup in which an ILD 88 is deposited. In one embodiment, the ILD 88 is a flowable film formed by a flowable CVD. In some embodiments, the ILD 88 is formed from a dielectric material such as phosphosilicate glass (PSC), borosilicate glass (BSG), undoped silicate glass (USG), or the like, and can be deposited by any suitable method such as CVD or PECVD.

[0068] In Fig. 23A, Fig. 23B and Fig. 23C allows a planarization process, such as a CMP, to be performed to bring the top surface of ILD 88 into a plane with the top surfaces of dummy gates 70 and 76. The CMP can also remove masks 72 and 78 on dummy gates 70 and 76. Accordingly, the top surfaces of dummy gates 70 and 76 are exposed by ILD 88.

[0069] In Fig. 24A, Fig. 24B and Fig. In step 24C, the dummy gates 70 and 76, the gate sealing spacers 80, and portions of the dummy dielectric layer 58 located directly beneath the dummy gates 70 and 76 are removed in one etching step, forming depressions 90. Each depression 90 exposes a channel region of a corresponding fin 56. Each channel region is positioned between adjacent pairs of epitaxial source / drain regions 82 and 84. During removal, the dummy dielectric layer 58 can be used as an etch stop layer when etching the dummy gates 70 and 76. The dummy dielectric layer 58 and the gate sealing spacers 80 can then be removed after the dummy gates 70 and 76 have been removed.

[0070] In Fig. 25A, Fig. 25B and Fig. In process 25C, gate dielectric layers 92 and 96 and gate electrodes 94 and 98 for replacement gates are formed. The gate dielectric layers 92 and 96 are deposited in a surface-conforming manner in the recesses 90, such as on the upper surfaces and side walls of the fins 96 and on side walls of the gate spacers 86, and on an upper surface of the ILD 88. According to some embodiments, the gate dielectric layers 92 and 96 comprise silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the gate dielectric layers 92 and 96 comprise a high-k dielectric material, and in these embodiments the gate dielectric layers 92 and 96 may have a k-value higher than about 7.0, and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.The formation methods for the gate dielectric layers 92 and 96 can include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD and the like.

[0071] Next, the gate electrodes 94 and 98 are deposited over the gate dielectric layers 92 and 96, respectively, and fill the remaining portions of the wells 90. The gate electrodes 94 and 98 can be made of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. After the gate electrodes 94 and 98 have been deposited, a planarization process such as CMP can be performed in step 228 to remove the excess portions of the gate dielectric layers 92 and 96 and the material of the gate electrodes 94 and 98, the excess portions of which are located above the top surface of the ILD. The resulting remaining portions of the material of the gate electrodes 94 and 98 and the gate dielectric layers 92 and 96 thus form substitute gates of the resulting FinFETs.

[0072] The formation of the gate dielectric layers 92 and 96 can occur simultaneously, so that the gate dielectric layers 92 and 96 are made of the same materials, and the formation of the gate electrodes 94 and 98 can also occur simultaneously, so that the gate electrodes 94 and 98 are made of the same materials. However, in other embodiments, the gate dielectric layers 92 and 96 can be formed by different processes, so that the gate dielectric layers can be made of different materials, and the gate electrodes 94 and 98 can be formed by different processes, so that the gate electrodes 94 and 98 can be made of different materials. When different processes are used, different masking steps can be employed to mask and expose appropriate areas.

[0073] In Fig. 26A, Fig. 26B and Fig. 26C results in the deposition of an ILD 100 above the ILD 88. Furthermore, in Fig. 26A, Fig. 26B and Fig. Figure 26C illustrates that contacts 102 and 104 are formed by the ILD 100 and the ILD 88, and contacts 106 and 108 are formed by the ILD 100. In one embodiment, the ILD 100 is a flowable film formed by a flowable CVD process. In some embodiments, the ILD 100 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable process, such as CVD and PECVD. Openings for contacts 102 and 104 are formed by the ILDs 88 and 100. Openings for contacts 106 and 108 are formed by the ILD 100. These openings can all be formed simultaneously in the same process or in separate processes. The openings can be formed using acceptable photolithography and etching techniques.A lining, such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The lining can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from a surface of the ILD 100. The remaining lining and conductive material form contacts 102 and 104 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain regions 82 and 84 and contacts 102 and 104, respectively.The contacts 102 are physically and electrically coupled to the epitaxial source / drain regions 82, the contacts 104 are physically and electrically coupled to the epitaxial source / drain regions 84, the contact 106 is physically and electrically coupled to the gate electrode 94, and the contact 108 is physically and electrically coupled to the gate electrode 98.

[0074] In Fig. 27A, Fig. 27B and Fig. In 27C, an intermetal dielectric (IMD) 100 is deposited over the ILD 100. Furthermore, in Fig. 27A, Fig. 27B and Fig. Figure 27C illustrates that intermediate connections 124, 126, 128, and 130 are formed by the IMD 110 to establish contact with respective conductive features in the underlying ILD 100 (e.g., contacts 102, 104, 106, and / or 108). In one embodiment, the IMD 110 is a multilayer film stack formed by the above in Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig. 7 and / or Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. The process described in Section 12 and the corresponding paragraphs is formed. A layer 114 corresponds to the etch stop layer 14 described above, a layer 116 corresponds to the first dielectric layer 16 described above, a layer 118 corresponds to the insert layer 18 or 26 described above, and a layer 120 corresponds to the second dielectric layer described above. These layers are similar to the corresponding layers described above in the preceding embodiments, and the descriptions are not repeated here. Openings for the intermediate connections 124, 126, 128, and 130 are formed by the IMD 110 by a similar process to that described above. Fig. 4 and the corresponding paragraphs. These openings can all be formed simultaneously in the same process, or they can be formed in separate processes. The intermediate connections 124, 126, 128 and 130 are formed by a similar process to the one described above. Fig. 5 to Fig. 6 and / or Fig. 11 to Fig. The intermediate connection 124 is physically and electrically coupled to contact 106, the intermediate connection 126 is physically and electrically coupled to contact 108, the intermediate connections 128 are physically and electrically coupled to contacts 102, and the intermediate connections 130 are physically and electrically coupled to contacts 104.

[0075] Although no explicit description is given, an average professional will easily understand that the structure in Fig. 27A, Fig. 27B and Fig.27C allows for further processing steps. For example, different IMDs and their corresponding metallizations can be formed over the IMD 110.

[0076] By providing the insert layer (e.g., layers 18, 16, and / or 118) as a frame for additional structural support, the typically weaker porous material of the surrounding dielectric layers (e.g., layers 16, 20, 116, and / or 120) can be supported. This additional support helps to reduce variations between different openings caused by their proximity (or lack thereof) to adjacent openings. This prevents complications that could arise during subsequent gap-filling processes.

[0077] In one embodiment, a method comprises the deposition of a first dielectric layer over a substrate, the formation of a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a hardness greater than that of the first dielectric layer and a k-value higher than that of the first dielectric layer, and the deposition of a third dielectric layer over the second dielectric layer, wherein the third dielectric layer has a hardness less than that of the second dielectric layer and a k-value lower than that of the second dielectric layer. The method further comprises etching the third dielectric layer, the second dielectric layer, and the first dielectric layer to form a first opening that exposes a first region above the substrate.wherein the first opening comprises a via opening with a first width and a trench opening with a second width, wherein the trench opening overlaps the via opening, the second width is greater than the first width, a bottom face of the trench opening is separated from a face of the second dielectric layer by a first section of the first dielectric layer or a first section of the third dielectric layer, and the first opening is filled with a conductive material to form a first conductive intermediate that is in contact with the first region of the substrate, wherein the first conductive intermediate has a via section in the via opening and a trench section in the trench opening.

[0078] Another embodiment is a method comprising the deposition of a first dielectric layer of a first thickness over a conductive element over a substrate, the performance of a plasma treatment process to form a insert layer on the first dielectric layer, wherein the insert layer has a k-value that is higher than that of the first dielectric layer, wherein the first dielectric layer has a second thickness that is less than the first thickness after the plasma treatment process, and the deposition of a second dielectric layer over the insert layer, wherein the second dielectric layer has a k-value that is lower than that of the insert layer.The method further comprises etching the second dielectric layer, the insert layer and the first dielectric layer to form a via opening that exposes the conductive element above the substrate, and etching the second dielectric layer to form a trench opening that overlaps the via opening, wherein the trench opening has a greater width than the via opening, with a first section of the second dielectric layer being inserted between a bottom surface of the trench opening and an upper surface of the insert layer.

[0079] Another embodiment is a structure comprising a first dielectric layer over a substrate, an insert layer over and in contact with the first dielectric layer, wherein the insert layer has a hardness greater than that of the first dielectric layer and a k-value higher than that of the first dielectric layer, a second dielectric layer over and in contact with the insert layer, wherein the second dielectric layer has a hardness less than that of the insert layer and a k-value lower than that of the insert layer, and a first conductive intermediate extending through the second dielectric layer, the insert layer, and the first dielectric layer to contact a first region over the substrate.wherein the first conductive intermediate connection comprises a via section with a first width and a trench section with a second width, wherein the trench section overlaps the via section, the second width being greater than the first width, and wherein a bottom face of the trench section is separated from a face of the insert layer by a first section of the first dielectric layer or a first section of the second dielectric layer.

Claims

[1] Procedure, encompassing: Deposition of a first dielectric layer (16) over a substrate (10); Forming a second dielectric layer (18, 26) on the first dielectric layer (16), wherein the second dielectric layer (18, 26) has a hardness greater than that of the first dielectric layer (16) and a k-value higher than that of the first dielectric layer (16); Deposition of a third dielectric layer (20) over the second dielectric layer (18, 26), wherein the third dielectric layer (20) has a hardness that is lower than that of the second dielectric layer (18, 26) and has a k-value that is lower than that of the second dielectric layer (18, 26); Etching of the third dielectric layer (20), the second dielectric layer (18, 26), and the first dielectric layer (16) to form a first opening (22) exposing a first region (12) above the substrate (10), wherein the first opening (22) has a via opening with a first width and a trench opening with a second width, the trench opening overlapping the via opening, the second width being greater than the first width, and a bottom surface of the trench opening being separated by a first section of the first dielectric layer (16) or a first section of the third dielectric layer (20) from a surface of the second dielectric layer (18, 26); and Filling the first opening (22) with a conductive material to form a first conductive intermediate connection (24) which is in contact with the first region (12) of the substrate (10), wherein the first conductive intermediate connection (24) has a via section (24b) in the via opening and a trench section (24a) in the trench opening, the formation of the second dielectric layer (18, 26) on the first dielectric layer (16) comprises the following: Performing a plasma treatment process on the first dielectric layer (16) to form the second dielectric layer (18, 26) on the first dielectric layer (16), wherein the first dielectric layer (16) after the plasma treatment process has a thickness that is less than the thickness of the first dielectric layer (16) before the plasma treatment process, wherein the plasma treatment process converts an upper section of the first dielectric layer (16) into the second dielectric layer (18, 26). [2] Method according to claim 1, wherein the first region (12) above the substrate (10) comprises a conductive element (12), wherein the first conductive intermediate connection (24) is in contact with the conductive element. [3] Method according to claim 1 or 2, wherein the second dielectric layer (18, 26) is in contact with the via section of the first conductive intermediate connection (24). [4] Method according to one of the preceding claims, wherein the second dielectric layer (18, 26) is in contact with the trench section of the first conductive intermediate connection (24). [5] Method according to any of the preceding claims, wherein forming the second dielectric layer (18, 26) on the first dielectric layer (16) comprises: Deposition of the second dielectric layer (18, 26) on the first dielectric layer (16). [6] Method according to any of the preceding claims, wherein filling the first opening (22) with the conductive material comprises: Covering the first opening (22) with a barrier layer; Filling the covered first opening (22) with the conductive material; and Planarizing the conductive material, the barrier layer and the third dielectric layer (20) to remove excess conductive material and excess barrier layer over an upper surface of the third dielectric layer (20) to form the first conductive intermediate connection (24) that is in contact with the first region (12) above the substrate (10). [7] Method according to any one of the preceding claims, further comprising: Deposition of an etch stop layer over the substrate (10), wherein the first dielectric layer (16) is formed over the etch stop layer and is in contact with it, wherein the first opening (22) extends through the etch stop layer. [8] Method according to any of the preceding claims, wherein the first dielectric layer (16) has a k-value of 2.6 or less, and the second dielectric layer (18, 26) has a k-value of 2.8 or more. [9] Procedures, comprehensive: Deposition of a first dielectric layer (16) with a first thickness over a conductive element (12) over a substrate (10); Performing a plasma treatment process to form a insert layer (18, 26) on the first dielectric layer (16), wherein the insert layer (18, 26) has a k-value that is higher than that of the first dielectric layer (16), wherein the first dielectric layer (16) has a second thickness after the plasma treatment process that is less than the first thickness, wherein the plasma treatment process converts an upper section of the first dielectric layer (16) into the insert layer (18, 26); Deposition of a second dielectric layer (20) over the insert layer (18, 26), wherein the second dielectric layer (20) has a k-value that is lower than that of the insert layer (18, 26); Etching of the second dielectric layer (20), the insert layer (18, 26) and the first dielectric layer (16) to form a via opening that exposes the conductive element (12) above the substrate (10); and Etching of the second dielectric layer (20) to form a trench opening that overlaps the via opening, wherein the trench opening has a greater width than the via opening, wherein a first section of the second dielectric layer (20) is inserted between a bottom surface of the trench opening and an upper surface of the insert layer (18, 26). [10] Method according to claim 9, wherein the first dielectric layer (16) has a k-value of 2.6 or less, and the insert layer (18, 26) has a k-value of 2.8 or more. [11] Method according to claim 9 or 10, further comprising: Filling the via opening and the trench opening with a conductive material to form a first conductive intermediate connection (24) which is in contact with the conductive element (12) on the substrate (10), wherein the first conductive intermediate connection (24) comprises a via section (24b) in the via opening and a trench section (24a) in the trench opening. [12] Method according to claim 11, wherein the insert layer (18, 26) is in contact with the via section of the first conductive intermediate connection (24). [13] Method according to any one of claims 9 to 12, further comprising: Deposition of an etch stop layer over the substrate (10) and the conductive element (12) in the substrate (10), wherein the first dielectric layer (16) is formed over the etch stop layer and is in contact with it, and wherein the via opening extends through the etch stop layer. [14] Method according to any one of claims 9 to 13, wherein the conductive element (12) is a conductive contact, the conductive contact being electrically connected to a source / drain region of a Fin field-effect transistor (FinFET). [15] Structure, comprehensive: a first dielectric layer (16) over a substrate (10), wherein the first dielectric layer (16) consists of a first dielectric material; a insert layer (18, 26) over and in contact with the first dielectric layer (16), wherein the insert layer (18, 26) has a hardness greater than that of the first dielectric layer (16) and a k-value higher than that of the first dielectric layer (16), wherein the insert layer (18, 26) consists of plasma-treated first dielectric material; a second dielectric layer (20) above and in contact with the insert layer (18, 26), wherein the second dielectric layer (20) has a hardness lower than that of the insert layer (18, 26) and a k-value lower than that of the insert layer (18, 26); and a first conductive intermediate connection (24) extending through the second dielectric layer (20), the insert layer (18, 26), and the first dielectric layer (16) to contact a first region (12) above the substrate (10), wherein the first conductive intermediate connection (24) comprises a via section (24b) having a first width and a trench section (24a) having a second width, the trench section overlapping the via section, the second width being greater than the first width, and a bottom surface of the trench section being separated from a surface of the insert layer (18, 26) by a first section of the first dielectric layer (16) or a first section of the second dielectric layer (20). [16] Structure according to claim 15, wherein the first area (12) above the substrate (10) comprises a conductive element (12), wherein the first conductive intermediate connection (24) is in contact with the conductive element. [17] Structure according to claim 16, wherein the conductive element is a conductive contact, the conductive contact being electrically connected to a source / drain region of a Fin field-effect transistor (FinFET). [18] Structure according to one of claims 15 to 17, wherein the insert layer (18, 26) is in contact with the via section of the first conductive intermediate connection (24). [19] Structure according to one of claims 15 to 18, wherein the insert layer (18, 26) is in contact with the trench section of the first conductive intermediate connection (24).

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