Fingerprint sensor device and method for manufacturing therefrom

Abstract

A method for manufacturing a semiconductor device, the method comprising the following: Attaching a sensor surface material (123) over a sensor chip (104), wherein the sensor chip (104) is a fingerprint sensor and comprises the following: - a semiconductor substrate (111); and - an electrode array (120) between the semiconductor substrate (111) and the sensor surface material (123), wherein the electrode array (120) is used to measure the difference in capacitance between different areas of a finger placed on the sensor in order to measure the fingerprint; Attaching a high-voltage chip (141) in electrical connection with the sensor chip (104), wherein the high-voltage chip (141) is configured to supply a high voltage between 5 V and 50 V to the sensor chip (104) to enhance the sensitivity of the sensor chip (104), wherein the high-voltage chip (141) is located on a side of the sensor chip (104) opposite the sensor surface material (123); and Attaching the sensor chip (104) to a substrate (150), wherein the high-voltage chip (141) is located within an opening (151) of the substrate (150) after the sensor chip (104) has been attached to the substrate (150).

Description

BACKGROUND

[0001] As user devices become increasingly smaller and more portable, it has become easier for malicious individuals to hijack user devices. If such devices contain sensitive user information, thieves can access that information unless obstacles are placed within the user device. One such obstacle is a fingerprint sensor, which can be used to scan the fingerprint of the person attempting to access the device. If the fingerprint is not the same as the user's fingerprint, access may be denied.

[0002] However, as consumer devices such as mobile phones become increasingly smaller, each of the individual components within the consumer device is under pressure to also experience a corresponding reduction in size. Therefore, there is pressure to reduce the size of the fingerprint package, which includes the fingerprint sensor, without compromising performance. Therefore, improvements are needed to achieve the desired reduction in size.

[0003] The prior art relevant to the invention is given by US 6 150 724 A, WO 2013 / 085497 A1, US 2014 / 0138788 A1, US 2012 / 0256280 A1 and DE 10 2008 005 607 A1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A-1F illustrates a fingerprint sensor package using vias removed laterally from a sensor, according to some embodiments. Fig. 2A-2B illustrates an embodiment using vias extending through the fingerprint sensor in conjunction with a redistribution layer, according to some embodiments. Fig. 3A-3B illustrates an embodiment using vias extending through the fingerprint sensor without a redistribution layer, according to some embodiments. Fig. 4 illustrates an incorporation of the fingerprint sensor package into a semiconductor device according to some embodiments. Fig. 5 illustrates an incorporation of the fingerprint sensor package into a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0004] The following describes embodiments with reference to a fingerprint sensor in a system-in-package (SiP) solution or an integrated fan-out (InFO) structure. However, embodiments may be used in any suitable assembly.

[0005] With reference to Fig. 1A illustrates an embodiment that utilizes a carrier substrate 101, an adhesion layer 103, a polymer layer 105, a first redistribution layer 107, first substrate vias (TSVs) 109, and a sensor chip 104 that is a fingerprint sensor. In one embodiment, the carrier substrate 101 comprises, for example, silicon-based materials such as glass or silicon oxide, or other materials such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate 101 is planar to facilitate attachment of devices such as the fingerprint sensor.

[0006] The adhesive layer 103 can be disposed over the support substrate 101 to assist in attaching overlying structures to the support substrate 101. In one embodiment, the adhesive layer 103 is a die attach film (DAF), such as an epoxy resin, a phenolic resin, acrylic rubber, silica filler, or a combination thereof, and is applied using a lamination technique. However, any other suitable material and formation method may be used.

[0007] The polymer layer 105 is first formed over the adhesion layer 103. In one embodiment, the polymer layer 105 may be composed of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. The polymer layer 105 may be formed by a process such as chemical vapor deposition (CVD), although any suitable process may be used, and may have a thickness between about 0.5 µm and about 5 µm, such as about 9.25 kÅ.

[0008] Once the polymer layer 105 is formed, under-bump metallization layers 137 and the first redistribution layers 107 may be formed over the polymer layer 105. In one embodiment, the under-bump metallization layers 137 may comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, suitable for forming the under-bump metallization layers 137. Any suitable materials or material layers that may be used for the under-bump metallization layers 137 are intended to be included within the scope of the embodiments.

[0009] In one embodiment, the under-bump metallization layers 137 are created by forming each layer over the polymer layer 105. The formation of each layer may be performed using a plating process such as electrochemical plating, although alternatively, depending on the desired materials, other processes such as sputtering, evaporation, or a PECVD process may be used. The under-bump metallization layers 137 may be formed to have a thickness of between about 0.7 μm and about 10 μm, such as about 5 μm.

[0010] In one embodiment, the first redistribution layer 107 comprises a series of conductive layers 133 (such as two conductive layers) embedded in a series of dielectric layers 135 (such as three dielectric layers). In one embodiment, a first of the series of dielectric layers 135 is formed over the polymer layer 105, and the first of the series of dielectric layers 135 may be a material such as a polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative may be used. The first of the series of dielectric layers 135 may be arranged, for example, using a spin-coating process, although any suitable process may be used.

[0011] After the first of the series of dielectric layers 135 is formed, openings may be created through the first of the series of dielectric layers 135 by removing portions of the first of the series of dielectric layers 135. The openings may be formed using a suitable photolithographic mask and etching process, although any suitable method or methods may be used to pattern the first of the series of dielectric layers 135.

[0012] Once the first of the series of dielectric layers 135 is formed and patterned, a first of the series of conductive layers 133 is formed over the first of the series of dielectric layers 135 and through the openings formed in the first of the series of dielectric layers 135. In one embodiment, the first of the series of conductive layers 133 may be formed by first forming a seed layer (not shown) of a titanium-copper alloy using a suitable formation process such as CVD or sputtering. Subsequently, a photoresist (also not shown) may be formed to cover the seed layer, and the photoresist may then be patterned to expose the portions of the seed layer located where the first of the series of conductive layers 133 is to be disposed.

[0013] Once the photoresist has been formed and patterned, a conductive material such as copper can be formed on the seed layer by a deposition process such as plating. The conductive material can be formed to have a thickness between about 1 µm and about 10 µm, such as about 5 µm. While the discussed material and processes are suitable for forming the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable formation processes, such as CVD or PVD, can be used to form the first of the series of conductive layers 133. Once the conductive material has been formed, the photoresist can be removed by a suitable removal process such as ashing.Additionally, after removal of the photoresist, the portions of the seed layer that were covered by the photoresist may be removed, for example, by any suitable etching process using the conductive material as a mask.

[0014] Once the first of the series of conductive layers 133 is formed, a second of the series of dielectric layers 135 and a second of the series of conductive layers 133 can be formed by repeating the steps in the same manner as the first of the series of dielectric layers 135 and the first of the series of conductive layers 133. These steps can be repeated as desired to connect each of the series of conductive layers 133 to an underlying one of the series of conductive layers 133 and can be repeated any number of times until a topmost one of the series of conductive layers 133 and a topmost one of the series of dielectric layers 131 are formed.In one embodiment, the deposition and patterning of the series of conductive layers 133 and the series of dielectric layers 135 may continue until the first redistribution layers 107 have a desired number of layers, such as two layers, although any suitable number of individual layers may be used.

[0015] Once the redistribution layers 107 are formed over the carrier substrate 101, the first TSVs 109 are formed in electrical connection with the first redistribution layers 107. In one embodiment, the first TSVs 109 may be formed by first forming a seed layer (not individually Fig. 1A). In one embodiment, the seed layer is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The seed layer may include an approximately 1,000 Å thick layer of titanium followed by an approximately 5,000 Å thick layer of copper. The seed layer may be formed using methods such as sputtering, evaporation, or PECVD, depending on the desired materials. The seed layer may be formed to have a thickness between about 0.3 µm and about 1 µm, such as about 0.5 µm.

[0016] Once the seed layer is formed, a photoresist (also not in Fig. 1A) is disposed over the seed layer. In one embodiment, the photoresist may be disposed, e.g., using a spin-coating process, at a height between about 50 µm and about 250 µm, such as about 120 µm, on the seed layer. Once disposed, the photoresist may then be patterned by exposing the photoresist to a patterned energy source (e.g., a patterned light source) in such a way as to initiate a chemical reaction, thereby causing a physical change in the portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to exploit the physical changes and remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending on the desired pattern.In one embodiment, the pattern formed in the photoresist is a pattern for the first TSVs 109. The first TSVs 109 are formed in an arrangement such that they are located on different sides of subsequently attached devices, such as the sensor chip 104, which is a fingerprint sensor. However, any suitable arrangement for the pattern of the first TSVs 109 may be used.

[0017] In one embodiment, the first TSVs 109 are formed from one or more conductive materials such as copper, tungsten, other conductive materials, or the like within the photoresist and can be formed, for example, by electroplating, electroless plating, or the like. For example, an electroplating process is used in which the seed layer and the photoresist are submerged or immersed in an electroplating solution. The seed layer is electrically connected to the negative side of an external DC power supply such that the seed layer acts as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also submerged in the solution and is attached to the positive side of the power supply. The atoms of the anode are dissolved in the solution, from which the cathode, e.g.the seed layer, which absorbs solute atoms and thereby plates the exposed conductive regions of the seed layer in the opening of the photoresist.

[0018] Once the first TSVs 109 have been formed using the photoresist and seed layer, the seed layer may be removed using a suitable removal method. In one embodiment, a plasma ashing process may be used to remove the photoresist, where the temperature of the photoresist may be increased until the photoresist undergoes thermal degradation and can be removed. However, any other suitable method, such as a wet strip, may be used. Removal of the photoresist may expose the underlying portions of the seed layer.

[0019] Once exposed, removal of the exposed portions of the seed layer may be performed. In one embodiment, the exposed portions of the seed layer (e.g., the portions not covered by the first TSVs 109) may be removed, for example, using a wet or dry etching process. In a dry etching process, for example, reactants may be directed toward the seed layer using the first TSVs 109 and masks. In another embodiment, etchants may be sprayed onto or otherwise contacted with the seed layer to remove the exposed portions of the seed layer. After the exposed portion of the seed layer is etched away, a portion of the first redistribution layers 107 between the first TSVs 109 is exposed.

[0020] Once the first TSVs 109 are formed, the sensor chip 104, which is a fingerprint sensor, can be disposed on the first redistribution layer 107. In one embodiment, the sensor chip 104 includes a semiconductor substrate 111 having a first side 113 and a second side 115, and an electrode array 120 disposed adjacent to the first side 113. In one embodiment, the semiconductor substrate 111 may include bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0021] Additionally, although not individually in Fig. 1A, the sensor chip, which is a fingerprint sensor 104, may also include active devices and metallization layers to control the input of signals from the electrode array 120 and receive them, or otherwise control the functionality and subsequent output of the sensor chip 104. In one embodiment, the active devices of the sensor chip 104 include a wide range of active devices and passive devices, such as capacitors, resistors, inductors, and the like, which may be used to create the desired structural and functional design requirements for the sensor chip 104. The active devices may be formed either in or on the semiconductor substrate 111 using any suitable methods.

[0022] The metallization layers are formed over the semiconductor substrate 111 and the active devices of the sensor chip 104 and are designed to connect the various active devices to form functional circuits. In one embodiment, the metallization layers are formed from alternating layers of dielectric and conductive material and can be formed by any suitable method (such as deposition, damascening, dual damascening, etc.). In one embodiment, there may be four metallization layers separated from the second semiconductor substrate by at least one interlayer dielectric layer (ILD), although the exact number of metallization layers depends on the design of the sensor chip 104.

[0023] The electrode array 120 is electrically connected to the metallization layers of the sensor chip 104 and is used to measure the difference in capacitance between different areas of a resting finger in order to measure the fingerprint. In one embodiment, the electrode array 120 comprises a conductive material such as aluminum or copper and is formed, for example, using a deposition and patterning process, wherein a capping layer of conductive material is applied using a process such as CVD, PVD, ALD, or the like, and the capping layer of material is then patterned using a photolithographic masking and etching process. However, any suitable materials or processes may be used to form the electrode array 120.

[0024] Furthermore, while the formation of the electrode array 120 using a cap deposition followed by subsequent patterning and securing has been described, this method is intended to be merely illustrative and not limiting. Rather, any suitable method for fabricating the electrode array 120, such as using a damascene or dual-damascene process, may be used. All such methods are intended to be fully encompassed within the scope of the embodiments.

[0025] Contact pads 119 are formed to provide an electrical connection to a subsequently formed second redistribution layer 121 (in Fig. 1A not shown but below with reference to Fig. 1B). In one embodiment, the contact pads 119 are formed from a conductive material such as aluminum, although any other suitable materials such as copper, tungsten, and the like may be used. The contact pads 119 may be formed using a process such as CVD or PVD, although other suitable materials and processes may be used. Once the material for the contact pads 119 has been deposited, the material may be formed into the contact pads 119, e.g., using a photolithographic masking and etching process.

[0026] Once the contact pads 119 are formed, a first protective layer 122 may be disposed and patterned. In one embodiment, the first protective layer 122 may be a protective material such as polybenzoxazole (PBO) or polyimide (PI), silicon oxide, silicon nitride, silicon oxynitride, benzocyclobutene (BCB), or any other suitable protective material. Depending on the material chosen, the first protective layer 122 may be formed using a method such as a spin-on process, a deposition process (e.g., chemical vapor deposition), or another suitable method, and may be formed to a thickness of between about 1 μm and 100 μm, such as about 20 μm.

[0027] Once formed, the first protective layer 122 is patterned to form openings and expose the contact pads 119. In one embodiment, the first protective layer 122 may be patterned using, for example, a photolithographic masking and etching process. In such a process, a photoresist (in Fig. 1B not shown individually) is applied to the first protective layer 122 and then exposed to a patterned light source. The light source falls on the photoresist and induces a change in a property of the photoresist, which is then used to remove either the exposed portion or the unexposed portion and expose the first protective layer 122. The photoresist is then used as a mask, e.g., during an etching process that removes portions of the first protective layer 122 to expose the contact pads 119. Once the first protective layer 122 is patterned, the photoresist can be removed, e.g., using an ashing process.

[0028] In another embodiment, the first protective layer 122 may be thinned to expose the contact pads 119. In this embodiment, a planarization process, such as a chemical mechanical polishing process, by which chemicals and abrasives are applied to the first protective layer 122 while a polishing pad abrades material, may be used to remove the material of the first protective layer 122 from above the contact pads 119 and thereby expose the contact pads 119, while also planarizing the first protective layer 122 with the contact pads 119. Any method for forming the contact pads 119 and the first protective layer 122 may be used.

[0029] The sensor chip 104 is arranged on the first redistribution layer 107 between the first TSVs 109, e.g., using a second adhesion layer 112. In one embodiment, the second adhesion layer 112 may be a similar material and applied in a similar manner as the adhesion layer 103, although any suitable material may be used. The sensor chip 104 is arranged facing upwards, such that the first side 113 faces away from the carrier substrate 101. Additionally, the contact pads 119 are connected to the electrode array 120 and the metallization layers of the sensor chip 104 on the first side 113 of the sensor chip 104.

[0030] Fig. 1B illustrates an encapsulation of the sensor chip 104 and the first TSVs 109 with an encapsulation material 125. In one embodiment, the encapsulation material 125 may be a molding compound and may be formed using a molding device (in Fig. 1B not shown). The sensor chip 104 can be arranged, for example, in a cavity of the molding device, and the cavity can be hermetically sealed. The encapsulant material 125 can either be placed in the cavity before the cavity is hermetically sealed, or can be injected into the cavity through an injection point. In one embodiment, the encapsulant material 125 can be a molding resin such as polyimide, PPS, PEEK, PES, a heat-resistant crystal resin, combinations thereof, or the like.

[0031] Once the encapsulation material 125 has been placed in the cavity such that the encapsulation material 125 encapsulates the area surrounding the sensor chip 104 and the first TSVs 109, the encapsulation material 125 may be cured to harden the encapsulation material 125 for optimal protection. While the exact curing method depends at least in part on the particular material selected as the encapsulation material 125, in one embodiment where the molding compound is selected as the encapsulation material 125, the curing could be accomplished by a method such as heating the encapsulation material 125 to between about 100°C and about 130°C, such as about 125°C, for about 60 seconds to about 3000 seconds, such as about 600 seconds. Additionally, initiators and / or catalysts may be included in the encapsulation material 125 to better control the curing process.

[0032] However, one of ordinary skill in the art will recognize that the curing method described above is merely an exemplary method and is not intended to limit the current embodiments. Other curing methods, such as irradiation or even allowing the encapsulation material 125 to cure at ambient temperature, may be used. Any suitable curing method may be used, as all such methods are intended to be fully encompassed within the scope of the embodiments discussed herein.

[0033] Fig. 1B additionally illustrates thinning of the encapsulation material 125 to expose the contact pads 119 of the sensor chip 104. In one embodiment, the thinning may be performed, for example, using a mechanical grinding or chemical mechanical polishing (CMP) process, wherein chemical etchants and abrasives are used to react and abrade the encapsulation material 125. The encapsulation material 125 may be thinned until the contact pads 119 are exposed.

[0034] While the CMP process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process may be used to encapsulate the sensor chip 104 while exposing the contact pads 119. For example, a chemical etchant or series of chemical etchants may be used, or an encapsulation process that does not cover the contact pads 119 may be used. These processes and any other suitable processes may be used to apply the encapsulation material 125, and all such processes are intended to be fully encompassed within the scope of the embodiments.

[0035] Fig. 1B also illustrates the formation of a second redistribution layer 121 to electrically connect the first TSVs 109 to the contact pads 119 of the sensor chip 104. In one embodiment, the second redistribution layer 121 may be the first redistribution layer 107 described above with reference to Fig. 1A. In a specific embodiment, there may be a single one of the series of conductive layers 133 disposed between two of the series of dielectric layers 135. However, any suitable combination of conductive layers and dielectric layers may be used to connect the contact pads 119 of the sensor chip 104 to the first TSVs 109.

[0036] Once the second redistribution layer 121 is formed, a sensor surface material 123 may be attached to the second redistribution layer 121, e.g., using an intermediate layer 136 such as an adhesive layer or a color overcoat layer. In one embodiment, the sensor surface material 123 may be attached by first applying the intermediate layer 136 to the second redistribution layer 121 and subsequently applying the sensor surface material 123 to the intermediate layer 136. The intermediate layer 136 may be similar to that described above with reference to Fig. 1A, although any suitable material may be used.

[0037] In one embodiment, the sensor surface material 123 is a material such as sapphire or glass that enables the measurement of capacitive changes between the sensor chip 104 and a resting finger to detect the contours of a fingerprint on the finger. In one embodiment, the sensor surface material 123 can be deposited using a physical placement method. Additionally, the sensor surface material 123 can have a first thickness T1 between about 50 µm and about 1000 µm, such as about 100 µm. However, any suitable material and thickness can be used.

[0038] In other embodiments where the intermediate layer 136 is a color overcoat layer, the sensor surface material may be omitted. For example, in one specific embodiment, the intermediate layer 136 may be disposed solely over the second redistribution layer 121 without subsequently disposing the sensor surface material on the intermediate layer 136. Any suitable combination of materials may be used.

[0039] Fig. 1C illustrates stripping the support substrate 101 and patterning the polymer layer 105 to expose the under-bump metallization layers 137. In one embodiment, the support substrate 101 may be stripped by first bonding the sensor surface material 123 to, for example, a ring structure 152. The ring structure 152 may be a metal ring designed to provide support and stability to the structure during and after the stripping process. In one embodiment, the sensor surface material 123 may be attached to the ring structure 152 using, for example, an ultraviolet tape 154, although any other suitable adhesive or attachment may be used.

[0040] Once attached, the carrier substrate 101 can be detached from the structure using, for example, a thermal process to modify the adhesion properties of the adhesion layer 103. In a particular embodiment, an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser is used to irradiate and heat the adhesion layer 103 until the adhesion layer 103 loses at least some of its adhesion properties. Once performed, the carrier substrate 101 and the adhesion layer 103 can be physically separated and removed from the structure comprising the sensor chip 104 and the sensor surface material 123.

[0041] Once peeled off, the polymer layer 105 is patterned to expose the underlying under-bump metallization layers 137. In one embodiment, the polymer layer 105 may be patterned using, for example, a laser drilling process. In such a process, a protective layer, such as a light-to-heat conversion (LTHC) layer or a Hogomax layer (in Fig. 1C not individually shown) is first applied over the polymer layer 105. Once protected, a laser is directed at the portions of the polymer layer 105 to be removed to expose the underlying under-bump metallization layers 137. During this laser drilling process, the drilling energy may range from 0.1 mJ to about 30 mJ and a drilling angle may range from about 0 degrees (normal to the polymer layer 105) to about 85 degrees normal to the polymer layer 105. In one embodiment, the patterning may be formed such that openings are formed over the under-bump metallization layers 137 to have a width of about 100 µm to about 300 µm, such as about 200 µm.

[0042] In another embodiment, the polymer layer 105 may be patterned by first applying a photoresist (in Fig. 1C not individually shown) is applied to the polymer layer 1105, and the photoresist is then exposed to a patterned energy source (e.g., a patterned light source) such that a chemical reaction is initiated, thereby causing a physical change in the portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to exploit the physical changes and, depending on the desired pattern, remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, and the underlying exposed portion of the polymer layer 105 is removed, e.g., using a dry etching process. However, any other suitable method for patterning the polymer layer 105 may be used.

[0043] Fig. 1D illustrates that once the polymer layer 105 is patterned to expose the under-bump metallization layers 137, a high-voltage chip 141 can be connected through the polymer layer 105 to the under-bump metallization layers 137 to form a first sensor package 149. In one embodiment, the high-voltage chip 141 is configured and connected to supply a high voltage, such as between about 5 V and about 50 V, such as 33 V, to the sensor chip 104 to enhance the sensitivity of the sensor. By integrating the high-voltage chip 141 with the sensor chip 104 such that a high voltage chip can be supplied to the sensor chip 104, the sensitivity of the sensor chip 104 can be increased tenfold by increasing the input voltage from, for example, 3.3 V to 33 V.

[0044] In one embodiment, the high-voltage chip 141 may include a second semiconductor substrate (not individually shown), active devices (not individually shown), metallization layers (not individually shown) used to connect the active devices of the high-voltage chip 141, and first external connections 143 to connect the high-voltage chip 141 to the sensor chip 104. The second semiconductor substrate may include bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0045] The active devices of the high-voltage chip 141 include a wide range of active devices and passive devices such as capacitors, resistors, inductors, and the like, which can be used to create the desired structural and functional design requirements for the high-voltage chip 141. The active devices can be formed either in or on the semiconductor substrate using any suitable methods.

[0046] The metallization layers for the high-voltage chip 141 are formed over the second semiconductor substrate and the active devices of the high-voltage chip 141 and are designed to connect the various active devices to form functional circuits. In one embodiment, the metallization layers are formed from alternating layers of dielectric and conductive material and can be formed by any suitable method (such as deposition, damascening, dual damascening, etc.). In one embodiment, there may be four metallization layers separated from the second semiconductor substrate by at least one interlayer dielectric layer (ILD), although the exact number of metallization layers depends on the design of the high-voltage chip 141.

[0047] The first external connections 143 may be configured to connect the high-voltage chip 141 to the sensor chip 104 and may be, for example, contact bumps, although any suitable connection may be used. In an embodiment where the first external connections 143 are contact bumps, the first external connections 143 may comprise a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In an embodiment where the first external connections 143 are tin solder contact bumps, the first external connections 143 may be formed by first forming a layer of tin by commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc., to a thickness of, for example, between about 30 µm and about 100 µm.Once a layer of tin is formed on the structure, reflow can be performed to form the material into the desired bump shape.

[0048] The high voltage chip 141 may be formed to have a first width W1 between about 1 mm and about 5 mm, such as about 1.5 mm, and may also be formed to have a second thickness T2 between about 70 µm and about 150 µm, such as about 100 µm. In addition, although not in Fig. 1D, since it would extend into and out of the figure, the high-voltage chip 141 may also be formed to have a first length between about 1 mm and about 5 mm, such as about 2 mm. However, any suitable dimensions for the high-voltage chip 141 may be used.

[0049] The high-voltage chip 141 may be connected to the under-bump metallization layers 137, for example, by applying a solder paste to the exposed under-bump metallization layers 137 and then flip-chip-connecting the high-voltage chip 141 to the under-bump metallization layers 137. In one embodiment, the high-voltage chip 141 may be connected by subsequently dipping the first external connections 143 of the high-voltage chip 141 in flux and then using a pick-and-place tool to physically align the first external connections 143 of the high-voltage chip 141 with individual ones of the under-bump metallization layers 137.In an embodiment where the first external connections 143 are solder balls, once the high-voltage chip 141 is positioned, a reflow process may be performed to physically connect the high-voltage chip 141 to the underlying under-bump metallization layers 137, and flux cleaning may be performed. However, any other suitable connector or connection method, such as metal-to-metal bonding or the like, may be used.

[0050] Once the high-voltage chip 141 is connected to the under-bump metallization layers 137, an underfill material 147 may be disposed between the high-voltage chip 141 and the sensor chip 104 to help protect and insulate the devices. In one embodiment, the underfill material 147 is a protective material used to cushion and protect the high-voltage chip 141 from operational and environmental degradation, such as stresses caused by heat generation during operation. For example, the underfill material 147 may comprise a liquid epoxy or other protective material and then be cured to harden, and may be dispensed, for example, by injection.

[0051] Additionally, after the first polymer layer 105 has been patterned, second external interconnects 139 may be used to provide an external connection point for electrical connection to the first redistribution layer 107, and may, for example, be a contact bump as part of a ball grid array (BGA), although any suitable interconnect may be used. In an embodiment in which the second external interconnects 139 are contact bumps, the second external interconnects 139 may comprise a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In an embodiment in which the second external interconnects 139 are tin solder contact bumps, the second external interconnects 139 may be formed by first depositing a layer of tin by commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc., to a thickness of, for example,approximately 250 µm. Once a layer of tin is formed on the structure, reflow can be performed to form the material into the desired bump shape.

[0052] Fig. Figure 1E illustrates connecting the structure to a substrate 150. In one embodiment, the substrate may be, for example, a circuit board that interconnects various electrical components to provide a desired functionality for a user. Alternatively, the substrate 150 may be a flexible substrate or may include multiple conductive layers (not individually shown) that may be etched into traces of various widths and lengths and connected by interlayer vias. Together, these lines and vias may form an electrical network to carry DC power, ground, and signals from one side of the substrate 150 to the other.Those skilled in the art will appreciate that the substrate 150 may be made of an organic (laminate) material such as bismaleimide triazine (BT), a polymer-based material such as liquid crystal polymer (LCP), a ceramic material such as low-temperature cofired ceramics (LTCC), a silicon or glass interposer, or the like. Those skilled in the art will also appreciate that the conductive layers and vias may be formed of any suitable conductive material, such as copper, aluminum, silver, gold, other metals, alloys, combinations thereof, and / or the like, and may be formed by any suitable method such as electrochemical plating (ECP), electroless plating, other deposition methods such as sputtering, printing, and chemical vapor deposition (CVD) methods, or the like.The substrate 150 may be formed or obtained with a third thickness T3 of between about 100 µm and about 1000 µm, such as about 200 µm, although any suitable thickness may be used.

[0053] In some embodiments, the substrate 150 may further include electrical elements such as resistors, capacitors, signal distribution circuits, combinations of these, or the like. These electrical elements may be active, passive, or a combination thereof. In other embodiments, the substrate 150 is free of both active and passive electrical elements therein. All such suitable combinations are intended to be fully encompassed within the scope of the embodiments.

[0054] Additionally, to accommodate the presence of a high-voltage chip 141, the substrate 150 may be formed with or have a first opening 151 therein. In one embodiment, the first opening 151 is sized to receive the high-voltage chip 141, and as such, the dimensions of the first opening 151 depend at least in part on the dimensions of the high-voltage chip 141. However, in an embodiment where the high-voltage chip 141 has the first width W1, the first length, and the second thickness T2, the first opening 151 may be formed to have a second width W2 between about 2 mm and about 6 mm, such as about 2.5 mm. Additionally, the first opening 151 may have a second length (in Fig. 1E, since the second length would extend in and out of the figure) between 2 mm and 6 mm, such as 3.5 mm. However, any suitable dimensions that accommodate the high-voltage chip 141 may be used.

[0055] Additionally, in some embodiments, as in Fig. 1E, the first opening 151 extends all the way through the substrate 150. Therefore, the first opening 151 has the third thickness T3 of the substrate 150, as indicated by being between about 0.1 mm and about 1 mm, such as about 0.2 mm. However, any suitable dimension may be used.

[0056] In another embodiment (shown in Fig. 1E by the dashed lines), the opening 151 may be formed to extend partially, but not completely, through the substrate 150. In this embodiment, the first opening may be formed to extend a first depth D1 between about 50 µm and about 500 µm, such as about 100 µm, into the substrate 150. However, any suitable depth may be used to accommodate the high-voltage chip 141.

[0057] The substrate 150 may further comprise second contact pads 153 that enable electrical connection to the second external connections 139. In one embodiment, the second contact pads 153 may be formed from similar materials using similar methods as the contact pads 119 described above with reference to Fig. 1A. For example, the second contact pads 153 may be aluminum contact pads formed using a process such as CVD or PVD. However, any suitable material or process for manufacturing the second contact pads 153 may be used.

[0058] To connect the second contact pads 153 to the second external connections 139, the second contact pads 153 and the second external connections 139 are first aligned with each other. In one embodiment, for example, the second external connections 139 may be aligned with the second contact pads 153 and arranged in physical contact therewith. Once arranged and aligned, the external connections 139 may be reflowed to physically and electrically connect the second external connections 139 to the substrate 150.

[0059] By attaching the sensor chip 104 to the substrate 150 such that the high-voltage chip 141 is disposed within the first opening 151, the overall height of the structure can be reduced. For example, in one embodiment, the overall height of the substrate 150, together with the attached sensor chip 104, may be a first height H1 of between about 0.4 mm and about 1.5 mm, such as about 0.5 mm. However, any suitable height may be used.

[0060] Fig. 1F illustrates another embodiment in which the high voltage chip 104 may be positioned as desired relative to the sensor chip 104, rather than being centered under the sensor chip 104. In the Fig. For example, in the embodiment illustrated in Figure 1F, the high-voltage chip 141 may be arranged at a second distance D2 from a first side of the sensor chip 104 (in this top-down view) of between about 800 µm and about 4000 µm, such as about 1000 µm, and further arranged at a third distance D3 from a second side of the sensor chip 104 of between about 80 µm and about 4000 µm, such as about 1500 µm. However, any suitable arrangement of the high-voltage chip 141 with respect to the sensor chip 104 may be used.

[0061] By forming the first sensor package 149 as described above, not only can the sensitivity of the sensor chip 104 be improved by minimizing the sensing gap between the electrode array 120 and the finger, but a fan-in design is used to integrate the high-voltage chip 141 and increase the charge (Q = C * V). Such an increase enables an increase in the sensitivity of the sensor.

[0062] Fig. 2A depicts another embodiment illustrating a second sensor package 200 that uses substrate vias 201 extending through the semiconductor substrate 111 to connect the electrode array 120 and a third redistribution layer 203. However, in this embodiment, the substrate vias 201 are used to connect the electrode array 120 and the metallization layers located on the first side 113 of the sensor chip 104 to the second side 115 of the sensor chip 104. The substrate vias 201 may be formed by first applying and developing a photoresist to the semiconductor substrate 111 prior to forming the metallization layers, and then etching the semiconductor substrate 111 to create TSV openings.The openings for the substrate vias 201 can be formed at this time such that they extend into the semiconductor substrate 111 to a depth that is at least greater than the later desired height of the finished semiconductor substrate 111.

[0063] Once the openings for the substrate vias 201 are formed, the openings for the substrate vias 201 may be filled, for example, with a barrier layer and a conductive material. The barrier layer may comprise a conductive material such as titanium nitride, although other materials such as tantalum nitride, titanium, a dielectric, and the like may be used. The barrier layer may be formed using a CVD process such as PECVD. However, other processes such as sputtering or metal organic chemical vapor deposition (MOCVD) may be used. The barrier layer may be formed to contour the underlying shape of the openings for the substrate vias 201.

[0064] The conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like may be used. The conductive material may be formed by depositing a seed layer and then electroplating copper onto the seed layer, filling and overfilling the openings for the substrate vias 201. Once the openings for the substrate vias 201 are filled, excess barrier layer and excess conductive material outside the openings for the substrate vias 201 may be removed by an abrasive process such as CMP, although any suitable removal process may be used.

[0065] Once the conductive material is in the openings for the substrate vias 201, thinning of the semiconductor substrate 111 may be performed to expose the openings for the substrate vias 201 and to form the substrate vias 201 from the conductive material extending through the semiconductor substrate 111. In one embodiment, thinning of the semiconductor substrate 111 may be performed by a planarization process such as CMP or etching, thereby making the substrate vias 201 flush with the semiconductor substrate 111.

[0066] However, as one of ordinary skill in the art will appreciate, the above-described method for forming the substrate vias 201 is merely one method for forming the substrate vias 201, and other methods are also intended to be fully included within the scope of the embodiments. For example, forming the openings for the substrate vias 201, filling the openings for the substrate vias 201 with dielectric material, thinning the semiconductor substrate 111 to expose the dielectric material, removing the dielectric material, and filling the openings for the substrate vias 201 with a conductor may also be used. These and any other suitable methods for forming the substrate vias 201 in the semiconductor substrate 111 are intended to be fully included within the scope of the embodiments.

[0067] Once the substrate vias 201 are formed (and the active devices and metallization layers are also completed as desired), the third redistribution layer 203 may be formed in electrical connection with the substrate vias 201 to provide a connection between the substrate vias 201 and, for example, the high-voltage chip 141 and the second external connections 139. In one embodiment, the third redistribution layer 203 may be formed with similar materials and using similar methods as described above with respect to the first redistribution layer 107. The third redistribution layer 203 may, for example, be formed from multiple layers of conductive and dielectric materials, which may be formed using deposition and photolithographic masking and etching techniques.However, any suitable materials or formation methods may be used to form the third redistribution layer 203.

[0068] Once the third redistribution layer 203 has been formed, the high-voltage chip 141 of the third redistribution layer 203 may be connected, and the second external connections 139 may be arranged to be in electrical connection with the third redistribution layer 203. In one embodiment, the first high-voltage chip 141 and the second external electrical connections 139 may be formed as described above with reference to Fig. 1D. For example, the high-voltage chip 141 can be connected to the third redistribution layer 203, and the first external connections 129 can be arranged and reflowed.

[0069] Additionally, after or before the high voltage chip 141 and the first external connections 129 are formed or arranged, the sensor surface material 123 may be attached to the first sensor chip 104 using, for example, the intermediate layer 136. In one embodiment, the third sensor surface material 123 may be formed as described above with reference to Fig. 1B, be connected to the intermediate layer 136. For example, the intermediate layer 136 may be physically contacted with both the sensor surface material 123 and the sensor chip 104. However, any suitable method for attaching the sensor surface material 123 may be used.

[0070] Fig. 2B illustrates an attachment of the substrate 150 to the second sensor package 200. In one embodiment, the second sensor package 200 is as described above with reference to Fig. 1E, to the substrate 150. For example, the second external connections 139 are aligned with the second contact pads 153, and a reflow process is performed to electrically and physically connect the second external connections 139 to the second contact pads 153. However, any suitable method for connecting the second sensor package 200 to the substrate 150 may be used.

[0071] Additionally, during the bonding process, the high-voltage chip 141 is aligned with and inserted into the first opening 151 disposed in (or through) the substrate 150. In one embodiment, the first opening 151 is formed or arranged to receive the second high-voltage chip 141 and allows the overall height of the combined substrate 150 and the second sensor package 200 to be reduced. The overall height of the structure in this embodiment may be reduced, for example, to a second height H2 of between about 370 µm and about 1500 µm, such as about 400 µm. However, any suitable height may be used.

[0072] By forming the third redistribution layer 203 together with the substrate vias 201 as described, the substrate vias 201 and the third redistribution layer 203 can be used to output a redistribution signal from the sensor chip 104. Additionally, by incorporating the substrate 150 and the first opening 151 in the substrate 150, a flexible SMT process can be achieved with the high-voltage chip 141 in the first opening 151.

[0073] Fig. 3A-3B illustrates another embodiment in which the substrate vias 201 are formed in electrical connection with the second electrical connections 139 and the high-voltage chip 141 without the use of the third redistribution layer 203 to form a third sensor package 300. In this embodiment, instead of forming the third redistribution layer 203 on the second side 115 of the semiconductor substrate 111, third contact pads 301 are formed directly above and in physical and / or electrical connection with the substrate vias 201. In one embodiment, the third contact pads 301 may be formed using similar materials and methods as described above with respect to the contact pads 119. For example, the third contact pads 301 may be formed from aluminum using a deposition and patterning process.However, any suitable method may be used to form the third contact pads 301.

[0074] Once the third contact pads 301 are formed, a second protective layer 303 may be formed over the third contact pads 301. In one embodiment, the second protective layer 303 may be a protective material such as polybenzoxazole (PBO) or polyimide (PI), silicon oxide, silicon nitride, silicon oxynitride, benzocyclobutene (BCB), or any other suitable protective material. Depending on the material chosen, the second protective layer 303 may be formed using a method such as a spin-on process, a deposition process (e.g., chemical vapor deposition), or another suitable method, and may be formed to a thickness of between about 1 μm and 100 μm, such as about 20 μm. Once disposed, the second protective layer 303 may be patterned to expose the third contact pads 301.

[0075] Once the third contact pads 301 are formed, the sensor surface material 123 can be arranged over the sensor chip 104, the high-voltage chip 141 can be connected to the third contact pads 301, and the second external connections 139 can be arranged to be in electrical connection with the third contact pads 301. In one embodiment, the first sensor surface material 13, the high-voltage chip 141, and the second external connections 149 can be arranged as described above with reference to Fig. 1B-1D. For example, the sensor surface material 123 can be bonded to the second adhesive layer 126, the high-voltage chip 141 can be connected to the third contact pads 301, and the first external connections 129 can be arranged and reflowed.

[0076] Fig. 3B illustrates an attachment of the substrate 150 to the third sensor package 300. In one embodiment, the third sensor package 300 is as described above with reference to Fig. 1E, to the substrate 150. For example, the second external connections 139 are aligned with the second contact pads 153, and a reflow process is performed to electrically and physically connect the second external connections 139 to the second contact pads 153. However, any suitable method for connecting the third sensor package 300 to the substrate 150 may be used.

[0077] Additionally, during the bonding process, the high-voltage chip 141 is aligned with and inserted into the first opening 151 disposed in (or through) the substrate 150. In one embodiment, the first opening 151 is configured or arranged to receive the second high-voltage chip 141, allowing the overall height of the combined substrate 150 and third sensor package 300 to be reduced.

[0078] By connecting the high-voltage chip 141 directly above the substrate vias 201, the process steps used to form the third redistribution layer 203 can be avoided, enabling a simpler and less complicated manufacturing process. Additionally, by not forming the third redistribution layer 203, the overall height of the structure without the third redistribution layer 203 can be reduced. In one embodiment, the entire structure may, for example, have a third height H3 of between about 360 µm and about 1500 µm, such as about 390 µm. However, any suitable height may be used.

[0079] Fig. 4 illustrates an embodiment in which the substrate 150 and the first sensor package 149 are enclosed, for example, in a semiconductor device structure 400, with the first sensor package 140 disposed on a first side of the semiconductor device structure 400 and a display device 409 disposed on a second side opposite the first side. In one embodiment, the semiconductor device structure 400 includes a multi-chip packaging system (MCPS) 413, with the sensor chip 104 attached to the MCPS 413 by the substrate 150, with the substrate 150 connected to the MCPS 413, for example, by connectors 417, such as solder pads, although any suitable connector may be used.

[0080] In some embodiments, in addition to the MCPS 413, other electrical components 415a and 415b are also attached to the substrate 150 through the connectors 417. The electrical components 415a and 415b may be the same or different from each other. As an example, the electronic component 415a may be a semiconductor die or a semiconductor package, and the electronic component 415b may be a discrete electrical component, e.g., a passive or active device such as a capacitor, an inductor, a resistor, a transistor, a diode, or the like. Those skilled in the art will recognize that Fig. 4 is only an illustration, as different numbers of the MCPS 413 and the electrical components 415a / 415b could be used together with the sensor chip 104 without departing from the spirit of the present disclosure.

[0081] As in Fig. 4, a battery 411 is electrically connected to the substrate 150 by a cable 419, with the MCPS 413 disposed between the battery 411 and the substrate 150. In such embodiments, the cable 419 is a flexible cable, such as a flexible printed circuit (FPC) cable. The display device 409, such as an LCD display, is disposed adjacent to the battery 411, with the battery 411 disposed between the MCPS 413 and the display device 409. The display device 409 is, in some embodiments, electrically connected to the substrate 150 by a cable 421, such as an FPC cable.

[0082] Additionally, the semiconductor device structure 400 includes a package 401 according to some embodiments. In some embodiments, the semiconductor device 400 comprises a wearable device such as a smartwatch, a fitness device, or a health monitoring device.

[0083] By attaching the first sensor package 149 to the substrate 150 as described and enclosing the structure in the semiconductor device structure 400, the thickness of the individual components can be reduced, enabling a larger sized battery 411.

[0084] Fig. 5 illustrates an alternative embodiment where the size savings may not be used to include a larger battery, but may instead be used to reduce the overall size of the semiconductor structure 400. In this embodiment, the semiconductor device 400 may be reduced to have a fifth overall height H5 of between about 8 mm and about 15 mm, such as about 10 mm. However, any suitable size may be used. By reducing the size, a smaller overall structure may be achieved.

[0085] In addition, while the Fig. 4 and Fig. 5 described embodiments with reference to the above with reference to Fig. While the first sensor package 149 described in Figures 1A-1F is described, the embodiments are not limited to the first sensor package 140. Instead, any suitable sensor package, such as the second sensor package 200 or the third sensor package 300, may be used. All suitable combinations are intended to be fully encompassed within the scope of the embodiments.

[0086] According to one embodiment, a method for manufacturing a fingerprint scanner is provided, comprising attaching a sensor surface material over a sensor chip. The sensor chip includes a semiconductor substrate and an electrode array between the semiconductor substrate and the sensor surface material. A high-voltage chip is attached in electrical communication with the sensor chip, wherein the high-voltage chip is located on an opposite side of the sensor chip than the sensor surface material. The sensor chip 104 is attached to a substrate, wherein the high-voltage chip is disposed in an opening of the substrate after the sensor chip is attached to the substrate.

[0087] According to another embodiment, a method of manufacturing a fingerprint scanner is provided, the method comprising forming vias through a semiconductor substrate. An electrode array is formed over the semiconductor substrate, the electrode array being in electrical communication with active devices on a first side of the semiconductor substrate, and a sensor surface material is mounted over the first side of the semiconductor substrate. A high-voltage chip is mounted in electrical communication with the active devices, the high-voltage chip being disposed on a side of the semiconductor substrate opposite the electrode array, and the high-voltage chip being disposed in an opening located in a substrate.

[0088] According to yet another embodiment, a semiconductor device is provided that includes a sensor chip 104, which is a fingerprint sensor. Vias electrically connect a first side of the fingerprint sensor to a conductive element on a second side of the fingerprint sensor, which is opposite the first side. A high-voltage chip is in electrical connection with the vias, and a substrate is in electrical connection with the vias, with the high-voltage chip being disposed in an opening of the substrate.

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Attaching a sensor surface material (123) over a sensor chip (104), wherein the sensor chip (104) is a fingerprint sensor and comprises: - a semiconductor substrate (111); and - an electrode array (120) between the semiconductor substrate (111) and the sensor surface material (123), the electrode array (120) being used to measure the difference in capacitance between different areas of a resting finger in order to measure the fingerprint; Attaching a high-voltage chip (141) in electrical connection with the sensor chip (104), wherein the high-voltage chip (141) is configured to supply a high voltage between 5 V and 50 V to the sensor chip (104) to enhance the sensitivity of the sensor chip (104), wherein the high-voltage chip (141) is located on an opposite side of the sensor chip (104) than the sensor surface material (123); and Attaching the sensor chip (104) to a substrate (150), wherein the high-voltage chip (141) is located within an opening (151) of the substrate (150) after the sensor chip (104) has been attached to the substrate (150). [2] The method of claim 1, wherein the opening (151) of the substrate (150) extends the entire distance through the substrate (150). [3] The method of claim 1, wherein the opening (151) of the substrate (150) extends only partially through the substrate (150). [4] The method according to any one of the preceding claims, wherein the sensor chip (104) further comprises a second redistribution layer (121) located between the sensor surface material (123) and the semiconductor substrate (111). [5] The method of claim 4, further comprising: Forming vias (109) prior to attaching the sensor surface material (123); Arranging the sensor chip (104) within the vias (109); and Encapsulating the vias (109) and the sensor chip (104) after arranging the sensor chip (104). [6] A method according to any one of the preceding claims, further comprising forming contact pads in direct physical contact with substrate vias (201) located within the sensor chip (104). [7] A method of manufacturing a semiconductor device, the method comprising: Forming substrate vias (201) through a semiconductor substrate (111) of a sensor chip (104) which is a fingerprint sensor; Forming an electrode array (120) over the semiconductor substrate (111), the electrode array (120) being used to measure the difference in capacitance between different areas of a resting finger to measure the fingerprint, the electrode array (120) being in electrical communication with active devices on a first side (113) of the semiconductor substrate (111); Attaching a sensor surface material (123) over the first side (113) of the semiconductor substrate (111); Attaching a high-voltage chip (141) in electrical connection with the active devices, wherein the high-voltage chip (141) is configured to supply a high voltage between 5 V and 50 V to the sensor chip (104) in order to enhance the sensitivity of the sensor chip (104), wherein the high-voltage chip (141) is arranged on a side of the semiconductor substrate (111) opposite the electrode array (120); and Arranging the high voltage chip (141) in an opening (151) located within the substrate (150). [8] The method of claim 7, further comprising forming a third redistribution layer (203) in electrical communication with the substrate vias (201) on a second side (115) of the semiconductor substrate (111) opposite the active devices, wherein attaching the high voltage chip (141) attaches the high voltage chip (141) to the third redistribution layer (203). [9] The method of claim 8, further comprising attaching first external connections (143) to the third redistribution layer (203). [10] The method of any one of claims 7 to 9, further comprising forming contact pads in physical contact with the substrate vias (201), wherein attaching the high voltage chip (141) attaches the high voltage chip (141) to the contact pads. [11] The method of claim 10, further comprising attaching first external connections (143) to the contact pads. [12] The method of any one of claims 7 to 11, wherein the opening (151) extends from one side of the substrate (150) to a second side of the substrate (150) opposite the first side. [13] The method of any one of claims 7 to 12, wherein the opening (151) extends into the substrate (150) a distance of between about 50 µm and about 500 µm. [14] The method of any one of claims 7 to 13, wherein the substrate (150) is a printed circuit board. [15] A semiconductor device comprising: a sensor chip (104) which is a fingerprint sensor; Vias (109) connecting a first side (113) of the sensor chip (104) to a conductive element arranged on a second side (115) of the sensor chip (104) opposite the first side (113); an electrode array (120) on the first side (113) of the sensor chip (104), the electrode array (120) being used to measure the difference in capacitance between different areas of a resting finger to measure the fingerprint; a sensor surface material (123) over the first side (113) of the sensor chip (104); a high-voltage chip (141) in electrical connection with the vias (109), wherein the high-voltage chip (141) is configured to supply a high voltage between 5 V and 50 V to the sensor chip (104) in order to enhance the sensitivity of the sensor chip (104); and a substrate (150) in electrical connection with the vias (109), wherein the high voltage chip (141) is arranged in an opening (151) of the substrate (150). [16] The semiconductor device according to claim 15, wherein the conductive element is a first redistribution layer (107). [17] A semiconductor device according to claim 15, wherein the conductive element is a contact pad. [18] A semiconductor device according to any one of claims 15 to 17, wherein the vias (109) are arranged through a semiconductor substrate (111). [19] A semiconductor device according to any one of claims 15 to 18, wherein the vias (109) are arranged by an encapsulation material (125) and separated from the sensor chip (104), the encapsulation material (125) being in physical contact with the vias (109). [20] A semiconductor device according to any one of claims 15 to 19, wherein the substrate (150) is a printed circuit board.

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