Parallelization compilation methods, parallelization compilers, and electronic control devices

Abstract

Parallelization compilation procedure, which is executed by a processor (13) to generate a parallelization program for a multiprocessor system for an embedded system from a sequential program for a single-processor system for an embedded system, wherein the parallelization compilation procedure includes: a read step that reads the sequential program executed in the single-processor system from a storage medium (18), wherein the sequential program includes a condition description which is selected as to be compiled or not compiled by conditional compilation in accordance with an input information; a division step (S210) that divides the processes described in the sequential program into a multitude of macro tasks, independent of the input information; an extraction step (S220) that extracts parallelizable macro tasks based on data dependencies between macro tasks, which can be executed in parallel by a multitude of processor units that configure the multiprocessor system; and a scheduling step (S110) that assigns each of the macro tasks to any of the processor units, assigns all or some of the parallelizable macro tasks to different processor units, and performs static scheduling to generate a parallelization program executed by the multiprocessor system, wherein The scheduling step performs static scheduling according to predetermined two or more types of input information, and generates parallelization programs according to the two or more types of input information; In the scheduling step, a comparison program is generated by removing the condition description that is selected as not to be compiled in accordance with the input information from each of the parallelization programs that correspond to the types of input information and are generated in the static scheduling; the parallelization compilation process further includes: a verification step (S120) which, with respect to the static schedulings corresponding to the input information types, verifies the performance of the comparison programs generated in the scheduling step according to each of the input information types; and a selection step (S120) which, based on a verification result of the verification step, selects from the static schedules either a static schedule that makes it possible to generate a comparison program with the relatively best performance, or a static schedule that makes it possible to generate a comparison program with a predetermined performance; a generation step that specifies a description as a compilation target based on a value of an argument of a conditional compilation switch from the parallelization program and generates binary data through the selected schedule, the binary data executing a multi-core processor; and a storage step that stores the generated binary data in the storage medium, and The input information is the value of the argument of the conditional compilation switch.

Description

[0001] The invention relates to a parallelization compilation method, a parallelization compiler and an electronic control device.

[0002] Non-Patent Literature 1 discloses an on-board device with a multi-core processor. Throughput in the on-board device is improved by distributing functions to each core of the multi-core processor. A parallelization compiler generates a parallelization program from a program for a single-core processor (also referred to as a single-core processor system). The generated parallelization program is processed in parallel by a multi-core processor. Incidentally, a program for a single-core processor system is referred to as a sequential program.

[0003] Non-patent literature 1: K. Seo, J. Yoon, J. Kim, T. Chung, K. Yi and N. Chang, “Coordinated implementation and processing of a unified chassis control algorithm with multi-central processing unit,” JAUTO1346, IMechE, 2009, Vol. 224, Part D.

[0004] Furthermore, US 2014 / 0 277 590 A1 discloses state machine engines, including those with an inter-rank bus control system, that include a register. The state machine engine includes a plurality of configurable elements such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells analyze data and output an analysis result. The inter-rank bus control system can halt a write operation of data to be analyzed by the cells based at least in part on one or more conditions.

[0005] The inventors of this invention have discovered the following: A description regarding a compilation target in a sequential program can be selected by a conditional compilation switch in accordance with a target or the like. Selecting a description of a compilation by a compilation condition switch is called conditional compilation. When generating a parallelization program from a sequential program with a parallelization compiler, generally, a section to be the compilation target is specified based on the compilation condition switch from the sequential program. After the specification, the parallelization program is generated from the specified section.

[0006] However, if the section that is to be the compilation target changes, the data dependency and control dependency between macro tasks that configure the sequential program may also change. Therefore, multiple parallelization programs with different targets can be generated from the same sequential program, each of which may have the same or similar functionality. However, the process contents assigned to each processor core may differ significantly. This can cause difficulties in maintaining the quality and managing the parallelization program.

[0007] The invention aims to provide a technology that facilitates maintaining the quality and management of a parallelized program. This object is achieved by a parallelization compilation method having the features of claim 1, a parallelization compiler having the features of claim 8, and an electronic control device having the features of claim 9. The dependent claims are directed to advantageous developments of the invention.

[0008] According to the invention, the parallelization program is generated from the sequential program while including all condition descriptions. When the input information is specified, it is possible to remove the section that is not compiled from the parallelization program based on the condition description.

[0009] Therefore, when any type of input information is specified, a different process (for example, a process that is always executed regardless of the content of the input information) can always be assigned to the same processor unit as a process that conforms to the condition description. Therefore, it may be possible to further improve the similarity of parallelization programs of each type even when multiple types of parallelization programs with different objectives are generated by specifying the input information. Therefore, it may be possible to easily maintain the quality and manage the parallelization program.

[0010] The above and other objects, features, and advantages of the invention will become more apparent from the following detailed description with reference to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating a configuration of a personal computer on which an automatic parallelization compiler is installed; Fig. 2 a flowchart illustrating an automatic parallelization process; Fig. 3 a flowchart illustrating a software structure analysis process; Fig. 4 is a block diagram showing a configuration of an on-board device; Fig. 5 is a diagram illustrating a sequential program, assignment information, and a comparison program in a first specific example; Fig. 6 is a diagram illustrating a process time or the like of a process described in the sequential program in the first specific example; Fig. 7 is a diagram illustrating a verification result of a performance of the comparison program generated in the first specific example; Fig. 8 is a diagram illustrating a sequential program and a macrotask graph in a second specific example; Fig. 9 is a diagram illustrating the macro task graph and assignment information in the second specific example; Fig. 10 is a diagram illustrating a process time of a process described in the sequential program in the second specific example; Fig. 11 is a diagram illustrating a parallel execution time of the comparison program generated in the second specific example; Fig. 12 is a diagram illustrating a verification result of a performance of a comparison program generated in a third specific example; Fig. 13 is a diagram illustrating a sequential program in a fourth specific example; Fig. 14 is a diagram illustrating an argument or the like of a compilation condition switch in the fourth specific example; Fig. 15 is a diagram illustrating arguments of the compile condition switch corresponding to each type in the fourth specific example; Fig. 16 is a diagram illustrating a comparison program generated in the fourth specific example; and Fig. 17 is a diagram illustrating a parallelization program in the fourth specific example.

[0011] An embodiment of the invention will be described below with reference to the drawings. It should be noted that the invention is not limited to the following embodiment, and that the invention includes various modifications within the technical scope of the invention. (Exemplary Example)(1. Automatic Parallelization Compiler)

[0012] An automatic parallelization compiler of the present embodiment generates a parallelization program for a multiprocessor system for an embedded system from a source program for a single-processor system for an embedded system. The source program for the single-processor system is referred to as a sequential program. (1-1. Design concept of the automatic parallelization compiler)

[0013] The automatic parallelization compiler of the present embodiment has the following functions: (Function 1) A multi-grain parallel process; (Function 2) Insertion of static planning code at compile time; (Function 3) Generation of dynamic planning code at execution time; (Function 4) Implementation of a hierarchical macro data flow; (Function 5) A parallelism extraction such as a division and / or merger of a macro task, and a loop distribution and / or loop exchange; (Function 6) Improving data transmission efficiency through data localization; and (Function 7) Reducing the power consumption of a compiler. (1-2. Internal process of the automatic parallelization compiler)

[0014] The automatic parallelization compiler has three stages, including a front-end (hereinafter referred to as an FE), a middle-path (hereinafter referred to as an MP), and a back-end (hereinafter referred to as a BE). Each stage is independent as an implementation. Code exchange is performed using an intermediate language generated from the FE and the MP.

[0015] The FE performs a lexical analysis and a syntax analysis of the source code for the sequential program. The FE generates the intermediate language, which enables parsing in the MP and parsing in the MP. The intermediate language generated by the FE is expressed by a syntax tree that basically has four operands. The intermediate language generated by the FE provides a single block as a whole in an unstructured manner.

[0016] The MP performs control dependency analysis, data dependency analysis, and optimization. The MP performs a multi-grain parallel process of coarse-grain parallelization, medium-grain parallelization, and near-fine-grain parallelization using the data from the control dependency analysis, data dependency analysis, and optimization.

[0017] The BE reads the parallelization intermediate language generated by the MP to generate actual machine code. The BE includes a backend that generates assembly code for the target multi-core architecture and another backend that generates parallelization Fortran code and parallelization C code for OpenMP.

[0018] Furthermore, the BE includes another backend that outputs code according to different architectures, such as a backend that generates parallelization code including a memory arrangement and data transfer via a parallelization API. (1-3. Parallelism analysis of the automatic parallelization compiler)

[0019] The automatic parallelization compiler performs a macro dataflow process to divide a sequential program into three types of coarse-grained tasks, including a basic block (also called a BB), a repetition block (also called an RB), and a subroutine block (also called an SB). These three types of coarse-grained tasks are called macrotasks (MT).

[0020] Depending on a form of a program, the macro data flow process cannot improve the utilization efficiency of a processor, and cannot extract sufficient coarse-grain parallelism.

[0021] In the automatic parallelization compiler, a conventional single-hierarchy macro dataflow process technique can be extended to apply the hierarchical macro dataflow process. The hierarchical macro dataflow process uses a hierarchical macro dataflow process for the inside of a macro task. In the hierarchical macro dataflow process, macro tasks are defined hierarchically, and parallelism between the macro tasks is analyzed for the macro task in each hierarchy. (Creating a macroflow graph)

[0022] The automatic parallelization compiler analyzes the control dependencies and data dependencies between macro tasks for a generated macro task in each hierarchy. The analysis result is expressed as a macroflow graph (MFG). (Generation of a macro task graph)

[0023] The MFG represents the control dependency and data dependency between macro tasks. However, the MFG does not represent parallelism between macro tasks. To extract parallelism, it is necessary to perform an earliest executable condition analysis for each macro task. The earliest executable condition analysis considers the control dependency and data dependency. Incidentally, the earliest executable condition is a condition under which an MT becomes executable at the earliest possible time, and the condition is determined from the following execution conditions.

[0024] (Execution Condition 1) If an MTi has a data dependency on an MTj, the MTi is not executed until an execution of the MTj is completed.

[0025] (Execution condition 2) If a conditional branch target of the MTj is fixed, the MTi that has a data dependency on the MTj becomes executable even if an execution of the MTj is not finished.

[0026] Therefore, a general form of the earliest executable condition is as follows:

[0027] (The MTj with the control dependency with or from the MTi branches to the MTi) AND ((an MTk with the data dependency to the MTi ( (0 ≤ k ≤ |N|) ends) OR (it is determined that the MTk is not executed).

[0028] A macrotask graph (MTG) expresses the earliest executable conditions of the macrotask. (1-4. Multi-grain parallel process)

[0029] In addition to conventional loop parallelization, the automatic parallelization compiler implements multi-grain parallel processing, effectively combining coarse-grain task parallel processing and near-fine-grain parallel processing (see also Reference 1). Coarse-grain task parallel processing utilizes parallelism between coarse-grain tasks in loops and subroutines. Near-fine-grain parallel processing utilizes parallelism between statements.

[0030] Reference 1: Hiroki Honda, Masahiko Iwata and Hironori Kasahara, “Coarse grain parallelism detection scheme of a Fortran program” Transactions of IEICE DI. Vol. J73-DI No. 12, pp. 951-960, 1990. (Coarse grain feed parallel process)

[0031] The automatic parallelization compiler generates the macroflow graph (MFG), which expresses the control dependence and data dependence between the MTs, such as the BB, the RB, and the SB. Furthermore, the automatic parallelization compiler expresses the parallelism between the MTs derived from the MFG as the macrotask graph (MTG) through the earliest-executable condition analysis (see also Reference 1 and Reference 2).

[0032] Reference 2: Hironori Kasahara, Kento Aida, Akimasa Yoshida, Masami Okamoto and Hiroki Honda “A macro-task generation scheme for Fortran macro-dataflow computation,” Transactions of IEICE DI. Vol. J75-DI, No. 8, pp. 511-525, 1992.

[0033] One or more processor elements (PEs) have been grouped into a processor group (PG). The automatic parallelization compiler assigns the MTs of the MTG to PGs. (Medium grain parallel process)

[0034] When the MT assigned to the PG is processed in parallel at a DOALL loop or iteration level, the processor in a processor cluster executes mid-grain parallel processing. Mid-grain parallel processing represents a parallel process using parallelism between DO loop iterations. Mid-grain parallel processing is the most general type of parallel processing in a multiprocessor. (Almost fine-grain parallel process)

[0035] Near-fine-grain parallel processing represents the parallel processing of a near-fine-grained task at the expression or statement level. Near-fine-grain parallel processing enables parallel execution within an expression or statement that has no dependencies, thereby reducing execution time. (1-5. Macro task planning)

[0036] In the coarse-grained task parallel process, a macrotask generated in each hierarchy is assigned to the PG and executed. Scheduling techniques that determine which PG a macrotask is assigned to include dynamic scheduling and static scheduling. The scheduling technique is selected based on the shape of the macrotask graph and the nondeterminism or uncertainty regarding the execution time of the macrotask graph. (Dynamic Planning)

[0037] If an indeterminacy exists at execution time, such as a conditional branch, a macrotask is assigned to the PG at execution time through dynamic scheduling. According to the completion of the macrotask and / or the determination of a branch direction of the macrotask, a dynamic scheduling routine operates on a macrotask execution control table and examines the earliest-executable condition of each macrotask.

[0038] If the macro task is executable, it is placed in a ready queue. The macro tasks in the ready queue are sorted according to a priority. The macro task positioned at the front of the ready queue is assigned to a processor cluster that is in an idle state.

[0039] When generating dynamic scheduling code, a concentrated scheduling system or a distributed scheduling system can be used, depending on the number of processors and synchronous overhead of a system. In the concentrated scheduling system, a single, exclusively used processor performs scheduling. In the distributed scheduling system, the scheduling function is distributed among each processor. (Static planning)

[0040] Static scheduling is used when the macro task graph has only one data dependency boundary. In static scheduling, the automatic parallelization compiler determines the assignment of the macro task to the PG at compile time.

[0041] Since static scheduling allows to eliminate scheduling overhead at execution time and allows to minimize data transfer and synchronization overhead, static scheduling can be effectively used with respect to a task with a fine grain size.

[0042] At the time of executing static scheduling, static scheduling uses a task cost estimate in the automatic parallelization compiler regarding the cost of a task. Alternatively, the actual costs of a task (also referred to as real costs) can be estimated using an automatic case analysis or profile feedback function of the automatic parallelization compiler.

[0043] When the automatic profile feedback function is used, a sequential program is decomposed into macrotasks (MTs) in a first phase. A profiling function, or profiler function, is inserted into each MT, and a sequential program with the profiling function is generated. The profiling function measures the cost of one task execution (one clock cycle) and the total number of task executions. When the sequential program, into which the profiling function is inserted, is executed once on a target machine, a file containing information about the task execution cost and the total number of output executions on the target machine is output.

[0044] In a second phase, the automatic parallelization compiler receives the output file from the first phase and the sequential program. The automatic parallelization compiler generates a parallelization program in which scheduling is performed based on actual costs. (1-6. Data localization)

[0045] The automatic parallelization compiler enables cache optimization across the entire program. The automatic parallelization compiler analyzes the parallelism between loops. After this analysis, if the automatic parallelization compiler detects that a data dependency exists between the loops, the automatic parallelization compiler attempts to perform a global cache optimization between the loops with the data dependency (see also Reference 3: JP Patent No. 4177681).

[0046] Specifically, the automatic parallelization compiler examines an array accessed in each loop, adjusts so that identical split loops access the same portion of the array, and assigns the identical split loops to the same processor. Accordingly, all array data is reused in a buffer in identical split loops.

[0047] This localization technology relates to the following local storage management technology and the consequences of data transmission technology (see also Reference 5: UK Patent No. 2478874). More specifically, the localization technology has the following features.

[0048] (Feature 1) Given a local memory or a distributed shared memory with an arbitrary size, before accessing the local memory or distributed shared memory using DMA (DTU) (see also Reference 4: JP Patent No. 4476267), data is preloaded into a local memory or distributed shared memory located close to the processor and reused across a program. DMA represents direct memory access, and DTU represents a data transfer unit.

[0049] (Feature 2) When a receiver memory is full, and when a source processor is notified by a synchronous flag representing a DTU of a receiver processor that the source processor has swapped out data to a shared memory or the like based on a swap priority, the source processor automatically transfers data to the receiver memory.

[0050] (Feature 3) When data that will be reused in the future and not used for a while is stored in a memory area, and when it is necessary to release the memory area, the DTU moves the data to a concentrated shared memory behind a task execution by a CPU, and reloads before the time of use. (1-7. Generation of the parallelization program)

[0051] A parallelization program in the automatic parallelization compiler is generated by an automatic parallelization interface or automatic parallelization API in a source-to-source parallelization manner such as C parallelization or FORTRAN parallelization (see also Reference 7: “Optimally Scheduled Advanced Multiprocessor Application Program Interface”, WASEDA University, 2008).

[0052] In this case, the automatic parallelization compiler converts a directive section of C or Fortran into a runtime library call for each processor using a standard automatic parallelization API translator, so that the parallelization program is executable on different platforms.

[0053] After converting the code to a runtime library call, the automatic parallelization compiler compiles code for each processor using a sequential compiler to generate a binary file (with reference to a binary code). The binary files are linked together. A parallelization program is executable on a target multiprocessor. (2. Parallelization step and method of a sequential program for an embedded system)

[0054] A feature of a sequential program for an embedded system will be described below. A parallelization method in accordance with the automatic parallelization compiler according to the invention will be explained. Incidentally, the embedded system may be, for example, an on-board device, and may be any electronic device other than the on-board device. The sequential program may be a program automatically generated by model-based design, and may be a program automatically generated by, for example, Matlab (registered trademark) or Simulink (registered trademark) produced by MathWork. The on-board device refers to a device mounted on a vehicle.

[0055] The automatic parallelization compiler is configured from a conditional branch and an assignment expression. The automatic parallelization compiler performs inline expansion and renaming to a sequential program with a fine-grained process to extract parallelism. The automatic parallelization compiler performs task merging to hide a conditional branch to maintain a real-time nature. The automatic parallelization compiler performs static scheduling to reduce overhead. In addition, the automatic parallelization compiler can use the automatic profile feedback function to perform static scheduling at actual cost.

[0056] Conditional compilation may be performed for the sequential program. In conditional compilation, a description is selected in favor of a compilation target in accordance with an embedded system type through a conditional compilation switch (also called a preprocessor instruction). Incidentally, each embedded system type may have different targets, different functions, and different hardware configurations. In a case where selection is performed, information (information representing a target, etc.) corresponding to any embedded system type is specified as an argument of each compilation condition switch of the sequential program, so that binary code corresponding to the embedded system type is generated from the sequential program.

[0057] In contrast, the automatic parallelization compiler of the present embodiment discards the selection of the compilation target by conditional compilation. The automatic parallelization compiler performs macro task division, parallelism extraction, and static scheduling for all sections of the sequential program. The automatic parallelization compiler generates a parallelization program. After generating the parallelization program, the automatic parallelization compiler specifies a description from the parallelization program that is not a compilation target through conditional compilation. After removing the description that is not the compilation target, binary data for operating a multi-core processor is generated. (2-1. Operating environment of the automatic parallelization compiler)

[0058] The automatic parallelization compiler 1 is provided to a user in a state stored in a storage medium 18 configured as an optical disk, a magnetic disk, a semiconductor memory such as a DVD, a CD-ROM, a USB memory, or a memory card. The automatic parallelization compiler 1 can be provided to the user via a network.

[0059] A personal computer (PC) 10, on which the automatic parallelization compiler 1 is installed, functions as an automatic parallelization compilation device. The personal computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, and a reading section 17.

[0060] The display 11 displays a video image of a video signal received from the CPU 13 to a user.

[0061] The input device 16 includes a keyboard and a mouse. When the user operates the input device 16, the input device 16 outputs a signal corresponding to the operation to the CPU 13.

[0062] The reading section 17 reads data from the storage medium 18 where the automatic parallelization compiler 1 has been stored.

[0063] The RAM 15 is a readable and writable volatile memory. The ROM 14 is a non-volatile read-only memory. A program is pre-stored in the ROM 14 and on the HDD 12. The CPU 13 reads and executes the program.

[0064] When the CPU 13 executes the program stored in the ROM 14 or on the HDD 12, the RAM 15 functions as a storage area for temporarily storing a program and working data.

[0065] The CPU 13 reads an operating system (OS or BS) from the HDD 12 and executes it. The CPU 13 executes various programs stored on the HDD 12 as a process within the operating system. During this process, the CPU 13 receives a signal input from the input device 16 as needed. The CPU 13 outputs the video signal to the display 11. The CPU 13 controls the reading and writing of data to the RAM 15 or the HDD 12.

[0066] The personal computer 10 is installed with the automatic parallelization compiler 1, which is read from the storage medium 18 via the reading section 17. The automatic parallelization compiler 1 is one of the applications stored on the HDD 12 and executed as a process in the operating system.

[0067] The automatic parallelization compiler is used for developing the parallelization program for the embedded system for an on-board device. However, the automatic parallelization compiler is not limited to this type of development of the parallelization program for the embedded system for an on-board device. For example, the automatic parallelization compiler according to the invention can be used for developing various parallelization programs for an embedded system for various applications, such as an information application, and can be used for developing a parallelization program for applications other than embedded systems. (2-2. Automatic parallelization process)

[0068] The automatic parallelization process that generates the parallelization program based on the sequential program for which the conditional compilation is performed is described below with reference to a flowchart of Fig. 2. Incidentally, conditional compilation generates binary data mounted on an embedded system from the sequential program. This type of embedded system corresponds to the value of an argument referenced by the compilation condition switch. The automatic parallelization compiler 1 operating in the personal computer 10 begins the process in accordance with a user instruction.

[0069] In S100, the automatic parallelization compiler 1 specifies a condition description in the sequential program based on the compilation condition switch described in the sequential program and separates the condition description into one or more condition blocks. Incidentally, the description condition selects whether or not to perform compilation through conditional compilation. Each of the condition blocks is separated into a macro task (also referred to as a conditional macro task). Incidentally, S100 may be described as performing compilation switch analysis.

[0070] The condition block can be a series of descriptions that are collectively selected by a set of compilation condition switches in accordance with the value of the argument as to whether or not they are a compilation target. The condition block can be any of several series of descriptions that are to be the selection target. Incidentally, a specific example of specifying the condition block is described in a fourth specific example.

[0071] In S105, the automatic parallelization compiler 1 performs a software structure analysis process (see also Fig. 3) and generates an MTG. The automatic parallelization compiler 1 selects one of the embedded system types operated by the sequential program, and the process proceeds to S110. Incidentally, one of the embedded system types corresponds to a value of the argument of a compilation condition switch corresponding to any of the embedded system types.

[0072] In S110, the automatic parallelization compiler 1 performs static scheduling according to the currently selected type based on the MTG generated by the software structure analysis process. Accordingly, macro tasks that can be executed in parallel are assigned to different PGs. The macro tasks that can be executed in parallel can be referred to as parallelizable macro tasks. A parallelization program (hereinafter also referred to as a comparison program) is generated. Assignment information indicates a result of the assignment. In this case, a comparison program is generated according to each type of embedded system. That is, the static scheduling corresponding to a single type of embedded system generates multiple comparison programs having the same content according to each of the types.Hereinafter, a type corresponding to a comparison program is referred to as a final type.

[0073] Incidentally, a compilation condition switch is specified in the comparison program for the description corresponding to each of the conditional macro tasks. The compilation condition switch of the comparison program has the same content as a compilation condition switch specified in the condition description corresponding to the description in the sequential program. Therefore, if the argument of the compilation condition switch of the comparison program is set to a value corresponding to any of the types, the comparison program becomes a parallelization program corresponding to the selected type.

[0074] In static scheduling, the automatic parallelization compiler 1 can specify the actual cost (e.g., a process time) at the time of executing each macro task with an automatic profile feedback function. Furthermore, the automatic parallelization compiler 1 can assign the macro tasks that can be executed in parallel to each PG so that process loads on the PGs are almost equal. Furthermore, the automatic parallelization compiler 1 can specify a macro task that should not be a compilation target in the selected type based on the compilation condition switch, and can perform static scheduling considering that there is no process load of the macro task.

[0075] The automatic parallelization compiler 1 can convert the parallelization program to which an automatic parallelization API is added into another parallelization program in which a runtime library is implemented. Therefore, the parallelization program can be run on different platforms.

[0076] In S115, the automatic parallelization compiler 1 determines whether static scheduling has been performed for all types of embedded systems operated by the sequential program. If a positive determination is made (S115: YES), the process proceeds to S120. If a negative determination is made (S115: NO), another type in which static scheduling has not been performed is selected, and the process proceeds to S110.

[0077] In S120, the automatic parallelization compiler 1 verifies the performance of all comparison programs generated in S110 to S115 and selects an appropriate static schedule based on the verification result. The process proceeds to S125. In this case, a static schedule that enables the generation of a comparison program with the relatively best performance can be selected. Alternatively, a static schedule that enables the generation of a comparison program with a predetermined performance can be selected.

[0078] In S125, the automatic parallelization compiler 1 determines whether the static scheduling is successfully selected. Specifically, for example, if exactly one static scheduling that enables generation of a comparison program with the relatively best performance is obtained, it can be considered that the selection is successful. If two or more static schedulings that enable generation of comparison programs with the relatively best performance are obtained, it can be considered that the selection fails. Alternatively, if the static scheduling with a predetermined performance exists, it can be considered that the selection is successful. If the static scheduling with the predetermined performance does not exist, it can be considered that the selection fails.If a positive determination is obtained (S125: YES), a type of embedded system operated by the sequential program is selected, and the process proceeds to S130. If a negative determination is obtained (S125: NO), the process proceeds to S145.

[0079] A comparison program selected by static scheduling and corresponding to the selected type of the embedded system is called a selection program. In S130, the automatic parallelization compiler 1 analyzes a compilation switch described in the selection program and performs preprocessing. In the preprocessing, the automatic parallelization compiler 1 executes a process according to the analysis result of the compilation switch. Based on the compilation condition switch, the automatic parallelization compiler 1 specifies a description that is not or will not be compiled in the selected type from the selection program. The process proceeds to S135.

[0080] In S135, the automatic parallelization compiler 1 generates binary data for causing the multi-core processor to operate based on the description compiled in the selection program. The process proceeds to S140.

[0081] In S140, the automatic parallelization compiler 1 determines whether binary data corresponding to all types of embedded systems has been generated. If a positive determination is made (S140: YES), the process ends. If a negative determination is made (S140: NO), another type for which binary data has not been generated is selected, and the process proceeds to S130.

[0082] In S145, the automatic parallelization compiler 1 notifies via a display 11 or the like that it cannot select static scheduling. In this case, the automatic parallelization compiler 1 may cause the display 11 or the like to display, for example, a parallel execution time of each comparison program, a reduction ratio of each comparison program, a maximum parallel execution time of comparison programs generated by static scheduling, and a minimum reduction ratio of comparison programs as a verification result of the performance of comparison programs. Then, the automatic parallelization compiler 1 terminates the process. It may be described that S145 notifies of a verification result. (2-3. Software structure analysis process)

[0083] The software structure analysis process that generates the MTG from the sequential program is described with reference to the flowchart of Fig. 3. This process is performed in the automatic parallelization process.

[0084] In S200, the automatic parallelization compiler 1 performs inline expansion for the sequential program, and the process proceeds to S205. In inline expansion, a description that calls a subroutine is replaced or substituted with a description of a process defined by the subroutine. The sequential program for the embedded system generally has a fine-grained process. It may be difficult to perform parallelization to a coarse degree or coarse gradation. By performing inline expansion, it may be possible to effectively utilize parallelism in the subroutine.

[0085] In step S205, the automatic parallelization compiler 1 renames a local variable. For example, in a sequential program automatically generated from a Simulink model, the same local variable may be used repeatedly in many places to reduce ROM usage. In this case, it may be determined that data dependency exists during parallelization analysis, and it may be difficult to adequately resolve the parallelism. Therefore, in step S205, the repeatedly used local variable is renamed.

[0086] Specifically, the automatic parallelization compiler 1 specifies multiple process blocks in which a local variable with the same name is used in each function of the sequential program. The automatic parallelization compiler 1 modifies the sequential program so that a local variable with a unique name is used in each of the specified process blocks.

[0087] Incidentally, the process block can be an aggregation including the branching process statement, such as a loop process, an if statement, and a switch case statement, and an assignment statement related to the statement. The process block can, for example, be an aggregation of descriptions corresponding to each block in the Simulink model that generates the sequential program.

[0088] In S210, the automatic parallelization compiler 1 divides the sequential program for which the above process is performed into macro tasks. Incidentally, each conditional block is divided into at least one macro task (referred to as a conditional macro task). The automatic parallelization compiler 1 analyzes the data dependency and control dependency between the macro tasks and generates the MFG. The process proceeds to S215.

[0089] In S215, the automatic parallelization compiler 1 specifies a start-end task and a termination-end task based on the control dependency specified by the MFG. The start-end task branches to a different macro task. The termination-end task is the first macro task among macro tasks that are commonly executed sequentially in multiple sequential processes. The multiple sequential processes have a common start-end task as a starting point and are executed in parallel.

[0090] The automatic parallelization compiler 1 merges (i) the specified start-end task, (ii) the specified end-end task included in a process with the specified start-end task as the starting point, and (iii) all macrotasks executed after execution of the start-end task and before execution of the end-end task into a single macrotask. The process proceeds to S220. This process can be referred to as task merging.

[0091] Regarding the completion end task, in order to break down a granularity of a macro task, it may be preferable that the completion end task be the first macro task executed among the macro tasks that are collectively executed in a plurality of sequential processes as described in S215. The plurality of sequential processes have the common initial end task as the starting point and are executed in parallel. However, a manner for specifying the completion end task is not limited to this manner. Any of the macro tasks that are executed in the second and subsequent order among the plurality of macro tasks can be specified as the completion end task.

[0092] Consider applying near-fine parallelization or coarse task parallelization to the sequential program for an embedded system (especially for an on-board device), since the sequential program for an embedded system does not traverse as many loop structures. To reduce execution overhead, the automatic parallelization compiler 1 uses coarse task parallelization.

[0093] In a sequential program, the cost of each macro task can be several tens of cycles. However, when the automatic parallelization compiler 1 performs dynamic scheduling, an overhead of several tens to several hundred cycles generally occurs. Therefore, dynamic scheduling may not be suitable for a sequential program.

[0094] In a case where a macro task has a conditional branch, a branch target is determined dynamically at execution time. Static scheduling, which allocates the processor core at compile time, cannot be used for macro tasks with conditional branching.

[0095] According to the invention, the automatic parallelization compiler 1 executes a task merging algorithm, so that a section from a macro task with a conditional branch to a macro task after the branch is merged into a single coarse task (referred to as a block task). By performing task merging, the MFG loses control dependency, and static scheduling can be used.

[0096] In S220, the automatic parallelization compiler 1 analyzes the earliest executable condition of each macro task based on the MFG that the task merging is performed, and generates the MTG and terminates the process. (3. Configuration of the on-board device)

[0097] A configuration of an on-board device 20 will be described with reference to Fig. 4. The on-board device 20 operates based on the parallelization program generated by the automatic parallelization compiler 1 of the present embodiment. Note that the automatic parallelization compiler 1 makes it possible to generate a parallelization program that causes various electronic devices with a configuration similar to that of the on-board device 20 to operate.

[0098] The on-board device 20 includes a multi-core processor 21, a communication section 22, a sensor 23, and an input and output port 24.

[0099] The multi-core processor 21 includes a ROM 21a, a RAM 21b and several PEs 21c, 21d.

[0100] The ROM 21a stores a parallelization program 21a-1 (for example, binary data) generated by the automatic parallelization compiler 1. The multi-core processor 21 operates in accordance with the parallelization program 21a-1 and integrally controls the on-board device 20.

[0101] The RAM 21b is accessed by the PEs 21c, 21d.

[0102] The communication section 22 communicates with another ECU connected via an in-vehicle LAN.

[0103] The sensor 23 includes various sensors for detecting a status of a control target.

[0104] The input and output port 24 sends and receives various signals that control a control target. (Specific example)

[0105] Hereinafter, a specific example of a process in which a parallelization program is generated by the automatic parallelization compiler 1 of the present embodiment will be explained. Hereinafter, a description such as "process A" or the like represents a description of a series of processes including various calculations, a substitution, a branch process, and a function call. (1. First specific example)

[0106] In a first specific example, comparison programs are generated based on a sequential program 300 in which a conditional compilation is performed according to two types (a specification A and a specification B) of embedded systems and a performance of each of the comparison programs is verified (see also Fig. 5). Incidentally, Specification A and Specification B may also be referred to as "Spec A" and "Spec B" in the drawing, respectively.

[0107] Incidentally, in the first specific example, a parallelization program executed by a multi-core processor with two PEs (a first core and a second core) is generated.

[0108] Furthermore, in the sequential program 301, a "process C1" and a "process C2" correspond to a condition description. A compilation condition switch 301 selects one of the "process C1" and the "process C2" as a compilation target. Specifically, in a case of specification A ("CSW = A"), the process C1 is selected as the compilation target. In a case of specification B ("CSW ≠ A"), the process C2 is selected as the compilation target (referring to Fig. 5 and Fig. 6)

[0109] The automatic parallelization compiler 1 specifies each of the process C1 and the process C2 in the sequential program 300 as a condition block in S100 of the automatic parallelization process. Incidentally, "the process C1 and the process C2" may be specified as a condition block.

[0110] In S105 (a software structure analysis process), the automatic parallelization compiler 1 designates each of “the process A, the process B, the process C1, and the process C2” as the macro task and generates the MTG.

[0111] In the process from S110 to S115, the automatic parallelization compiler 1 performs the static scheduling A according to the specification A and the static scheduling B according to the specification B based on the sequential program 300.

[0112] Assignment information 310 in Fig. 5 represents assignment information generated by static scheduling A. Assignment information 311 represents assignment information generated by static scheduling B.

[0113] "Process A," "process B," "process C1," and "process C2" in allocation information 310 and allocation information 311 indicate macro tasks corresponding to each process in the sequential program. For example, in each of the static schedulings, a process time of each process is considered as a process load of each process. Furthermore, in static scheduling A, it is considered that there is no process load of "process C2." In static scheduling B, it is considered that there is no process load of "process C1."

[0114] According to the above static scheduling, four comparison programs AA, AB, BA, and BB are generated. The comparison programs AA and AB are generated by static scheduling A. The final type of the comparison program AA is specification A. The final type of the comparison program AB is specification B. The comparison programs BA and BB are generated by static scheduling B. The final type of the comparison program BA is specification A. The final type of the comparison program BB is specification B.

[0115] A comparison program 320 in Fig. 5 represents the comparison programs AA, AB. A comparison program 322 represents the comparison programs BA, BB. If a value "CSW," which is the argument of the compilation condition switches 321, 323 in the comparison programs 320, 322, is specified, one of the comparison programs AA, AB, BA, BB is generated.

[0116] In S120, the automatic parallelization compiler 1 verifies the performance of the comparison programs AA, AB, BA, BB generated in S110 to S115. Based on the verification result, the automatic parallelization compiler 1 selects the optimal static scheduling. In this case, the automatic parallelization compiler 1 calculates the parallel execution time and the reduction ratio of each of the comparison programs AA, AB, BA, BB. Verification is performed based on the parallelization times and the reduction ratio.

[0117] The parallel execution time refers to the maximum value of the sum of the processing times of the macro tasks assigned to each core (PG) in a comparison program. Incidentally, when the sum is calculated, the processing time of a macro task that is not or will not be compiled in a final type according to the comparison program is zero. Incidentally, a macro task that is not or will not be compiled can also be referred to as a macro task that cannot be compiled or as a macro task that is not a compilation target.

[0118] The reduction ratio is an estimation result of the difference between the performance of a multi-core processor running the comparison program and a single-core processor running a sequential program of the same type as the comparison program. The reduction ratio is calculated as the ratio of the parallel execution time of the comparison program to the sum (also referred to as the total process time) of each process executed by a single-core processor running the sequential program in which conditional compilation according to a final type has been performed in accordance with the comparison program. The reduction ratio is calculated as (1 - "the parallel execution time of a comparison program" / "the total process time") × 100.

[0119] Fig. 6 shows the process times “of the processes A, B, C1, C2”. Fig. Figure 7 shows the parallel execution time and reduction ratio calculated for the comparison programs AA, AB, BA, and BB. Incidentally, the total processing time of the sequential program of specification A is 240 µs (microseconds). The total processing time of the sequential program of specification B is 190 µs.

[0120] The maximum value (also referred to as maximum parallel execution time) of the parallel execution time in the comparison programs AA, AB generated by static scheduling A is 120 µs. The minimum value (also referred to as minimum reduction ratio) of the reduction ratio is 37%. In contrast, the maximum parallel execution time of the comparison programs BA, BB generated by static scheduling B is 140 µs. The minimum reduction ratios of the comparison programs BA, BB are 42%.

[0121] Therefore, when the optimal static scheduling is selected based on the parallel execution time, the maximum parallel execution time of static scheduling A is relatively smaller than that of static scheduling B. The maximum parallel execution time (120 µs in this example) of static scheduling A is smaller than the maximum parallel execution time (140 µs in this example) of static scheduling B. Therefore, it is determined that a comparison program generated by static scheduling A has relatively better performance, so static scheduling A is selected.

[0122] In contrast, when the optimal static scheduling is selected based on the reduction ratio, the minimum reduction ratio of static scheduling B is relatively larger than the minimum reduction ratio of static scheduling A. Therefore, it is determined that a comparison program generated by static scheduling B has relatively better performance, so static scheduling B is selected.

[0123] Incidentally, if static scheduling is generally selected based on the maximum parallel execution time, and if the maximum parallel execution times of the static schedules are equal to each other (or substantially equal to each other), static scheduling can be selected based on the minimum reduction ratio. Conversely, if static scheduling is generally selected based on the minimum reduction ratio, and if the minimum reduction ratios of the static schedules are equal to each other (or substantially equal to each other), static scheduling can be selected based on the maximum parallel execution time.

[0124] Similarly, if there are three or more types of specifications, static scheduling can be selected based on the maximum parallel execution time and / or the minimum reduction ratio. (2. Second specific example)

[0125] In the second specific example, the comparison program is generated based on a sequential program 400 in which conditional compilation is performed according to the two types (specification A and specification B) of embedded systems. The performance of each comparison program is verified (see also Fig. 8).

[0126] In the second specific example, a parallelization program is generated that runs on a multi-core processor with two PEs (a first core and a second core). Each macro task is assigned to either the first core or the second core.

[0127] Furthermore, in the sequential program 400, "processes D1, D2, F, G" correspond to condition descriptions. Compilation condition switches 401, 402, 403 select a part of the above condition descriptions as a compilation target. Specifically, in a case of specification A ("CSW = A"), "the processes D1, F" are selected. In a case of specification B ("CSW ≠ A"), "the processes D2, G" are selected (referring to Fig. 8 and Fig. 10).

[0128] In S100 of the automatic parallelization process, the automatic parallelization compiler 1 specifies “the processes D1, D2, F, G” in the sequential program 400 as conditional blocks.

[0129] Incidentally, a single condition block may include "the processes D1, D2" that are collectively selected as to whether or not they should be a compilation target in accordance with a value of an argument by a statement of the compilation condition switch 401. A single condition block may include "the processes F, G" that are collectively selected as to whether or not they should be compilation targets in accordance with values ​​of arguments by the two statements of the compilation condition switches 402, 403.

[0130] In S105 (the software structure analysis process), the automatic parallelization compiler 1 identifies each of the processes A to I (A, B, C, D1, D2, F, G, H, I) as a macro task and generates the MTG. The MTG 410 in Fig. 8 is generated based on a sequential program 400. Incidentally, in the automatic parallelization process, parallelization is extracted for all processes described in the sequential program 400 regardless of a compilation condition switch. Therefore, a data dependency of all macro tasks to be compiled in each type is expressed in the MTG 410.

[0131] In a section from S110 to S115, the automatic parallelization compiler 1 executes static scheduling A and static scheduling B based on the sequential program 400. Static scheduling A conforms to specification A. Static scheduling B conforms to specification B. These static schedulings are performed based on a process load of each macro task. The process load can be expressed, for example, as a process time.

[0132] An MTG 411 in Fig. Figure 9 is an MTG based on the sequential program 400. In the MTG 411, a macro task to be compiled with specification A is shown by a solid line, and a non-compiled macro task is shown by a dotted line. The processes A, B, C, D1, F, H, and I are compilation targets, so they are shown by solid lines. The processes G and D2 are not compilation targets, so they are shown by dotted lines. The MTG 412 in Fig. 9 is an MTG based on the sequential program 400. In the MTG 412, a macro task to be compiled with specification B is shown by a solid line, and an uncompiled macro task is shown by a dotted line. Therefore, in the MTG 412, processes A, B, C, G, D2, H, and I are compilation targets. Processes D1 and F are not compilation targets.

[0133] In static scheduling A, it is considered that there is no process load of the macro task shown by the dotted line in MTG 411. Similarly, in static scheduling B, it is considered that there is no process load of the macro task shown by the dotted line in MTG 412.

[0134] In these static schedules (i.e., static schedule A and static schedule B), a group of several macrotasks connected by a data dependency is specified. Specifically, a group of "processes A, B, D2, I," a group of "processes A, B, D1, I," a group of "processes A, C, F, I," a group of "processes A, G, H, I," and a group of "processes A, H, I" are specified.

[0135] The automatic parallelization compiler 1 calculates the sum of the processing times of the macrotasks belonging to each group. A macrotask configuring a group with the largest sum of processing times is assigned to the first core. Furthermore, another macrotask is assigned to the first core or the second core in such a way that the maximum processing time (a maximum value of the sum of the processing times of the macrotasks assigned to each core) is minimized.

[0136] Incidentally, multiple macro tasks with data dependencies are generally assigned to the same core. In some cases, multiple macro tasks with data dependencies may be assigned to different cores. In this case, a process in one core may wait for another core to terminate another process. Therefore, the sum of the process times of the macro tasks assigned to each core includes the wait time.

[0137] Assignment information 420 and assignment information 421 represent assignment information generated by static scheduling A. Assignment information 422 and assignment information 423 represent assignment information generated by static scheduling B. Assignment information 420 and assignment information 422 correspond to a case where the final type is specification A. Assignment information 421 and assignment information 423 correspond to a case where the final type is specification B. In these assignment information 420, 421, 422, 423 in Fig. 9, a macro task that should be a compilation target is shown by a solid line, and a macro task that should not be a compilation target is shown by a dotted line.

[0138] A description “WAIT” in the allocation information 420, 421, 422, 423 represents that the second core is waiting for the end of a process while the first core is executing “the process A” or “the process I”.

[0139] According to the above static scheduling, four comparison programs AA, AB, BA, and BB are generated. The comparison programs AA and AB are generated by static scheduling A. The final type of the comparison program AA is specification A. The final type of the comparison program AB is specification B. The comparison programs BA and BB are generated by static scheduling B. The final type of the comparison program BA is specification A. The final type of the comparison program BB is specification B.

[0140] In S120, the automatic parallelization compiler 1 verifies the performance of the comparison programs AA, AB, BA, BB generated in the process from S110 to S115. Based on the verification result, the automatic parallelization compiler 1 selects the optimal static scheduling. To select the optimal static scheduling, the automatic parallelization compiler 1 calculates the parallel execution time of each of the comparison programs AA, AB, BA, BB. Based on the parallelization times, the automatic parallelization compiler 1 verifies the performance.

[0141] Fig. 10 shows the process times “of the processes A, B, C, D1, D2, F, G, H, I”. Fig. Figure 11 shows the parallel execution times calculated for the comparison programs AA, AB, BA, BB.

[0142] The maximum parallel execution time of static scheduling A is 200 µs. The maximum parallel execution time of static scheduling B is 190 µs. Therefore, when selecting the optimal static scheduling based on parallel execution time, static scheduling B is selected.

[0143] Similar to the first specific example, the optimal static scheduling can be selected based on the reduction ratio or a combination of the parallel execution time and the reduction ratio. (3. Third specific example)

[0144] In the third specific example, a comparison program is generated based on a sequential program for which conditional compilation is performed according to three types of embedded systems (a specification A, a specification B, and a specification C). The performance of the comparison programs is verified. A performance verification method is explained in detail below.

[0145] A process from S100 to S115 in the automatic parallelization process generates nine comparison programs AA, AB, AC, BA, BB, BC, CA, CB, CC (referring to Fig. 12).

[0146] The comparison programs AA, AB, AC are generated by the static scheduling A. The final type of the comparison program AA corresponds to specification A. The final type of the comparison program AB corresponds to specification B. The final type of the comparison program AC corresponds to specification C.

[0147] The comparison programs BA, BB, BC are generated by the static scheduling B. The final type of the comparison program BA corresponds to specification A. The final type of the comparison program BB corresponds to specification B. The final type of the comparison program BC corresponds to specification C.

[0148] The comparison programs CA, CB, CC are generated by the static scheduling C. The final type of the comparison program CA corresponds to specification A. The final type of the comparison program CB corresponds to specification B. The final type of the comparison program CC corresponds to specification C.

[0149] In S1 20, the automatic parallelization compiler 1 verifies the performance of these comparison programs. Based on the verification result, the automatic parallelization compiler 1 selects the optimal static scheduling. The parallel execution time and the reduction ratio of each comparison program are calculated. See also Fig. 12). The automatic parallelization compiler 1 determines whether each of the static schedules satisfies a selection condition that is determined based on both the parallel execution time and the reduction ratio. Incidentally, an example of Fig. 12, that the total process time of the sequential program of specification A is 100 µs, the total process time of the sequential program of specification B is 50 µs, and the total process time of the sequential program of specification C is 50 µs.

[0150] Specifically, assume, for example, that a first selection condition is specified. The first selection condition is that the parallel execution time of a comparison program in which the final type conforms to specification A is less than 65 µs, the parallel execution time of the comparison program in which the final type conforms to specification B is less than 35 µs, and the parallel execution time of the comparison program in which the final type conforms to specification C is less than 35 µs.

[0151] In the Fig. In the example described in Figure 12, the comparison programs BA, BB, and BC generated by static scheduling B satisfy the first selection condition. Therefore, automatic parallelization compiler 1 selects static scheduling B.

[0152] Incidentally, the first selection condition can be used in a case where multi-core processors mounted on different types of embedded systems have different performances.

[0153] For example, assume that a second selection condition is specified. The second selection condition is that the parallel execution time of the comparison program in which the final type conforms to specification A is less than 65 µs, and the minimum value of the reduction ratios of the comparison program in which the final type conforms to specification B and the comparison program in which the final type conforms to specification C is relatively large.

[0154] In the Fig. In the example described in Figure 12, the comparison programs generated by static scheduling B satisfy the second selection condition. Automatic parallelization compiler 1 selects static scheduling B.

[0155] Incidentally, the second selection condition can be used in a case where multi-core processors mounted on different types of embedded systems have substantially the same performances, and the process load of the sequential program that is specification A is larger than a process load of the sequential program that is another type. (4. Fourth specific example)

[0156] In a fourth specific example, a comparison program is generated based on a sequential program in which conditional compilation is performed according to three types (a specification A, a specification B, and a specification C) of embedded systems by three compilation condition switches 501, 502, 503. The compilation condition switches 501, 502, 503 use different multiple arguments. A method for dividing a condition description 500 in the sequential program into macro tasks is explained (referring to Fig. 13).

[0157] The compilation condition switches 501, 502, 503 use arguments “NA”, “JC” and “TM” respectively. Fig. 14 shows values ​​of arguments that can be set. Fig. 15 shows fixed values ​​of the arguments in each of the types.

[0158] In S100, the automatic parallelization compiler 1 specifies each of “the processes A, B, C, D, E” described in a sequential program 500 as a conditional block.

[0159] In S105 (corresponding to the software structure analysis process), the automatic parallelization compiler 1 determines each of "the processes A, B, C, D, E" specified as the condition block as a macro task. The automatic parallelization compiler 1 generates an MTG. Macro tasks corresponding to "the processes A, B, C, D, E" are respectively referred to as "macro tasks A, B, C, D, E."

[0160] In a process from S110 to S115, the automatic parallelization compiler 1 performs static scheduling according to each type. The automatic parallelization compiler 1 assigns each of the macro tasks A, B, C, D, E to any of the PGs and generates comparison programs with the specifications A, B, C as the final type. Fig. 16 shows a description corresponding to “the macro tasks A, B, C, D, E” in the comparison program.

[0161] The "processes A, B, C, D, E" corresponding to "the macro tasks A, B, C, D, E" are described in the comparison program. A compilation condition switch is specified for each of "the processes A, B, C, D, E." The compilation condition switches specified in "processes A, B, C, D, E" have a content similar to that of the compilation condition switches specified for processes in the condition description 500 of the sequential program.

[0162] In the comparison program, if an argument of the compilation condition switch is set to a value corresponding to the type, a process corresponding to the type is selected as the compilation target.

[0163] Incidentally, among “the processes A, B, C, D, E” described in the condition description 500 of the sequential program, “the processes A, B, C” and “the processes D, E” may be different condition blocks in S100.

[0164] In this case, "a macro task X" and "a macro task Y" are generated and specified by corresponding to "the processes A, B, C" and "the processes D, E," respectively. The "processes A, B, C" corresponding to "the macro task X" are described in the comparison program, and "the processes D, E" corresponding to "the macro task Y" are described in the comparison program. Compilation condition switches are respectively specified for these processes. The compilation condition switches specified for each of "the processes A, B, C" and "the processes D, E" have contents similar to those of the compilation condition switches specified for the processes in the condition description 500 of the sequential program. (Effect)

[0165] The automatic parallelization compiler 1 of the present embodiment generates a parallelization program from a sequential program while including all condition descriptions. The automatic parallelization compiler 1 removes a section that is not compiled in or from a type of embedded system corresponding to the parallelization program and generates binary code that causes the type of embedded system to operate. Incidentally, the embedded system is provided by a system including a multi-core processor.

[0166] Therefore, it may be possible to always assign a process other than the one corresponding to an operation description to the same processor group. Incidentally, the process other than the one corresponding to the condition description represents a process that is commonly executed in all types of parallelization programs. It may be possible to further improve the commonality between types of parallelization programs, making it easier to maintain the quality and manage parallelization programs.

[0167] The automatic parallelization compiler 1 performs static scheduling based on the real cost (e.g., process load) of a macro task. Specifically, to ensure that process loads are essentially the same in each PG, macro tasks that can be executed in parallel are assigned to different PGs. Therefore, it may be possible to improve the performance of a multi-core processor operating in accordance with the parallelization program.

[0168] The automatic parallelization compiler 1 performs static scheduling corresponding to a type of any of the sequential programs. In this case, it is considered that a macro task that is not compiled in the corresponding type has no process load. Accordingly, if a description that is not compiled in the type corresponding to the static scheduling is removed from a comparison program generated by the static scheduling, it may be possible to obtain optimal performance. It may be possible to improve the performance of the parallelization program generated by the automatic parallelization compiler 1.

[0169] The automatic parallelization compiler 1 performs static scheduling corresponding to each type and generates multiple comparison programs corresponding to each type in each static scheduling. The automatic parallelization compiler 1 verifies the performance of each comparison program. Based on the comparison result, the automatic parallelization compiler 1 selects a static scheduling program that enables the generation of a comparison program with the optimal performance.

[0170] Furthermore, a section (also referred to as a non-compilation target section) that is or will not be compiled is removed from the comparison program generated by the selected static scheduling, and a parallelization program corresponding to each type is generated. Accordingly, a process common to each type in the parallelization program is always assigned to the identical PG, so it may be possible to further improve the commonality between parallelization programs of each type.

[0171] Since static scheduling is selected based on the performance verification results of benchmark programs, it is possible to generate a parallelization program with high performance. Therefore, while preventing a reduction in the performance of a parallelization program, it is possible to maintain the quality and facilitate the management of the parallelization program.

[0172] The automatic parallelization compiler 1 calculates the parallel execution time and reduction ratio of each comparison program. The automatic parallelization compiler 1 verifies the performance of each comparison program based on both or one of the parallel execution time and reduction ratio. Therefore, it may be possible to accurately determine the performance of each comparison program and select a more appropriate static scheduling method.

[0173] In a case where the automatic parallelization compiler 1 does not select static scheduling, the automatic parallelization compiler 1 notifies a user of this situation. Accordingly, it may be possible to improve the usability of the automatic parallelization compiler 1. (Other embodiments)

[0174] As mentioned above, although the embodiments have been described, the invention is not limited to the present embodiments but may have various embodiments.

[0175] (1) The automatic parallelization process in the present embodiment performs static scheduling corresponding to all types of sequential compilers. Alternatively, static scheduling corresponding to any of the static scheduling types may be performed, and a comparison program generated by the static scheduling may be a parallelization program corresponding to each type. Incidentally, a user can select the type.

[0176] The automatic parallelization process may perform a plurality of types of static scheduling corresponding to a part of types or all types of sequential compilers, and may verify a performance of each comparison program similarly to the present embodiment, so that any one of the static scheduling may be selected.

[0177] In this case, it may be possible to further improve the commonality between the types of parallelization programs and make maintaining the quality and managing the parallelization programs easy.

[0178] (2) The automatic parallelization compiler 1 of the present embodiment performs inline expansion of the sequential program in S200 of the software structure analysis process and performs renaming of local variables in S205. However, both or one of the inline expansion and renaming may be omitted. In this case, depending on a structure of a sequential program, it may be possible to obtain similar effects to those in the present embodiment.

[0179] (3) A function included in a single configuration element may be distributed among multiple configuration elements, and functions included in multiple configuration elements may be combined into a single configuration element. At least part of the configuration in the embodiments may be replaced by a known configuration having the identical function. Part of the configuration in the present embodiments may be omitted. At least part of the configuration in one embodiment may be added to or replaced by the configuration in another embodiment.

[0180] (4) The invention can be implemented by the automatic parallelization compiler described in the present embodiment, the automatic parallelization compiler device, a storage medium storing the automatic parallelization compiler, a method corresponding to a process performed by the automatic parallelization compiler, and various embodiments.

[0181] The automatic parallelization compiler 1 may correspond to an example of an automatic parallelization compiler. The on-board device 20 may correspond to an example of an electronic device.

[0182] The processor group (PG) may correspond to an example of a processor unit.

[0183] S110 of the automatic parallelization process may correspond to an example of a scheduling step and a scheduling means. S120 may correspond to an example of a verification step, a verification means, a selection step, and a selection means. S145 may correspond to an example of a notification step and a notification means.

[0184] S210 of the software analysis process may correspond to an example of a division step and a division means. S220 may correspond to an example of an extraction step and an extraction means.

[0185] The value of the argument of the compile condition switch can correspond to a sample of input information.

[0186] The parallel execution time may correspond to an example of the maximum process load of a comparison program. The reduction ratio may correspond to an example of the difference between the performance of a multi-processor system operating according to the comparison program and a single-processor system operating according to the sequential program.

[0187] It is noted that a flowchart or the process of the flowchart in the present application includes steps (also referred to as sections), each of which is represented, for example, as S100. Furthermore, each step may be divided into multiple substeps, while multiple steps may be combined into a single step.

Claims

[1] Parallelization compilation procedure performed by a processor (13) to generate a parallelization program for a multiprocessor system for an embedded system from a sequential program for a single-processor system for an embedded system, wherein the parallelization compilation procedure includes: a read step that reads the sequential program executed in the single-processor system from a storage medium (18), wherein the sequential program includes a condition description which is selected as to be compiled or not compiled by conditional compilation in accordance with an input information; a division step (S210) that divides the processes described in the sequential program into a multitude of macro tasks, independent of the input information; an extraction step (S220) that extracts parallelizable macro tasks based on data dependencies between macro tasks, which can be executed in parallel by a multitude of processor units that configure the multiprocessor system; and a scheduling step (S110) that assigns each of the macro tasks to any of the processor units, assigns all or some of the parallelizable macro tasks to different processor units, and performs static scheduling to generate a parallelization program executed by the multiprocessor system, wherein The scheduling step performs static scheduling according to predetermined two or more types of input information, and generates parallelization programs according to the two or more types of input information; In the scheduling step, a comparison program is generated by removing the condition description that is selected as not to be compiled in accordance with the input information from each of the parallelization programs that correspond to the types of input information and are generated in the static scheduling; the parallelization compilation process further includes: a verification step (S120) which, with respect to the static schedulings corresponding to the input information types, verifies the performance of the comparison programs generated in the scheduling step according to each of the input information types; and a selection step (S120) which, based on a verification result of the verification step, selects from the static schedules either a static schedule that makes it possible to generate a comparison program with the relatively best performance, or a static schedule that makes it possible to generate a comparison program with a predetermined performance; a generation step that specifies a description as a compilation target based on a value of an argument of a conditional compilation switch from the parallelization program and generates binary data through the selected schedule, the binary data executing a multi-core processor; and a storage step that stores the generated binary data in the storage medium, and The input information is the value of the argument of the conditional compilation switch. [2] Parallelization compilation method according to claim 1, wherein: The scheduling step performs static scheduling based on the process loads of the macro tasks. [3] Parallelization compilation method according to claim 2, wherein: The scheduling step performs the static scheduling according to a predetermined input information; and The scheduling step takes into account that in static scheduling, a macro task that corresponds to the condition description but is not compiled by the input information has no process load. [4] Parallelization compilation method according to claim 1, wherein: Regarding each of the comparison programs, the verification step calculates a sum of the process loads of the macro tasks assigned to each of the processor units; a maximum value of the sum is defined as a maximum process load of the comparison program; and The selection step selects any of the static schedules based on the maximum process load. [5] Parallelization compilation method according to claim 1, wherein: Regarding each of the comparison programs, the verification step estimates a difference from (i) a performance of the multiprocessor system operating in accordance with the comparison program, and (ii) a performance of the single-processor system operating in accordance with the sequential program in which the condition description selected as not to be compiled is removed by the input information, in accordance with the comparison program; and The selection step selects any one of the static schedules based on an estimated result of the difference in performance. [6] Parallelization compilation method according to claim 1, wherein: regarding each of the comparison programs, the verification step A sum of the process loads of the macro tasks assigned to each of the processor units is calculated, and a maximum value of the sum is defined as a maximum process load of the comparison program. estimates a difference from (i) a performance of the multiprocessor system operating in accordance with the comparison program, and (ii) a performance of the single-processor system operating in accordance with the sequential program in which the condition description selected as not to be compiled is removed by the input information, in accordance with the comparison program; and The selection step selects any of the static schedules based on the maximum process load and an estimated result of the difference in performance. [7] Parallelization compilation method according to any one of claims 1-6, further comprising: a notification step (S145) that notifies that static scheduling will not be selected if the selection step does not select static scheduling. [8] Parallelization compiler executed by a processor (13) to generate a parallelization program for a multiprocessor system for an embedded system from a sequential program for a single-processor system for an embedded system, wherein the parallelization compiler causes a computer to act as: a reading device that reads the sequential program executed in the single-processor system from a storage medium (18), wherein the sequential program includes a condition description which is selected, in accordance with an input information, as to be compiled or not by conditional compilation; a partitioning tool (S210) that divides the processes described in the sequential program into a multitude of macro-tasks, independent of the input information; an extraction agent (S220) that extracts parallelizable macrotasks based on data dependencies between macrotasks, which can be executed in parallel by a multitude of processor units that configure the multiprocessor system; and a scheduling tool (S110) that assigns each of the macro tasks to any of the processor units, assigns all or some of the parallelizable macro tasks to different processor units, and performs static scheduling to generate a parallelization program executed by the multiprocessor system, wherein The scheduling tool performs static scheduling according to predetermined two or more types of input information, and generates parallelization programs according to the two or more types of input information; A comparison program is generated by the scheduling tool by removing the condition description that is selected as not to be compiled in accordance with the input information from each of the parallelization programs that correspond to the types of input information and are generated in the static scheduling; the parallelization compiler also includes: a verification tool that verifies the performance of the comparison programs generated by the scheduling tool with respect to the static schedules corresponding to the types of input information, according to each of the types of input information; a selection tool that, based on a verification result of the verification tool, selects from the static schedules a static schedule that makes it possible to generate a comparison program with the relatively best performance, or a static schedule that makes it possible to generate a comparison program with a predetermined performance; a generation tool that specifies a description as a compilation target based on a value of an argument of a conditional compilation switch from the parallelization program and generates binary data through the selected schedule, the binary data being executed by a multi-core processor; and a storage device that stores the generated binary data in the storage medium, and The input information is the value of the argument of the conditional compilation switch. [9] Electronic control device comprising: a multiprocessor system operated by a parallelization program generated by the parallelization compilation method according to claim 1.

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