PARALLELIZATION PROCESSING, PARALLELIZATION TOOL AND VEHICLE-BASED DEVICE

Abstract

Parallelization method for generating a parallel program from multiple processing operations (A11 to A14, A21, A22, B11 to B14, B21, B22) in a single program for a single-core microcomputer with one core, which is then parallelized for a multi-core microcomputer with multiple cores, by analyzing a dependency of the multiple processing operations (A11 to A14, A21, A22, B11 to B14, B21, B22) in the single program and assigning the multiple processing operations (A11 to A14, A21, A22, B11 to B14, B21, B22) to different cores of the multi-core microcomputer, wherein the parallelization method comprises: a partitioning procedure (S10 to S12) for assigning, for each of the multiple processing operations (A11 to A14, A21, A22, B11 to B14, B21, B22) to the cores to be assigned, assigning the processing with the dependency of a dependent task and assigning the processing with no dependency of a non-dependent task;and an allocation procedure (S15) for allocating to the parallel program a function for executing the processing that is assigned to the non-dependent task of an own kernel when the dependent task of the own kernel is placed in a wait state, so that execution of the processing that is assigned to the dependent task of the own kernel is started from a completion of the execution of the processing that is assigned to the dependent task of another kernel.

Description

The present disclosure relates to a parallelization method and a parallelization tool for generating a parallel program for a multi-core microcomputer from a program for a single-core microcomputer, and an in-vehicle device implementing the parallel program generated by the parallelization method.Up to now, as an example of the parallelization method for generating the parallel program for the multi-core microcomputer from the program for the single-core microcomputer, there is a parallelization compilation method disclosed in JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1).In the parallelization compilation method, after a sequential program of an embedded system to be executed by a single core processor system is divided into a plurality of macro tasks (hereinafter referred to as "MTs"), the macro tasks having a control dependency are aggregated into one macro task. Thereafter, in the parallelization compiling method, parallelizable macro tasks are extracted on the basis of data dependency, and static scheduling is executed to generate a parallel program.However, the parallel program generated in a method disclosed in JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1) includes synchronization processing for waiting for execution of a macro task associated with one core to be completed and then allowing a macro task associated with another core to be executed. In this way, in the parallel program, since a wait state for causing the core to execute the macro task occurs, the performance of the multi-core microcomputer is not fully used.Reference is also made to the following prior art: Last, S. et al.: Work Controlling Scheduler for Automatic Parallelization in Fist. In: Proceedings of the Linux Audio Conference 2010, Utrecht, The Netherlands, 2010. S.147-152 http: / / lac.linuxaudio.org / 2010 / download / lac2010proceedings.pdfReference is also made to JP H03-080,337 A, JP 2010-254 662 A, JP 2013-125 607 A and JP 2012-272 714 A from the Japanese parallel method.In view of the above difficulties, an object of the present disclosure is to provide a parallelization method and a parallelization tool that can generate a parallel program that can reduce the wait state, and to provide an in-vehicle device that can reduce the wait state.The object is achieved by the subject matters and methods of the independent claims. Advantageous further developments are found in the dependent claims.In a first aspect of the present disclosure, a parallelization method for generating a plurality of processes in a single program is provided for a single-core microcomputer having a core of a parallel program that is parallelized for a multi-core microcomputer having a plurality of cores by analyzing a dependency of the plurality of processes in the single program and allocating the plurality of processes to different cores of the multi-core microcomputer. The parallelization method includes: a division procedure for, for each of the plurality of processings to be assigned to the cores, assigning the processing with the dependency of a dependent task and assigning the processing with no dependency of a non-dependent task; and a division procedure for assigning, to the parallel program, a function for executing the processing assigned to the non-dependent task of an own core when the dependent task of the own core is placed in a waiting state, so that execution of the processing assigned to the dependent task of the own core is started from completion of execution of the processing assigned to the dependent task of another core.As described above, for each of the plurality of processings associated with the cores, the above parallelization method associates the processing with the dependency of the dependent task and associates the processing with no dependency of the non-dependent task. With the above configuration, the dependent task including the processing with the dependency and the non-dependent task including the processing with no dependency are assigned to each core. Further, in the above parallelization method, the parallel program is given the function for executing the processing associated with the independent task of the own core when the dependent task of the own core is placed in the waiting state. Thus, the above parallelization method can provide the parallel program that executes the processing of the non-dependent task while the execution of the processing of the dependent task by each core is in the waiting state. In other words, the above parallelization processing can generate the parallel program that can reduce the wait state in which each of the cores does not execute any of the dependent task processing and the non-dependent task processing.In a second aspect of the present disclosure, there is provided a parallelization tool including a computer for generating a plurality of processes in a single program for a single-core microcomputer having a core of a parallel program that is parallelized for a multi-core microcomputer having a plurality of cores by analyzing a dependency of the plurality of processes in the single program and allocating the plurality of processes to different cores of the multi-core microcomputer. The parallelization tool is configured to execute: division processing for, for each of the plurality of processings to be assigned to the cores, assigning the processing with the dependency of a dependent task and assigning the processing with no dependency of a non-dependent task; and assignment processing for assigning, to the parallel program, a function for executing the processing assigned to the non-dependent task of an own core when the dependent task of the own core is placed in a waiting state, so that execution of the processing assigned to the dependent task of the own core is started from completion of execution of the processing assigned to the dependent task of another core.The parallelization tool may generate the parallel program that can reduce the wait state as in the parallelization method.In a second aspect of the present disclosure, there is provided an in-vehicle apparatus including: a multi-core microcomputer having multiple cores; and a parallel program parallelized for the multi-core microcomputer from multiple processings of a single program for a single-core microcomputer having one core. In the parallel program, the plurality of processes are assigned to a plurality of cores of the multi-core microcomputer based on an analysis of dependency of the plurality of processes. For each of the cores, the parallel program includes a dependent task associated with processing with a dependency and a non-dependent task associated with processing with no dependency. The multi-core microcomputer includes a non-dependent task execution unit for executing the processing associated with the non-dependent task of an own core when the dependent task of the own core is placed in a wait state, so that execution of the processing associated with the dependent task of the own core is started from completion of the execution of the processing associated with the dependent task of another core.As described above, the in-vehicle device includes the parallel program including, for each of the cores, the dependent task to which the processing with the dependency is associated and the non-dependent task to which the processing with no dependency is associated. The parallel program is parallelized for the multi-core microcomputer. When the self core places the dependent task in the waiting state, the multi-core microcomputer executes the processing associated with the non-dependent task of the self core. For this reason, the in-vehicle device can reduce the waiting state in which each core does not execute any of the dependent task processing and the non-dependent task processing.The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the drawings.The following are shown: FIG. 1 is a block diagram illustrating a schematic configuration of a parallelization tool according to a first embodiment; FIG. 2 is a block diagram illustrating a schematic configuration of an in-vehicle device according to the first embodiment; FIG. 3 is a diagram illustrating a part of a parallelization method according to the first embodiment; FIG. 4 is a diagram illustrating a schematic configuration of a parallel program according to the first embodiment; FIG. 5 is a flowchart illustrating a processing operation during task waking up according to the first embodiment; FIG. 6 is a flow chart illustrating the processing operation during execution of a dependent task according to the first embodiment; FIG. 7 is a flowchart illustrating a processing operation during execution of a non-dependent task according to the embodiment; FIG. 8 is a flowchart illustrating a processing operation during synchronization processing according to the embodiment; FIG. 9 is a flowchart illustrating a processing operation during first termination processing according to the first embodiment; FIG. 10 is a flowchart illustrating a processing operation during second termination processing according to the embodiment; and FIG. 11 is a diagram illustrating a processing operation of a first core and a second core according to the embodiment.Hereinafter, embodiments will be described with reference to the drawings. The present embodiment shows an example of generating a parallel program 21 a 1 parallelized for a multi-core microcomputer 21 having a first core 21 cand a second core 21 dfrom a plurality of processes A 11 to A 14 in a single program for a single-core microcomputer having a core. The processings may also be called "processing blocks" or "macro tasks" (task is a synonym for the well-known technical term "task" at this point and in the remaining application documents). The multi-core microcomputer may also be called a "multi-core processor.".A background for generating the parallel program 21 afrom the single program is that the multi-core microcomputer including a plurality of cores becomes a general trend in an increase in heat generation or an increase in power consumption of the microcomputer, or a problem of limitation of a clock frequency. The parallel program 21a is required to make the processing executable with high reliability and at high speed while shortening a development time and development cost of software.When generating the parallel program 21 a 1, as disclosed in JP 2015-1 807 A (corresponds to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1), a dependence of the plurality of macro tasks is analyzed in the single program and the plurality of macro tasks are assigned to different cores 21 cand 21 dof the multi-core processor 21. In this regard, reference is made to JP 2015-1 807 A (corresponds to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1).An example of the single program of the present embodiment includes processings A 11 to A 14, A 21, A 22, B 11 to B 14, B 21, and B 22. The plurality of processings A 11 include processings having dependency on each other. In the present embodiment, the processes A 21, A 22, B 21, and B 22 have no dependency on each other, and the process A 11 has a dependency on another process.The dependency is, for example, a relationship in which processing refers to data updated by other processing performed earlier than the one processing. Specifically, the plurality of processings include preceding processing to be executed earlier in the processing order in the single program and subsequent processing to be executed after the preceding processing is executed. The subsequent processing is affected by the previous processing, and uses data whose contents are likely to have been updated in the previous processing.A configuration of the computer 10 will be described with reference to FIG. 1. The computer 10 corresponds to a parallelization tool that executes a parallelization process, and generates the parallel program 21 a 1. The computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, and a reading unit 17. the computer 10 can read storage contents stored in a storage medium 18. An automatic parallelization compiler 1 is stored in the storage medium 18. HDD is an abbreviation for a hard disk drive. CPU is an abbreviation for central processing unit. ROM is an abbreviation for read-only memory. The RAM is an abbreviation for random access memory. For the configurations of the computer 10 and the storage medium 18, reference is made to a personal computer 100, and a storage medium 118 is disclosed in JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1).The automatic parallelization compiler 1 includes a procedure for generating the parallel program 21 a 1. The automatic parallelization compiler 1 corresponds to a parallelization method. Specifically, the automatic parallelization compiler 1 is a program including the parallelization method. The automatic parallelization compiler 1 additionally includes a division procedure and an allocation procedure in accordance with the procedures disclosed in JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1). The division procedure and the allocation procedure will be described later.Next, a configuration of the in-vehicle device 20 will be described. As illustrated in FIG. 2, the in-vehicle device 20 includes the multi-core processor 21, a communication unit 22, a sensor unit 23, and an input-output port 24. the multi-core processor 21 includes a ROM 21 a, a RAM 21 b, the first core 21 c, and the second core 21 d. The in-vehicle device 20 may be applied to an engine control device or a hybrid control device mounted on an automobile. In this example, an example in which the in-vehicle device 20 is applied to the engine control device is employed. In this case, the parallel program 21 a 1 may be regarded as an automobile control program such as an engine controller. However, the parallel program 21 a 1 is not limited to the above. The cores may also be called "processor elements.".For the RAM 21 b, the communication unit 22, the sensor unit 23, and the input-output port 24, reference is made to the RAM 420, a communication unit 430, a sensor unit 450, and an input-output port 460 disclosed in JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1).The parallel program 21 a 1 generated by the automatic parallelization compiler 1 is stored in the ROM 21 a. The first core 21 cand the second core 21 dexecute the parallel program 21 a 1 to execute engine control. The parallel program 21 a 1 includes a program to be executed by the first core 21 cand a program to be executed by the second core 21 d.Next, the processing operation for the computer 10 to execute the automatic parallelization compiler 1 in FIGS. 3 and 4 will be described. The computer 10 executes the automatic parallelization compiler 1 to generate the parallel program 21 a 1.As disclosed in the method of JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1), the computer 10 analyzes the dependency of the data on the basis of each processing of the single program and extracts the processings that are parallelizable from the single program. As disclosed in the method of JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1), the computer 10 allocates the plurality of processings to the first core 21 cand the second core 21 dbased on the dependency and the processing time. In this example, at this point, the processes A 11 to A 14, A 21, and A 22 are assigned to the first core 21 c, and the processes B 11 to B 14, B 21, and B 22 are assigned to the second core 21 b. In the following description, the processes A 11 to A 14, A 21, A 22 associated with the first core 21 care also called "first processing group", and the processes B 11 to B 14, B 21, and B 22 associated with the second core 21 dare also called "second processing group".Thereafter, the computer 10 operates for the respective processing groups as illustrated in a flowchart of FIG. 3.In step S10, it is determined whether or not the processing has the dependency (division processing). When the computer 10 determines that the processing has the dependency, the computer 10 proceeds to step S 11. When the computer 10 determines that the processing does not have the dependency, the computer 10 proceeds to step S 12. For example, when the current destination is the processing A 11, since the computer 10 determines that the processing has the dependency, the computer 10 proceeds to step S 11. When the current destination is the processing A 21, since the computer 10 determines that the processing does not have the dependency, the computer 10 proceeds to step S 12.At step S11, the processing is assigned to the dependent task (division processing). The computer 10 allocates the processing determined to have the dependency to the dependent task at S10. At step S12, the processing is assigned to the non-dependent task (division processing). The computer 10 allocates the processing determined not to have dependency to the non-dependent task at S 10.At S 13, it is determined whether or not the allocation of all the processings has been completed. If the computer 10 determines that all the processings have been completed, the computer 10 proceeds to step S 14. If the computer 10 determines that all the processings have not been assigned, the computer 10 returns to step S10.Thus, as illustrated in FIG. 4, when the processes A 11 to A 14, A 21, A 22 of the first processing group are targets, the computer 10 allocates the processes A 11 to A 14 to a first task serving as the dependent task and allocates the processes A 21 and A 22 to a second task serving as the non-dependent task. In addition, when the processes B 11 to B 14, B 21, and B 22 of the second processing group are targets, the computer 10 allocates the processes B 11 to B 14 to a third task serving as the dependent task, and allocates the processes B 21 and B 22 to a fourth task serving as the non-dependent task.In this way, the computer 10 executes steps S10 to S12 for assigning the processings having the dependency on each other to the dependent task, and assigns the processings having no dependency to the non-dependent task for each of the plurality of processings assigned to the respective cores 21c and 21d. Thus, steps S10 to S12 correspond to the division procedure.The first to fourth tasks are an execution unit of the program. The first task to the fourth task are executed every predetermined time, such as 8 milliseconds. The processing such as A 11 and the like is a function of an operation performed by each task. In addition, each task is placed in a SUSPENDED state, a READY state, a RUN state or a WAIT state. A wait state and a processing wait state, which will be described later, correspond to the WAIT state.At S 14, the parallel program 21 ais assigned a function of, on a core-by-core (core-by-core) basis, waking up the dependent task and the non-dependent task simultaneously and putting the non-dependent task in the processing waiting state at a task waking time (waking processing). In this way, the computer 10 allocates the function of waking up the first task and the second task once to the parallel program 21 aand putting the second task in the waiting state when the first task and the second task wake up. Further, the computer 10 allocates the function of waking up the third task and the fourth task once to the parallel program 21 aand putting the fourth task in the waiting state when the third task and the fourth task wake up. Thus, step S 14 corresponds to a wake-up procedure.Above, the wake-up time is a transition time between non-standby and standby to execute the processing. After waking up, since a treatment of another task having a higher priority or the like priority is in progress, a task enters a wait state for assigning a use right of the device such as the core 21 cor 21 d. After the device use right of the core 21c or 21d is assigned to a task, the one task enters the running state.At step S15, the parallel program 21a1 is assigned a function for setting the dependent task in the processing state and cancelling the processing waiting state of the non-dependent task when the tasks are set in a synchronization waiting state (assignment processing). In this way, the computer 10 allocates to the parallel program 21a1 the function of putting the dependent task of the own core in the waiting state so as to start the execution of the processing associated with the dependent task of the own core from a completion of the execution of the processing associated with the dependent task of another core. The waiting state corresponds to the synchronization waiting state and the processing waiting state. The computer 10 allocates to the parallel program 21a1 the function for executing the processing associated with the non-dependent task of the own core when the tasks are placed in the synchronization waiting state. Thus, step S15 corresponds to the allocation procedure.For example, the computer 10 allocates the function of putting the first task into the waiting state to the parallel program 21 a 1 to start the execution of the processing A 12 associated with the first task from the completion of the execution of the processing B 11 associated with the third task. Further, the computer 10 allocates, to the parallel program 21 a 1, the function of executing the processing A 21 associated with the second task when the tasks are placed in the waiting state.At step S16, the parallel program 21a becomes a function of setting at a synchronization completion time of the non-dependent tasks in the processing waiting state and cancelling the processing waiting state of the dependent task (changeover processing). The synchronization completion time is when the execution of the processing of another core that is a synchronization waiting target is completed. Specifically, the synchronization completion time is when the execution of the processing of the own core is completed and the execution of the processing of another core that is in the synchronization waiting state is enabled. In this manner, the computer 10 allocates to the parallel program 21a1 the function of putting the non-dependent task of another core in the waiting state and cancelling the waiting state of the dependent task of another core when the execution of the processing associated with the dependent task of the own core is completed and the dependent task of another core is in the waiting state. Thus, step S16 corresponds to the switching procedure. For example, the computer 10 allocates, to the parallel program 21 a 1, the function of putting the fourth task in the waiting state and cancelling the waiting state of the third task when the execution of the processing associated with the first task is completed and the third task is in the waiting state.The computer 10 executes the automatic parallelization compiler 1 to generate the parallel program 21 a 1 illustrated in FIG. 4. In the parallel program 21 a 1, programs A 11 to A 14 associated with the first task and processes A 21 and A 22 associated with the second task are programs to be executed by the first core 21 c. Further, in the parallel program 21 a 1, processes B 11 to B 14 associated with the third task and processes B 21 and B 22 associated with the fourth task are programs to be executed by the second core 21 d.In the present embodiment, the computer 10 executes the automatic parallelization compiler 1 to generate the parallel program 21 a 1. However, the present embodiment is not limited to the above configuration. In another embodiment, a worker may execute steps S 10 to S 16 in addition to the parallelization method disclosed in JP 2015-1 807 A (corresponding to US 2014 / 372 995 A1 and DE 10 2014 211 047 A1), thereby generating the parallel program 21 a1.Next, the operation of the in-vehicle device 20 will be described with reference to FIGS. 5 to 11.First, the in-vehicle device 20 operates as described in a flowchart of FIG. 5 when the task wakes up. In step S 20, the in-vehicle device 20 performs processing. In this example, the processing is different from the first processing group and the second processing group, and is processing to be executed every millisecond, for example.Thereafter, the multi-core processor 21 wakes up the first task and the second task, and sets the second task to the processing waiting state (wake-up processing unit, steps S 21 to S 23). Similarly, the multi-core processor 21 wakes up the third task and the fourth task, and sets the third task to the processing waiting state (wake-up processing unit, steps S 24 to S 26).Meanwhile, in the present embodiment, the two cores 21 cand 21 dare provided. However, the multi-core processor 21 may include three or more cores. In this case, for all the cores, the multi-core processor 21 may wake up the dependent tasks and the non-dependent tasks once, and may put the non-dependent tasks in the waiting state (wake-up processing unit).At step S27, processing is executed. In this example, the processing is different from the first processing group and the second processing group, and is processing to be executed every millisecond, for example.With the above processing, each of the cores 21 cand 21 dexecutes the dependent task after the task wakes up. When the dependent task is executed, each of the cores 21c and 21d operates as illustrated in a flowchart of Fig. 6.Each of the cores 21 cand 21 dexecutes the processing of step S 30 and executes synchronization processing at step S 31. The first core 21 creceeds to execute step S 30 and step S 31. Specifically, the first core 21 cexecutes the processing A 11 in the first step S 30, executes the processing A 12 in the subsequent step S 30, and so on, thereby executing the processing A 11 to A 14 in sequence. On the other hand, the second core 21 dreceeds repeatedly executes step S 30 and step S 31. Specifically, the second core 21 dexecutes the processing B 11 in the first step S 30, executes the processing B 12 in the subsequent step S 30, and so on, thus executing the processing B 11 to B 14 in sequence.For example, as illustrated in FIG. 11, the first core 21 c completes the execution of the processing A 11 and executes the synchronization processing, and enters the waiting state for waiting for the execution of the processing B 11 by the second core 21 to be completed. In addition, the first core 21 cis placed in the processing waiting state when an execution time of the processing B 11 is extended by the second core 21 d.Similarly, the second core 21 d completes the execution of the processing B 12 and executes the synchronization processing, and enters the waiting state for waiting that the execution of the processing A 12 is completed by the first core 21. In addition, the second core 21 dgoes into the processing waiting state when the execution time of the processing A 12 is extended by the first core 21 c.In step S32, first termination processing is executed. The first termination processing will be described later.Next, the synchronization processing will be described with reference to FIG. 8. In executing the synchronization processing, each of the cores 21 cand 21 doperates as illustrated in a flowchart of FIG. 8. For illustrative purposes, it is assumed that the self core functions as the first core 21c and another core functions as the second core 21d.At step S50, the self-core synchronization waiting is stored. Specifically, at step S50, a synchronization waiting history is stored. When the first core 21 cexecutes the synchronization processing, the multi-core processor 21 stores information indicating that the first core 21 cis in the synchronization waiting state in the RAM 21 bor the like.In step S51, it is determined whether or not all the other cores are in the synchronization waiting state. The multi-core processor 21 confirms the RAM 21b and determines whether or not the second core 21d is in the waiting state. When the multi-core processor 21 determines that the second core 21 dis in the synchronization waiting state, the multi-core processor 21 proceeds to step S 52. When the multi-core processor 21 determines that the second core 21 dis not in the synchronization waiting state, the multi-core processor 21 proceeds to step S 55. If the number of cores is 3 or more, if all the other cores are determined to be in the synchronization waiting state, the self core proceeds to step S52. If not all the other cores are determined to be in the synchronization waiting state, the self core proceeds to step S55.At step S52, the synchronization waiting history is cleared. The multi-core processor 21 clears not only the synchronization waiting history of the first core 21 cbut also the synchronization waiting history of the second core 21 d.At step S53, the processing waiting state of the dependent task of another core is canceled (changeover processing unit). At step S54, the non-dependent task of another core is set to the processing waiting state (changeover processing unit). As described above, when steps of processing in the dependent task of the own core are completed and the dependent task of another core is in the waiting state, the multi-core processor 21 places the non-dependent task of another core in the waiting state and cancels the waiting state of the dependent task of another core. Thus, when the third task is in the processing waiting state in a situation where the first core 21 c completes the execution of the processing in the first task and executes the synchronization processing, the fourth task is placed in the processing waiting state and the processing waiting state of the third task is canceled.At step S55, the processing waiting state of the non-dependent task of the self core is canceled (non-dependent task execution unit). At step S56, the dependent task of the self core is set to the processing waiting state (non-dependent task execution unit). Specifically, when the first task is placed in the waiting state to start the execution of the processing associated with the first task from the completion of the execution of the processing associated with the third task, the multi-core processor 21 executes the processing associated with the second task. For example, as illustrated in FIG. 11, when the first task is placed in the processing waiting state to start the processing A 12 from the completion of the execution of the processing B 11 by the second core 21 d, the first core 21 cexecutes the processing A 21.As described above, the first task and the third task are placed in the processing waiting state by the self core and placed in the processing waiting state by another core. On the other hand, the second task and the fourth task are shifted in the processing waiting state by another core and are released from the processing waiting state by the own core.In this example, when executing the non-dependent task, each of the cores 21c and 21d operates as illustrated in a flowchart of Fig. 7. Each of the cores 21 cand 21 dexecutes the processing at S 40 and executes a second termination processing at step S 41. The first core 21c repeatedly executes step 40 according to the number of processes associated with the second task. Specifically, the first core 21 cexecutes the processing A 21 in the first step S 40 and executes the second termination processing after executing the processing A 22 in the subsequent step S 40. As described above, the first core 21 cexecutes the processings A 21 and A 22 associated with the second task in order. On the other hand, the second core 21 dreceeds to execute step S 40 according to the number of processes associated with the fourth task. Specifically, the second core 21 dexecutes the processing B 21 in the first step S 40 and executes the second termination processing after executing the processing B 22 in the subsequent step S 40. As described above, the second core 21 dexecutes the processes B 21 and B 22 associated with the fourth task in order.As described above, when the first task is in the processing waiting state, the first core 21 cexecutes the processing of the second task. Similarly, when the third task is in the processing waiting state, the second core 21 dexecutes the processing of the fourth task. For example, as illustrated in FIG. 11, during the processing waiting state for waiting for the execution of the processing B 11 to be completed, the first core 21 cexecutes the processing A 21. During the processing waiting state for waiting for the execution of the processing A 12 to be completed, the second core 21 bexecutes the processing B 21.When each core 21c and 21d is placed in the processing waiting state during the execution of the processing, the core interrupts the processing. When the processing waiting state is canceled while each of the cores 21 cand 21 dinterrupts the processing, each of the cores restarts the execution of the interrupted processing. For example, in an example of FIG. 11, the second task is placed in the processing waiting state during execution of the processing A 21. Thereafter, the first task is placed in the processing waiting state from the completion of the execution of the processing A13, and the processing waiting state of the second task is canceled. Then, the first core 21 crestarts execution of the processing A 21. Further, when the processing waiting state of the first task is continued at the time when the execution of the processing A 21 is completed, the first core 21 cexecutes the processing A 22.Next, the first termination processing will be described with reference to FIG. 9. In executing the first termination processing, each of the cores 21c and 21d operates as illustrated in a flowchart of Fig. 9.At step S60, a completion history of the dependent task of the self core is stored. The first core 21 cstores the completion history of the first task in the RAM 21 bor the like. Similarly, the second core 21 dstores the completion history of the third task in the RAM 21 bor the like.At step S61, it is determined whether or not the non-dependent task of the self core is completed. The first core 21 cdetermines whether or not the second task is completed, and when the second task is determined to be completed, the first core 21 cproceeds to step S 64. If the second task is determined not to be completed, the first core 21 cproceeds to step S 62. Similarly, the second core 21 ddetermines whether or not the fourth task is completed, and when the fourth task is determined to be completed, the second core 21 dproceeds to step S 64. If the fourth task is determined not to be completed, the second core 21 dproceeds to step S 62.At step S62, the processing waiting state of the non-dependent task of the self core is canceled. The first core 21c cancels the processing waiting state of the second task. Similarly, the second core 21 ddebates the processing waiting state of the fourth task.At step S63, the dependent task of the own core is set to the processing waiting state. The first core 21c sets the first task to the processing waiting state. Similarly, the second core 21d sets the third task in the processing waiting state.At step S64, it is determined whether or not all tasks of the other core are completed. The first core 21 cdetermines whether or not the third task and the fourth task are completed, and when the third task and the fourth task are determined to be completed, the first core 21 cproceeds to step S 65. When the third task and the fourth task are determined not to be completed, the first core repeats the determination at step S 64. Similarly, the second core 21 ddetermines whether or not the first task and the second task are completed, and when the first task and the second task are determined to be completed, the second core 21 dproceeds to step S 65. When the first task and the second task are determined not to be completed, the second core 21 dreceeds the determination at step S 64.In step S 65, the tasks of all cores are terminated completely or comprehensively. The first core 21 cand the second core 21 dterminate the tasks of all the cores completely. For example, the first core 21 cterminates all the tasks including the tasks of the second core 21 din addition to the tasks of the first core 21 c. However, the present embodiment is not limited to the above configuration. Note that in this example, all the tasks means all the tasks waking up in the flowchart of FIG. 5.Each of the cores 21c and 21d executes the non-dependent task when the non-dependent task of the self core is not completed, and waits for completion of another core when the non-dependent task is completed.Next, the second termination processing will be described with reference to FIG. 10. In executing the second termination processing, each of the cores 21c and 21d operates as illustrated in a flowchart of Fig. 10.At step S70, a completion history of the non-dependent task of the self core is stored. The first core 21 cstores the completion history of the second task in the RAM 21 bor the like. Similarly, the second core 21 dstores the completion history of the fourth task in the RAM 21 bor the like.At step S71, it is determined whether or not the dependent task of the self core is completed. The first core 21 cdetermines whether or not the first task is completed, and when the first task is determined to be completed, the first core 21 cproceeds to step S 72. When the first task is determined not to be completed, the first core 21 creceeds the determination at step S 71. Similarly, the second core 21 ddetermines whether or not the third task is completed, and when the third task is determined to be completed, the second core 21 dproceeds to step S 72. When the third task is determined not to be completed, the second core 21 dreceeds the determination at step S 71.At step S72, the processing waiting state of the dependent task of the self core is canceled. The first core 21 cdebates the processing waiting state of the first task. Similarly, the second core 21 ddebates the processing waiting state of the third task. As described above, each of the cores 21c and 21d carries out step S71 in a loop while the dependent task associated with each core is not completed and waits for synchronization.At step S73, the non-dependent task of the own core is set to the processing waiting state. The first core 21c sets the second task to the processing waiting state. Similarly, the second core 21d sets the fourth task in the processing waiting state.As described above, by the automatic parallelization compiler 1, the processings having the dependency on each other are associated with the first task and the third task, and the processings having no dependency are associated with the second task and the fourth task for each of the plurality of processings associated with the corresponding cores 21 cand 21 d. With the above configuration, the first task and the third task including the processings with the dependency and the second task and the fourth task including the processing with no dependency are assigned to the corresponding cores 21 cand 21 d.Further, the automatic parallelization compiler 1 allocates, to the parallel program 21 a, the function of, when the first task of the first core 21 cis placed in the waiting state, executing the processing associated with the second task of the first core 21 c. Thus, the automatic parallelization compiler 1 can provide the parallel program 21 a 1 by the first core 21 cexecuted the processing of the second task while putting the execution of the processing of the first task in the waiting state. Similarly, the automatic parallelization compiler can provide the parallel program 21 a 1 in which the second core 21 dexecutes the processing of the fourth task while putting the execution of the processing of the third task in the waiting state.Specifically, the automatic parallelization compiler 1 can generate the parallel program 21 athat can reduce the waiting state by the first core 21 cnot executing any of the processing of the first task and the processing of the second task. Similarly, the automatic parallelization compiler 1 can generate the parallel program 21 a 1 that can reduce the waiting state by the second core 21 dnot executing any of the third task processing and the fourth task processing.From the above viewpoint, the automatic parallelization compiler 1 can generate the parallel program 21 a 1 that can suppress a reduction in performance of the multi-core microcomputer 21 caused by the wait state while having advantages of a synchronization system. In addition, the automatic parallelization compiler 1 can reduce man-hours required for division and schedule setting to reduce the waiting state.Also, the computer 10 executes the automatic parallelization compiler 1 to generate the parallel program 21 a 1. Thus, the computer 10 can obtain the same advantages as those of the automatic parallelization compiler 1.Further, the in-vehicle device 20 includes the parallel program 21 a 1 in which, for respective cores 21 cand 21 d, the processings with the dependency of the first task or the third task are assigned and the processing with no dependency of the second task or the fourth task are assigned. The parallel program 21 a 1 is parallelized for the multi-core microcomputer 21. When the first core 21c puts the first task in the waiting state, the multi-core microcomputer executes the processing associated with the second task. Similarly, when the second core 21d puts the third task in the waiting state, the multi-core microcomputer 21 performs the processing associated with the fourth task. For this reason, the in-vehicle device 20 can reduce the waiting state in which the first core 21 cis not executing any of the processing of the first task and the processing of the second task. Similarly, the in-vehicle device 20 can reduce the waiting state in which the second core 21 ddoes not execute any of the third task processing and the fourth task processing.Although the embodiments have been illustrated above, the present invention is not limited to the above embodiments, and the embodiments may be variously modified without departing from the spirit and scope of the present invention.

Claims

A parallelization method for generating, from a plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) in a single program for a single-core microcomputer having a core of a parallel program that is parallelized for a multi-core microcomputer having a plurality of cores, by analyzing a dependency of the plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) in the single program and allocating the plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) to different cores of the multi-core microcomputer, wherein the parallelization method comprises: a sharing procedure (S10 to S12) for, for each of the plurality of processings (A11 to A14, A21, A22, B11 to B14, B21, B22) to be assigned to the cores, assigning the processing with the dependency of a dependent task and assigning the processing with no dependency of a non-dependent task; and an allocating procedure (S15) for allocating to the parallel program a function for executing the processing associated with the independent task of an own core when the dependent task of the own core is placed in a waiting state, so that execution of the processing associated with the dependent task of the own core is started from completion of execution of the processing associated with the dependent task of another core.The parallelization processing according to claim 1, further comprising: a wake-up procedure (S14) for allocating, to the parallel program, a function of, at the wake-up time of the dependent task and the non-dependent task, waking up the dependent task and the non-dependent task once and putting the non-dependent task in the wait state on a core-by-core basis.The parallelization processing according to claim 1 or 2, further comprising: a switching procedure (S16) for allocating to the parallel program a function for putting the non-dependent task of the other core into the waiting state and cancelling the waiting state of the dependent task of the other core when the execution of the processing associated with the dependent task of the own core is completed and the dependent task of the other core is in the waiting state.A parallelization tool including a computer for generating a plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) in a single program for a single-core microcomputer having a core of a parallel program parallelized for a multi-core microcomputer having a plurality of cores, by analyzing a dependency of the plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) in the single program and allocating the plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) to different cores of the multi-core microcomputer, wherein the parallelization tool is configured to execute: division processing (S 10 to S 12) for, for each of the plurality of processings (A 11 to A 14, A 21, A 22, B 11 to B 14, B 21, B 22) to be assigned to the cores, assigning the processing with dependency of a dependent task, and assigning the processing with no dependency of a non-dependent task; and an allocating processing (S15) for allocating to the parallel program a function for executing the processing associated with the independent task of an own core when the dependent task of the own core is placed in a waiting state, so that execution of the processing associated with the dependent task of the own core is started from completion of execution of the processing associated with the dependent task of another core.The parallelization tool according to claim 4, further comprising: wake-up processing (S14) for allocating, to the parallel program, a function of, at the wake-up time of the dependent task and the non-dependent task, waking up the dependent task and the non-dependent task once and putting the non-dependent task in the wait state on a core-by-core basis.The parallelization tool according to claim 4 or 5, further comprising: changeover processing (S16) for allocating to the parallel program a function for putting the non-dependent task of the other core into the waiting state and cancelling the waiting state of the dependent task of the other core when the execution of the processing associated with the dependent task of the own core is completed and the dependent task of the other core is in the waiting state.An in-vehicle device, comprising: a multi-core microcomputer having a plurality of cores; and a parallel program parallelized for the multi-core microcomputer from a plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) of a single program for a single-core microcomputer having a core, wherein in the parallel program, the plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22) are associated with a plurality of cores of the multi-core microcomputer based on an analysis of a dependency of the plurality of processes (A11 to A14, A21, A22, B11 to B14, B21, B22), wherein, for each of the cores, the parallel program includes a dependent task associated with a processing having a dependency and a non-dependent task associated with a processing having no dependency, and the multi-core microcomputer includes: a non-dependent task executing unit (S55, S56) for executing the processing associated with the non-dependent task of an own core when the dependent task of the own core is placed in a waiting state, so that execution of the processing associated with the dependent task of the own core is started from completion of execution of the processing associated with the dependent task of another core.The in-vehicle device according to claim 7, wherein the multi-core microcomputer further includes: a wake-up processing unit (S21 to S26) for, at the wake-up time of the dependent task and the non-dependent task, waking up the dependent task and the non-dependent task once and putting the non-dependent task in the waiting state, wherein the wake-up processing unit (S21 to S26) is provided for each of the cores.The in-vehicle apparatus according to claim 7 or 8, wherein the multi-core microcomputer further comprises: a switching processing unit (S53, S54) for putting the non-dependent task of the other core into the waiting state and releasing the waiting state of the dependent task of the other core when the execution of the processing associated with the dependent task of the own core is completed and the dependent task of the other core is in the waiting state.

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