Semiconductor diode and electronic circuit arrangement herewith

Abstract

Bulk conductive semiconductor diode with a semiconductor body (10), comprising a first main surface (3) formed from an inner surface (30) on which a first contact layer (300) is arranged and from an outer surface (32), with a current path between the first contact layer (300) and a second contact layer (900), wherein the latter is arranged on a second main surface (9) opposite the first main surface (3), wherein the semiconductor diode is designed by the configuration of the first contact layer (300) or the semiconductor body (10) such that, when current flows through the current path, a partial current path (602) is formed through a further partial surface (600) of the inner surface (30), namely through the one with the greatest heating per unit volume, wherein this further partial surface (600) of the inner surface (30) and thus of the semiconductor diode is not arranged in its center, i.e. surrounding a central axis (100), wherein the semiconductor body (10) has a pn junction (2), wherein the further sub-surface (600) is formed beyond a boundary (500) of an inner sub-surface (50) of the inner surface (30) to an outer sub-surface (60) adjacent to this inner sub-surface (50) and as part of this outer sub-surface (60), and wherein either the inner sub-surface (50) is formed and limited by the fact that the first contact layer (300) above the inner sub-surface (50) has a higher ohmic resistance than the contact layer (300) of the adjacent outer sub-surface (60) or the inner sub-surface (50) is formed and limited by the fact that an electrically insulating layer, formed as a semiconductor oxide (12) of the semiconductor body (10), is arranged in the area of ​​the inner sub-surface (50).

Description

[0001] The invention describes a semiconductor diode, preferably a power semiconductor diode, and an electronic, preferably power electronic, circuit arrangement herewith.

[0002] Semiconductor diodes with a pn junction in their semiconductor body are known from the generally accepted state of the art. These semiconductor diodes consist, for example, of a semiconductor material with a first doping layer and a trough-shaped region with a second doping layer. The trough-shaped region with the second doping layer is formed, for example, from a section of the first main surface of the semiconductor body and has a first metallic contact layer on its surface. The second main surface, opposite the first, has a second metallic contact layer on its surface.

[0003] Schottky diodes with a metal-semiconductor junction and metallic contact layers on opposite main surfaces are also generally standard in the industry.

[0004] A disadvantage of both semiconductor diode designs is that in circuit configurations where the semiconductor diodes are mounted on a substrate, and current flows between the first and second contact layers, the center of the semiconductor diode is the area of ​​the diode's surface that heats up the most per unit volume compared to all surrounding areas. This greatest heating is usually due to the fact that heat dissipation from the center of the semiconductor diode is less efficient than from the outer regions. This is often accompanied by higher power dissipation per unit volume.

[0005] US patent 2011 / 0227187A1 discloses a Schottky diode with a complex trench structure which, in a special embodiment, has a circumferential rim region that includes an additional pn junction.

[0006] DE 19 26 459 A discloses a surge-resistant semiconductor diode with a semiconductor disk having a pn junction, which is contacted on both sides with planar electrodes and the resistivity of the semiconductor disk varies along its front faces, wherein at least one of the electrodes and an optionally adjacent highly doped zone has a recess within which the resistivity of the semiconductor base material has a minimum, wherein the semiconductor zone located at this recess, which is outside the space charge region before the occurrence of an avalanche breakdown, has a resistance between the edge of the recess and the edge of a region of lowest resistivity of the semiconductor base material in which the avalanche breakdown is initiated.

[0007] DE 10 66 283 A discloses a switching diode with a plate-shaped semiconductor body of a conductivity type and with electrodes attached to opposite surfaces and each of these an upstream zone of opposite conductivity type, wherein the upstream zones have the same shape and size as the electrodes, wherein one electrode area is about four times as large as the other, wherein furthermore, in operation, a voltage of such polarity is applied between the two electrodes that the rectifying junction of the larger electrode area is forward-biased, and so high that it is above the breakdown voltage of the smaller electrode and a current increases as the voltage decreases, and wherein the semiconductor body itself has no electrodes between the two junctions.

[0008] GB 927 625 A discloses a negative differential resistance device with two terminals, comprising a semiconductor body comprising at least two ohmic contact electrodes, each connected to the first and second terminals of the device, wherein a first region of a given conductivity type is provided with at least one of the following: ohmic contacts connected to the first terminal, a second region of the opposite conductivity type, also provided with at least one of the ohmic contacts connected to the second terminal, a first junction between the first and second regions, an electrode-free layer more heavily doped but of the same conductivity type as the second region and at least partially covering the first junction and the parts of the first and second regions near the first junction, without extending to or covering their ohmic contacts.and a second transition between the layer and the part of the first area that is covered by this layer.

[0009] DE 22 18 928 A discloses a semiconductor arrangement with an electroluminescent transition formed by a zone diffused into a substrate, the surface of which is provided with contact elements, at least one of which has the form of a ring extending around the circumference of the zone, wherein the contact element includes a layer of a material opaque to the light emitted by the transition, which extends within and along the ring.

[0010] JP S64-89527A discloses a Schottky diode with an insulating film formed on a semiconductor substrate, the insulating film having an annular window. An annular Schottky junction is formed, while the contact metal forming the Schottky contact is connected to the semiconductor substrate in the region of the window. A terminal metal, connected to the annular contact metal, is arranged on the insulating film.

[0011] In light of the aforementioned circumstances, the invention is based on the objective of presenting a semiconductor diode and a circuit arrangement in which, during operation, the center of the semiconductor diode heats up less compared to the prior art.

[0012] This problem is solved according to the invention by a semiconductor diode having the features of claim 1, and by a circuit arrangement having the features of claim 5. Preferred embodiments are described in the respective dependent claims.

[0013] The volume-conducting semiconductor diode according to the invention is formed with a semiconductor body, with a first main surface formed from an inner surface on which a first contact layer is arranged and from an edge surface, and with a current path between the first contact layer and a second contact layer arranged on a second main surface opposite the first main surface, wherein the semiconductor diode is designed by the configuration of the first contact layer or the semiconductor body such that, when current flows through the current path, a partial current path passes through a further partial surface of the inner surface, namely through the one with the greatest heating per unit volume, wherein this further partial surface of the inner surface and thus of the semiconductor diode is not arranged in its center, i.e. surrounding a central axis.

[0014] The first and second contact layers are preferably designed according to the aforementioned state of the art.

[0015] The semiconductor diode is formed with a pn junction in the semiconductor body. The semiconductor diodes according to the invention explicitly do not have a cell or trench structure, as is known, for example, from IGBTs (insulated gate bipolar transistors). However, the basic concept can certainly also be applied to diodes with a cell structure, whereby a semiconductor diode according to the invention is also formed.

[0016] In a preferred embodiment, an inner subsurface has a contour that is round or square, or at least substantially identical to an outer contour of the semiconductor diode. The outer contour can, in principle, be of any shape. It is frequently round, square, or rectangular; however, hexagonal outer contours are also known and feasible.

[0017] It is preferred if an inner sub-surface has a planar extent that is a maximum of 25%, preferably a maximum of 15%, and a minimum of 3%, preferably a minimum of 10%, of the area of ​​the inner surface.

[0018] According to the invention, the further sub-surface beyond a boundary of an inner sub-surface of the inner surface is formed as an outer sub-surface adjacent to this inner sub-surface and as part of this outer sub-surface.

[0019] It is in accordance with the invention if the inner partial surface is formed and limited by one of the following variants, which do not necessarily have to be alternative: • The first contact layer above the inner sub-surface has a higher ohmic resistance than the contact layer of the adjacent sub-surface. • In the area of ​​the inner surface, an electrically insulating layer, preferably a semiconductor oxide of the semiconductor body, is arranged. This insulating layer can also be covered by the first contact layer. This embodiment also proves to be preferably applicable for diodes with a cell structure.

[0020] It is further preferred if the ratio of lateral extent along the main surfaces to the thickness of the semiconductor diode, i.e. the distance between the main surfaces, is at least 5 to 1, preferably at least 10 to 1.

[0021] The circuit arrangement according to the invention is designed with a semiconductor diode described above, with a substrate and with a connecting device, wherein the first contact layer of the semiconductor diode is electrically connected to a further part of the circuit arrangement by means of the connecting device.

[0022] Preferably, the connecting device is designed as a wire bond connection or as a flexible or rigid flat metal body.

[0023] It can be advantageous if the further part of the circuit arrangement is designed as a terminal element, or as a power semiconductor component, or as a conductor track of the substrate.

[0024] Further explanations of the invention, advantageous details and features, will become apparent from the following description of the invention contained in the Fig. 1 to 8 schematically illustrated embodiments of the invention, or of respective parts thereof. Fig. Figures 1 to 3 show three variants of semiconductor diodes in a side cross-sectional view through their center. Fig. Figures 4 to 6 show three variants of semiconductor diodes in a top view. Fig. Figure 7 shows a circuit arrangement according to the invention. Fig. Figure 8 shows temperature profiles of various semiconductor diodes from the respective center to the edge of the respective semiconductor diode when used in a circuit arrangement.

[0025] Fig. Figures 1 to 3 show three variants of semiconductor diodes in a side cross-sectional view through their center. Each of these semiconductor diodes has a semiconductor body 10 with a first doping, here an n-type doping. In the semiconductor body 10, symmetrically about its center, is a well 40, in which Fig. 1 and Fig. 3 a professionally trained tub 40 and in Fig. 2 A quasi-ring-shaped well 40, which leaves the center, more precisely the area around the central axis 100, free, is formed for a second doping, here a p-doping. A pn ​​junction 2 is thus formed between the first and the second doping. The respective semiconductor body 10 has a first and an oppositely arranged second main surface 3, 9, with the well 40 for the second doping being arranged starting from the first main surface 3.

[0026] The first main surface 3 consists of an inner surface 30 arranged centrally around the central axis 100 of the semiconductor diode and an outer surface 32 extending from this inner surface and to the edge. According to the prior art, but not shown here, field rings or a field ring structure with field rings and field plates covering them can be arranged in the region of the outer surface 32. A first contact layer 300, which is typically designed as a multilayer metal contact layer, is arranged on the inner surface 30, but does not completely cover it. A second contact layer 900, which is typically designed as a multilayer metal contact layer, is arranged on the second main surface 9, but does not completely cover it. The two contact layers 300 and 900 are not necessarily identical, i.e., they do not necessarily have the same layer sequence.Rather, the two contact layers differ in their structure due to the different connection methods intended to be implemented with these contact layers. Common examples include solder joints, sintered joints, or, specifically for the first contact layer, wire bonds. This results, in principle, in a volume-conducting semiconductor diode for current flow between the first and second contact layers 3, 9.

[0027] According to a first embodiment of the semiconductor diode according to Fig. 1. The first contact layer 300 is not fully formed, but has a central recess. This results in, see also Fig. 4, an inner sub-surface 50 of the inner surface 30, which is free in the middle from the first contact layer 300. An outer sub-surface 60 borders this inner sub-surface 50; this outer sub-surface 60 is completely covered by the first contact layer 300 and extends almost to the edge of the inner surface 50. This is generally necessary because the first contact layer 300 may only be in electrically conductive contact with the area, the well 40, of the second doping, and for this purpose must be spaced away from the edge of the well 40, i.e., from the pn junction 2, which here extends to the first main surface 3.

[0028] Although not shown, a further metallization, of potentially any design, may also be arranged in the inner region 50. However, this further metallization is not electrically conductive during operation of the semiconductor diode and therefore does not contribute to the current flow between the first and second contact layers 300, 900.

[0029] According to a second embodiment of the semiconductor diode according to Fig. 2, the first contact layer 300 is basically identical to that according to Fig. 1. Additionally, the well 40 with the second doping also has a lateral extent equal to that of the first contact layer 300, i.e., lying in the plane of the first main surface 3, whereby, as explained above, not only the outer edge of the first metallization 300 is spaced away from the pn junction 2, but for the same reason, so is the inner edge of the first contact layer 300. Thus, the first contact layer covers the p-well region 40, leaving a marginal strip of the p-well region 40 uncovered both inside and outside.

[0030] According to a third embodiment of the semiconductor diode according to the invention Fig. 3 The inner sub-surface 50 is formed and bounded by the presence of an electrically insulating layer, here a semiconductor oxide 12 formed by oxidation of the semiconductor body 10, in the region of the inner sub-surface 50. The insulating layer should have an ohmic resistance that is at least two, preferably four, orders of magnitude greater than that of the region, the well 40, of the second doping. The insulating layer can also be applied to the semiconductor body 10 by means of an epitaxial process. Due to the ease of fabrication, it is particularly advantageous to form the first contact layer 300 here over its entire surface, virtually analogous to the prior art, whereby the insulating layer is completely covered by the first contact layer 300.

[0031] For all the aforementioned configurations of the semiconductor diode, when current flows between the first contact layer 300 and the second contact layer 900, a partial current path 602 is assigned to a further sub-area 600 of the inner surface 30, which exhibits the greatest heating per unit volume. This further sub-area 600 is formed beyond a boundary 500 of the inner sub-area 50 as part of the outer sub-area. This further sub-area 600 defines the location of the unit volume with the greatest heating during operation, with the unit volume extending from the further sub-area 600 of the first main surface 3 into the semiconductor body 10 up to the second main surface 9.

[0032] Fig. Figures 4 to 6 show three variants of semiconductor diodes.

[0033] The Fig. 4 and Fig. 5 show semiconductor diodes according to the Fig. 1 or Fig. 2 in top view. Shown is the first main surface 3, formed from the inner surface 30 and the edge surface 32. The inner surface 30 has a central inner sub-surface 50 which has no contact layer. This inner sub-surface 50 is surrounded by an outer sub-surface 60 which has the first metallization 300.

[0034] In Fig. 4 is, purely schematically, the further sub-area 600 of the outer sub-area 60, which is arranged beyond the boundary 500 from inner to outer sub-area 50, 60 and is assigned to the partial flow path with the greatest heating per unit volume.

[0035] The inner sub-surface 50 of this semiconductor diode has a round sub-surface contour 52.

[0036] Fig. Figure 5 shows a semiconductor diode having a cushion-shaped partial surface contour 52, essentially following the square outer contour shown here. Also shown are contact areas 804 of a wire bond connection, with which the first contact layer 300 of the semiconductor diode is connected within a circuit arrangement, cf. Figure 5. Fig. 7, can be electrically connected.

[0037] Fig. Figure 6 shows a round semiconductor diode, in which a plurality of recesses 502 are arranged in the first contact layer 300 in the center, thereby defining the inner sub-area 50. The area of ​​these recesses 502 is more than 50% of the area of ​​the inner sub-area 50.

[0038] Fig. Figure 7 shows a circuit arrangement according to the invention comprising a semiconductor diode 1, a substrate 70, and a connecting device 80. The substrate 70 has an insulating layer or, alternatively, an insulating body, each with conductive traces 700 arranged thereon. This is a conventional substrate, for example, a so-called DCB (direct copper bonding) substrate, as is commonly used for power semiconductor modules. The second contact layer 900 of the semiconductor diode 1 is electrically connected to a conductive trace 700 by means of a force-fit or material-fit connection, for example, by means of a solder joint. The first contact layer 300 of the semiconductor diode 1 is electrically connected to a further conductive trace 700 of the circuit arrangement, more precisely of the substrate 70, by means of a connecting device 80.This connecting device 80 is also designed in the usual way, here as a metal bracket 800, but can also be designed as an electrically conductive foil or as a wire bond connection.

[0039] Fig. Figure 8 shows temperature profiles of various semiconductor diodes from their respective centers to their edges when used in a circuit arrangement. Curve A shows the temperature profile of a state-of-the-art semiconductor diode. Such a semiconductor diode heats up most in its center because heat dissipation to a substrate or heat sink is least efficient from this area. This results in a maximum temperature of over 173°C, and thus the area of ​​greatest temperature increase per unit volume, in the center of the semiconductor diode.

[0040] In an optimized embodiment, according to curve B, of the semiconductor diode according to the invention, the area with the highest operating temperature, i.e., the volume area extending into the semiconductor body and adjoining the further partial surface, shifts towards the edge of the semiconductor diode, although the above-mentioned measures according to the invention, for example according to the Fig. 1 to 3, the effective cross-sectional area of ​​the semiconductor diode is reduced compared to the prior art. Crucially, the design of the semiconductor diode according to the invention now results in a maximum temperature of only 167°C in the area of ​​greatest heating per unit volume.

[0041] Curve C shows an "excessive" shift of the area of ​​greatest heating per unit volume towards the edge of the semiconductor diode. Here, only the cross-sectional area of ​​the semiconductor diode effective for current flow between the first and second metal layers is reduced to such an extent that the maximum temperature increases again.

[0042] The optimization of the specific design of the semiconductor diode can be based on thermal simulations or determined empirically. Key influencing factors are the thickness and width (i.e., the lateral dimensions) of the semiconductor diode, its doping, and thus its suitability for different voltage classes.

Claims

[1] A volume-conductive semiconductor diode comprising a semiconductor body (10), with a first main surface (3) formed from an inner surface (30) on which a first contact layer (300) is arranged and from an edge surface (32), with a current path between the first contact layer (300) and a second contact layer (900), wherein the latter is arranged on a second main surface (9) opposite the first main surface (3), wherein the semiconductor diode is formed by the design of the first contact layer (300) or the semiconductor body (10) such that, when current flows through the current path, a partial current path (602) is formed through a further partial surface (600) of the inner surface (30), namely through the one with the greatest heating per unit volume, wherein this further partial surface (600) of the inner surface (30) and thus of the semiconductor diode is not arranged in the center thereof, i.e. surrounding a central axis (100), wherein the semiconductor body (10) has a pn junction (2), wherein the further partial area (600) is formed beyond a boundary (500) of an inner partial area (50) of the inner surface (30) to an outer partial area (60) adjoining this inner partial area (50) and as part of this outer partial area (60) and in this case either the inner partial surface (50) is formed and limited in that the first contact layer (300) above the inner partial surface (50) has a higher ohmic resistance than the contact layer (300) of the adjacent outer partial surface (60) or the inner partial surface (50) is formed and delimited by an electrically insulating layer, formed as a semiconductor oxide (12) of the semiconductor body (10), being arranged in the region of the inner partial surface (50) [2] Semiconductor diode according to claim 1, wherein the inner partial surface (50) has a partial surface contour (52) which is round or square, or is formed identically to an outer contour of the semiconductor diode. [3] Semiconductor diode according to one of the preceding claims, wherein the inner partial area (50) has a planar extent which is a maximum of 25%, preferably a maximum of 15%, and a minimum of 3%, preferably a minimum of 10%, of the area of the inner area (30). [4] Semiconductor diode according to one of the preceding claims, wherein a ratio of lateral extent along the main surfaces (3, 9) to a thickness of the semiconductor diode (1), i.e. the distance between the main surfaces (3, 9) is at least 5 to 1, preferably at least 10 to 1. [5] Circuit arrangement with a semiconductor diode according to one of the preceding claims, with a substrate (70) and with a connecting device (80), wherein the first contact layer (300) of the semiconductor diode is electrically conductively connected to a further part of the circuit arrangement by means of the connecting device (80). [6] Circuit arrangement according to claim 5, wherein the connecting device (80) is designed as a wire bond connection or as a flexible or rigid flat metal molded body (800). [7] Circuit arrangement according to claim 5 or 6, wherein the further part of the circuit arrangement is designed as a connection element, or as a power semiconductor component or as a conductor track (700) of the substrate (70).

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