FINFET SRAM WITH DISPENTIAL PMOS RIBBED LEADS

Abstract

Integrated circuit (IC) chip, comprising: a logic circuit cell array (100) comprising a plurality of logic circuit cells (131-140) adjacent to each other in a first direction, wherein the logic circuit cells (131-140) have one or comprising several continuous first fins (110, 111, 310, 311), each extending over at least three of the adjacent logic circuit cells (131-140) in the first direction; and a static random access memory (SRAM) cell array (200) comprising a plurality of SRAM cells (210-217, 500, 500A, 500B) adjacent to each other in the first direction, wherein the SRAM cell array (200) comprises discontinuous second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B), wherein the first and second fins (110, 111, 220-224, 230-234, 310, 311, 511, 511A, 511A, 512, 512A, 512B) each comprise a channel area as well as source / drain areas, and wherein the logic circuit cell array (100) further comprises one or more isolation transistors, each located between two associated adjacent logic circuit cells (131-140); and a gate (400, 410) of each of the isolation transistors is electrically connected to a voltage source (Vdd, Vss) such that each of the isolation transistors is configured to provide electrical isolation between the two associated adjacent circuit cells (131-140), wherein: the logic circuit cell array (100) and the SRAM cell array (200) each comprise one NMOSFET and one PMOSFET; a gate of the PMOSFET of the logic circuit cell array (100) comprises a first exit work metal (760); a gate of the PMOSFET of the SRAM cell array (200) comprises a second exit working metal (770); a gate of the NMOSFET of the logic circuit cell array (100) includes a third exit working metal (761); a gate of the NMOSFET of the SRAM cell array (200) comprises a fourth exit working metal (771); and at least one of the first, second, third and fourth exit metal (760, 761, 770, 771) differs from a residue of the first, second, third and fourth exit metal (760, 761, 770, 771), wherein the first exit work metal (760) is thicker than the second exit work metal (770), and wherein the third exit work metal (761) has a higher aluminium content than the fourth exit work metal (771).

Description

BACKGROUND

[0001] In sub-micrometer integrated circuit technology, embedded static random-access memory (SRAM) devices have become popular memory units for high-speed data transmission, image processing, and system-on-a-chip (SoC) products. The amount of embedded SRAM in microprocessors and SoCs increases to meet the performance requirements of each new technology generation. As silicon technology continues to scale from one generation to the next, the influence of variations in the intrinsic threshold voltage (Vt) in planar mass transistors with minimal geometry decreases the static noise margin (SNM) of complementary metal-oxide-semiconductor (CMOS) SRAM cells. This reduction in SNM, caused by increasingly smaller transistor geometries, is undesirable. The SNM is further reduced when Vcc is scaled to a lower voltage.

[0002] To solve SRAM problems and improve cell miniaturization, fin field-effect transistor (FinFET) devices have been widely used in some applications. FinFETs offer both speed and device stability. A FinFET has a channel (referred to as a fin or rib channel) associated with a top surface and opposing sidewalls. Advantages can be derived from the greater sidewall width (ion power) as well as better short-channel control (sub-threshold leakage). Thus, FinFETs should offer advantages in terms of gate length scaling and intrinsic voltage fluctuations. However, existing FinFET SRAM devices still have shortcomings, such as limitations in cell write areas or chip speeds.

[0003] Therefore, although the existing FinFET SRAM devices were generally suitable for their intended purposes, they are not satisfactory in every respect.

[0004] US 2016 / 0260719 A1 discloses integrated circuit devices with fin structures, wherein logic and memory regions are arranged side by side on a substrate. Transistors can be provided in the regions by depositing a gate structure over semiconductor fins. In an SRAM cell in the memory region of the circuit device, semiconductor fins of a pull-up transistor are interrupted.

[0005] US 2013 / 0292777 A1 discloses a semiconductor device with an SRAM cell, wherein FinFET transistors are provided by parallel semiconductor fins and gates arranged perpendicular to them. Two adjacent semiconductor fins are alternately formed in an N- and P-doped well, such that pairs of N- and P-doped semiconductor fins are arranged in parallel. The semiconductor fins in the N-doped well are partially interrupted.

[0006] DE 10 2010 024 480 B4 discloses a logic circuit and a memory matrix coupled to the logic circuit, wherein the memory matrix is ​​made of semiconductor fins extending in a first direction, and wherein transistors are manufactured in the memory matrix by gates extending perpendicular to the semiconductor fins. The semiconductor fins can be made of a SiGe substrate. The logic circuit can also include FinFET transistors.

[0007] Publication US 2009 / 0134472A1 discloses a semiconductor device suitable for implementing SRAM memory cells. The memory cell comprises two n-channel transfer transistors, two n-channel driver transistors, and two p-channel load transistors. A sacrificial device region includes a dummy fin that lacks source / drain areas and transistor function to achieve a more uniform fin geometry.

[0008] Publication KR 10 2014 107 090 A and US 2015118812 A1 disclose a method for manufacturing parasitic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] An improved semiconductor device is provided by claims 1 and 11 and by a method according to claim 14. The inventive solution of an improved FinFET-SRAM device is provided by semiconductor devices and a method according to the independent claims. Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with the usual practice in the industry, various elements are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of discussion.It is also emphasized that the accompanying drawings only show typical embodiments of this invention and should therefore not be understood as limiting in scope, since the invention can equally be applied to other embodiments. Fig. Figure 1A is a perspective view of an example FinFET device. Fig. Figure 1B shows a schematic cross-sectional side view of FinFET transistors in a CMOS configuration. Fig. Figure 2 shows a top view of a standard (STD) cell array according to embodiments of the present disclosure. Fig. Figure 3 shows a top view of an SRAM cell array according to embodiments of the present disclosure. Fig. Figure 4 shows a top view of a standard (STD) cell array according to embodiments of the present disclosure. Fig. Figure 5 shows a top view of an SRAM cell array according to embodiments of the present disclosure. Fig. Figure 6A shows circuit diagrams of various logic gates according to some embodiments of the present disclosure. Fig. 6B shows the top view of the layout that leads to the logic gates of Fig. 6A belongs, according to some embodiments of the present disclosure. Fig. Figure 6C shows a schematic partial cross-sectional view of the corresponding cells, which are in Fig. 6B are shown according to some embodiments of the present disclosure. Fig. Figure 7A shows a circuit diagram for a single-port SRAM cell according to embodiments of the present disclosure. Fig. Figure 7B shows the layout in a top view of the single-port SRAM cell of Fig. 7A according to embodiments of the present disclosure. Fig. Figure 8A shows a cross-sectional side view of two adjacent SRAM cells according to embodiments of the present disclosure. Fig. 8B shows the layout of the two adjacent SRAM cells of Fig. 8A in a top view according to embodiments of the present disclosure. Fig. Figure 9A is a schematic partial cross-sectional side view of a part of a CMOSFET device in a standard cell according to embodiments of the present disclosure. Fig. Figure 9B is a schematic partial cross-sectional side view of a part of a CMOSFET device in an SRAM cell according to embodiments of the present disclosure. Fig. Figure 10 is a schematic partial cross-sectional side view of a part of a connection structure according to embodiments of the present disclosure. Fig. Figure 11 is a flowchart illustrating a method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0011] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or device to other element(s) or device(s), as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly.

[0012] The present disclosure relates, without limitation, to a rib-like field-effect transistor (FinFET) device. The FinFET device may, for example, be a complementary metal-oxide-semiconductor (CMOS) device, including a p-metal-oxide-semiconductor (PMOS) FinFET device and an n-metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure proceeds with one or more FinFET examples to describe various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

[0013] The use of FinFET devices is becoming increasingly popular in the semiconductor industry. With regard to Fig. Figure 1A shows a perspective view of an exemplary FinFET device 50. The FinFET device 50 is a non-planar multi-gate transistor fabricated on a substrate (such as a bulk substrate). A thin silicon-containing rib-like structure or fin (hereinafter referred to as the 'fin') forms the body of the FinFET device 50. The fin extends along an X-direction in the Fig. 1A. Die Finne hat eine Finnenbreite W fin , which is measured along a Y-direction that is perpendicular to the X-direction. A gate 60 of the FinFET device 50 encloses this fin, for example around the top and the opposite sidewall surfaces of the fin. Thus, part of the gate 60 lies above the fin in a Z-direction that is perpendicular to both the X-direction and the Y-direction.

[0014] LG denotes a length (or width, depending on the perspective) of the gate 60, measured in the X direction. The gate 60 can have a gate electrode component 60A and a gate dielectric component 60B. The gate dielectric 60B has a thickness t ox , measured in the Y direction. Part of the gate 60 lies above a dielectric insulation structure, for example, a shallow trench insulation (STI). A source 70 and a drain 80 of the FinFET device 50 are formed in extensions of the fin on opposite sides of the gate 60. A section of the fin enclosed by the gate 60 serves as the channel for the FinFET device 50. The effective channel length of the FinFET device 50 is determined by the dimensions of the fin.

[0015] Fig. Figure 1B shows a schematic cross-sectional side view of FinFET transistors in a CMOS configuration. The CMOS FinFET comprises a substrate, for example, a silicon substrate. An N-well and a P-well are formed in the substrate. A dielectric insulation structure, such as a shallow trench insulation (STI), is formed over the N-well and the P-well. A P-FinFET 90 is formed over the N-well, and an N-FinFET 91 is formed over the P-well. The P-FinFET 90 has fins 95 that extend upwards from the STI, and the N-FinFET 91 has fins 96 that extend upwards from the STI. The fins 95 encompass the channel regions of the P-FinFET 90, and the fins 96 encompass the channel regions of the N-FinFET 91. In some embodiments, the fins 95 are made of silicon-germanium, and the fins 96 are made of silicon. A gate dielectric is formed over the fins 95-96 and over the STI, and a gate electrode is formed over the gate dielectric.In some embodiments, the gate dielectric comprises a high-k dielectric material and the gate electrode is a metal gate electrode, for example, aluminum and / or other refractory metals. In some other embodiments, the gate dielectric may comprise SiON₂ and the gate electrode polysilicon. A gate contact is formed on the gate electrode to establish an electrical connection with the gate.

[0016] FinFET devices offer several advantages over conventional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (also known as planar transistor devices). These advantages can include improved chip area efficiency, enhanced carrier mobility, and a fabrication technique compatible with that used for planar devices. Therefore, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for part or all of the IC chip.

[0017] Conventional FinFET fabrication methods can still have drawbacks, such as a lack of optimization for embedded SRAM fabrication. For example, conventional FinFET fabrication can have difficulties related to SRAM cell write area and logic circuit speed. The present disclosure describes FinFET logic circuits and SRAM cells that have an improved SRAM cell write area without reducing the logic circuit speed, as described in more detail below.

[0018] Fig. Figure 2 shows a top view of a standard (STD) cell array 100 according to embodiments of the present disclosure. The standard cell array 100 may include logic circuits or logic devices and is also referred to as a logic cell array or logic circuit array. In various embodiments, the logic circuits or devices may include components such as inverters, NAND gates, NOR gates, flip-flops, or combinations thereof.

[0019] As in Fig. As shown in Figure 2, the standard cell array comprises 100 N-FinFET transistors with an N-well and P-FinFET transistors with an N-well. The standard cell array 100 also includes a variety of elongated fins, for example, fins 110-111 as part of the P-FinFET transistors and fins 120-121 as part of the N-FinFET transistors. The P-FinFET fins 110-111 are located above the N-wells, whereas the N-FinFET fins 120-121 are located above the P-wells.

[0020] As an example, the standard cell array shown here comprises 100 standard cells 131 to 140, with cells 131 to 135 arranged in a first column and cells 136 to 140 arranged in a second column adjacent to the first column. Of course, this shows Fig. 2 is only one example of the standard cell array 100 and other embodiments may have different quantities of cells and / or may be arranged differently.

[0021] As in Fig. As shown in Figure 2, fins 110-111 and 120-121 each extend over a corresponding column of the standard cells (e.g., fins 110 and 120 extend over standard cells 1-5 and fins 111 and 121 over standard cells 6-10) in the X direction (the X direction of Fig. 1A). Thus, fins 110-111 and 120-121 can each be described as “throughout” or continuous.

[0022] As above with reference to Fig. As described in Figure 1A, fins 110-111 and 120-121 each comprise a channel region as well as source / drain regions located adjacent to (e.g., on opposite sides of) the channel region. The FinFET transistors of the STD cell array 100 each comprise an associated gate electrode that surrounds an associated fin 110-111 or 120-121 in the manner described above with reference to Figure 1A. Fig. 1A is described. In the present embodiments, the P-FinFET (PMOSFET) fins 110-111 are made of a silicon-germanium (SiGe) material (to increase the voltage effect), whereas the N-FinFET (NMOSFET) fins 120-121 are made of a semiconductor material without germanium, for example, silicon (Si). Thus, in some embodiments, the PMOSFET has a SiGe channel, while the NMOSFET has a Si channel. In some embodiments, the fin channel width of the NMOSFET is narrower than the fin channel width of the PMOSFET. In some embodiments, the source / drain regions of the NMOSFET comprise an epi-material selected from the group consisting of: SiP, SiC, SiPC, SiAs, Si, or combinations thereof. In some embodiments, the source / drain region of the PMOSFET has a greater width than the channel region.

[0023] In some embodiments of the PMOSFET, the atomic germanium concentration in the SiGe channel region is lower than the atomic germanium concentration in the source / drain region. For example, in some embodiments, the atomic germanium concentration in the SiGe channel region may be in a range between approximately 10% and approximately 40%, and the atomic germanium concentration in the source / drain region may be in a range between approximately 30% and approximately 75%.

[0024] In some embodiments, the SiGe channel fin width for the PMOSFET is smaller than the SiGe channel sidewall depth. For example, in some embodiments, the SiGe channel fin width for the PMOSFET can be in a range between approximately 3 nanometers (nm) and approximately 10 nm, and the SiGe channel sidewall depth (in Fig. 1A (labeled as channel sidewall depth 85) lies in a range between approximately 30 nm and approximately 90 nm.

[0025] As described above, all fins 110-111 and 120-121 of the standard cell array 100 are continuous. For example, fins 110-111 and 120-121 each extend over at least three adjacent cells (e.g., cells adjacent to each other in the X direction). In the embodiment described in Fig. As shown in Figure 2, fins 110 and 120 each extend over five adjacent standard cells 1-5, and fins 111 and 121 each extend over five other adjacent standard cells 6-10.

[0026] With reference to Fig. Figure 3 shows a top view of an SRAM cell array 200 according to embodiments of the present disclosure. The SRAM cell array 200 comprises SRAM cells, for example SRAM cells 210-217. In the embodiment shown, the SRAM cells 210-213 are arranged in a first column extending in the X direction (from Fig. 1A) extends and arranges the SRAM cells 214-217 in a second column extending in the X direction, with the first column adjacent to the second column in the Y direction (from Fig. 1A). Each of the SRAM cells 210-217 comprises two pull-up (PU) transistors and two pull-down (PD) transistors, which can be implemented as FinFETs.

[0027] The SRAM cell array 200 comprises a variety of elongated fins, for example, fins 220-224 and 230-234 as part of the P-FinFET transistors in the pull-up (PU) section of the SRAM cell array 200, and fins 240-243 as part of the N-FinFET transistors in the pass-gate (PG) and pull-down (PD) sections of the SRAM cell array 200. The P-FinFET fins 220-224 and 230-234 are located above the N-wells, whereas the N-FinFET fins 240-243 are located above the P-wells.

[0028] The fins 220-224, 230-234, and 240-243 each extend across one or more associated SRAM cells in the X direction. For example, the N-FinFET fins 240-241 each extend continuously across SRAM cells 210-213, and the N-FinFET fins 242-243 each extend continuously across SRAM cells 214-217. In contrast, the P-FinFET fins 220-224 and 230-234 are "interrupted" or "separated" or discontinuous. For example, the P-FinFET fin 220 extends partially into the SRAM cell 210, the fin 221 partially into the SRAM cells 210-211, the fin 222 partially into the SRAM cells 211-212, the fin 223 partially into the SRAM cells 212-213, and the fin 224 partially into the SRAM cell 213. The fin 221 overlaps the fins 220 and 222 in the X direction, but has a distance from the fins 220 and 222 in the Y direction.Similarly, fin 223 overlaps fins 222 and 224 in the X direction, but has a distance from fins 222 and 224 in the Y direction.

[0029] In the adjacent column of cells 214-217, the P-FinFET fin 230 extends partially into SRAM cell 214, fin 231 partially into SRAM cells 214-215, fin 232 partially into SRAM cells 215-216, fin 233 partially into SRAM cells 216-217, and fin 234 partially into SRAM cell 217. Fin 231 overlaps fins 230 and 232 in the X direction but is spaced apart from fins 230 and 232 in the Y direction. Similarly, fin 233 overlaps fins 232 and 234 in the X direction but is spaced apart from fins 232 and 234 in the Y direction.

[0030] As above with reference to Fig. As described in Figure 1A, the fins 220-224, 230-234, and 240-243 each comprise a channel region as well as source / drain regions located adjacent to (e.g., on opposite sides of) the channel region. The FinFET transistors each comprise a gate electrode that surrounds a corresponding fin 220-224, 230-234, and 240-243 in the manner described above with reference to Figure 1A. Fig. 1A is described. In the present embodiments, the P-FinFET fins 220-224 and 230-234 consist of a silicon-germanium (SiGe) material (to increase the voltage effect), whereas the N-FinFET fins 240-243 consist of a semiconductor material without germanium, for example Si.

[0031] It turns out that while fins 110-111 are for the P-FinFETs and fins 120-121 are for the N-FinFETs in the standard cell array 100, which is in Fig. 2 is shown, each continuous and the fins 240-243 for the N-FinFETs in the SRAM cell array 200, which is in Fig. As shown in Figure 3, the fins 220-224 and 230-234 for the P-FinFETs in the SRAM cell array 200 are "interrupted". For example, the P-FinFET fins 220-224 could be implemented as a single continuous fin (e.g., similar to the N-FinFET fin 240) spanning the SRAM cells 210-213, but according to the various aspects of the present disclosure, this hypothetical single fin is divided into five separate fins 220, 221, 222, 223, and 224. Fins 220 and 222 are separated by a gap 250 spanning the boundary between SRAM cells 210-211 (in the X direction), and fins 222 and 224 are separated by a gap 251 spanning the boundary between SRAM cells 212-213 (in the X direction). Fins 221 and 223 are separated by a gap 252 spanning the boundary between SRAM cells 211-212 (in the X direction).At least partly due to these gaps 250-252, it can be said that the P-FinFETs in the SRAM cells 200 have interrupted or separated fins.

[0032] The fins 230-234 in the SRAM cells 214-217 are arranged in a similar manner (i.e., divided into interrupted fins) to fins 230-234. Thus, although each of the fins 220-224 and 230-234 extends partially over two adjacent SRAM cells, the SRAM cell array 200 has an overall "interrupted" fin shape for its P-FinFETs, which is not the case for the N-FinFETs of the standard cell array 100. In some embodiments, the end of each "interrupted" fin lies beneath a gate electrode of another CMOSFET. In some embodiments, the interrupted or separated fins 220-224 and 230-234 each extend over at most two adjacent SRAM cells.

[0033] The reason the fins for the standard cell array 100 are continuous, while the fins (for P-FinFETs) for the SRAM cell array 200 are interrupted, lies in problems with ions (during current flow). If the P-FinFET devices for the SRAM cells have continuous fins, the ion current is too high, which is detrimental to SRAM write areas. According to the present disclosure, the P-FinFET fins for the SRAM cell array 200 are configured in a "separated" or "interrupted" manner. This eliminates or reduces the voltage effect (for the SiGe strained channels). Consequently, the ion current for the P-FinFET fins of the SRAM cell array 200 is reduced, thus mitigating problems with the SRAM write area. At the same time, continuous fins are beneficial for the speed of logic circuits. The continuous fins also solve problems related to shrinkage control issues at the line end in PMOSFET layouts of logic circuits.As such, the logic cells (or STD cells) are configured to have continuous fins.

[0034] Fig. Figures 4-5 show a further embodiment of the STD cell array 100 and the SRAM cell array 200, respectively. The embodiments of the STD cell array 100 and the SRAM cell array 200 are similar to the embodiment shown in the Fig. 2-3 and therefore similar elements appearing in both embodiments are marked the same here. The embodiment of the STD cell array 100 in Fig. However, 4 does not include the N-FinFET fins 120-121 and the embodiment of the SRAM cell array 200 in Fig. 5 does not have the N-FinFET fins 240-243. Nevertheless, the embodiment of the SRAM cell array 200 in Fig. 5. For the same reasons as described above (i.e., the ion current), still separate or interrupted fins for its P-FinFETs.

[0035] The Fig. 6A, Fig. 6B, Fig. Figure 6C shows one or more standard cells according to some embodiments of the present disclosure. Figure 6C shows in more detail... Fig. 6A the circuit diagrams of some common logic gates manufactured using CMOS FinFETs, Fig. 6B the layout in top view, which the logic gates of Fig. 6A corresponds to, and 6C to a schematic partial cross-sectional side view of the corresponding cells of Fig. 6B. It is understood that the layout in the top view of Fig. 6B one or more of the STD cells (or parts of them) of the Fig. 2 or Fig. can correspond to 4.

[0036] For example, the logic gates of Fig. 6A includes an inverter gate, a NAND gate, and a NOT gate. The inverter gate, the NAND gate, and the NOR gate each comprise one or more N-MOSFETs (NMOSFETs) and one or more PMOSFETs (PMOSFETs). The specific type of logic gate is determined by coupling the gate, source, and drain of the NMOSFETs and the PMOSFETs in a specific configuration, as shown in the Fig. Figures 6A-6B are shown. The input and output terminals of each logic gate are shown in Fig. 6A is marked as such.

[0037] The layout in top view of Fig. Figure 6B shows PMOSFETs with an N-well region and NMOSFETs with a P-well region. A multitude of elongated fins 310-311 and 320-321 extend in an elongated manner in the X direction. Fins 310-311 are part of the PMOSFET, and fins 320-321 are part of the NMOSFET. The PMOSFET fins 310-311 lie above the N-well region, whereas the NMOSFET fins 320-321 lie above the P-well region.

[0038] As above with reference to Fig. As described in Figure 1A, the fins 310-311 and 320-321 each comprise a channel region as well as source / drain regions located adjacent to (e.g., on opposite sides of) the channel region. In the present embodiments, the PMOSFET fins 310-311 are made of a silicon-germanium (SiGe) material (to increase the voltage effect), whereas the NMOSFET fins 320-321 are made of a semiconductor material without germanium, for example, Si. The fins 310-311 and 320-321 are each continuous, for example, each extending over three or more adjacent cells (adjacent in the X direction).

[0039] In each of the circuit cells (e.g., the inverter, the NAND, or the NOR), one or more CMOS gates 350 extend into both the N-well and P-well regions in the Y direction. The portion of the gate 350 that lies above the N-well region forms the gate of the PMOSFET, and the portion of the gate 350 that lies above the P-well region forms the gate of the NMOSFET. Each of the gates 350 encloses the fins 310-311 and 320-321 in the diagram above. Fig. as described in Figure 1A. For example, gates 350 in the PMOSFET enclose fins 310-311, and gates 350 in the NMOSFET enclose fins 320-321. The source / drain contacts (which establish the electrical connection with the source / drains of the FinFETs) are also shown in the layout in the top view of Figure 1A. Fig. Figure 6B shows some examples of which are labelled here as source contacts 370 and drain contacts 380. It is understood that silicide layers can form on the source / drain regions and that the source / drain contacts can form on the silicide layers.

[0040] According to the various aspects of the present disclosure, a variety of isolation transistors are implemented between adjacent cells to establish electrical isolation between the neighboring circuit cells. More specifically, the PMOSFET isolation transistors comprise gates 400 and the NMOSFET isolation transistors comprise gates 410. Gates 400-410 are each located at a boundary between two adjacent circuit cells, for example, at the boundary between the inverter cell and the NAND cell, at the boundary between the NAND cell and the NOR cell, etc. The gates 400 of the PMOSFET isolation transistors are each connected to a voltage source Vdd, and the gates 410 of the NMOSFET isolation transistors are each connected to a voltage source Vss.

[0041] In the PMOSFET isolation transistors, their gates 400 enclose the fins 310-311, which feature the SiGe channels. The source region of the PMOSFET isolation transistor corresponds to the P-source / drain region of one of the PMOSFET transistors in the standard cells, and the drain region of the PMOSFET isolation transistor corresponds to the P-source / drain region of another of the PMOSFET transistors in the standard cells. Similarly, in the NMOSFET isolation transistors, their gates 410 enclose the fins 320-321, which feature Si channels. The source region of the NMOSFET isolation transistor matches the N-source / drain region of one of the NMOSFET transistors of the standard cells, and the drain region of the NMOSFET isolation transistor matches the N-source / drain region of another of the NMOSFET transistors of the standard cells.

[0042] At least partially due to their position (e.g., that the gates 410 are located on the circuit cell boundaries) and their electrical configuration (e.g., that the gates 410 are electrically connected to Vdd), the PMOSFET isolation transistors provide electrical isolation between adjacent circuit cells for the PMOSFET, for example, between the inverter cell and the NAND cell or between the NAND cell and the NOR cell. Similarly, the NMOSFET isolation transistors provide electrical isolation between adjacent circuit cells for the NMOSFET, for example, between the inverter cell and the NAND cell or between the NAND cell and the NOR cell.

[0043] The cross-sectional side view of Fig. 6C is created by cutting along a cutting line 450 in the N-trough area of ​​the top view of the standard cell layout of Fig. Received 6B. As in Fig. As shown in Figure 6C, the standard cell has an N-well formed in a silicon substrate. The continuous fin 310 is formed over the N-well. A variety of source and drain regions (including a common node) are formed in the fin 310, and a variety of gates are formed over the fin 310. Some of these gates are the gates 400 of the isolation transistors described above. A variety of contacts (CO) are formed over the source and drain regions to establish electrical connections with them.

[0044] Fig. Figure 7A shows a circuit diagram for a single-port SRAM cell 500 and Fig. Figure 7B shows the corresponding layout in a top view of the single-port SRAM cell 500 according to embodiments of the present disclosure. The single-port SRAM cell 500 comprises pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass-gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are P-transistors, such as the P-FinFETs described above, and transistors PG1, PG2, PD1, and PD2 are the N-FinFETs described above.

[0045] The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data flip-flop. The gates of transistors PU2 and PD2 are coupled to each other and to the drains of transistors PU1 and PD1 to form a first memory node SN1, and the gates of transistors PU1 and PD1 are coupled to each other and to the drains of transistors PU2 and PD2 to form a complementary first memory node SNB1. The sources of pull-up transistors PU1 and PU2 are connected to a supply voltage CVdd, and the sources of pull-down transistors PD1 and PD2 are connected to a ground voltage CVss.

[0046] The first memory node SN1 of the first data flip-flop is coupled via a bit line BL through the pass-gate transistor PG1, and the complementary first memory node SNB1 is coupled via a complementary bit line BLB through the pass-gate transistor PG2. The first memory node SN1 and the complementary first memory node SNB1 are complementary nodes that often operate at opposite logic levels (logic high or logic low). The gates of the pass-gate transistors PG1 and PG2 are coupled via a word line WL.

[0047] As shown in the layout in the top view of Fig. As shown in Figure 7B, the single-port SRAM cell 500 comprises a variety of fins 510-513 (also referred to as the active area or OD). The N-fins 510 and 513 are made of a non-germanium semiconductor material, such as silicon. The P-fins 511-512 are made of silicon-germanium to improve the voltage effect.

[0048] Similar to the above with reference to Fig. In the SRAM cells described in section 5, fins 510 and 513, which lie above a P-shaped basin area of ​​SRAM cell 500, extend continuously in the X-direction, whereas fins 511 and 512, which lie above an N-shaped basin area of ​​SRAM cell 500, extend intermittently in the X-direction. In other words, fins 511 and 512 each extend partially into SRAM cell 500, but not completely through it. According to the Fig. In the embodiment shown in Figure 7B, fin 511 extends into SRAM cell 500 from the "bottom" of SRAM cell 500 and terminates in SRAM cell 500 on the drain side of pull-up transistor PU1. Fin 512 extends into SRAM cell 500 from the "top" of SRAM cell 500 and terminates in SRAM cell 500 on the drain side of pull-up transistor PU2. This type of configuration prevents data node leakage current between the drain nodes of adjacent pull-up transistors.

[0049] Fig. Figure 8A shows a cross-sectional side view of two adjacent SRAM cells 500A-500B and Fig. Figure 8B shows the corresponding layout of the two adjacent SRAM cells 500A-500B in a top view according to embodiments of the present disclosure. The SRAM cells 500A and 500B are each identical to the SRAM cell 500 in the Fig. 7A-7B configured. In Fig. 8B is the SRAM cell 500A "inverted" and connected to the SRAM cell 500B, which is not inverted. In other words, the SRAM cells 500A and 500B are arranged symmetrically around an axis 520.

[0050] As above with reference to Fig. As described in Figure 7B, the NMOSFET fins 510 and 513 (located above the P-well region) extend continuously through at least the two SRAM cells 500A-500B. In contrast, the SRAM cells 500A-500B have discontinuous PMOSFET fins. For example, fins 511A-511B are PMOSFET fins located above the N-well region and contain SiGe components. Fin 511A extends partially into SRAM cell 500A but not into SRAM cell 500B, fin 512 extends partially (but not completely) into both SRAM cells 500A and 500B, and fin 511B extends partially into SRAM cell 500B but not into SRAM cell 500A. Fins 511A, 512, and 511B are not connected to each other. The interrupted fins 511A-511B and 512 each terminate in the drain side of the pull-up transistors PU1 or PU2. As above with reference to Fig. As described in 7B, this type of interrupted fin layout is used here to prevent or reduce data node leakage current between the drain node of the pull-up transistor of an SRAM cell 500A and the drain node of the pull-down transistor of an adjacent SRAM cell 500B.

[0051] The cross-sectional side view, which is in Fig. As shown in 8A, this is achieved by cutting the top view of Fig. 8B is obtained along a section line 530. Due to the position of the section line 530, the fin 512 is visible in the section view of Fig. Figure 8A shows the fin 512 located above an N-shaped well formed in / over a substrate. Source and drain regions are formed within the fin 512, and gates for the pull-up transistors PU1 and PU2 are formed above the fin 512. Contacts (Co) are formed over the source and drain regions to establish electrical connections. The interrupted structure of the PMOSFET fins is shown in Fig. 8A, because fin 512 does not extend fully laterally; for example, it does not extend fully under gates 550 and 551. As also in Fig. As shown in Figure 8A, both ends of fin 512 terminate on their respective sides of the drains.

[0052] Another aspect of the present disclosure concerns several exit working metals for the standard cells and the SRAM cells. This is explained in more detail in the Fig. 9A and Fig. 9B shown, where Fig. 9A is a schematic partial cross-sectional side view of a CMOSFET device 700 in a standard cell (e.g. as part of the standard cell array 100 described above) and Fig. Figure 9B is a schematic partial cross-sectional side view of a CMOSFET device 701 in an SRAM cell (e.g., as part of the SRAM cell array 100 described above). It is understood that the cross-sectional side views of the Fig. 9A and Fig. 9B by cutting along the Y direction in Fig. 1A will be obtained. The PMOS and NMOS sections of the CMOSFET devices 700-701 are in the Fig. 9A and Fig. Marked 9B.

[0053] The CMOSFET devices 700-701 each comprise a dielectric insulation structure 710, for example, a shallow trench insulation (STI). The STD cell CMOSFET device 700 comprises fin structures 720 and 721, which are vertically (e.g., in the Z-direction of Fig. 1A) protrude from the dielectric insulation structure 710. The fin structure 720 is part of the PMOS of the STD cell CMOSFET device 700, and the fin structure 721 is part of the NMOS of the STD cell CMOSFET device 700. The SRAM cell CMOSFET device 701 comprises fin structures 730 and 731, which extend vertically (e.g., in the Z-direction of Fig. 1A) protrude from the dielectric insulation structure 710. The fin structure 730 is part of the PMOS of the SRAM cell CMOSFET device 701, and the fin structure 731 is part of the NMOS of the SRAM cell CMOSFET device 701. As described above, the fin structures 720 and 730 for the PMOS comprise silicon germanium (SiGe), whereas the fin structures 721 and 731 for the NMOS comprise semiconductor material without germanium, such as silicon (Si). The channel regions of the CMOSFET devices 700 and 701 are formed in the fin structures 720-721 and 730-731.

[0054] The CMOSFET device 700 comprises a gate dielectric layer 740 formed over the dielectric insulation structure 710 and over the fin structures 720-721, and the CMOSFET device 701 comprises a gate dielectric layer 750 formed over the dielectric insulation structure 710 and over the fin structures 730-731. In some embodiments, the gate dielectric layers 740 and 750 comprise silicon oxynitride, silicon nitride, or silicon oxide. In other embodiments, the gate dielectric layers 740 and 750 comprise a high-k dielectric material, which is a material with a dielectric constant greater than that of SiO2. In one embodiment, the high-k dielectric material comprises hafnium oxide (HfO2), which has a dielectric constant in the range of about 18 to about 40.In alternative embodiments, the high-k dielectric material can include ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HdO, HfAlO, HeO, HfTiO, HfTaO or SrTiO.

[0055] A P-type output function metal layer 760 is formed over the gate dielectric layer 740 in the PMOS region of the CMOSFET device 700, and an N-type output function metal layer 761 is formed over the gate dielectric layer 740 in the NMOS region of the CMOSFET device 700. Simultaneously, a P-type output function metal layer 770 is formed over the gate dielectric layer 750 in the PMOS region of the CMOSFET device 701, and an N-type output function metal layer 771 is formed over the gate dielectric layer 750 in the NMOS region of the CMOSFET device 701.

[0056] In some embodiments, the P-exit work metal layers 760 and 770 each comprise a metal material that is titanium nitride (TiN) or tantalum nitride (TaN). It is understood that additional metal layers may be stacked on top of the P-exit work metal layers 760 and 770. In some embodiments, the N-exit work metal layers 761 and 771 each comprise a metal material that is titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum-aluminum (TaAl), tantalum-aluminum nitride (TaAlN), tantalum-aluminum carbide (TaAlC), or tantalum-carbon nitride (TaCN).

[0057] As in the Fig. 9A and Fig. As shown in Figure 9B, the P-outflow metal layer 760 has a thickness of 780 and the P-outflow metal layer 770 has a thickness of 790. The thickness 780 is greater than the thickness 790. In some embodiments, the thickness 790 is in a range between about 5 angstroms and about 80 angstroms, and the thickness 780 is in a range between about 5 angstroms and about 30 angstroms. The different thicknesses result in the P-outflow metal layer 760 having a lower threshold voltage Vt than the P-outflow metal layer 770. In some embodiments, the threshold voltage Vt associated with the P-outflow metal layer 760 is 50 mV to 200 mV lower than the threshold voltage Vt associated with the P-outflow metal layer 770.

[0058] The N-exit work metal layer 761 has a lower threshold stress Vt than the N-exit work metal layer 771. This lower threshold stress Vt is achieved by adjusting the aluminum content of the exit work layers 761 and 771. The exit work metal layer 761 has a higher aluminum content (e.g., in the TaAl or TiAl compound) than the exit work metal layer 771. In some embodiments, the aluminum concentration for the two layers 761 and 771 is in the range between about 2% and about 50%, although it is clear that the aluminum concentration for layer 761 is still higher than for layer 771.In some embodiments, by adjusting the aluminum content for the output-work metal layers 761 and 771 differently, the threshold voltage Vt corresponding to the N output-work metal layer 761 is 50 mV to 200 mV lower than the threshold voltage Vt corresponding to the N output-work metal layer 771. As such, the SRAM CMOSFET has a higher threshold voltage Vt than the logic circuit CMOSFET (for both the PMOS and NMOS). This is desirable because SRAM cells typically require a higher threshold voltage Vt than standard logic circuit cells.

[0059] A filler metal 800 is also formed over the output metals 760-761 and 770-771. The filler metal 800 serves as the essential conductive section of the gate electrode. In some embodiments, the filler metal 800 comprises tungsten (W). In other embodiments, the filler metal 800 comprises aluminum (Al). The output metal layers 760-761 and 770-771 and the filler metal 800 together form the metal gate electrode for the CMOSFET. A dielectric layer 810 also surrounds the metal gate electrode. In some embodiments, the dielectric layer 810 comprises a low-k dielectric material.

[0060] Fig. Figure 10 is a schematic partial cross-sectional side view of a portion of a connection structure 850 according to embodiments of the present disclosure. The connection structure 850 can be used to connect the elements of the standard cells or SRAM cells described above. As shown in Fig. As shown in Figure 10, the interconnect structure 850 comprises a variety of metal layers, for example, metal layers M1, M2, M3, and M4. Insulation structures such as shallow trench insulation (STI) are formed within the substrate. A variety of gates are formed across the substrate. Conductive contacts (Co) are formed across the substrate and across the gates. Some of these contacts are butted contacts (BTC). A variety of vias (such as via0, via1, via2, via3) provide electrical connections between the metal layers and the gates (and other components such as source / drain).

[0061] Fig.Figure 11 is a flowchart illustrating a method 900 according to an embodiment of the present disclosure. The method 900 comprises a step 910 in which one or more continuous first fins are formed in a logic circuit cell array comprising a plurality of logic circuit cells adjacent to one another in a first direction. The one or more continuous first fins are formed such that they each extend over at least three of the adjacent logic circuit cells in the first direction.

[0062] Method 900 comprises a step 920 in which interrupted second fins are formed in a static random-access memory (SRAM) cell array comprising a plurality of SRAM cells adjacent to one another in the first direction. The interrupted second fins each extend into at most two of the adjacent SRAM cells.

[0063] In some embodiments, all interrupted second fins extend in the first direction over at most two of the adjacent SRAM cells.

[0064] In some embodiments, the interrupted second fins comprise at least: a first segment extending partially into a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell; a second segment extending partially into the second SRAM cell and a third SRAM cell adjacent to the second SRAM cell; and a third segment extending partially into the third SRAM cell and a fourth SRAM cell adjacent to the third SRAM cell. In some embodiments, the first segment is separated from the third segment in the first direction by a first gap, the second segment is separated from the first segment or the third segment in a second direction by a second gap, the second direction being different from the first direction, and the first gap extending across a boundary between the second SRAM cell and the third SRAM cell.

[0065] In some embodiments, the SRAM cell array comprises PMOSFETs and NMOSFETs; and the interrupted second fins are fins for the PMOSFETs. In some embodiments, the SRAM cell array comprises one or more continuous third fins for the NMOSFETs. In some embodiments, all continuous third fins extend in the first direction over at least three of the adjacent SRAM cells. In some embodiments, the interrupted second fins each comprise silicon-germanium; and the continuous third fins each comprise a semiconductor material without germanium.

[0066] In some embodiments, each of the SRAM cells includes a pull-up transistor; and each of the interrupted second fins terminates in a drain of the pull-up transistor.

[0067] In some embodiments, the logic circuit cell array further comprises one or more isolation transistors, each located between two associated adjacent logic circuit cells; and each of the isolation transistors is configured to provide electrical isolation between the two associated adjacent circuit cells. In some embodiments, the isolation transistors comprise a PMOSFET isolation transistor and an NMOSFET isolation transistor; one gate of the PMOSFET isolation transistor is electrically connected to a Vdd voltage source; and one gate of the NMOSFET isolation transistor is electrically connected to a Vss ground. In some embodiments, each of the isolation transistors comprises an associated gate located at a respective boundary between two adjacent logic circuit cells.

[0068] In some embodiments, the logic circuit cell array and the SRAM cell array each comprise an NMOSFET and a PMOSFET; a gate of the PMOSFET of the logic circuit cell array comprises a first exit work metal; a gate of the PMOSFET of the SRAM cell array comprises a second exit work metal; a gate of the NMOSFET of the logic circuit cell array comprises a third exit work metal; a gate of the NMOSFET of the SRAM cell array comprises a fourth exit work metal; and at least one of the first, second, third, and fourth exit work metals is distinct from the remainder of the first, second, third, and fourth exit work metals. In some embodiments, the first exit work metal is thicker than the second exit work metal. In some embodiments, the third exit work metal has a higher aluminum content than the fourth exit work metal.

[0069] It is understood that additional procedures may be performed before, during, or after steps 910-920 of procedure 900. For the sake of simplicity, these steps are not described in detail here.

[0070] Based on the above descriptions, it is evident that the present disclosure offers advantages over conventional FinFET SRAM devices. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, nor is any particular advantage required for all embodiments. One advantage is that the interrupted PMOS fins for the SRAM reduce the voltage effect, which suppresses the ion current. The reduction in ion current improves the SRAM write areas. Simultaneously, the fins for the logic circuit cells are continuous. The continuous fins result in faster chip speeds. Another advantage is that the isolation transistors are implemented to provide electrical isolation between adjacent cells.Another advantage is the implementation of multiple work-effect metals for the logic circuit cells and the SRAM cells. The content and / or thickness of these work-effect metals are configured to give the SRAM MOSFETs a higher threshold voltage (Vt) than the logic circuit MOSFETs, which is also desirable. Other advantages include compatibility with existing manufacturing processes and ease of implementation.

[0071] One aspect of the present disclosure relates to an integrated circuit (IC) chip. The IC chip comprises a logic cell array and a static random-access memory (SRAM) array. The logic cell array comprises a plurality of logic cells adjacent to one another in a first direction. The logic cell array includes one or more continuous first fins, each extending over at least three of the adjacent logic cells in the first direction. The static random-access memory (SRAM) cell array comprises a plurality of SRAM cells adjacent to one another in the first direction. The SRAM cell array includes discontinuous second fins. The first and second fins each comprise a channel region as well as source / drain regions.The logic circuit cell array further comprises one or more isolation transistors, each located between two associated adjacent logic circuit cells, and a gate of each of the isolation transistors is electrically connected to a voltage source, such that each of the isolation transistors is configured to provide electrical isolation between the two associated adjacent circuit cells.

[0072] Another aspect of the present disclosure relates to a semiconductor device. A plurality of logic circuit cells are arranged adjacent to one another in a first direction. The first fin extends continuously over at least three of the logic circuit cells in the first direction. A plurality of static random-access memory (SRAM) cells are arranged adjacent to one another in the first direction. A plurality of second fins each extend over at most two of the SRAM cells. The second fins are separated from each other. The second fins are PMOS fins. The second fins each comprise silicon germanium. The first and second fins each comprise a channel region as well as source / drain regions.The semiconductor device further comprises a plurality of PMOS isolation transistors and NMOS isolation transistors, each comprising a gate located at a boundary between two respective adjacent logic circuit cells. The gate of each of the PMOS isolation transistors is electrically connected to a Vdd voltage source, and the gate of each of the NMOS isolation transistors is electrically connected to a Vss voltage source, such that the NMOS isolation transistors and the PMOS isolation transistors each provide electrical isolation between their respective adjacent circuit cells.

[0073] A further aspect of the present disclosure relates to a method. One or more continuous first fins are formed in a logic circuit cell array comprising a plurality of logic circuit cells adjacent to one another in a first direction. The one or more continuous first fins are formed such that each extends over at least three of the adjacent logic circuit cells in the first direction. Interrupted second fins are formed in a static random-access memory (SRAM) cell array comprising a plurality of SRAM cells adjacent to one another in the first direction. The interrupted second fins each extend over at most two of the adjacent SRAM cells.The first and second fins each comprise a channel region as well as source / drain regions, and the logic circuit cell array further comprises one or more isolation transistors, each located between two associated adjacent logic circuit cells. One gate of each isolation transistor is electrically connected to a voltage source, so that each isolation transistor is configured to provide electrical isolation between the two associated adjacent circuit cells.

[0074] The foregoing describes features of several embodiments so that a person skilled in the art can better understand the following detailed description. The person skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced here. For example, different resistances for the conductors can be achieved by implementing different thicknesses for the bit line conductor and the word line conductor. However, other techniques for changing the resistance of the metal conductors can also be used.

Claims

[1] Integrated circuit (IC) chip, comprising: a logic circuit cell array (100) comprising a plurality of logic circuit cells (131-140) adjacent to each other in a first direction, wherein the logic circuit cells (131-140) have one or comprising several continuous first fins (110, 111, 310, 311), each extending over at least three of the adjacent logic circuit cells (131-140) in the first direction; and a static random access memory (SRAM) cell array (200) comprising a plurality of SRAM cells (210-217, 500, 500A, 500B) adjacent to each other in the first direction, wherein the SRAM cell array (200) comprises discontinuous second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B), wherein the first and second fins (110, 111, 220-224, 230-234, 310, 311, 511, 511A, 511A, 512, 512A, 512B) each comprise a channel area as well as source / drain areas, and wherein the logic circuit cell array (100) further comprises one or more isolation transistors, each located between two associated adjacent logic circuit cells (131-140); and a gate (400, 410) of each of the isolation transistors is electrically connected to a voltage source (Vdd, Vss) such that each of the isolation transistors is configured to provide electrical isolation between the two associated adjacent circuit cells (131-140), wherein: the logic circuit cell array (100) and the SRAM cell array (200) each comprise one NMOSFET and one PMOSFET; a gate of the PMOSFET of the logic circuit cell array (100) comprises a first exit work metal (760); a gate of the PMOSFET of the SRAM cell array (200) comprises a second exit working metal (770); a gate of the NMOSFET of the logic circuit cell array (100) includes a third exit working metal (761); a gate of the NMOSFET of the SRAM cell array (200) comprises a fourth exit working metal (771); and at least one of the first, second, third and fourth exit metal (760, 761, 770, 771) differs from a residue of the first, second, third and fourth exit metal (760, 761, 770, 771), wherein the first exit work metal (760) is thicker than the second exit work metal (770), and wherein the third exit work metal (761) has a higher aluminium content than the fourth exit work metal (771). [2] IC chip according to claim 1, wherein each of the interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) extends over at most two of the adjacent SRAM cells (210-217, 500, 500A, 500B) in the first direction. [3] IC chip according to claim 1 or 2, wherein the interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) comprise at least: a first segment (221) that partially extends into a first SRAM cell (210) and a second SRAM cell (211) that adjoins the first SRAM cell (210); a second segment (222) that extends partially into the second SRAM cell (211) and a third SRAM cell (212) that adjoins the second SRAM cell (211); and a third segment (223) that extends partially into the third SRAM cell (212) and a fourth SRAM cell (213) that adjoins the third SRAM cell (212); and whereby: the first segment (221) is separated from the third segment (223) in the first direction by a first gap (252); the second segment (222) is separated from the first segment (221) or the third segment (223) in a second direction by a second gap, wherein the second direction is different from the first direction; and the first gap (252) extends over a boundary between the second SRAM cell (211) and the third SRAM cell (212). [4] IC chip according to any of the preceding claims, wherein: the SRAM cell array comprises (200) PMOSFETs and NMOSFETs; and the interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) are fins for the PMOSFETs. [5] IC chip according to any of the preceding claims, wherein the SRAM cell array (200) comprises one or more continuous third fins (240-243, 510, 513) for the NMOSFETs. [6] IC chip according to any of the preceding claims, wherein all continuous third fins (240-243, 510, 513) extend in the first direction over at least three of the adjacent SRAM cells (210-217, 500, 500A, 500B). [7] IC chip according to any one of the preceding claims, wherein: the interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) each contain silicon-germanium; and the continuous third fins (240-243, 510, 513) each have a semiconductor material without germanium. [8] IC chip according to any one of the preceding claims, wherein: Each of the SRAM cells (210-217, 500, 500A, 500B) includes a pull-up transistor; and Each of the interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) terminates in a drain of the pull-up transistor. [9] IC chip according to any one of the preceding claims, wherein: The isolation transistors include a PMOSFET isolation transistor and an NMOSFET isolation transistor; a gate (400) of the PMOSFET isolation transistor is electrically connected to a Vdd voltage source; and a gate (410) of the NMOSFET isolation transistor is electrically connected to a Vss ground. [10] IC chip according to one of the preceding claims, wherein each of the isolation transistors comprises an associated gate (400, 410) located at a respective boundary between two adjacent logic circuit cells (131-140). [11] Semiconductor device comprising: a plurality of logic circuit cells (131-140) arranged adjacent to one another in a first direction; a first fin (110, 111, 310, 311) which extends continuously over at least three of the logic circuit cells (131-140) in the first direction; a large number of static random access memory (SRAM) cells (210-217, 500, 500A, 500B) arranged adjacent to each other in the first direction; and a multitude of second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) which are located in at most two of the SRAM cells (210-217, 500, 500A, extend to 500B); where: the second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) are separated from each other; the second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) are PMOS fins; and the second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) each have silicon germanium, wherein the first and second fins (110, 111, 220-224, 230-234, 310, 311, 511, 511A, 511A, 512, 512A, 512B) each comprise a channel region as well as source / drain regions, and the semiconductor device further comprises: a plurality of PMOS isolation transistors and NMOS isolation transistors, each comprising a gate (400, 410) located at a boundary between two respective adjacent logic circuit cells (131-140); where: the gate (400) of each of the PMOS isolation transistors is electrically connected to a Vdd voltage source; and the gate (410) of each of the NMOS isolation transistors is electrically connected to a Vss voltage source, such that the NMOS isolation transistors and the PMOS isolation transistors each provide electrical isolation between the respective adjacent logic circuit cells (131-140), wherein: the logic circuit cells (131-140) and the SRAM cells (210-217, 500, 500A, 500B) each comprise one NMOS and one PMOS; a gate of the PMOS of the logic circuit cells comprises a first exit working metal (760); a gate of the PMOS of the SRAM cells (210-217, 500, 500A, 500B) includes a second exit working metal (770); a gate of the NMOS logic circuit cells (131-140) includes a third exit working metal (761); a gate of the NMOS of the SRAM cells (210-217, 500, 500A, 500B) includes a fourth exit working metal (771); the first exit work metal (760) is thicker than the second exit work metal (770); and the third exit metal (761) has a higher aluminium content than the fourth exit metal (771). [12] Semiconductor device according to claim 11, further comprising: a third fin (240-243, 510, 513) extending continuously over at least three of the SRAM cells (210-217, 500, 500A, 500B) in the first direction, wherein the third fin (240-243, 510, 513) comprises silicon but no germanium. [13] Semiconductor device according to claim 11 or 12, wherein: Each of the SRAM cells (210-217, 500, 500A, 500B) includes a pull-up transistor; and Each of the second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) terminates in a drain of the pull-up transistor. [14] Procedures, including: Training one or more continuous first fins (110, 111, 310, 311) in a logic circuit cell array (100) comprising a plurality of logic circuit cells (131-140) adjacent to one another in a first direction, wherein the one or more continuous first fins (110, 111, 310, 311) are configured to each extend over at least three of the adjacent logic circuit cells (131-140) in the first direction; and Forming interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) in a static random access memory (SRAM) cell array (200) comprising a plurality of SRAM cells (210-217, 500, 500A, 500B) comprising adjacent fins in the first direction, wherein the interrupted second fins (220-224, 230-234, 511, 511A, 511A, 512, 512A, 512B) each extend into at most two of the adjacent SRAM cells (210-217, 500, 500A, 500B), the first and second fins (110, 111, 220-224, 230-234, 310, 311, 511, 511A, 511A, 512, 512A, 512B) each comprise a channel area as well as source / drain areas, and wherein the logic circuit cell array (100) further comprises one or more isolation transistors, each located between two associated adjacent logic circuit cells (131-140); and a gate (400, 410) of each of the isolation transistors is electrically connected to a voltage source (Vdd, Vss) such that each of the isolation transistors is configured to provide electrical isolation between the two associated adjacent circuit cells (131-140), wherein: the logic circuit cell array (100) and the SRAM cell array (200) each comprise one NMOSFET and one PMOSFET; a gate of the PMOSFET of the logic circuit cell array (100) comprises a first exit work metal (760); a gate of the PMOSFET of the SRAM cell array (200) comprises a second exit working metal (770); a gate of the NMOSFET of the logic circuit cell array (100) includes a third exit working metal (761); a gate of the NMOSFET of the SRAM cell array (200) comprises a fourth exit working metal (771); and at least one of the first, second, third and fourth exit metal (760, 761, 770, 771) differs from a residue of the first, second, third and fourth exit metal (760, 761, 770, 771), wherein the first exit work metal (760) is thicker than the second exit work metal (770), and wherein the third exit work metal (761) has a higher aluminium content than the fourth exit work metal (771).

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