Devices with back metal structures and methods for their manufacture

Abstract

A method for manufacturing a semiconductor device, comprising: Forming trenches (11) filled with sacrificial material, wherein the trenches (11) extend from a first side into a semiconductor substrate (10); Formation of an epitaxial layer (14) over the first side of the semiconductor substrate (10) and the trenches (11); from one of the second sides of the semiconductor substrate opposite the first side (10), removal of the sacrificial material in the trenches (11); and Filling the trenches (11) with a conductive material (17), wherein an upper part of the trenches (11) is filled with the epitaxial layer (14) and a lower part of the trenches (11) is filled with the conductive material (17).

Description

TECHNICAL AREA

[0001] The present invention relates generally to a semiconductor process and, in certain embodiments, to devices with rear-facing metal structures and methods for their manufacture. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic and other applications. Well-defined and highly stable oxide and metal structures are essential for the fabrication of semiconductor devices. One particularly useful oxide structure is a buried oxide (BOX) structure, which is an oxide structure embedded within a semiconductor substrate. BOX structures can be used, for example, as insulating layers and etch stops. A common substrate for the formation of BOX structures is a silicon-on-insulator (SOI) wafer. SOI wafers have a BOX layer sandwiched between semiconductor layers, but they have high fabrication costs due to additional wafer processing, such as separation by oxygen implantation (SIMOX) or smart-cut processes. It is desirable to provide an improved method for fabricating a semiconductor device.The state of the art can be found in US 2013 / 0 299 950 A1 and US 2015 / 0 048 476 A1. SUMMARY

[0003] The problem is solved by the teachings of the independent claims. Further embodiments are defined in the dependent claims. According to one embodiment of the present invention, a method for manufacturing a semiconductor device comprises forming trenches filled with a sacrificial material. The trenches extend from a first side into a semiconductor substrate. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate, opposite the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

[0004] According to another embodiment of the present invention, a method for fabricating a semiconductor device comprises forming trenches filled with a conductive material. The trenches extend from a first side into a semiconductor substrate. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. The semiconductor substrate is thinned from a second side of the semiconductor substrate opposite the first side to expose the conductive material. A back-side contact material layer is deposited over the conductive material from the second side.

[0005] According to another embodiment of the present invention, a method for fabricating a semiconductor device comprises forming trenches in a semiconductor substrate from a first side. The semiconductor substrate comprises a second side opposite the first side. The trenches are oxidized to form an oxide lining. A filler material is deposited using a chemical vapor deposition process. The filler material and the underlying oxide lining are etched to expose an upper surface, or top surface, of the semiconductor substrate at the first side. The etching removes portions of the filler material and the oxide lining from the upper regions of the trenches.

[0006] Device areas are formed above the semiconductor substrate. The semiconductor substrate is thinned from the second side. The filler material and oxide lining are removed from the interior of the trench. The trench is filled with a contact metal.

[0007] According to another embodiment of the present invention, a semiconductor device comprises a trench extending through a semiconductor substrate. An epitaxial layer is arranged over a first side of the semiconductor substrate. The epitaxial layer partially fills a region of the trench. A back-side metal layer is arranged over a second side of the semiconductor substrate. The back-side metal layer extends into the trench and fills the remaining region of the trench, where the epitaxial layer partially filling the trench contacts the back-side metal layer, which fills the remaining region in the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions, which are made in conjunction with the accompanying drawings, in which: Fig. 1 illustrates a cross-sectional view of a semiconductor device with rear-side metal structures according to an embodiment of the present invention; Fig. 2 illustrates a cross-sectional view of an alternative embodiment of a semiconductor device with rear-side metal structures; Fig. 3A and Fig. 3B illustrates a semiconductor device with a plurality of devices on a single substrate according to an embodiment of the present invention, wherein Fig. 3A illustrates a cross-sectional view and Fig. 3B illustrates a sectional view from above; Fig. Figure 4 illustrates a cross-sectional view of a semiconductor device with rear-side metal structures according to an alternative embodiment of the present invention; Fig. 5 illustrates a cross-sectional view of yet another alternative embodiment of the semiconductor device with rear-side metal structures; Fig. Figure 6 illustrates a cross-sectional view of an embodiment of a semiconductor device with rear-side metal structures; Fig. Figure 7 illustrates a cross-sectional view of an alternative embodiment of a semiconductor device with rear-side metal structures; Fig. Figures 8A - 8D and 9A - 9H illustrate an embodiment for forming a substrate with rear metal structures using BOX structures according to an embodiment of the present invention. where Fig. Figure 8A illustrates a cross-sectional view of a substrate after the formation of deep trenches, where Fig. Figure 8B illustrates an embodiment of a top view of the substrate after the formation of deep trenches, where Fig. Figure 8C illustrates an alternative embodiment of a top view of the substrate after the formation of deep trenches, where Fig. Figure 8D illustrates another alternative embodiment of a top view of the substrate after the formation of deep trenches, where Fig. Figure 9A illustrates a cross-sectional view of the substrate after the formation of a lining, where Fig. Figure 9B illustrates a cross-sectional view of the substrate after the formation of a filler layer, where Fig. Figure 9C illustrates a cross-sectional view of the substrate after a polishing process that removes part of the filler layer and lining. where Fig. Figure 9D illustrates a cross-sectional view of the substrate after the formation of a first epitaxial layer. where Fig. Figure 9E illustrates a cross-sectional view of the substrate after the formation of a second epitaxial layer, where Fig. Figure 9F illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using a backside etching step. where Fig. Figure 9G illustrates a cross-sectional view of the substrate after removal of the BOX structures using a backside etching step, and where Fig. Figure 9H illustrates a cross-sectional view of the substrate after deposition of a metal layer according to an embodiment of the present invention; Fig. Figures 10A - 10C illustrate an alternative embodiment for forming a substrate with rear-side metal structures using BOX structures according to an embodiment of the present invention. where Fig. Figure 10A illustrates a cross-sectional view of a substrate with BOX structures after exposure of the BOX structures using a chemical-mechanical planarization step (CMP). where Fig. Figure 10B illustrates a cross-sectional view of the substrate after removal of BOX structures using an etching step, and where Fig. Figure 10C illustrates a cross-sectional view of the substrate after deposition of metal layers; Fig. Figures 11A - 11C illustrate an alternative embodiment for forming BOX structures according to embodiments of the present invention. where Fig. Figure 11A illustrates a cross-sectional view of a substrate with deep trenches filled with a filler material. where Fig. Figure 11B illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using an etching step, and where Fig. Figure 11C illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using a CMP step; Fig. Figures 12A - 12C illustrate an alternative embodiment for forming BOX structures according to embodiments of the present invention. where Fig. Figure 12A illustrates a cross-sectional view of a substrate with deep trenches filled with a lining and a fill layer, and exhibiting a void within the fill layer. where Fig. Figure 12B illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using an etching step, and where Fig. Figure 12C illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using a CMP step; and Fig. Figures 13A - 13D illustrate a semiconductor device during a manufacturing process according to an alternative embodiment of the present invention. DETAILED DESCRIPTION OF ILLUSTRATIVE FORMATIONS

[0009] It is advantageous to form BOX structures using bulk substrates instead of, for example, SOI substrates to reduce manufacturing costs. However, many of the methods for forming buried oxide (BOX) structures on conventional bulk semiconductor wafers have various disadvantages and limitations.

[0010] One method for forming BOX structures on bulk semiconductor wafers involves first depositing the oxide onto the substrate, then lithographically structuring the oxide, and finally covering the oxide structures with epitaxial lateral overgrowth (ELO). In the case of oxide deposition followed by lithographic structuring, oxide structures are formed that exhibit sidewalls with significant topographic variation and a rough top surface. This high topographic variation of the sidewalls and rough surfaces increases the risk of crystal defect generation during the subsequent epitaxial lateral overgrowth (ELO) process. Furthermore, the height of the oxide features above the substrate necessitates extensive overgrowth, resulting in increased processing time.Another way to form BOX structures involves creating trenches in the substrate, then forming an oxide layer using thermal oxidation, and finally covering the oxide layer using ELO. In contrast, the process of thermally oxidizing the lower surface or bottom of the trenches produces very thin BOX structures, which then allow the sidewall oxide to be removed. The presence of a thermal oxide only in the trenches can also create mechanical stress, which can lead to distortion or curvature of the substrate. In both cases, the BOX structures are too thin to be used as an etch stop, while wet etching techniques are used to etch the substrate between the BOX structures.

[0011] Embodiments of the present invention improve the methods for forming BOX structures on bulk semiconductor wafers by means of novel processing methods described herein.

[0012] According to various embodiments, the present invention discloses various methods for forming BOX structures within a bulk substrate. The following description details the different embodiments. Exemplary embodiments for devices utilizing rear-facing metal structures are described using the Fig. 1-7 described. An embodiment for forming metal structures on the back side of the wafer by generating BOX structures using ELO processes and exposing the BOX structures with an etching step is described using the Fig. 8-9 described. An alternative embodiment for forming metal structures on the back side of the wafer using a chemical-mechanical planarization (CMP) step is described in Fig. 10. Additional embodiments for forming different types of BOX structures are described in Fig. 11 - 13 described.

[0013] Fig. Figures 1-3 illustrate semiconductor devices with rear-side metal structures according to embodiments of the present invention.

[0014] Fig. Figure 1 illustrates a cross-sectional view of an embodiment of a semiconductor device, while Fig. Figure 2 illustrates a cross-sectional view of an alternative embodiment of a semiconductor device.

[0015] The semiconductor device can, in various embodiments, include active and passive devices. The semiconductor device can be a power semiconductor device. Examples of power semiconductor devices include discrete PN diodes, Schottky diodes, junction-gate field-effect transistors, metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, insulated-gate bipolar transistors, depletion-enrichment metal-oxide-semiconductor field-effect transistors, lateral double-diffused metal-oxide-semiconductor field-effect transistors, and others. The power semiconductor devices can be wide-bandgap semiconductor devices such as silicon carbide and gallium nitride.

[0016] Referring to Fig. 1 and Fig. 2 The semiconductor devices comprise a lower contact 27, a first doped layer 24, a second doped layer 25, and an upper contact 29. In one embodiment, the first doped layer 24 and the second doped layer 25 have opposite types of doping, forming a pn junction at the interface between the first doped layer 24 and the second doped layer 25, and the device is a diode. In one embodiment, the second doped layer 25 forms a Schottky diode with the upper contact 29. In another embodiment, the second doped layer 25 forms a resistive contact with the upper contact 29.

[0017] The semiconductor device further comprises semiconductor spacers 20, which provide a structure for the lower contact 27 and stability for the device. However, they are not involved in the electrical functionality of the device. In one embodiment, the semiconductor spacers 20 are formed from the original semiconductor substrate during the fabrication of the device. In another embodiment, a single structured feature of the lower contact 27 provides contact with the first doped layer 24 as shown in Fig. 1 here. Accordingly, the semiconductor device of Fig. 1 a single contact surface with the first doped layer 24. In another embodiment, a plurality of structured projections of the lower contact 27, separated by semiconductor spacers 20, form a contact with the first doped layer 24 as in Fig. 2. In a further embodiment, the first doped layer 24 can be partially located between the spacers 20.

[0018] Fig. Figure 3A illustrates a cross-sectional view of an embodiment of semiconductor devices, which are a plurality of devices on a single substrate, while Fig. 3B a sectional view from above of the embodiment of the semiconductor devices of Fig. 3A illustrates this.

[0019] Referring to Fig. 3A and Fig. 3B is a process in which a multitude of semiconductor devices are fabricated on the same substrate in an array configuration. In one embodiment, the individual semiconductor devices share a lower contact 27 and have separate upper contacts 29. For example, the upper contacts 29 can include contacts to different regions of the device, such as gate contacts and source contacts, which must be isolated from each other. In another embodiment, the first doped layer 24 can be partially located between the spacers 20. Alternatively, the upper contacts 29 can be restricted due to limitations imposed by design rules associated with the upper metallization. A singulation process can be performed after completion of the fabrication steps for realizing the intended device structure. This can be achieved, for example, by cutting or laser treatment in the area between the different upper contacts.

[0020] Fig. Figures 4-5 illustrate an embodiment of semiconductor devices with rear-side metal structures according to embodiments of the present invention. Fig. Figure 4 illustrates a cross-sectional view of a trench-gate MOSFET device, while Fig. Figure 5 illustrates a cross-sectional view of an alternative embodiment of a trench-gate MOSFET device.

[0021] Referring to Fig. 4 and Fig. The semiconductor device comprises a lower contact 27, semiconductor spacers 20, a first doped layer 24, a second doped layer 25, and a plurality of upper contacts 29 as previously described. The semiconductor device further comprises a well region 22 arranged in the second doped layer 25. In one embodiment, the well region 22 has the opposite doping type to the second doped layer 25. A doped region 23 is also arranged within the well region 22. In another embodiment, the doped region 23 has the opposite doping type to the well region 22 and the same doping type as the second doped layer 25. Finally, a gate material 21 is arranged in the doped region 23 and the well region 22. The doped region 23 and the well region 22 are separated from the gate material 21 by an insulating layer 30.In one embodiment, the gate material 21 lies directly above a lower contact 27. Similar to other embodiments described previously, the first doped layer 24 may be partially located between the spacers 20.

[0022] In one embodiment, the first doped layer 24 and the second doped layer 25 are of the same doping type, and the device is a trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET). The trench-gate MOSFET can be a power semiconductor device. In an alternative embodiment, the first doped layer 24 and the second doped layer 25 are of opposite doping types, and the device is an insulated-gate, trench-gate bipolar transistor (IBGT).

[0023] Fig. Figures 6-7 illustrate an embodiment of semiconductor devices with rear-side metal structures according to embodiments of the present invention. Fig. Figure 6 illustrates a cross-sectional view of a planar MOSFET device, while Fig. Figure 7 illustrates a cross-sectional view of an alternative embodiment of a planar MOSFET device.

[0024] Referring to Fig. 6 and Fig. 7 The semiconductor device comprises a lower contact 27, semiconductor spacers 20, a first doped layer 24, a second doped layer 25, and a plurality of upper contacts 29 with a doped region 23 and a well region 22, as previously described. In contrast to previous embodiments, the semiconductor device further comprises an insulating layer 30 arranged on the doped region 23 and the well region 22 beneath an upper contact 29. In one embodiment, an upper contact 29 positioned above the insulating layer 30 forms the gate of a transistor.

[0025] Similar to previous embodiments, in one embodiment the device is a planar power MOSFET if the first doped layer 24 and the second doped layer 25 have the same doping type, and in an alternative embodiment the device is a planar IGBT if the first doped layer 24 and the second doped layer 25 have different doping types. Similar to other previously described embodiments, the first doped layer 24 may be partially located between the spacers 20.

[0026] Although the in Fig. The illustrated embodiments 1-7 are structures constructed using the material shown in Fig. The structural embodiments formed by the methods described in sections 10A - 10C also include structures corresponding to the Fig. 1 - 7, which use the in Fig. The methods described in 9A - 9H, 11A - 11C, 12A - 12C and 13A - 13C are formed.

[0027] Fig. Figures 8A - 8D and 9A - 9H illustrate an embodiment for forming a substrate with rear metal structures using BOX structures according to an embodiment of the present invention.

[0028] Fig. Figure 8A illustrates a cross-sectional view of a substrate after forming deep trenches according to an embodiment of the present invention.

[0029] Referring to Fig. 8A is a plurality of deep trenches 11 formed within a substrate 10. In various embodiments, the substrate 10 is a semiconductor substrate. The substrate 10 can, in various embodiments, be a silicon substrate, a germanium substrate, or a composite semiconductor substrate comprising indium antimonide, indium arsenide, indium phosphide, gallium nitride, gallium antimonide, gallium arsenide, silicon carbide, or combinations thereof. In various embodiments, the substrate 10 is a silicon substrate, and in one embodiment, it is highly doped. The highly doped substrate 10 can have a concentration of at least approximately 10 19 cm -3in silicon. In an alternative embodiment, the substrate 10 is a silicon wafer with a highly doped epitaxial layer on its top surface. In a further alternative embodiment, the substrate 10 is a silicon wafer that is highly doped by diffusion. For example, a doped layer is deposited over the undoped substrate, and the substrate is cured to allow the dopants to diffuse from the doped layer into the undoped substrate.

[0030] In various embodiments, the deep trenches 11 in the substrate 10 are formed using an etching process. In different embodiments, the etching process is a reactive ion etching (RIE) process, and in one embodiment, a deep RIE process such as the Bosch process. The deep trenches 11 can be formed with a high aspect ratio and nearly vertical, well-defined sidewalls. In some cases, the sidewalls can be re-entering at an angle between 88° and 90° with respect to the substrate surface or retrograde at an angle between 90° and 92° with respect to the substrate surface. In some embodiments, the etching process produces periodic, undulating sidewalls.

[0031] Fig. Figure 8B illustrates an embodiment of a top view of the substrate after the formation of the deep trenches, while Fig. 8C and Fig. Figure 8D illustrates alternative embodiments of a top view of the substrate after forming the deep trenches.

[0032] Referring to Fig. In 8A - 8D, the deep trenches 11 have a width d1, a length d2, and a height h. The width d1 is very narrow, and the height h is relatively large in various embodiments. In one embodiment, the height h is between 0.3 µm and 5 µm. In other embodiments, the width d1 can vary between 100 nm and 100 nm, and the height h can vary between 0.3 µm and 5 µm. The ratio h:d1 ranges from 1:2 to 1:50 in other embodiments. In one embodiment, the ratio of the horizontal width d1 to the vertical height h is approximately 1:10.

[0033] According to various embodiments, the shapes of the deep trenches 11, from a top-down perspective, are rectangles, squares, or lines as in Fig. 8B, Fig. Figures 8C and 8D illustrate this. The deep trenches 11 are separated from each other by a distance d3, which in some embodiments is similar to the width d1. In one embodiment, the ratio d1 : d2 is approximately 1:1. Alternatively, the ratio d1 : d2 is approximately 1:10, and in some embodiments on the order of 1:5000. According to one embodiment, the ratio d1 : d3 is approximately 1:1, and in some embodiments, the ratio d1 : d3 ranges from 1:3 to 1:10.

[0034] In one embodiment, the surface of the substrate 10 lies on the (100) plane, and the lateral direction is along the direction d1 (in Fig. 8B) runs along a

[100] direction. In an alternative embodiment, however, the lateral direction runs along the direction d1 (in Fig. 8B) along a

[110] direction.

[0035] Fig. Figure 9A illustrates a cross-sectional view of the substrate after forming a lining according to embodiments of the present invention.

[0036] Referring to Fig. In 9A, a lining 12 is formed on the surfaces of the substrate 10 and the deep trenches 11. The lining 12 is relatively thin with respect to the width d1 of the deep trenches 11, so that after the lining 12 is formed, an opening remains in the deep trenches 11. For example, the lining 12 can be between 1% and 20% of the width d1. In various embodiments, the lining 12 conforms to the surface and forms a layer on the surface of the substrate 10 and on the side walls and bottom surface of the deep trenches 11.

[0037] The lining 12 can be formed using a deposition process or a thermal process. In one embodiment, the lining 12 is formed using a thermal oxidation process by exposing the surface of the exposed substrate 10 to an oxidizing atmosphere. Alternatively, the lining 12 can be formed using thermal nitriding, chemical vapor deposition (CVD), plasma-enhanced CVD, chemical solution deposition, physical vapor deposition, and atomic layer deposition, although other deposition processes such as molecular beam epitaxy, sputtering, and spin or centrifugal coating can also be used in some embodiments. The lining 12 can be an oxide, a nitride, or another material in various embodiments.

[0038] Fig. Figure 9B illustrates a cross-sectional view of the substrate after the formation of a filler layer according to embodiments of the present invention.

[0039] Referring to Fig. 9B is a filler layer 13 formed on the lining 12. In one embodiment, the filler layer 13 is formed using a chemical vapor deposition (CVD) process. In alternative embodiments, the filler layer 13 can be formed using thermal oxidation, thermal nitridation, plasma-assisted CVD, deposition using a chemical solution, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, sputtering, and centrifugal coating. According to various embodiments, the filler layer 13 is, for example, a thermal oxide, a deposited oxide, a nitride, a ternary carbide, a ternary nitride, a metal, or graphite. In one embodiment, the filler layer 13 is a CVD oxide.In various embodiments, the lining 12 and the filler layer 13 have a similar etch selectivity, so that they are etched simultaneously.

[0040] As mentioned previously, the lining 12 can be omitted, and the filler layer 13 is directly deposited in some embodiments. The filler layer 13 can be a ternary carbide, a ternary nitride, or a metal. Fig. Figures 11A - 11C are illustrations of these embodiments and are subsequently described in more detail.

[0041] Fig. Figure 9C illustrates a cross-sectional view of the substrate after removal of areas of the filler layer and lining to expose a surface of the substrate according to an embodiment of the present invention.

[0042] Referring to Fig. In 9C, the filler layer 13 and the lining 12 are removed from the surface of the substrate 10 and, as illustrated, at least partially from the deep grooves 11. According to various embodiments, an etching process is used that is specific to the filler layer 13 and the lining 12 and does not etch the substrate 10. In some embodiments, the etching process is a chemical wet etching. Alternatively, a chemical-mechanical planarization (CMP) process can be used to planarize the top surface down to the surface of the substrate 10, followed by etching of the filler layer 13 and the lining 12. A sidewall surface of the substrate 10 and a top surface of the substrate 10 are obtained after the etching process that exposes the semiconductor material.

[0043] In various embodiments, the filler layer 13 and the lining 12 form BOX structures that are very thin and tall, with well-defined sidewalls and a planar top surface over short distances. This is a result of the precise dimensionality of the deep grooves 11 and allows the BOX structures to be used as a reproducible etch stop with low overall thickness variation. Furthermore, various embodiments of the present invention expose only a planar top surface of the BOX structure prior to an ELO processing step.

[0044] Fig. Figure 9D illustrates a cross-sectional view of the substrate after forming a first epitaxial layer according to an embodiment of the present invention.

[0045] Referring to Fig. In 9D, a first epitaxial layer 14 is formed on the remainder of the filler layer 13 and the lining 12, and over the substrate 10, by utilizing an epitaxial lateral growth (ELO) process. The ELO process is a method for cultivating an epitaxial layer that begins with a germination or seed material and progresses laterally over a partially masked substrate. In various embodiments, the filler layer 13 and the lining 12 form a mask for the ELO process, and the upper surfaces of the substrate 10 are the seed material. In one or more embodiments, the first epitaxial layer 14 can be cultivated using an epitaxial process in a vapor phase. In other embodiments, an epitaxial process in a liquid phase can also be used.

[0046] The ELO process forms nuclei on the top and side walls of the substrate 10 and consequently begins directly on the top surfaces of the infill layer 13 and the lining 12. This is a result of the infill layer 13 and the lining 12 being entirely within part of the deep trenches 11, in contrast to the conventional methods for forming BOX structures described earlier. Advantageously, the first epitaxial layer 14 grows laterally over the surfaces of the infill layer 13 and the lining 12, and there are no rough surfaces that could produce crystal defects. Moreover, only the top surface and the upper part of the trench need to be covered by the epitaxial layer, resulting in a much shorter ELO processing time compared to conventional methods for forming BOX structures.

[0047] During the formation of the first epitaxial layer 14, growth occurs in directions perpendicular to the upper surfaces and sidewalls of the substrate 10. The formation of the first epitaxial layer 14 buries the filler layer 13 and the lining 12, creating BOX structures within the substrate 10. After a certain time, the independent epitaxial growths of each BOX structure meet and merge, forming a continuous layer on the substrate 10. The time required for the formation of a continuous layer is determined by the spacing of the BOX structures and the specific processing parameters for a given ELO layer.

[0048] In one embodiment, only the deep trenches 11 are filled by the first epitaxial layer 14 up to a top surface of the substrate 10. In an alternative embodiment, the deep trenches 11 are filled, and the epitaxial growth continues laterally across the substrate 10, resulting in a uniform crystalline, defect-free first epitaxial layer 14 covering the substrate 10. In various embodiments, the first epitaxial layer 14 has the same material composition as the substrate 10. Alternatively, the first epitaxial layer 14 has a different material composition than the substrate 10. The first epitaxial layer 14 is silicon in various embodiments and highly doped in one embodiment.

[0049] Fig. Figure 9E illustrates a cross-sectional view of the substrate after the formation of a second epitaxial layer according to an embodiment of the present invention.

[0050] Referring to Fig. In 9E, a second epitaxial layer 15 is formed on the first epitaxial layer 14. The process for forming the second epitaxial layer 15 can be different from the process used to form the first epitaxial layer 14. Furthermore, in various embodiments, the second epitaxial layer 15 has a different material composition than the first epitaxial layer 14 or the substrate 10. In one embodiment, the substrate 10, the first epitaxial layer 14, and the second epitaxial layer 15 have the same material composition. In various embodiments, the second epitaxial layer 15 is silicon.

[0051] According to various embodiments, the second epitaxial layer 15 is lightly doped and, in one embodiment, serves as a device layer. In one embodiment, the second epitaxial layer 15 acts as a drift zone for a semiconductor device. Furthermore, other regions, such as source regions, can be formed within the second epitaxial layer 15 during subsequent processing. Additional embodiments include an optional buffer layer on or below the second epitaxial layer 15.

[0052] Various additional doped areas, contacts, and metallization layers can be formed according to specific device requirements for completing front-end processing of the substrate. In some embodiments, the front of the substrate can be coated with a passivation layer 19, for example, a thick oxide layer as shown in Fig. 9E shown, must be covered to protect the front during subsequent reverse processing.

[0053] Fig. Figure 9F illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures by utilizing an etching step according to an embodiment of the present invention.

[0054] Referring to Fig. In 9F, the BOX structures comprising the lining 12 and the filler layer 13 are used as an etch stop during an etching process that is selective with respect to the substrate 10. According to various embodiments, the etching process is carried out from the back side of the substrate 10 opposite the first epitaxial layer 14. This backside etching serves to thin the wafer and expose the lower surface of the BOX structures. According to various embodiments, the etching process is a crystal-oriented wet etch. For example, the crystal-oriented wet etch can be an etch with tetramethylammonium hydroxide (TMAH) or an etch with potassium hydroxide (KOH). The crystal-oriented wet etch is an anisotropic etch that is selective with respect to the (100) crystal plane and progresses between the BOX structures until only (111) surfaces (or orthogonally equivalent ones) remain.The surfaces of the resulting substrate 10 are rough compared to the wafer thinning process that will be described subsequently.

[0055] Precise control of the distances d1, d3, and h improves the accuracy of crystal-oriented wet etching processes that utilize BOX structures as etch stops, compared to conventional methods for forming BOX structures, as previously described. Advantageously, the small dimensions of the lateral distances d1 and d3, as well as the height h of the BOX structures, allow the two (111) planes to intersect, thus reducing the etch rate of the substrate 10 etching process between the BOX structures. The etching process can then be terminated during the period after it has slowed down. Consequently, the substrate 10 can be etched in a controlled manner to expose the BOX structures without removing the substrate 10 between the BOX structures.

[0056] Fig. Figure 9G illustrates a cross-sectional view of the substrate after removal of the BOX structures using an etching step according to an embodiment of the present invention.

[0057] According to various embodiments, the BOX structures can be removed using wet etching that selectively targets oxide materials, such as etching with hydrofluoric acid (HF) or buffered oxide etching with ammonium fluoride (NH4F) and HF. Alternatively, the BOX structures can be removed using a plasma etching technique with etchants such as CF4, SF6, or NF3.

[0058] Fig. Figure 9H illustrates a cross-sectional view of the substrate after deposition of a metal layer according to an embodiment of the present invention.

[0059] Referring to Fig. In step 9H, a metal 17 is deposited, filling the spaces previously occupied by the BOX structures. Optionally, according to various embodiments, a dopant implantation step followed by a subsequent curing step, such as laser curing, can be performed before the deposition of the back-side metal 17. The dopant implantation step results in an implantation area 26 within the first epitaxial layer 14. This creates a good ohmic contact or a back-side emitter for devices. Optionally, a diffusion barrier layer (not shown) can be formed before the deposition of the back-side metal 17.

[0060] Since the rear metal 17 fills the spaces left behind by the removal of the BOX structures, its shape and dimensions are similar to those previously described for the BOX structures. The underside of the rear metal 17 can conform to the V-shaped topography of the substrate 10 as shown in Fig. 9H is shown.

[0061] According to various embodiments, the back-side metal 17 comprises, for example, a pure metal, a metal carbide, a metal nitride, and metal silicides. In one embodiment, the back-side metal 17 is a ternary carbide. In another embodiment, the back-side metal 17 is a ternary nitride. The back-side metal 17 comprises, in various embodiments, titanium, tungsten, nickel, chromium, vanadium, tin, silver, copper, or aluminum.

[0062] The back metal 17 provides stability to the structures and reduces distortion of the first epitaxial layer 14 and the second epitaxial layer 15. Furthermore, the additional stability helps to prevent the metal from flaking off the substrate 10, which occurs on flat surfaces.

[0063] In various embodiments, an optional back metal layer 18 is formed over the metal 17. According to various embodiments, the back metal layer 18 is deposited, for example, by sputtering, vapor deposition, printing, electroplating, or electroless electroplating.

[0064] Removing the BOX structures to form well-defined metal structures promotes greater stabilization of ultrathin wafers and dies. The metal 17 and the back-side metal layer 18 also provide thermal conductivity and vertical electrical conductivity down to the back-side metallization for device applications.

[0065] Subsequent processing proceeds as in conventional semiconductor processing. For example, if necessary, the passivation layer is removed or structured to expose front-side contacts, and the substrate 10 is cut to form individual semiconductor dies.

[0066] A singulation process can be carried out after the manufacturing steps for realizing the intended device structure have been completed. Singulation can be performed using mechanical cutting or laser treatment in the area between the various upper contacts.

[0067] Fig. Figures 10A - 10C illustrate a method for forming a substrate with metal structures using BOX structures according to an alternative embodiment of the present invention.

[0068] Fig. Figure 10A illustrates a cross-sectional view of a substrate with BOX structures after exposure of the BOX structures by utilizing a chemical-mechanical planarization (CMPS) step according to an embodiment of the present invention.

[0069] Referring to Fig. 10A the BOX structures will be as in Fig. 8A and 9A-9E are described. The back surface of substrate 10 is then removed using a CMP process until the bottom surface of the BOX structures is reached. The resulting surface of substrate 10 is smooth, unlike the rough etched surface of previously described embodiments. Furthermore, CMP-polished surfaces differ from the V-shaped surfaces described in Fig. 9F - 9H are illustrated, planar. Backside wafer thinning using CMP can be used, for example, for vertical structures and devices of metal-oxide semiconductors (MOS) and insulated-gate bipolar transistors (IGBT).

[0070] Fig. Figure 10B illustrates a cross-sectional view of a substrate after removal of BOX structures using an etching step according to an embodiment of the present invention.

[0071] As previously described, etching the BOX structures can be done similarly to using... Fig. 9G described above.

[0072] Fig. Figure 10C illustrates a cross-sectional view of a substrate after deposition of metal layers according to an embodiment of the present invention.

[0073] Referring to Fig. 10C is the deposition of metal structures similar to those found in Fig. 9H was described.

[0074] Fig. Figures 11A - 11C illustrate an alternative embodiment for forming BOX structures.

[0075] Fig. Figure 11A illustrates a cross-sectional view of a substrate with deep trenches filled with a filler layer, according to embodiments of the present invention.

[0076] Referring to Fig. In various embodiments, 11A comprises a plurality of deep grooves 11 formed in a substrate 10 according to the method described herein. In further embodiments, the processing step for forming a lining on the substrate 10 and on the surfaces of the deep grooves 11 is omitted, and the lining is omitted. Accordingly, the deep grooves 11 in the substrate 10 are filled only with a filler layer 13. As before, the filler layer 13 can be, for example, a thermal oxide, a deposited oxide, a nitride, or graphite.

[0077] Fig. Figure 11B illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using an etching step according to an embodiment of the present invention.

[0078] Fig. Figure 11C illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using a CMP step according to an embodiment of the present invention.

[0079] Referring to Fig. 11B and Fig. 11C will process the substrate 10, which contains the BOX structures with a filling layer 13, in a similar manner as in Fig. 9C - 9E described. In one embodiment, the substrate 10 is then thinned using a crystal-oriented etching process, as previously described and in Fig. 9F was illustrated. This results in an analogous design, which is shown in Fig. Figure 11B illustrates this. Alternatively, substrate 10 is prepared using a CMP process as previously described and in Fig. Figure 10B illustrates a thinned form. This results in an analogous shape, which is shown in Fig. Figure 11C illustrates this. Subsequent processing to remove the BOX structures comprising a filler layer 13 proceeds as previously described and creates shapes that correspond to those of the Fig. 9G or Fig. 10B are identical.

[0080] Fig. Figures 12A - 12C illustrate an alternative embodiment for forming BOX structures according to embodiments of the present invention.

[0081] Fig. Figure 12A illustrates a cross-sectional view of a substrate with deep trenches filled with a lining and a filler layer, and having a cavity within the filler layer, according to an embodiment of the present invention.

[0082] Referring to Fig. In various embodiments, a plurality of deep trenches 11 are formed in a substrate 10 according to the method described herein. In further embodiments, the filler layer 13 is formed in the deep trenches 11 and covers only the side walls, top, and bottom of the deep trenches 11, leaving a void 16 within a central region of the filler layer 13. According to various embodiments, the void 16 is a narrow, elongated blister zone within the filler layer 13. In an alternative embodiment, a plurality of voids can be formed within one or more of the deep trenches 11.

[0083] Fig. Figure 12B illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures by utilizing an etching step according to an embodiment of the present invention.

[0084] Fig. Figure 12C illustrates a cross-sectional view of the substrate with BOX structures after exposure of the BOX structures using a CMP step according to an embodiment of the present invention.

[0085] Referring to Fig. 12B and Fig. 12C will enclose the substrate 10, which contains the BOX structures comprising a lining 12, a filling layer 13 and a cavity 16, in a similar manner as in the Fig. 9C - 9E described in detail. In further embodiments, subsequent processing utilizes crystal-oriented etching or CMP processes to create analogous shapes. Fig. 9F and Fig. to produce 11B as in Fig. 12B and Fig. Figure 12C illustrates this. As previously described, further processing to remove the BOX structures comprising a lining 12, a filler layer 13, and a cavity 16 produces features similar to those of the Fig. 9G or Fig. 10B are identical.

[0086] Fig. Figures 13A - 13D illustrate a semiconductor device during a manufacturing process according to an alternative embodiment of the present invention.

[0087] While earlier embodiments used a "metal last" approach, embodiments of the present invention can use a "metal first" process if the metal can be modified for heat management during front-end machining. Accordingly, in one embodiment, after forming the deep grooves 11, a metal lining 312 and a contact metal 313 can be deposited directly into the deep grooves 11. The contact metal 313 can comprise a metal nitride, metal carbides such as ternary nitrides, ternary carbides, graphite, carbon, and other materials that are resistant to or insensitive to high-temperature machining.

[0088] Further processing can be carried out as in previous embodiments, for example using the Fig. 9A - 9H described, continue; for example, as next in Fig. 13B is described after polishing the metal lining 312 and the contact metal 313. Fig. Figure 13C illustrates the device during back-side processing after anisotropic etching. The metal lining 312 must be insensitive to the etchant used to etch the substrate 10. Otherwise, the metal lining 312 will be removed during etching. In an alternative embodiment, the polishing process, as shown in Fig. 10A - 10C, described for back-side thinning. Subsequent processing continues as described in previous embodiments. For example, as described in Fig.Figure 11D illustrates the formation of the back metal 17 and, if required, the optional back metal layer 18. Advantageously, in this embodiment, the deep grooves 11 are already filled with metal, thus offering greater flexibility in forming the back metal 17. For example, stress optimization can be controlled independently, since the metal of the back metal 17 does not fill the deep grooves 11.

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Forming trenches (11) filled with sacrificial material, wherein the trenches (11) extend from a first side into a semiconductor substrate (10); Formation of an epitaxial layer (14) over the first side of the semiconductor substrate (10) and the trenches (11); from one of the second sides of the semiconductor substrate opposite the first side (10), removal of the sacrificial material in the trenches (11); and Filling the trenches (11) with a conductive material (17), wherein an upper part of the trenches (11) is filled with the epitaxial layer (14) and a lower part of the trenches (11) is filled with the conductive material (17). [2] Method according to claim 1, further comprising forming a device area in the epitaxial layer (14). [3] Method according to claim 2, wherein the device area comprises a source area of ​​a transistor. [4] Method according to any of the preceding claims, further comprising thinning the semiconductor substrate (10) from the second side to expose the sacrificial material. [5] Method according to claim 4, wherein a surface of the sacrificial material that is exposed is substantially planar. [6] Method according to claim 4, wherein a vertical cross-section of a surface of the sacrificial layer that is exposed has a v-shape. [7] Method according to any one of claims 4 to 6, wherein thinning the semiconductor substrate (10) comprises a chemical-mechanical planarization process. [8] Method according to any one of claims 4 to 7, wherein thinning the semiconductor substrate (10) comprises an anisotropic wet etching process. [9] Method according to claim 8, wherein the anisotropic wet etching process comprises a tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) etchant. [10] Method according to any of the preceding claims, wherein the trenches (11) comprise a plurality of side walls and a bottom surface and wherein forming the trenches (11) comprises: Forming a lining (12) over a main surface of the semiconductor substrate (10), the side walls of the trenches (11) and the bottom surfaces of the trenches (11); and Forming a filling material (13) over the lining (12). [11] The method of claim 10, further comprising: Etching of the filler material (13) and the underlying lining (12) to expose a top surface of the semiconductor substrate (10) on the first side, wherein the etching removes areas of the filler material (13) and the lining (12) from an upper area of ​​the trench (11). [12] Method according to any one of claims 1 to 9, comprising forming the trenches (11): Formation of the sacrificial material within the trenches (11), wherein the sacrificial material touches the semiconductor substrate (10). [13] Method according to any of the preceding claims, wherein the sacrificial material comprises: a cavity (16) in a central area of ​​the sacrificial material, wherein the cavity is completely surrounded by the sacrificial material. [14] Method according to any of the preceding claims, wherein the sacrificial material comprises at least one of a thermal oxide, a CVD oxide, a nitride, amorphous carbon and graphite, wherein the conductive material comprises at least one of a metal, a ternary carbide and a ternary nitride. [15] Semiconductor device comprising: a trench (11) extending through a semiconductor substrate (10) from a first side to a second side of the semiconductor substrate (10); an epitaxial layer (14) arranged above the first side of the semiconductor substrate (10), wherein the epitaxial layer (14) partially fills a region of the trench (11); and a back-side metal layer (17) arranged over a second side of the semiconductor substrate (10), wherein the back-side metal layer (17) extends into the trench (11) and fills the remaining area of ​​the trench (11), wherein the epitaxial layer (14) partially filling the trench (11) touches the back-side metal layer (17) which fills the remaining area within the trench (11). [16] Device according to claim 14, further comprising: a second trench (11) extending through the semiconductor substrate (10), wherein an upper region of the second trench (11) is filled with the epitaxial layer (14) and a lower region of the second trench (11) is filled with the backside metal layer (17). [17] Device according to claim 14, further comprising: a plurality of trenches (11) extending through the semiconductor substrate (10), wherein an upper region of each of the plurality of trenches (11) is filled with the epitaxial layer (14) and a lower region of each of the plurality of trenches (11) is filled with the backside metal layer (17). [18] Device according to any one of claims 14 to 17, further comprising: a source region of a vertical MOSFET arranged in the epitaxial layer (14), wherein the rear metal layer (17) forms a rear contact to the MOSFET. [19] Device according to claim 18, wherein the MOSFET comprises a trench-gate device, wherein the trench-gate is arranged above the trench (11). [20] Device according to any one of claims 14 to 19, wherein the semiconductor device is a vertical device, wherein the rear metal layer (17) forms a rear contact to the semiconductor device.

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