SRAM cell with balanced write connection

Abstract

SRAM cell (100) whose transistors (Tr1 - Tr8) are formed over a first (102), second (104), third (106), fourth (108) and fifth (110) active region, which are arranged in order from first to fifth along a first direction (X) and are aligned longitudinally along a second direction (Y) extending perpendicular to the first direction, wherein the first (102), second (104), third (106) and fourth (108) active region comprise channel regions and source / drain (S / D) regions of a first (Tr1), second (Tr2), third (Tr3), fourth (Tr4) transistor and the fifth active region comprises channel regions and S / D regions of a fifth (Tr5) and a sixth (Tr6) transistor;a first (G1), second (G2), third (G3), fourth (G4), fifth (G5) and sixth (G6) gate, each oriented along the first direction (X), wherein the first, second and sixth gates (G1, G2, G6) are each arranged along one straight line and the third, fourth and fifth gates (G3, G4, G5) are each arranged along another straight line, wherein the first to sixth gates (G1 - G6) are configured to switch the channel regions of the respective first to sixth transistors (Tr1 - Tr6), wherein the first and second gates (G1, G2) are electrically connected and the third and fourth gates (G3, G4) are electrically connected and the fifth gate is electrically isolated from the fourth gate by an insulating material (112), thereby preventing the metal elements of the fourth and fifth gates from mixing;one or more first conductive elements (130) electrically connecting one of the S / D regions of the first transistor (Tr1), one of the S / D regions of the second transistor (Tr2), and the third gate (G3); and one or more second conductive elements (128, 132, 134, 170, 172, 174) electrically connecting the second gate (G2), one of the S / D regions of the third transistor (Tr3), one of the S / D regions of the fourth transistor (Tr4), and the fifth gate (G5), wherein the one or more second conductive elements (128, 132, 134, 170, 172, 174) comprise: an S / D contact element (128) arranged over the S / D region of the fourth transistor (Tr4); and a conductive element (134) that electrically connects the S / D contact element to at least one upper section of the fifth gate (G5);wherein the fifth and sixth transistors (Tr5, Tr6) are read-terminal transistors forming a read terminal with read word / bit lines, and the first, second, third and fourth transistors (Tr1 to Tr4) are write-terminal transistors forming a write terminal, wherein the read terminal and the write terminal are separate from each other, and wherein the fifth transistor (Tr5) is connected to a low potential (VSS2).

Description

BACKGROUND The integrated semiconductor (IC) circuit industry has experienced rapid growth. During IC development, functional density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while geometric size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs. However, such miniaturization has also increased the complexity of IC processing and manufacturing, and similar advancements in IC manufacturing are needed to realize these improvements. For example, the conventional static 6T (6-transistor) random-access memory (SRAM) cell suffers from stability problems during read and write operations, where the cell is susceptible to noise. To address this problem, 8T (8-transistor) SRAM cell designs have been proposed, in which the write terminal (write word / bit lines with 6 transistors) is separate from the read terminal (read word / bit lines with 2 transistors). However, existing 8T SRAM cells are not entirely satisfactory. For example, the 6 transistors in the write terminal of conventional 8T SRAM cells are often unbalanced or asymmetrical, frequently resulting in an increased Vccmin (minimum operating voltage). An increased Vccmin leads to increased power consumption and is therefore undesirable. SRAM cells with additional dummy transistors are disclosed in DE 10 2016 117 328. German patent application DE 10 2017 117 936 A1 discloses a multiport memory cell comprising: first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines in a third metal layer, and fourth conductive lines in a fourth metal layer. The first conductive lines comprise a write bit line electrically coupled to a write bit line node; a first read bit line electrically coupled to a first read bit line node; and a second read bit line electrically coupled to a second read bit line node. The second conductive lines comprise a write word line electrically coupled to a write word line node.The fourth conductive lines comprise a first read word line electrically coupled to a first read word line node; and a second read word line electrically coupled to a second read word line node. The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with industry practice, various elements are not drawn to scale. In fact, the dimensions of the various elements may be enlarged or reduced arbitrarily for clarity of description. Fig. 1A shows a logic diagram of an SRAM cell according to aspects of the present disclosure. Fig. 1B shows a layout design and a top view of the SRAM cell of Fig. 1A according to some embodiments. Fig. 1C shows a cross-sectional view of the SRAM cell of Fig. 1B along the AA' line of Fig. 1B according to one embodiment. Fig. 1D shows a cross-sectional view of the SRAM cell of Fig. 1B along the AA' line of Fig. 1B according to another embodiment. Fig. 1E shows a cross-sectional view of the SRAM cell of Fig.Fig. 1B shows a cross-sectional view of the SRAM cell of Fig. 1B along the BB' line of Fig. 1B according to one embodiment. Fig. 1F shows a cross-sectional view of the SRAM cell of Fig. 1B along the BB' line of Fig. 1B according to another embodiment. Fig. 1G shows a cross-sectional view of the SRAM cell of Fig. 1B along the BB' line of Fig. 1B according to yet another embodiment. Fig. 1H shows a cross-sectional view of the SRAM cell of Fig. 1B along the BB' line of Fig. 1B according to one embodiment. Fig. 2A shows a layout design and a top view of another SRAM cell according to various aspects of the present disclosure. Fig. 2B shows the logic diagram of the SRAM cell of Fig. 2A in one embodiment. Fig. 3A shows a layout design and a top view of yet another SRAM cell according to various aspects of the present disclosure. Fig. 3B shows the logic diagram of the SRAM cell of Fig. 3A in one embodiment. Fig.Figure 4A shows a layout design and a top view of an SRAM cell according to various aspects of the present disclosure. Figure 4B shows a perspective view of the connectivity of the SRAM cell of Figure 4A according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples for implementing various elements of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations. Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or device to other element(s) or device(s), as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly. The present application relates generally to SRAM cell designs, in particular to 8T SRAM cell designs with a balanced write terminal layout. Elements of the present disclosure can be applied to SRAM designs with planar CMOS (complementary metal-oxide-semiconductor) FETs (field-effect transistors) or multi-gate FET devices, including dual-gate FETs, triple-gate FETs, omega-gate FETs, and gate-all-around (or surround-gate) and / or FinFETs (fin-channel field-effect transistors). Fig. 1A shows a schematic logic diagram of an SRAM cell 100 according to aspects of the present disclosure. Fig. 1B shows a top view (of certain layers) of the layout of the SRAM cell 100 in one embodiment. Referring to Fig. 1A, the SRAM cell 100 comprises a write terminal and a read terminal. The write terminal comprises two inverters cross-coupled for storage. The first inverter comprises a pull-up transistor PU1 (or Tr2) and a pull-down transistor PD1 (or Tr1) connected in series between a high and a low potential, VDD1 and VSS1, respectively. The second inverter comprises a pull-up transistor PU2 (or Tr3) and a pull-down transistor PD2 (or Tr4) connected in series between the high and low potentials, VDD1 and VSS1, respectively. The write terminal further comprises two pass-gate transistors, PG1 (or Tr7) and PG2 (or Tr8).The gate terminals of PG1 and PG2 are connected to the word line WL. One of the two source / drain (S / D) terminals of PG1 is connected to the gate terminals of PU2 and PD2, and the other of the two S / D terminals of PG1 is connected to the bit line BL. One of the two source / drain (S / D) terminals of PG2 is connected to the gate terminals of PU1 and PD1, and the other of the two S / D terminals of PG2 is connected to the inverse bit line (BLB). The read terminal comprises two transistors, Tr5 and Tr6. In the embodiment shown, the gate terminal of Tr5 is connected to the gate terminals of PU1 and PD1. One of the two S / D terminals of Tr5 is connected to a low potential, VSS2, and the other is connected to one of the two S / D terminals of Tr6. The other S / D pin of Tr6 is connected to the read bit line RBL. The gate pin of Tr6 is connected to the read word line RWL.Because the read port is separate from the write port, the 8T SRAM cell 100 has better noise immunity than conventional 6T SRAM cells. Referring to Fig. 1B, the transistors Tr1 to Tr8 of the SRAM cell 100 are configured over various active regions 102, 104, 106, 108, and 110. Specifically, the active regions 102, 104, 106, 108, and 110 are aligned longitudinally along the y-direction and arranged sequentially from first to fifth along the x-direction. The transistors Tr1 to Tr8 further comprise gates (or gate stacks or gate terminals) G1, G2, G3, G4, G5, G6, G7, and G8, respectively. The active regions 102, 104, 106, 108, and 110 can be in the form of planar active regions, where the respective gate is arranged over a flat surface of the respective active region. Alternatively, the active areas 102, 104, 106, 108 and 110 can be in the form of active fins, with the respective gate arranged over two or more surfaces of the respective active fin, making transistors Tr1 to Tr8 FinFETs. Still referring to Fig. 1B, the active region comprises 102 channel regions and S / D regions of transistors Tr1 and Tr7. The channel regions of Tr1 and Tr7 are located below gates G1 and G7, respectively, and the S / D regions of Tr1 and Tr7 are located on opposite sides of gates G1 and G7. In the present embodiment, Tr1 and Tr7 share an S / D region located between gates G1 and G7. In an alternative embodiment, Tr1 and Tr7 have separate S / D regions. Active region 104 comprises one channel region and two S / D regions of transistor Tr2. The channel region of Tr2 is located below gate G2, and the S / D regions of Tr2 are located on opposite sides of gate G2. Active region 106 comprises one channel region and two S / D regions of transistor Tr3. The channel region of Tr3 is located below gate G3, and the S / D regions of Tr3 are located on opposite sides of gate G3. The active region 108 comprises channel regions and S / D regions of transistors Tr4 and Tr8. The channel regions of Tr4 and Tr8 are located below gates G4 and G8, respectively, and the S / D regions of Tr4 and Tr8 are located on opposite sides of gates G4 and G8. In the present embodiment, Tr4 and Tr8 share an S / D region located between gates G4 and G8. In an alternative embodiment, Tr4 and Tr8 have separate S / D regions. The active region 110 comprises channel regions and S / D regions of transistors Tr5 and Tr6. The channel regions of Tr5 and Tr6 are located below gates G5 and G6, respectively, and the S / D regions of Tr5 and Tr6 are located on opposite sides of gates G5 and G6. In the present embodiment, Tr5 and Tr6 share an S / D region located between gates G5 and G6. In an alternative embodiment, Tr5 and Tr6 have separate S / D regions. Each of the active areas 102, 104, 106, 108 and 110 comprises one or more semiconductor materials such as silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP or combinations thereof. The channel regions of transistors Tr1 to Tr8 can be doped or undoped (e.g., unintentionally doped). The S / D regions of transistors Tr1 to Tr8 are doped with materials suitable for the conductivity type of the respective transistor. In one embodiment, transistors Tr2 and Tr3 are PMOSFETs (p-type conductivity), and the other transistors Tr1 and Tr4 to Tr8 are NMOSFETs (n-type conductivity). Therefore, the S / D regions of transistors Tr2 and Tr3 are doped with a p-type material such as boron, and the S / D regions of the other transistors are doped with an n-type material such as phosphorus. The S / D regions of transistors Tr1 to Tr8 can comprise epitaxially grown semiconductor material, such as epitaxially grown silicon for the NMOSFETs or epitaxially grown silicon-germanium for the PMOSFETs. Gates G1, G2, G3, G4, G5, G6, G7, and G8 are aligned longitudinally along the x-direction. In the present embodiment, gates G1, G2, G8, and G6 are aligned on one straight line, and gates G7, G3, G4, and G5 are aligned on another straight line. Each of gates G1 to G8 comprises a gate dielectric layer and a gate electrode layer above the gate dielectric layer. In some embodiments, each of gates G1 to G8 may further comprise an interface layer between the gate dielectric layer and the underlying channel semiconductor material. The gate electrode layer in gates G1 to G8 may comprise one or more exit work layers and a metal filler (or bulk metal) layer.Gates G1 and G2 are electrically connected, for example by sharing a common metal layer in the respective gates in the illustrated embodiment, or by metal connections at a higher level in an alternative embodiment. Gates G3 and G4 are electrically connected, for example by sharing a common metal layer in the respective gates in the illustrated embodiment, or by metal connections at a higher level in an alternative embodiment. The SRAM cell 100 further comprises various contact (or S / D contact) elements 122, 124, 126, 128, 136, 138, 140, 142, 144, and 146, which are arranged over the S / D regions of transistors Tr1 to Tr8. Contact 122 is arranged over the shared S / D region of Tr1 and Tr7. Contacts 124 and 140 are arranged over the other S / D regions of Tr1 and Tr7, respectively. Contact 124 serves as a VSS1 connection. Contact 140 serves as the BL connection. Contact 122 is also arranged over an S / D region of transistor Tr2 to electrically connect the S / D regions of Tr1, Tr2, and Tr7. Contact 126 is located above another S / D area of ​​Tr2 and serves as a VDD1 connection. Contact 128 is located above the shared S / D area of ​​Tr4 and Tr8. Contacts 146 and 142 are located above the other S / D areas of Tr4 and Tr8, respectively. Contact 142 serves as the BLB connection. Contact 146 serves as a VSS1 connection. Contact 128 is also located above an S / D area of ​​Tr3 to electrically connect the S / D areas of Tr3, Tr4, and Tr8. Contact 144 is located above another S / D area of ​​Tr3 and serves as a VDD1 connection. Contact 136 is located above an S / D section of Tr5 and serves as the VSS2 connection. Contact 138 is located above an S / D section of Tr6 and serves as the RBL connection. The SRAM cell 100 further comprises various conductive elements 130, 132, and 134. Conductive element 130 electrically connects the S / D contact 122 and gate G3. Conductive element 132 electrically connects the S / D contact 128 and gate G2. Conductive element 134 electrically connects the S / D contact 128 and gate G5. The conductive elements 130, 132, and 134 can comprise one or more elemental metals, a metal alloy, a conductive metal oxide, a conductive metal nitride, or other suitable conductive materials. Effectively, the S / D regions of transistors Tr1, Tr2, and Tr7 and gates G3 and G4 are electrically connected; and gates G1, G2, and G5 and the S / D regions of transistors Tr3, Tr4, and Tr8 are electrically connected. The SRAM cell 100 further comprises one or more insulating materials 112 and 114 for electrically isolating various components. In particular, the insulating material 112 is arranged between gates G4 and G5 to electrically isolate them. The insulating materials 112 and 114 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or one or more other suitable dielectric materials. The insulating material 112 and the insulating material 114 may comprise the same or different dielectric materials. In various embodiments, the transistors in the read terminal (Tr5 and Tr6) and the transistors in the write terminal (Tr1 to Tr4, Tr7, and Tr8) are designed to have different threshold voltages (Vt). For example, transistors Tr1 to Tr4 may be designed to have a standard Vt, while transistors Tr5 and Tr6 may be designed to have a low or very low Vt (lower than the standard Vt) to speed up read operations. Many factors influence a transistor's threshold voltage, one of which is the work function of the transistor's gate. Often, a gate with one or more suitable work function layers can be designed to provide an appropriate transistor threshold voltage.Although, for example, transistors Tr4 and Tr5 in one embodiment are both NMOSFETs, gate G5 may be designed to have a different work function than gate G4. In some SRAM cell designs, gates G4 and G5 are connected by sharing a common metal layer in their gate stacks (in these embodiments, gate G5 is not connected to contact 128). This could cause an imbalance between transistors Tr1 and Tr4, which are both NMOSFETs, for the following two reasons. First, gate G1 has an endcap to the left of the active region 102, while gate G4 extends fully to the active region 110. Here, "endcap" refers to the extension of a gate beyond the width of the active region (e.g., extension along the x-direction in Fig. 1B). A shorter endcap in gate G1 typically results in an increase in its work function. Second, gates G4 and G5 may have different gate stacks, such as different work function metal layers.If gates G4 and G5 share a common metal layer, the metal elements of the two gate stacks can mix in such a way that they affect the work function of both gates. In particular, if gate G5 has a lower work function, metal elements from gate G5 migrating into gate G4 would tend to decrease the work function of gate G4. One or both of the above reasons would result in a higher threshold voltage in transistor Tr1 than in transistor Tr4, which ideally should be equal. Consequently, in these 8T SRAM cells, transistor Tr4 requires a higher Vccmin to operate reliably, thus increasing the overall Vccmin of the 8T SRAM cell. In contrast, in SRAM cell 100 of the present embodiment, gates G4 and G5 are electrically isolated to resolve the imbalance problem described above. Referring to Fig. 1B, the insulating material 112 electrically isolates gates G4 and G5. The end cap of gate G4 to the right of the active area 108 can be adjusted to be the same size, shorter, or longer than the end cap of gate G1 to the left of the active area 102. This allows the two gates G1 and G4 (and thus transistors Tr1 and Tr4) to be matched. Furthermore, the insulating material 112 prevents the metal elements of gates G4 and G5 from mixing. There are several ways to isolate gates G4 and G5 from each other. One way is to define gates G4 and G5 as separate gates during mask fabrication and photolithography. Fig. 1C shows a structure of gates G4 and G5 formed by this method, according to one embodiment. Another way is to form a common gate and then divide the common gate into separate gates G4 and G5. Fig. 1D shows the structure of gates G4 and G5 formed by this gate-dividing method, according to one embodiment. Various other embodiments for forming gates G4 and G5 are considered to be within the scope of this disclosure. Figs. 1C and 1D are cross-sectional views of the SRAM cell 100 along the AA' line of Fig. 1B. Referring to Fig. 1C, in this embodiment the active regions, including 106, 108, and 110, have fin-like structures (fins), making transistors Tr1 to Tr8 FinFETs. The fins 106, 108, and 110 extend upwards from a substrate 96 and are isolated from each other by an insulating structure 98. In the present embodiment, the substrate 96 is a silicon substrate. Alternatively, the substrate 96 can comprise another elemental semiconductor, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The insulating structure 98 can consist of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. The insulating structure 98 can be a shallow trench insulating (STI) element. In one embodiment, the insulating structures 98 are formed by etching trenches into the substrate 96, for example, as part of the fin formation process. The trenches can then be filled with insulating material, followed by a chemical-mechanical planarization (CMP) process. Other insulating structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, are possible. The insulating structure 98 can have a multilayer structure, for example, comprising one or more thermal oxide lining layers. Still referring to Fig. 1C, gates G3, G4, and G5 are arranged above fins 106, 108, and 110, respectively. Gate G3 comprises a gate dielectric layer 150, one or more exit work layers 152, and a metal filler layer 158. Gate G4 comprises the gate dielectric layer 150, one or more exit work layers 154, and the metal filler layer 158. Gate G5 comprises the gate dielectric layer 150, one or more exit work layers 156, and the metal filler layer 158. Although not shown, an interface layer may be present beneath the gate dielectric layer 150. The interface layer can comprise a dielectric material such as a silicon oxide (SiO2) or silicon oxynitride (SiON) layer and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD and / or another suitable dielectric.The gate dielectric layer 150 can comprise a high-k dielectric layer such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof. The gate dielectric layer 150 can be formed by ALD and / or other suitable methods. The exit work layers 152, 154, and 156 can be p-type or n-type exit work layers, depending on the specific conductivity type of the transistor. The p-type exit work layer comprises a metal with a sufficiently high effective work function, selected from, but not limited to, the group consisting of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof.The n-workflow layer comprises a metal with a sufficiently low effective workflow, selected from, but not limited to, the group consisting of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The workflow layer 150 may comprise multiple layers and may be deposited by CVD, PVD, and / or another suitable method. The metal filler layer 158 may comprise aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials. The metal filler layer 158 may be formed by CVD, PVD, plating, and / or other suitable methods. The gate electrode in each of the gates G3, G4 and G5 comprises the respective exit working layer (152, 154 or 156) and the metal filler layer 158. In the present embodiment, the gates G3 and G4 are electrically connected by the common metal filler layer 158. In one embodiment, gates G3 / G4 and G5 are defined as separate gates during photolithography, which comprises several deposition and etching processes to form two separate trenches in place of gates G3 / G4 and G5. The trenches are surrounded on their sidewalls by insulating materials 112 and 114. Subsequently, the various layers 150, 152 / 154 / 156, and 158 are deposited in the two trenches to form gates G3, G4, and G5. In particular, the gate dielectric layer 150 is deposited on the sidewalls of the two trenches. Referring to Fig. 1D, in this embodiment, gates G3 / G4 and G5 are initially connected during their formation process. A splitting process is then performed to separate gate G5 from gates G3 / G4, resulting in a trench between gates G4 and G5. Subsequently, insulating material 112 is deposited to fill the trench. Consequently, the gate dielectric layer 150 is deposited on fins 106 / 108 / 110 and the insulating structure 98, but not on the upper portion of the insulating material 112. Referring again to Fig. 1B, connectivity between the read and write terminals of the SRAM cell 100 is achieved in the present embodiment by connecting gate G5 to the S / D contact 128. Specifically, the S / D contact 128 extends into the read terminal area between gates G5 and G6. The conductive element 134 then electrically connects the S / D contact 128 to gate G5. The conductive element 134 can comprise one or more layers of conductive material. Figs. 1E, 1F, 1G, and 1H show four different embodiments of the conductive element 134. All Figs. 1E, 1F, 1G, and 1H are cross-sectional views of the SRAM cell 100 along the BB' line of Fig. 1B. Various other embodiments for electrically connecting the S / D contact 128 to the gate G5 are considered to be within the scope of the present disclosure. Referring to Fig. 1E, in this embodiment the conductive element 134 is electrically connected to the upper section of gate G5, but not to the lower section of gate G5. In one embodiment, the conductive element 134 can be configured as part of an attached (or split) contact. For example, after gates G1-G8 have been formed in trenches surrounded by a dielectric gate spacer 166, which in turn is surrounded by the insulating material 114, one or more etching processes are performed to etch trenches into the insulating material 114 to expose the S / D regions of transistors Tr1-Tr8. As part of these etching processes, an upper and a side section of gate G5 are also exposed. In particular, a portion of the gate electrode is exposed, comprising the exit work layer 156 and the metal filler layer 158.Subsequently, one or more conductive materials are filled into the trenches to form the S / D contacts, including the S / D contact 128. The conductive element 134 is formed as part of the S / D contact 128 in this process. The S / D contact 128 (and the conductive element 134) can have a conductive barrier layer (such as TiN or TaN) and a metal layer over the conductive barrier layer. The metal layer can comprise aluminum (Al), copper (Cu), tungsten (W), or another suitable material. Referring to Fig. 1F, in this embodiment the conductive element 134 is electrically connected to the upper section of the gate G5, but not to the lower section of the gate G5. In one embodiment, the conductive element 134 can be configured as an attached (or split) contact, as described with reference to Fig. 1E. Furthering this embodiment, the etching processes do not completely remove the insulating material 114 between the S / D contact 128 and the gate spacer 166. In another embodiment, the S / D contact 128 and the conductive element 134 can be formed using different methods. For example, after the gate G5 and the S / D contact 128 have been formed, an etching process is carried out to create a groove between the gate G5 and the S / D contact 128 and to further expose a side section of the S / D contact 128 and a side section of the gate electrode of the gate G5.Then one or more conductive materials are deposited in the trench to form the conductive element134, which may include a conductive barrier layer (such as TiN or TaN) and a metal layer (such as Al, Cu or W) above the conductive barrier layer. Referring to Fig. 1G, in this embodiment the conductive element 134 is electrically connected to a side section of the gate electrode of gate G5 and to a side wall of the S / D contact 128. In particular, the conductive element 134 is connected to both the upper and lower sections of the side wall of the gate electrode of gate G5. In an exemplary embodiment, after the gate G5 and the S / D contact 128 have been formed, an etching process is carried out to form a groove between the gate G5 and the S / D contact 128. In one embodiment, the etching process is configured such that the insulating material 114 and the gate dielectric layer 150, but not the S / D contact 128 and the gate electrode 156 / 158, are selectively removed. The etching process exposes a side section of the S / D contact 128 and a side wall of the gate electrode of gate G5.In particular, the etching process completely exposes the sidewall of the exit working layer 156 of gate G5. Then, one or more conductive materials are deposited in the trench to form the conductive element 134, which may comprise a conductive barrier layer (such as TiN or TaN) and a metal layer (such as Al, Cu, or W) above the conductive barrier layer. Referring to Fig. 1H, the conductive element 134 in this embodiment comprises conductive terminal elements (or vias) 170 and 172 and a conductive wire 174. The terminal elements 170 and 172 are arranged above the S / D contact 128 and the gate G5, respectively. The wire 174 electrically connects the terminal elements 170 and 172. Both terminal elements 170 and 172 can comprise one or more conductive barrier layers (such as TiN or TaN) and a metal layer (such as Al, Cu, or W). The wire 174 can also comprise one or more conductive barrier layers (such as TiN or TaN) and a metal layer (such as Al, Cu, or W). The connection elements 170 and 172 can be formed by etching holes in the insulating material 114 above the S / D contact 128 and the gate G5 and subsequently filling the holes with one or more conductive materials.The wire 174 can be formed by etching a groove into the insulating material 114 and filling the groove with one or more conductive materials. The connecting elements 170 / 172 and the wire 174 can be formed by single-damascene, dual-damascene, or other suitable methods. Fig. 2A shows a top view of an SRAM cell 200 in one embodiment. Fig. 2B shows the logic diagram of the SRAM cell 200 in one embodiment. The SRAM cell 200 is essentially the same as the SRAM cell 100 shown in Fig. 1B, except that the read terminal transistors are interchanged in their function. Referring to Fig. 2A, the S / D contact 128 is electrically connected to gate G6 in the SRAM cell 200 instead of gate G5 in the SRAM cell 100. In the SRAM cell 200, the S / D contact 136 serves as the RBL terminal and the S / D contact 138 serves as the VSS2 terminal. The conductive element 134 can take the form of any of the embodiments shown in Figs. 1E-1H, or it can take other forms. Other aspects of the SRAM Cell 200 are the same as those of the SRAM Cell 100.If one considers SRAM cells 100 and 200 from a different perspective, SRAM cell 200 is the same as SRAM cell 100, with transistor Tr5 positioned above (along the y-direction) transistor Tr6. Fig. 3A shows a top view of an SRAM cell 300 in one embodiment. Fig. 3B shows the logic diagram of the SRAM cell 300 in one embodiment. The SRAM cell 300 is essentially the same as the SRAM cell 100 shown in Fig. 1B, except that the read terminal is located on the left side of the write terminal and the gate G5 is connected to the S / D contact 122 in the SRAM cell 300 instead of to the S / D contact 128 as in the SRAM cell 100. Referring to Fig. 3A, the S / D contact 122 extends into the area for the read terminal and between the gates G5 and G6. The conductive element 134 electrically connects the S / D contact 122 to the gate G5. The conductive element 134 can take the form of any of the embodiments shown in Figs. 1E-1H or can take other forms. Other aspects of the SRAM cell 200 are the same as those of the SRAM cell 100. Fig. 4A shows a top view of an SRAM cell 400 constructed according to aspects of the present disclosure. The SRAM cell 400 also includes transistors Tr1 to Tr8, but the arrangement of the transistors differs from that of the SRAM cell 100. In particular, the write terminal in the SRAM cell 400 is divided into a left part (left write terminal) and a right part (right write terminal). The left part includes transistors Tr1, Tr2, and Tr7. The right part includes transistors Tr3, Tr4, and Tr8. The read terminal is located between the left and right parts of the write terminal. The two gates G1 and G4 have end caps and can be designed and manufactured such that transistors Tr1 and Tr4 can be matched. Similar to the SRAM cells 100, 200 and 300, the SRAM cell 400 also offers the advantages of balanced transistors in the write connection and reduced Vccmin.Many aspects of the SRAM Cell 400 are similar to those of the SRAM Cell 100. Some differences are described below. The S / D contact 122 is electrically connected to the gate G3 via conductive elements 180 and 182. Specifically, conductive element 180 is positioned over the active region 110 without electrically contacting the S / D regions of transistors Tr5 and Tr6. Gates G1, G2, and G5 are electrically connected, for example, by sharing a common metal layer in the respective gates. Gate G5 extends further into the right-hand section of the write terminal. This extension of gate G5 is referred to as conductive element 184. Conductive element 184 is electrically connected to the S / D contact 128 via conductive element 186. Conductive element 186 can, in various embodiments, resemble conductive element 134. In the embodiment shown in Fig. 4A, the SRAM cell 400 comprises a residual gate element 188, which is a residual after a gate separation process that separates the gates G7, G6 and G3 / G4. Fig. 4B shows the conductive elements 180 and 182 according to one embodiment. Referring to Fig. 4B, the conductive elements 180 and 182 have the form of a local connection. The conductive element 180 is arranged above the S / D contact 122, the conductive element 182 is arranged above the gate G3, and the conductive elements 180 and 182 are directly connected. In one embodiment, the method for forming the conductive elements 180 and 182 comprises etching grooves into the insulating material 114 to define the shape of the local connection and to expose at least the upper surface of the S / D contact 122 and the upper surface of the gate G3. The method further comprises depositing one or more conductive materials in the groove. The one or more conductive materials can comprise one or more conductive barrier layers (such as TiN or TaN) and a metal layer (such as Al, Cu or W).In this embodiment, the conductive elements 180 and 182 are located on the same manufacturing level. In another embodiment, the conductive elements 180 and 182 can take the form of a connection in upper metal layers instead of a local connection. For example, each of the conductive elements 180 and 182 can comprise one or more vias and one or more metal wires, and the conductive elements 180 and 182 can be located in the same metal layer or in different metal layers. Although this is not intended to be restrictive, the present disclosure offers many advantages. For example, various designs and layouts of 8T SRAM cells according to the present disclosure provide balanced transistors, in particular balanced pull-down transistors, in the write terminal of the corresponding SRAM cell. The balanced transistors make it possible to reduce the minimum operating voltage (Vccmin) of the SRAM cells, thereby reducing their power consumption. Although 8T SRAM cells are used as examples, the present disclosure is not limited to 8T SRAM cells but is generally applicable to other types of SRAM cells and circuits. In one exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device has a first, second, third, fourth, and fifth active region, arranged in order from first to fifth along a first direction. The first, second, third, and fourth active regions comprise channel regions and source / drain (S / D) regions of a first, second, third, and fourth transistor, respectively, and the fifth active region comprises channel regions and S / D regions of a fifth and a sixth transistor. The semiconductor device further comprises a first, second, third, fourth, fifth, and sixth gate, aligned along the first direction. The first through sixth gates are configured to switch the channel regions of their respective first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected.The semiconductor device further comprises one or more first conductive elements that electrically connect one of the S / D regions of the first transistor, one of the S / D regions of the second transistor, and the third gate. The semiconductor device further comprises one or more second conductive elements that electrically connect the second gate, one of the S / D regions of the third transistor, one of the S / D regions of the fourth transistor, and the fifth gate. In one embodiment of the semiconductor device, each of the first to fifth active regions comprises a fin, and each of the first to sixth transistors is a FinFET. In one embodiment of the semiconductor device, the first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite to the first conductivity type, and the fifth and sixth transistors are of the same conductivity type. In one embodiment of the semiconductor device, the first active region further comprises a channel region and S / D regions of a seventh transistor, and the fourth active region further comprises a channel region and S / D regions of an eighth transistor. In another embodiment, the semiconductor device comprises a seventh and an eighth gate, wherein the seventh and eighth gates are configured to switch the channel regions of the seventh and eighth transistors, respectively. In one embodiment of the semiconductor device, the one or more second conductive elements comprise a S / D contact element arranged over the S / D region of the fourth transistor; and an attached contact connecting the S / D contact element to the fifth gate. In another embodiment, the S / D contact element is also arranged over the S / D region of the third transistor. In one embodiment of the semiconductor device, the one or more second conductive elements comprise a S / D contact element arranged over the S / D region of the fourth transistor; and a conductive element electrically connecting the S / D contact element to at least one lower section of the fifth gate. In one embodiment of the semiconductor device, the one or more second conductive elements comprise an S / D contact element arranged over the S / D region of the fourth transistor; a first terminal element arranged over the S / D contact element; a second terminal element arranged over the fifth gate; and a conductive wire connecting the first and second terminal elements. In one embodiment of the semiconductor device, the first, second and sixth gates are arranged along one straight line and the third, fourth and fifth gates are arranged along another straight line. In one embodiment of the semiconductor device, the first, second and fifth gates are arranged along one straight line and the third, fourth and sixth gates are arranged along another straight line. In a further exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a first, second, third, fourth, and fifth semiconductor fin, which are aligned longitudinally along a first direction and arranged in sequence from the first to the fifth along a second direction perpendicular to the first direction. The first, second, third, and fourth semiconductor fins comprise channel regions of a first, second, third, and fourth FinFET transistor, respectively, and the fifth semiconductor fin comprises channel regions of a fifth and sixth FinFET transistor. The semiconductor device further comprises a first, second, third, fourth, fifth, and sixth gate stack, which are aligned along the second direction, with the first through sixth gate stacks being arranged over the channel regions of the first through sixth associated transistors.The semiconductor device further comprises a first plurality of conductive elements that electrically connect a source / drain (S / D) region of the first transistor, an S / D region of the second transistor, and the third gate stack. The semiconductor device further comprises a second plurality of conductive elements that electrically connect the second gate stack, an S / D region of the third transistor, an S / D region of the fourth transistor, and the fifth gate stack. In the semiconductor device, the first and second gate stacks are electrically connected, the third and fourth gate stacks are electrically connected, the first and second FinFETs are of opposite conductivity types, the third and fourth FinFETs are of opposite conductivity types, and the fifth and sixth FinFETs are of the same conductivity type. In one embodiment of the semiconductor device, the second plurality of conductive elements comprises a split contact arranged over the S / D region of the third FinFET, the S / D region of the fourth FinFET, and the fifth gate stack. In another embodiment, the split contact is arranged over an upper surface of the fifth gate stack. In a further embodiment, the split contact is arranged over a side and a conductive section of the fifth gate stack. In one embodiment of the semiconductor device, the second plurality of conductive elements comprises a contact element arranged over the S / D region of the fourth FinFET; a first via arranged over the contact element; and a second via arranged over the fifth gate stack, wherein the first and second vias are electrically connected. In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a first, second, third, and fourth transistor arranged in order from first to fourth along a first direction. The first and fourth transistors are NMOSFETs. The second and third transistors are PMOSFETs. Each of the first through fourth transistors has a channel region, two source / drain (S / D) regions, and a gate stack above the respective channel region. The semiconductor device further comprises a fifth and a sixth transistor between the second and third transistors. The fifth and sixth transistors are of the same conductivity type. Both the fifth and sixth transistors comprise a channel region, two source / drain (S / D) regions, and a gate stack above the respective channel region.The gate stacks of the first, second, and fifth transistors, one of the S / D regions of the third transistor, and one of the S / D regions of the fourth transistor are electrically connected. The gate stacks of the third and fourth transistors, one of the S / D regions of the first transistor, and one of the S / D regions of the second transistor are electrically connected. In one embodiment of the semiconductor device, the fifth and sixth transistors are PMOSFETs. In another embodiment, the fifth and sixth transistors are NMOSFETs. In yet another embodiment, the first through sixth transistors are FinFETs. In a further exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a first, second, third, and fourth active region, arranged in order from first to fourth along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source / drain (S / D) regions of the first, second, third, and fourth transistors, respectively. The first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type, which is opposite to the first conductivity type. The semiconductor device further comprises a fifth active region between the second and third active regions, wherein the fifth active region comprises channel regions and S / D regions of the fifth and sixth transistors, which are of the same conductivity type.The semiconductor device further comprises a first, second, third, fourth, fifth, and sixth gate, wherein the first through sixth gates are arranged over the respective channel regions of the first through sixth transistors, the first, second, and fifth gates being electrically connected, and the third and fourth gates being electrically connected. The semiconductor device further comprises one or more first conductive elements that electrically connect one of the S / D regions of the first transistor, one of the S / D regions of the second transistor, and the third gate. The semiconductor device further comprises one or more second conductive elements that electrically connect the fifth gate, one of the S / D regions of the third transistor, and one of the S / D regions of the fourth transistor. In one embodiment of the semiconductor device, the one or more first conductive elements comprise a contact element located above one of the S / D regions of the second transistor and a local connection located directly above the contact element and the fifth gate. In another embodiment of the semiconductor device, the one or more first conductive elements comprise a conductive element located above and insulated from one of the S / D regions of the fifth and sixth transistors. In another embodiment of the semiconductor device, the first, second, and fifth gates share a common metal layer. In one embodiment of the semiconductor device, the first active region further comprises a channel region and S / D regions of a seventh transistor, and the fourth active region further comprises a channel region and S / D regions of an eighth transistor. In another embodiment, the semiconductor device further comprises a seventh and an eighth gate, wherein the seventh and the eighth gate are arranged over the channel regions of the seventh and eighth transistors, respectively. In one embodiment of the semiconductor device, each of the first through sixth transistors is a FinFET. In another embodiment, the fifth and sixth transistors share a common S / D region. In one embodiment, the fifth and sixth transistors are of the first conductivity type. In a further embodiment, the fifth and sixth transistors are of the second conductivity type.In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a first, second, third, and fourth FinFET, arranged in order from first to fourth along a first direction. The first and fourth transistors are of a first conductivity type, the second and third transistors are of a second conductivity type opposite to the first conductivity type, and each of the first through fourth transistors comprises a channel region, two source / drain (S / D) regions, and a gate stack above the respective channel region. The semiconductor device further comprises a fifth and a sixth FinFET between the second and third FinFETs.The fifth and sixth FinFETs are of the same conductivity type, and both have one channel region, two source / drain (S / D) regions, and a gate stack above their respective channel regions. In the semiconductor device, the gate stacks of the first, second, and fifth FinFETs, one S / D region of the third FinFET, and one S / D region of the fourth FinFET are electrically connected; the gate stacks of the third and fourth FinFETs, one S / D region of the first FinFET, and one S / D region of the second FinFET are electrically connected; and the fifth and sixth FinFETs share a common S / D region. In one embodiment of the semiconductor device, the first conductivity type is n-type and the second conductivity type is p-type. In one embodiment of the semiconductor device, the fifth and sixth FinFETs are of the first conductivity type. In another embodiment of the semiconductor device, the fifth and sixth FinFETs are of the second conductivity type. In one embodiment of the semiconductor device, the channel regions of the fifth and sixth FinFETs are located in the same fin. In one embodiment of the semiconductor device, the gate stacks of the first, second, and fifth FinFETs share a common metal layer. In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a first, second, third, fourth, fifth, and sixth transistor. The first and fourth transistors are NMOSFETs, the second and third transistors are PMOSFETs, and the fifth and sixth transistors are of the same conductivity type. Each of the first through sixth transistors comprises a channel region, two source / drain (S / D) regions, and a gate stack above the respective channel region.In the semiconductor device, the channel regions of the first to fifth transistors are arranged in order from first to fifth along a first direction; the gate stacks of the first, second and fifth transistors, one of the S / D regions of the third transistor and one of the S / D regions of the fourth transistor are electrically connected; and the gate stacks of the third and fourth transistors, one of the S / D regions of the first transistor and one of the S / D regions of the second transistor are electrically connected. In one embodiment of the semiconductor device, the channel regions of the fifth and sixth transistors are aligned along a second direction perpendicular to the first direction. In one embodiment of the semiconductor device, the fifth and sixth transistors are PMOSFETs. In one embodiment of the semiconductor device, the first through sixth transistors are FinFETs.

Claims

SRAM cell (100) whose transistors (Tr1 - Tr8) are formed over a first (102), second (104), third (106), fourth (108) and fifth (110) active region, which are arranged in order from first to fifth along a first direction (X) and are aligned longitudinally along a second direction (Y) extending perpendicular to the first direction, wherein the first (102), second (104), third (106) and fourth (108) active region comprise channel regions and source / drain (S / D) regions of a first (Tr1), second (Tr2), third (Tr3), fourth (Tr4) transistor and the fifth active region comprises channel regions and S / D regions of a fifth (Tr5) and a sixth (Tr6) transistor;a first (G1), second (G2), third (G3), fourth (G4), fifth (G5) and sixth (G6) gate, each oriented along the first direction (X), wherein the first, second and sixth gates (G1, G2, G6) are each arranged along one straight line and the third, fourth and fifth gates (G3, G4, G5) are each arranged along another straight line, wherein the first to sixth gates (G1 - G6) are configured to switch the channel regions of the respective first to sixth transistors (Tr1 - Tr6), wherein the first and second gates (G1, G2) are electrically connected and the third and fourth gates (G3, G4) are electrically connected and the fifth gate is electrically isolated from the fourth gate by an insulating material (112), thereby preventing the metal elements of the fourth and fifth gates from mixing;one or more first conductive elements (130) electrically connecting one of the S / D regions of the first transistor (Tr1), one of the S / D regions of the second transistor (Tr2), and the third gate (G3); and one or more second conductive elements (128, 132, 134, 170, 172, 174) electrically connecting the second gate (G2), one of the S / D regions of the third transistor (Tr3), one of the S / D regions of the fourth transistor (Tr4), and the fifth gate (G5), wherein the one or more second conductive elements (128, 132, 134, 170, 172, 174) comprise: an S / D contact element (128) arranged over the S / D region of the fourth transistor (Tr4); and a conductive element (134) that electrically connects the S / D contact element to at least one upper section of the fifth gate (G5);wherein the fifth and sixth transistors (Tr5, Tr6) are read-terminal transistors forming a read terminal with read word / bit lines, and the first, second, third and fourth transistors (Tr1 to Tr4) are write-terminal transistors forming a write terminal, wherein the read terminal and the write terminal are separate from each other, and wherein the fifth transistor (Tr5) is connected to a low potential (VSS2). SRAM cell (100) according to claim 1, wherein each of the first to fifth active regions (102, 104, 106) comprises a fin and each of the first to sixth transistors (Tr1 - Tr6) is a FinFET. SRAM cell (100) according to claim 1 or 2, wherein the first and fourth transistors (Tr1, Tr4) are of a first conductivity type, the second and third transistors (Tr2, Tr3) are of a second conductivity type opposite to the first conductivity type, and the fifth and sixth transistors (Tr5, Tr6) are of the same conductivity type. SRAM cell (100) according to one of the preceding claims, wherein the first active area (102) further comprises a channel area and S / D areas of a seventh transistor (Tr7) and the fourth active area (108) further comprises a channel area and S / D areas of an eighth transistor (Tr8). SRAM cell (100) according to claim 4, which further comprises a seventh and an eighth gate (G7, G8), wherein the seventh and the eighth gate (G7, G8) are configured to switch the channel ranges of the seventh and eighth transistors (Tr7, Tr8), respectively. SRAM cell (100) according to one of the preceding claims, wherein one or more second conductive elements (128, 132, 134, 170, 172, 174) comprise: a further S / D contact element (146) arranged over another of the S / D regions of the fourth transistor (Tr4). SRAM cell (100) according to claim 6, wherein a further S / D contact element (144) is provided, which is arranged over another of the S / D areas of the third transistor (Tr3). SRAM cell (100) whose transistors are formed over a first, a second, a third, a fourth and a fifth semiconductor fin (102, 104, 106, 108, 110), which are each aligned longitudinally along a first direction (Y) and are arranged in sequence from the first to the fifth along a second direction (X) perpendicular to the first direction, wherein the first (102), the second (104), the third (106) and the fourth (108) semiconductor fin comprise channel regions of a first, second, third and fourth FinFET transistor (Tr1 - Tr4) respectively, and the fifth semiconductor fin (110) comprises channel regions of a fifth and a sixth FinFET transistor (Tr5, Tr6);a first, second, third, fourth, fifth and sixth gate stack (G1 - G6), each oriented along the second direction, wherein the first, second and sixth gate stacks (G1, G2, G6) are each arranged along one straight line and the third, fourth and fifth gate stacks (G3, G4, G5) are each arranged along another straight line, wherein the first to sixth gate stacks (G1 - G6) are arranged over the channel regions of the respective first to sixth FinFET transistors (Tr1 - Tr6), wherein the fifth gate stack is electrically isolated from the fourth gate stack by an insulating material (112), thereby preventing the metallic elements of the fourth and fifth gate stacks from mixing; a first plurality of conductive elements (130) electrically connecting a source / drain (S / D) region of the first FinFET transistor (Tr1), an S / D region of the second FinFET transistor (Tr2) and the third gate stack (G3). connect;a second plurality of conductive elements (128, 132, 134, 170, 172, 174) electrically connecting the second gate stack (G2), an S / D region of the third FinFET transistor (Tr3), an S / D region of the fourth FinFET transistor (Tr4) and the fifth gate stack (G5), wherein the second plurality of conductive elements (128, 132, 134, 170, 172, 174) comprises: an S / D contact element (128) arranged over the S / D region of the fourth FinFET transistor (Tr4);and a conductive element (134) that electrically connects the S / D contact element to at least one upper section of the fifth gate stack (G5), wherein the first and second gate stacks (G1, G2) are electrically connected, the third and fourth gate stacks (G3, G4) are electrically connected, the first and second FinFET transistors (Tr1, Tr2) are of opposite conductivity types, the third and fourth FinFET transistors (Tr3, Tr4) are of opposite conductivity types, and the fifth and sixth FinFET transistors (Tr5, Tr6) are of the same conductivity type;wherein the fifth and sixth FinFET transistors (Tr5, Tr6) are read-terminal transistors forming a read terminal with read word / bit lines, and the first, second, third and fourth FinFET transistors (Tr1 to Tr4) are write-terminal transistors forming a write terminal, wherein the read terminal and the write terminal are separate from each other, and wherein the fifth FinFET transistor (Tr5) is connected to a low potential (VSS2). SRAM cell (100) according to claim 8, wherein the S / D contact element is a split contact (128) and the second plurality of conductive elements (132) comprises the split contact (128) which is arranged over the S / D region of the third FinFET transistor (TR3), the S / D region of the fourth FinFET transistor (TR4) and the fifth gate stack (G5). SRAM cell (100) according to claim 9, wherein the split contact (128) is arranged over an upper surface of the fifth gate stack (G5). SRAM cell (100) according to claim 9, wherein the split contact (128) is arranged over one side and a conductive section of the fifth gate stack (G5). SRAM cell (100) according to one of claims 8 to 11, wherein the second plurality of conductive elements (128, 132, 134, 170, 172, 174) comprises: the S / D contact element (128) arranged over the S / D region of the fourth FinFET transistor (Tr4); a first via (170) arranged over the S / D contact element (128); and a second via (172) arranged over the fifth gate stack (G5), wherein the first (170) and the second (172) vias are electrically connected. SRAM cell (100) according to one of the preceding claims, wherein the first (Tr1) and fourth (Tr4) transistors are NMOSFETs and the second (Tr2) and third (Tr3) transistors are PMOSFETs. SRAM cell (100) according to claim 13, wherein the fifth (Tr5) and sixth transistors (Tr6) are NMOSFETs or PMOSFETs.

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