Method for forming metal layers in openings

Abstract

A method comprising: forming a dielectric intermediate layer, ILD, (36) with a section (46A) at the same height as a metal gate of a transistor, wherein the ILD (36) and the metal gate are parts of a wafer (10); etching the ILD (36) to form a first contact opening (40), wherein a source / drain region (22) of the transistor is exposed through the first contact opening (40); placing the wafer (10) in a tool (100) for physical vapor deposition, PVD, wherein a metal target (110) is located in the PVD tool (100) and the metal target (110) has a first distance (S1) from a magnet (114) above the metal target (110) and a second distance (S2) from the wafer (10), and a ratio of the first distance (S1) to the second distance (S2) is greater than about 0.02 and less than about 0.03;Deposition of a metal layer (46) on the wafer (10), wherein the metal layer (46) comprises a bottom section (46A) in the first contact well (40) and a sidewall section (46B) in the first contact well (40); and performing an annealing process to react the bottom section (46A) of the metal layer (46) with the source / drain region (22) to form a silicide region (50).

Description

CLAIMING A PRIORITY AND CROSS-REFERENCE

[0001] The present application claims priority over the following provisional US patent application: Application No. 62 / 427,457, filed on November 29, 2016 and entitled “Methods for Forming Metal Layers in Openings and Apparatus for Forming Same”, which is incorporated herein by reference. GENERAL STATE OF THE ART

[0002] In the fabrication of integrated circuits, contact pins are used to connect to the source and drain regions and the gates of transistors. The source / drain contact pins are typically connected to source / drain silicide regions, which are formed by depositing a metal layer and then performing an annealing process to react the metal layer with the silicon of the source / drain regions. List of characters

[0003] The aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity in the discussion. Fig. 1 to Fig. Figure 11 shows cross-sectional views of intermediate stages in the formation of a transistor according to some embodiments. Fig. Figure 12 illustrates a cross-sectional view of a chamber for physical vapor deposition according to some embodiments. Fig. Figure 13 illustrates a process flow for forming a transistor according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples of various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purposes of simplicity and clarity and does not in itself prescribe a relationship between the various designs and / or configurations discussed.

[0005] Furthermore, terms describing a spatial relationship, such as "underlying," "below," "lower," "above," "upper," and the like, may be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It is intended that terms describing a spatial relationship, in addition to the orientation shown in the figures, encompass various orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the descriptions of spatial relationships used here may be interpreted accordingly.

[0006] A transistor having contact pins connected to silicide regions, and the method for their formation, are provided according to various embodiments. The intermediate stages of transistor formation are illustrated. Variations of some embodiments are discussed. Across the different views and illustrative embodiments, the same reference numerals are used to denote the same elements. The in Fig. 1 to Fig. The 11 steps shown are also schematically represented in the process flow. 200 illustrates, which in Fig. 13 is shown.

[0007] Fig. 1 to Fig. Figure 11 shows cross-sectional views of intermediate stages in the formation of a transistor and the corresponding contact pins according to some embodiments. With reference to Fig. 1 is a wafer 10 provided. The wafer 10 The substrate includes 20, which are formed from a semiconductor material, such as silicon, silicon germanium, silicon carbon, III-V composite semiconductor materials, or the like. The substrate 20 It can be a solid substrate or a semiconductor-on-insulator (SOI) substrate.

[0008] Gate stack 26A and 26B , which together form a gate stack 26 They are referred to as being above the substrate. 20 formed. According to some embodiments of the present disclosure, the gate stacks are 26A and 26B as gate stacking strips (in a top view of the wafer) 10 ) formed, which have longitudinal directions that are parallel to each other, wherein the distance between the gate stacks 26A and 26B is minimized. Each of the gate stacks 26A and 26B can the gate dielectric 24 , the gate electrode 28 above the gate dielectric and the hard mask38 above the gate electrode 28 include. According to some embodiments of the present disclosure, the gate stacks are 26 Replacement gate stacks are formed by creating dummy gate stacks (not shown), removing the dummy gate stacks to create recesses, and forming the replacement gates in the recesses. Consequently, each of the gate dielectrics comprises 24 a floor section located below the corresponding gate electrode 28 lies, and sidewall sections on the sidewalls of the corresponding gate electrode 28 The sidewall sections form rings that hold the corresponding gate electrodes. 28 surrounded.

[0009] According to some embodiments of the present disclosure, source and drain regions are 22 (hereinafter referred to as source / drain areas) 22 (designated), formed to migrate into the substrate 20to extend. According to alternative embodiments, source / drain regions are 22 formed after the formation of the contact opening, as in Fig. 2 shown. One of the source / drain areas. 22 can be a common source area or a common drain area that is connected by the gate stack 26A and 26B is divided. Accordingly, the gate stack can be... 26A a first transistor together with the source / drain regions on opposite sides of the gate stack 26A form and the gate stack 26B can combine a second transistor with the source / drain regions on opposite sides of the gate stack 26B form. The first transistor and the second transistor can be connected electrically in parallel to act as a single transistor.

[0010] The gate dielectric 24It can be a single layer or a composite layer comprising multiple layers. For example, the gate dielectric can be... 24 The system comprises an oxide interface layer and a high-k dielectric layer above the oxide layer. The oxide layer can be a silicon oxide layer formed by thermal or chemical oxidation. The high-k dielectric layer can have a k-value greater than 7 or even greater than 20. Examples of high-k dielectrics include hafnium oxide, zirconium oxide, lanthanum oxide, and the like.

[0011] According to some embodiments of the present disclosure, each gate electrode has 28 a single-layer structure formed from a homogeneous conductive material. According to alternative embodiments, each gate electrode has 28a composite structure comprising several layers formed from TiN, TaSiN, WN, TiAl, TiAlN, TaC, TaN, aluminum, or alloys thereof. The formation of gate electrodes. 28 This may include physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD), and / or other applicable processes. Hard masks 38 They can be formed from silicon nitride, for example.

[0012] According to alternative embodiments of the present disclosure, the gate stacks 26A and 26B , instead of being a replacement gate stack, formed by forming a gate dielectric cover layer and a gate electrode cover layer (such as a polysilicon layer) and then structuring the gate dielectric cover layer and the gate electrode cover layer.

[0013] Again with reference to Fig. 1 The contact etch stop layer (CESL) 34 is formed to protect the substrate 20 to cover, and can be found on the side walls of gate spacers 30 extend. According to some embodiments of the present disclosure, the CESL comprises 34 Silicon nitride, silicon carbide, or other dielectric materials. The inter-layer dielectric (ILD) 36 is located above the CESL and the gate stack. 26A and 26B formed. The ILD 36 It can be formed from an oxide, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate oxide (TEOS), or the like. Formation can involve, for example, chemical vapor deposition (CVD), flowable CVD (FCVD), spin coating, or similar processes.

[0014] With reference to Fig. 2, the ILD36 and the CESL 34 etched to create the contact opening 40 to form. The corresponding step is called step 202 in which Fig. The process flow shown in section 13 is illustrated. The opening 40 According to some embodiments, this is a source / drain contact opening. The source / drain area 22 lies (if it has already formed) opposite the contact opening 40 free. According to some embodiments of the present disclosure, the opening has 40 The aperture has a width W1 that is less than approximately 40 nm. The depth D1 can be greater than approximately 100 nm. Accordingly, the aperture has a width W1 that is less than approximately 40 nm. 40 a high aspect ratio.

[0015] According to the embodiments in which the source / drain regions 22If the source / drain areas have not yet formed at this time, a pre-amorphization implantation (PAI) and a source / drain implantation can be performed to create source / drain areas. 22 to form, whereby the type of PAI and the implanted foreign atom for forming the source / drain regions 22 through the opening 40 into the substrate 20 The PAI can be performed using germanium, silicon, or similar materials, disrupting the lattice structure of the implanted areas to control the depth of the subsequent source / drain implantation. Source / drain implantation can be performed using boron or indium if the corresponding transistor is a p-type transistor, or using phosphorus, arsenic, or antimony if the corresponding transistor is an n-type transistor.

[0016] Fig. Figure 3 illustrates the formation of the contact (pin) spacers 44 according to some embodiments of the present disclosure. The corresponding step is shown as step 204 in which Fig. The process flow shown in section 13 illustrates the formation of contact spacers. 44 This can involve the deposition of one or more conformal dielectric layers. The dielectric layers extend into the contact opening. 40 and include vertical sections on the side walls of the ILD 36 and horizontal sections at the bottom of the opening 40 as well as above the ILD 36The deposition process is carried out using a conformal deposition process, such as atomic layer deposition (ALD), CVD, or the like, such that the horizontal and vertical sections of the deposited layer have similar thicknesses. Anisotropic etching is then performed to remove the horizontal sections, leaving the vertical sections as contact spacers. 44 left behind. Anisotropic etching can be carried out using ammonia (NH3) and NF3 as etching gases. It should be noted that the contact spacers 44 the same opening 40 , in a top view of the wafer 10 Considered are sections of an integrated spacer ring.

[0017] According to some embodiments of the present disclosure, the spacers are 44Made from a dielectric material that exhibits high etch selectivity towards oxides, such that the spacers are not damaged in subsequent cleaning processes (in which oxides are removed). For example, the contact spacers 44 formed from silicon nitride, silicon oxycarbide, silicon oxynitride or the like.

[0018] According to alternative embodiments of the present disclosure, no spacers are used. 44 formed. Accordingly, the step 204 in Fig. Figure 13 is shown with a dashed box to indicate that this step can be performed or skipped. According to these embodiments, the subsequently formed metal layer can 46 ( Fig. 4) Have side wall sections that are aligned with the side walls of the ILD 36 are in contact.

[0019] Next, with reference to Fig. 4 the metal layer 46isolated. The corresponding step is described as a step. 206 in which Fig. The process flow shown in Figure 13 is illustrated. According to some embodiments of the present disclosure, the metal layer 46 a titanium (Ti) layer that can be formed using physical vapor deposition (PVD). The metal layer 46 includes the floor section 46A at the bottom of the opening 40 and the side wall sections 46B on the side wall surfaces of the ILD 36 The side wall sections 46B have sidewall thicknesses T1 and the lower section 46A The bottom wall has a thickness T2. The side wall thickness T1 can be set at a height equal to 2 / 3 of the depth D1 of the opening. 40 can be measured. The ratio T1 / T2 can be less than approximately 0.35 and can lie in the range between approximately 0.26 and approximately 0.34. The metal layer 46It has two functions. The first function is that the bottom section of the metal layer 46 with the underlying source / drain area 22 reacts to form a source / drain silicide region. Accordingly, it is desirable that the thickness T2 be of a high value, such that the contact resistance between the resulting silicide region and the contact pin above it is low. The second function is that the metal layer 46 It acts as an adhesive layer for the subsequently formed cover / adhesive layer. Accordingly, the sidewall thickness T1 preferably has a value greater than zero. Conversely, the thickness T1 cannot have a high value, as this would cause the upper section of the contact opening to 40is too narrow, resulting in a seam (defect) in the subsequently formed contact pin. Accordingly, to reduce the contact resistance without causing the defect, the base thickness T2 is increased and, according to some embodiments, the side wall thickness T1 is reduced to a small value (but not zero). Furthermore, the side wall sections can 46B according to some embodiments of the present disclosure, have a uniform thickness.

[0020] If the width W1 ( Fig. 2) the opening 40 Since the surface area is very small, it is difficult to increase the soil thickness T2 to, for example, greater than approximately 5 nm and especially greater than approximately 9 nm. Accordingly, a PVD tool is planned and designed to achieve such a goal. Fig. Figure 12 illustrates a PVD tool 100 according to some embodiments of the present disclosure. The PVD tool 100 The vacuum chamber includes102 Chuck 104 , the electromagnetic coil 106 , the collimator 108 , the target 110 , the target cover plate 112 and the magnet 114 are located in the vacuum chamber 102 .

[0021] The wafer 10 (which also in Fig. 3 is shown) is on the Chuck 104 placed and held to secure the metal layer 46 ( Fig. 4) to form. The target 110 It is formed from the metal to be deposited and can, for example, be a titanium target. The target 110 is on the target cover plate above it 112 attached. The magnet 114 is above the target cover plate 112 arranged. The magnet 114 can be on the disk 116 It should be attached. The plate 116 is designed to rotate around the vertical axis 118 to be rotated, which is directed towards the center of the target 110and is aligned with wafer 10. The magnet 114 may comprise one part or multiple parts, each located on one side of the axis 118 are located during the deposition process. 114 around the axis 118 rotated. A magnet is illustrated using a dotted line to show the place to which it can rotate.

[0022] The target 110 is from the magnet 114 spaced apart by a distance S1 and is by a distance S2 from the wafer 10 spaced apart. To increase the soil thickness T2 ( Fig. 4) the metal layer 46 The distance S2 is reduced. However, this can result in a loss of uniformity across the entire wafer in the thickness of the metal layer. 46 over the wafer 10 The thickness of the metal layer can vary. For example, the thickness of the metal layer can change. 46 at the edge of the wafer 10 and in the middle of the wafer10 Due to the reduction of the distance S2, the difference will be increased. The distance S1 is adjusted and increased to compensate for the unevenness in the thickness of the metal layer. 46 to reduce. According to some embodiments of the present disclosure, reducing the distance S1 includes adjusting the position of the magnet. 114 , to be higher, which can be achieved by changing or adjusting the hardware, for example, changing and adjusting the positions of the magnet's mounting mechanism 114 This can be accomplished. According to alternative embodiments, a hardware modification is performed to adjust the target. 110 to move downwards to decrease the distance S2 and increase the distance S1. The magnet 114 In addition to adjusting the target height, it can also be used 110 to be moved.

[0023] Experimental results show that if the S1 / S2 ratio is greater than approximately 0.02, the uniformity of the wafer and the thickness of the metal layer can be improved by optimizing the process conditions. 46 The ratio S1 / S2 can be satisfactory and can be brought into a specified range. The ratio S1 / S2 can be in the range between approximately 0.02 and approximately 0.03. According to some embodiments of the present disclosure, if the ratio S1 / S2 is greater than approximately 0.02, the distance S1 can be in the range between approximately 3.7 mm and approximately 3.9 mm, and the distance S2 can be in the range between approximately 184 mm and approximately 186 mm.

[0024] The thicknesses T1 and T2 are also influenced by various process conditions. According to some embodiments of the present disclosure, some process conditions are adjusted to achieve the desired thicknesses T1 and T2. For example, during the deposition of the metal layer,46 Argon is used as the process gas. The process gas flow rate is increased to raise the deposition rate and to increase the T2 / T1 ratio (such that the bottom thickness T1 is greater without increasing the sidewall thickness T2). The flow rate can be higher than approximately 160 sccm and can range between approximately 160 sccm and approximately 200 sccm. The process pressure can also be increased to increase the T2 / T1 ratio. For example, during the deposition of the metal layer, 46 the pressure in the chamber 102 ( Fig. 12) higher than about 80 mTorr and can be in the range between about 80 mTorr and about 120 mTorr.

[0025] Additional process conditions that affect thicknesses T1 and T2 include RF power. 126 , which comes with the target cover plate 112 connected is the direct current power 124 , which comes with the target cover plate 112is connected, and the current of the self-capacity tuning device (Auto Capacity Tuner - ACT) 120, which supplies the chuck 104 is provided. According to some embodiments of the present disclosure, the RF power is 126 lower than approximately 5 kW and can range between approximately 1200 watts and approximately 2100 watts (at a frequency of, for example, 13.5 MHz). The DC power 124 is lower than about 1.5 kW and can range between about 50 watts and about 800 watts.

[0026] By adjusting the hardware to fine-tune the S1 / S2 ratio and by adjusting the process conditions in the deposition, the metal layer can be 46 ( Fig. 4) have an increased base thickness T2 without increasing the thickness T1, even if the metal layer 46 into a very small opening 40(with a width W1, which is, for example, less than about 40 nm). Experimental results have shown that if the substrate thickness T2 is about 8 nm or less, the subsequently formed contact pin 56 ( Fig. 8) will have a seam. If, however, the base thickness T2 is approximately 9.5 nm or greater, the subsequently formed contact pin will 56 ( Fig. 8) have no seam. Accordingly, according to some embodiments of the present disclosure, the thickness T2 is greater than about 9.5 nm when the width W1 of the opening is less than about 40 nm. The thickness ratio T1 / T2 may be less than about 0.35 and may be in the range between about 0.26 and about 0.34.

[0027] With reference to Fig. 5 will be the top layer 48 isolated. The corresponding step is described as a step. 208 in which Fig. The process flow shown in section 13 is illustrated. The top layer48 It also acts as a diffusion barrier layer.

[0028] According to some embodiments of the present disclosure, the cover layer 48 is formed from a metal nitride, such as titanium nitride. The cover layer 48 can be formed using CVD, which can be formed in a CVD chamber. Accordingly, the wafer can 10 from the PVD chamber 102 ( Fig. 13) are removed and placed in the CVD chamber to form the top layer 48 to be placed. The top layer 48 It can be a conformal layer whose horizontal and vertical thicknesses are close together. According to alternative embodiments, the top layer 48 in the same chamber 102 formed, with additional nitrogen gas being introduced when the metal is removed from the target 110 is sputtered.

[0029] Fig. Figure 6 illustrates a silicide process for the formation of the silicide region. 50 According to some embodiments of the present disclosure, the silicide process is carried out by tempering, which is described by arrows. 52 is shown. The corresponding step is shown as step 210 in which Fig. Figure 13 illustrates the process flow shown. The annealing can be carried out by rapid thermal annealing (RTA), furnace annealing, or similar methods. The lower section reacts accordingly. 46A ( Fig. 5) the metal layer 46 with the source / drain area 22 , around the silicide area 50 to form. After the silicification process, sidewall sections remain 46B consist of, as in Fig. 6 shown. According to some embodiments of the present disclosure, the lower section 46A ( Fig. 5) completely reacts and the surface of the silicide area 50 is with the lower surface of the top layer 48 in contact. After silicide treatment, the ratio T1 / T3 is less than approximately 0.35, where the thickness T3 is the thickness of the silicide region. 50 is.

[0030] Next, metallic material will be used. 54 the remaining contact opening 40 was filled and the resulting wafer 10 is in Fig. 7 shown. The corresponding step is shown as step 212 in which Fig. The process flow shown in 13 is illustrated. Metallic material 54 It can be formed, for example, from tungsten, copper, aluminum, or a metal alloy. Next, a planarization process, such as chemical-mechanical polishing (CMP), is carried out to remove the excess sections of the metallic material. 54 , the top layer 48 and the metal layer 46above the ILD 36 to remove. The corresponding step is called step 214 in which Fig. The process flow shown in section 13 is illustrated. This is how the source / drain contact pin is used. 56 formed, as in Fig. 8 shown.

[0031] Fig. 9 and Fig. Figure 10 illustrates the formation of gate contact pins. One or more etching processes are performed to create the ILD. 36 and the mask layers 38 ( Fig. 8) to etch, in such a way that openings 58 be formed, as in Fig. 9 shown. The corresponding step is shown as step 216 in which Fig. The process flow shown in section 13 is illustrated.

[0032] Next, the contact openings will be 58 filled with conductive material(s) to form gate contact pins 60 to form, as in Fig. 10 is shown. The corresponding step is shown as step 218 in which Fig. The process flow shown in Figure 13 is illustrated. According to some embodiments of the present disclosure, the gate contact pins comprise 60 conductive bonding / barrier layers 62 and metallic material 64 above the detention / barrier layers 62 The adhesive / barrier layer 62 can be formed from a material selected from titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, or from several layers thereof. The metallic material 64 can be made from tungsten, copper, aluminum or alloys thereof and can be formed using PVD, metal-organic chemical vapor deposition (MOCVD) or plating.

[0033] According to some embodiments of the present disclosure, dielectric contact spacers 66 formed to connect the gate contact pins 60to surround. The material and process for forming dielectric contact spacers. 66 can affect the material or the educational process of contact spacers 44 They may be similar. According to alternative embodiments, the contact spacers 66 not formed, and therefore the gate contact pins are in contact with the side walls of the ILD. 36 Since the contact pins 56 and 60 Being close together can lead to the formation of dielectric contact spacers. 44 and 66 the electrical short-circuiting of the contact pins 56 and 60 eliminate, whereby an electrical short circuit is caused by a misalignment of the contact pins 56 and / or 60 can be caused.

[0034] Fig. Figure 11 illustrates the formation of the etch stop layer 70 , the dielectric layer 72 and the conductive features 74The corresponding step is called step 220 in which Fig. The process flow shown in Figure 13 is illustrated. According to some embodiments of the present disclosure, the conductive features are 74 Metal conductors and the dielectric layer 72 is an intermetal dielectric (IMD). According to alternative embodiments, the conductive features are 74 upper contact pins and the dielectric layer 72 is an upper ILD (in relation to the lower ILD) 36 According to some embodiments, dielectric contact spacers can 76 are formed to determine the conductive features 74 to surround. Alternatively, no dielectric contact spacers are used. 76 formed. Accordingly, the dielectric contact spacers are 76The formation of contact spacers is illustrated using dashed lines to indicate that they can be formed or omitted. 44 , 66 and 76 This can advantageously eliminate the possibility of bridging and electrically short-circuiting adjacent contact pins. 56 , 60 and 74 reduce.

[0035] The conductive features 74 can imprisonment / barrier layers 75 and metallic material 77 about detention / barrier layers 75 include. Similarly, the retention / barrier layers can 75 These can be metal layers, such as titanium, tantalum, or metal nitride layers. According to some embodiments, in which adhesive / barrier layers are used... 62 or 75 formed from metal layers, such as titanium or tantalum layers, the layers can 62 and / or75 using PVD in a PVD tool, which, except for the S1 / S2 ratio of the PVD tool for forming the layers 62 and / or 75 is smaller than the S1 / S2 ratio in the PVD tool for forming the metal layer 46 , essentially the same as the one in Fig. The PVD tool shown is number 12. The aspect ratio of the opening 58 ( Fig. 9) and / or the opening for forming the conductive features 74 can be smaller than the aspect ratio of the opening 40 in Fig. There will be two. Accordingly, it can be easier to layer the layers. 62 and / or 75 to form, as the metal layer 46 ( Fig. 4) to form. Furthermore, since no silicide is present in the layers. 62 and / or 75 The soil thicknesses of the layers will be formed. 62 and / or 75not be significantly larger than the corresponding sidewall thicknesses. Accordingly, the PVD tool for forming the layers can be used. 62 and / or 75 have an S1 / S2 ratio that is less than 0.02, where this ratio can be in the range between approximately 0.01 and approximately 0.02.

[0036] The embodiments of the present disclosure exhibit several advantageous features. To reduce the size of transistors, the widths of the contact pins are also reduced. However, reducing the widths of the contact pins results in an increase in contact resistance. According to some embodiments of the present disclosure, the PVD tool for depositing the metal layer used for silicide application (such as a titanium layer) is adapted, and the process conditions for depositing the metal layer are adjusted to increase the base thickness of the titanium layer while maintaining the sidewall thickness of the titanium layer and preventing it from increasing proportionally. This advantageously reduces the contact resistance without creating seams in the contact pins. Furthermore, dielectric spacers can be formed to eliminate electrical short-circuiting of the contact pins.The formation of dielectric spacers, however, further reduces the size of the source / drain contact opening. This problem can also be solved by modifying the PVD tool and adjusting the deposition process conditions.

[0037] According to some embodiments of the present disclosure, a method comprises forming an ILD with a section at the same height as a metal gate of a transistor, wherein the ILD and the metal gate are parts of a wafer, and etching the ILD to form a contact opening. A source / drain region of the transistor is exposed through the contact opening. The wafer is placed in a PVD tool. A metal target is located in the PVD tool, and the metal target has a first distance from a magnet above the metal target and a second distance from the wafer. The ratio of the first distance to the second distance is greater than approximately 0.02. A metal layer is deposited on the wafer. The metal layer has a bottom section in the first contact opening and a sidewall section in the first contact opening.A tempering process is carried out to react the bottom section of the metal layer with the source / drain region to form a silicide region.

[0038] According to some embodiments of the present disclosure, a method comprises forming an ILD with a section at the same height as a metal gate of a transistor, wherein the ILD and the metal gate are parts of a wafer, etching the ILD to form a source / drain contact opening, wherein a source / drain region of the transistor is exposed through the source / drain contact opening, and depositing a first titanium layer on the wafer. The first titanium layer has a bottom section in the source / drain contact opening and a sidewall section in the source / drain contact opening. The sidewall section has a first thickness. Annealing is carried out to react the bottom section of the first titanium layer with the source / drain region to form a silicide region. The silicide region has a second thickness. The ratio of the first thickness to the second thickness is less than about 0.35.

[0039] According to some embodiments of the present disclosure, a method comprises forming an ILD with a section at the same height as a metal gate of a transistor, wherein the ILD and the metal gate are parts of a wafer, etching the ILD to form a source / drain contact opening, wherein a source / drain region of the transistor is exposed through the source / drain contact opening, and setting a PVD tool. A metal target is located in the PVD tool, and the metal target has a first distance from a magnet above the metal target. The method includes increasing the first distance. A titanium layer is deposited on the wafer in the PVD tool. The titanium layer extends into the source / drain contact opening.

[0040] Previously, features of several embodiments were presented in such a way that the person skilled in the art could better understand the aspects of the present disclosure. The person skilled in the art should understand that the present disclosure can readily serve as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments introduced herein. The person skilled in the art should also understand that such equivalent designs do not deviate from the concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications to them without deviating from the concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62 / 427457

[0001]

Claims

[1] Procedure comprising the following: Forming an inter-layer dielectric (ILD) with a section at the same height as a metal gate of a transistor, where the ILD and the metal gate are parts of a wafer; Etching the ILD to form a first contact opening, whereby a source / drain region of the transistor is exposed through the first contact opening; Placing the wafer in a physical vapor deposition (PVD) tool, wherein a metal target is located in the PVD tool and the metal target has a first distance from a magnet above the metal target and a second distance from the wafer, and a ratio of the first distance to the second distance is greater than about 0.02; Deposition of a metal layer on the wafer, wherein the metal layer comprises a bottom section in the first contact well and a sidewall section in the first contact well; and Performing a tempering process to react the bottom section of the metal layer with the source / drain region to form a silicide region. [2] The method of claim 1, further comprising increasing the first distance to adjust the ratio from less than 0.02 to greater than about 0.

02. [3] Method according to claim 1 or 2, wherein the ratio is in a range between about 0.02 and about 0.

03. [4] Method according to one of the preceding claims, further comprising forming a contact spacer in the first contact opening, wherein the contact spacer surrounds a section of the metal layer. [5] Method according to any of the preceding claims, further comprising forming a cover layer over the metal layer, wherein the tempering is carried out while the cover layer covers the metal layer. [6] Method according to any of the preceding claims, wherein the metal layer has a side wall section having a first thickness, and the silicide region has a second thickness, and the ratio of the first thickness to the second thickness is less than about 0.

35. [7] Method according to any of the preceding claims, wherein the first contact opening has a width less than about 40 nm and the silicide region has a thickness greater than about 9 nm. [8] A method according to any of the preceding claims, further comprising: Etching the ILD and a mask layer over the metal gate to form a second contact opening; and Forming a gate contact pin and an additional contact spacer in the second contact opening, with the additional contact spacer surrounding the gate contact pin. [9] Procedure comprising the following: Forming an inter-layer dielectric (ILD) with a section at the same height as a metal gate of a transistor, wherein the ILD and the metal gate are parts of a wafer; Etching the ILD to form a source / drain contact opening, whereby a source / drain region of the transistor is exposed through the source / drain contact opening; Deposition of a first titanium layer on the wafer, wherein the first titanium layer comprises a bottom section in the source / drain contact orifice and a sidewall section in the source / drain contact orifice, the sidewall section having a first thickness; and Performing an annealing process such that the bottom section of the first titanium layer reacts with the source / drain region to form a silicide region, wherein the silicide region has a second thickness, and the ratio of the first thickness to the second thickness is less than about 0.

35. [10] Method according to claim 9, further comprising forming a contact spacer in the source / drain contact opening, wherein the contact spacer surrounds a section of the first titanium layer. [11] Method according to claim 9 or 10, wherein the source / drain contact opening has a width that is less than about 40 nm and the silicide region has a thickness that is greater than about 9 nm. [12] Method according to any one of claims 9 to 11, wherein the first titanium layer is deposited by physical vapor deposition (PVD) in a first PVD chamber, wherein the first metal target is located in the first PVD chamber and the first metal target has a first distance from a first magnet above the first metal target and a second distance from the wafer and a ratio of the first distance to the second distance is greater than about 0.

02. [13] The method of claim 12, further comprising: Formation of a dielectric layer over the ILD; Etching the dielectric layer to create an additional contact opening; and Deposition of a second titanium layer on the wafer, wherein the second titanium layer extends into the additional contact opening, wherein the second titanium layer is deposited in a second PVD chamber, wherein a second metal target is located in the second PVD chamber and the second metal target has a third distance from a second magnet above the second metal target and a fourth distance from the wafer and a ratio of the third distance to the fourth distance is less than 0.

02. [14] Method according to any one of claims 9 to 13, further comprising forming a cover layer over the first titanium layer, wherein the tempering is carried out while the cover layer covers the first titanium layer. [15] Method according to any one of claims 9 to 14, wherein the first titanium layer has a side wall section having a first thickness, and the silicide region has a second thickness, and the ratio of the first thickness to the second thickness is less than about 0.

35. [16] Method comprising the following: Forming an inter-layer dielectric (ILD) with a section at the same height as a metal gate of a transistor, wherein the ILD and the metal gate are parts of a wafer; Etching the ILD to form a source / drain contact opening, whereby a source / drain region of the transistor is exposed through the source / drain contact opening; Setting up a physical vapor deposition (PVD) tool, wherein a metal target is located in the PVD tool and the metal target has a first distance from a magnet above the metal target, and wherein setting up the PVD tool includes increasing the first distance; and Deposition of a titanium layer on the wafer in the PVD tool, wherein the titanium layer extends into the source / drain contact opening. [17] Method according to claim 16, wherein the metal target has a second distance from the wafer and the first distance is increased such that the ratio of the first distance to the second distance is increased from a value less than 0.02 to a value greater than about 0.

02. [18] Method according to claim 16 or 17, further comprising carrying out a tempering process wherein a bottom section of the titanium layer reacts with the source / drain region to form a silicide region. [19] Method according to claim 18, wherein the source / drain contact opening has a width that is less than about 40 nm and the silicide region has a thickness that is greater than about 9 nm. [20] Method according to any one of claims 16 to 19, further comprising forming a contact spacer in the source / drain contact opening, wherein the contact spacer surrounds a section of the titanium layer.