Gate stack for stacked fin channel and nanowire channel core I / O devices

Abstract

Semiconductor device comprising: a substrate (102); an I / O device (100A) above the substrate; and a core device (100B) above the substrate, wherein the I / O device and the core device are either both NFETs or both PFETS, wherein the I / O device comprises a gate trench (166), a stacked fin in the gate trench and a first gate structure (10A; 107A; 107C), wherein the stacked fin comprises a first and a second semiconductor material which are different and which are alternately stacked, where the first gate structure has: an interface layer (12; 120) over surfaces of the stacked fin; a first high-k dielectric stack (14A; 121) over the interface layer; and a conductive layer (16; 126) over and in physical contact with the first high-k dielectric stack, wherein the core device comprises a gate trench, nanowires in the gate trench, and a second gate structure (10B; 107B; 107D), the second gate structure comprising: the interface layer (12; 120); a second high-k dielectric stack (14B; 122) over the interface layer; and the conductive layer (16; 126) over and in physical contact with the second high-k dielectric stack, and wherein the first high-k dielectric stack (14A; 121) comprises the second high-k dielectric stack (14B; 122) and a third dielectric layer (15; 124) over the second high-k dielectric stack, wherein the first high-k dielectric stack (14A; 121) has at least two different high-k dielectric layers (122; 124) and the first high-k dielectric stack (14A; 121) and the second high-k dielectric stack (14B; 122) have at least the same bottommost high-k dielectric layer (122).

Description

BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth. Technical advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry size (i.e., the smallest component (or line) that can be generated using a fabrication process) has decreased. This downsizing process generally offers advantages in increasing production efficiency and lowering the costs associated therewith. Such downsizing has also increased the complexity of processing and manufacturing ICs.For example, as the scale down progresses, the source / drain (S / D) transition becomes more important for short channel control and determines the final performance of the device. Therefore, low temperature processes after the S / D formation are required. However, existing gate oxide processes typically use post-oxide anneal (POA), which is mostly a long high temperature process, to produce high quality gate oxide. This POA method sometimes affects the performance of the S / D transition. The production of gate stacks with a low temperature process and with sufficient reliability is an important task. As another example, since I / O (input / output or IO) devices operate at higher Vdd than core devices, a thicker gate oxide is needed for I / O devices. The continuous downsizing of gate stacks for I / O devices is a challenge for the semiconductor industry. The present disclosure aims to solve the above problems and other related problems.US 2014 / 0027859 A1 describes a semiconductor device which can have an I / O component and a standard transistor component. The I / O device includes an additional high-k dielectric layer between the gate insulating layer and another high-k dielectric layer.DE 10 2014 110 425 A1 describes a semiconductor device having a substrate which has a first and a second region, a first transistor (TR1) which is provided on the first region such that it has a first channel region, and a second transistor (TR2) which is provided on the second region such that it has a second channel region and a gate electrode which extends between the substrate and the second channel region. The first channel region may include a lower semiconductor structure including a material different from the second channel region and an upper semiconductor structure including the same material as the second channel region.The invention provides a semiconductor device according to claim 1 and a method according to claim 13. Embodiments of the invention are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with the usual practice in the industry, various elements are not drawn to scale and are only for description. Indeed, the dimensions of the various features may be increased or decreased as desired for clarity of description. FIG. 1 shows a schematic view of two gate stacks for I / O devices and core devices, in accordance with aspects of the present disclosure.FIGS. 2A and 2B show two cross-sectional views of an NFET (n-field effect transistor) I / O device in accordance with aspects of the present disclosure.FIGS. 3A and 3B show two cross-sectional views of an NFET core device in accordance with aspects of the present disclosure.FIGS. 4A and 4B show two cross-sectional views of a PFET (p-field effect transistor) I / O device in accordance with aspects of the present disclosure.FIGS. 5A and 5B show two cross-sectional views of a PFET core device in accordance with aspects of the present disclosure.FIGS. 6A and 6B show a flow diagram of a method of forming the devices shown in FIGS. 2A-5B, in accordance with aspects of the present disclosure.FIGS. 7A and 7B show a flow diagram of a method for preparing a structure to be processed with the method of FIGS. 6A-B, in accordance with aspects of the present disclosure.FIGS. 8A, 8B, 9A, 9B, 10, 11, 12, 13, 14, 15, 16, 17A, and 17B show cross-sectional views of a semiconductor structure during manufacturing methods according to the method of FIGS. 7A-B according to an embodiment.FIGS. 18, 19, 20, 21, 22, 23, 24, 25, and 26 show cross-sectional views of an NFET core device, an NFET I / O device, a PFET core device, and a PFET I / O device during manufacturing processes according to the process of FIGS. 7A-B, according to an embodiment.FIGS. 27, 28, 29, 30, 31, 32, 33, 34, and 35 show cross-sectional views of an NFET core device, an NFET I / O device, a PFET core device, and a PFET I / O device during manufacturing processes according to the process of FIGS. 6A-B, according to an embodiment.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples to implement various features of the subject matter recited. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.Further, spatially relative terms such as "bottom," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of an element or device with other element(s) or device(s) as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative terms used herein may also be interpreted accordingly.The present disclosure relates generally to semiconductor devices, and more particularly to integrated circuits (ICs) having I / O devices (or transistors) with a stacked fin channel and core devices (or transistors) with a nanowire channel. An object of the present disclosure is to form gate stacks for the I / O devices and the core devices by a low temperature method. This provides better S / D transition control for the IC. Another object of the present disclosure is to form the same interface layer in the I / O gate stacks and the core gate stacks and to tune one or more high-k dielectric layers over the interface layer to achieve different TDDB (gate dielectric) breakdown voltages in the two gate stacks. This provides a gain in performance by increasing the CET (capacity equivalent oxide thickness) scaling window. These and other advantages will become apparent after describing various embodiments of the present disclosure as exemplarily shown in FIGS. 1-35. Referring to FIG. 1, a gate stack (or gate structure) 10A for I / O devices and another gate stack (or gate structure) 10B for core devices are shown constructed in accordance with embodiments of the present disclosure. An I / O device provides input / output functions at the edge of an IC and a core device provides functionality within the IC (e.g., between core devices or between a core device and an I / O device). In an example, gate stacks 10A and 10B may be implemented in advanced process nodes, such as 2 nm processes. For example, in one embodiment, the I / O gate stack 10A may provide a breakdown voltage (V BD) of 3.0 V at a supply voltage (V dd) of 1.0 V, an n / p-TDDB (NFET-TDDB and PFET-TDDB) of 1.1 V, and a CET of 2.1 nm (21 angstroms (Å)). The core gate stack 10B provides a lower V BD, a lower n / p-TDDB, and a smaller CET than the I / O gate stack 10A.The I / O gate stack 10A includes an interfacial layer 12, a high-k dielectric stack 14A directly over the interfacial layer 12, and a conductive layer 16 directly over and in physical contact with the high-k dielectric stack 14A. The interfacial layer 12 may include silicon dioxide (SiO 2), aluminum oxide (Al 2 O3), aluminum silicon oxide (AlSiO), silicon oxynitride (SiON), or other suitable materials. In particular, in the present embodiment, the interfacial layer 12 has a thickness of 0.8 to 1.2 nm (8 to 12 Å), which is much thinner than the thickness of the conventional I / O gate oxide of about 3 to 4 nm (30 to 40 Å). The thin interfacial layer 12 avoids the high temperature post oxidation anneal (POA) process typically used to form a thick gate oxide in conventional I / O gate stacks. The high-k dielectric stack 14A includes one or more high-k dielectrics (or one or more layers of high-k dielectrics) such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO 2), aluminum oxide (Al 2 O3), zirconium oxide (ZrO 2), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), yttrium oxide (Y 2 O 3), strontium titanate (SrTiO 3) or a combination thereof. The conductive layer 16 includes one or more metal layers, such as one or more work function metal layers, conductive barrier layers, and metal fill layers. The work function metal layer may be a p- or an n-type work function layer, depending on the type (PFET or NFET) of the device. The p-type work function layer includes a metal selected from, without limitation, the group of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The n-type work function layer includes a metal selected from, without limitation, the group of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The metal fill layer may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials.The core gate stack 10B includes the interface layer 12, a high-k dielectric stack 14B directly over the interface layer 12, and the conductive layer 16 directly over and in physical contact with the high-k dielectric stack 14B. The high-k dielectric stack 14B includes one or more high-k dielectrics (or one or more layers of high-k dielectrics) such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO 2), aluminum oxide (Al 2 O3), zirconium oxide (ZrO 2), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), yttrium oxide (Y 2 O 3), strontium titanate (SrTiO 3) or a combination thereof.In the present embodiment, high-k dielectric stack 14A includes the same material layers as high-k dielectric stack 14B plus one or more additional high-k dielectric layers 15. In one example, high-k dielectric stack 14B includes a layer of HfO 2 of 1 to 2 nm (10 to 20 Å), and high-k dielectric stack 14A includes the same one or more layers as high-k dielectric stack 14B, and further includes a layer (layer 15) of Al 2 O 3 of 0.5 to 2 nm (5 to 20 Å). This simplifies the process flow of forming the I / O gate stack 10A and the core gate stack 10B in the same IC as will be shown later. In another example, high-k dielectric stack 14B includes a layer of HfO2over a layer of HfSiO, and high-k dielectric stack 14A includes the same layers as high-k dielectric stack 14B, and further includes a layer (layer 15) of Al2O3. In another embodiment, high-k dielectric stacks 14A and 14B comprise the same material layers, but high-k dielectric stack 14A is thicker than high-k dielectric stack 14B, for example, by 0.5 to 2 nm (5 to 20 Å). For example, both high-k dielectric stacks 14A and 14B may include a layer of HfO 2 but the layer of HfO 2 in high-k dielectric stack 14A is 0.5 to 2 nm (5 to 20Å) thicker than the HfO 2- layer in high-k dielectric stack 14B. The difference in thickness of the high-k dielectric stacks 14A and 14B may be tuned by selectively etching the high-k dielectric stack 14B.FIGS. 2A-5B show example semiconductor devices implementing gate stacks 10A and / or 10B. FIG. 2A shows a cross-sectional view of an NFET I / O device 100A cut along the length of the FET channel or the length of the fin in a FinFET (such a view is referred to as an "X-cut" below). FIG. 2B shows a cross-sectional view of the NFET I / O device 100A cut along the width of the FET channel or the width of the fin in a FinFET (such a view is referred to as a "Y-cut" below). FIGS. 3A and 3B show an NFET core device 100B in X-section and Y-section, respectively. FIGS. 4A and 4B show a PFET I / O device 100C in X-cut and Y-cut, respectively. FIGS. 5A and 5B show a PFET core device 100D in X-section and Y-section, respectively. Referring to FIGS. 2A and 2B, the device 100A includes a substrate 102 and a stacked fin 104A over the substrate 102. The stacked fin 104A includes multiple layers 105 of a first semiconductor material and multiple layers 106 of a second semiconductor material that are alternately stacked (therefore, the term "stacked fin"). The device 100A further includes an isolation structure 103 that isolates multiple stacked fins 104A (two in FIG. 2B ).The substrate 102 is a silicon substrate in the present embodiment. Alternatively, the substrate 102 may comprise another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In the present embodiment, the devices 100A, 100B, 100C, and 100D are constructed on the same substrate 102.The isolation structure 103 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), a low-k dielectric, and / or other suitable insulating material. The isolation structure 103 may be a shallow trench isolation (STI) feature. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures are possible. The isolation structure 103 may include a multilayer structure including, for example, one or more thermal oxide liner layers.The first semiconductor material (in the layers 105) differs from the second semiconductor material (in the layers 106) in material and / or composition. Each of the first semiconductor material and the second semiconductor material may include silicon, germanium, a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, or an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP. In the present embodiment, the layers 105 comprise silicon and the layers 106 comprise germanium or silicon-germanium alloy. The layers 105 and 106 in the stacked fin 104A may additionally include dopants to improve performance of the NFET I / O device 100A. For example, layer 105 may include one or more n-type dopants such as phosphorus or arsenic and layer 106 may include one or more p-type dopants such as boron or indium.The device 100A further includes a gate stack (or gate structure) 107A and gate spacers 108 on the sidewalls of the gate stack 107A. The gate stack 107A engages the stacked fin 104A in the channel region of the device, for example, on the top and sidewalls of the stacked fin 104A, as shown in FIG. 2B. Gate stack 107A includes an interfacial layer 120, a high-k dielectric stack 121 having high-k dielectric layers 122 and 124, and a conductive layer 126A. In an embodiment, the interface layer 120, high-k dielectric stack 121, and conductive layer 126A may use the same materials as the interface layer 12, high-k dielectric stack 14A, and conductive layer 16 of FIG. 1, respectively. For example, the interfacial layer 120 may include silicon dioxide (SiO 2) having a thickness of 0.8 to 1.2 nm (8 to 12 Å), the high-k dielectric layer 122 may include hafnium oxide (HfO 2) having a thickness of 1 to 2 nm (10 to 20 Å), the high-k dielectric layer 124 may include aluminum oxide (Al 2 O 3) having a thickness of 0.5 to 2 nm (5 to 20 Å), and the conductive layer 126A may include one or more n-type work function metal layers and a metal fill layer. Each of the high-k dielectric layers 122 and 124 may include one or more material layers. In the present embodiment, the interfacial layer 120 and the high-k dielectric stack 121 are formed as conformal layers on the top and sidewalls of the stacked fin 104A and on sidewalls of the gate spacers 108.The device 100A further includes S / D features 110A partially embedded in the stacked fin 104A and adjacent to the gate spacers 108, and dielectric layers 112, 114, and 116 over the S / D features 110A and between the gate spacers 108.The gate spacers 108 include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another dielectric material, or combinations thereof. The S / D features 110A may include n-doped silicon, such as n-doped epitaxially grown silicon, in one embodiment. The dielectric layer 112 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials. The dielectric layer 114 may comprise tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectrics. The dielectric layer 116 may include a nitride such as silicon nitride to protect the dielectric layer 114 during various etching processes, which will be described later.Referring to FIGS. 3A and 3B, cross-sectional views of the NFET core device 100B are shown. Many aspects of device 100B are the same as or similar to device 100A. For example, in the present embodiment, device 100B also includes substrate 102, isolation structure 103, gate spacers 108, S / D features 110A, and dielectric layers 112, 114, and 116. Unlike device 100A, device 100B includes nanowire channel 104B. In the present embodiment, nanowire channel 104B comprises nanowires of the first semiconductor material (made of layers 105), while layers 106 have been removed from the channel region of device 100B. It is noted that in the S / D regions of device 100B, layers 105 and 106 are still alternately stacked. Another difference between the devices 100A and 100B is that the device 100B includes a gate stack 107B configured for the core device 100B. Gate stack 107B includes interface layer 120, high-k dielectric layer 122 (which may include one or more layers of high-k dielectrics), and conductive layer 126A. In an embodiment, the interface layer 120, high-k dielectric layer 122, and conductive layer 126A may use the same materials as the interface layer 12, high-k dielectric stack 14B, and conductive layer 16 of FIG. 1, respectively. Gate stack 107B has a thinner high-k dielectric stack or fewer high-k dielectric layers between interfacial layer 120 and conductive layer 126A than gate stack 107A (see FIGS. 2A-B ). The gate stack 107B engages the nanowire channel 104B, for example, by enclosing the nanowires of the nanowire channel 104B, as shown in FIG. 3B. One reason that channel 104A (see FIGS. 2A-B) in the present embodiment has a stacked fin instead of the nanowires (such as channel 104B) is that device 100A may have a relatively thicker dielectric stack (including interface layer 120 and high-k dielectric layers 122 and 124), which may then be too thick to fit into the space between adjacent nanowires.Referring to FIGS. 4A and 4B, cross-sectional views of the PFET I / O device 100C are shown. Many aspects of device 100C are the same as or similar to device 100A. For example, the device 100C also includes the substrate 102, the isolation structure 103, the gate spacers 108, and the dielectric layers 112, 114, and 116. The device 100C includes a stacked fin 104C having alternating stacked layers 105 and 106. The layers 105 and 106 in the stacked fin 104C may additionally include dopants to improve performance of the PFET I / O device 100C. Device 100C includes gate stack 107C including interfacial layer 120, high-k dielectric stack 121, and conductive layer 126C, which may use the same materials as interfacial layer 12, high-k dielectric stack 14A, and conductive layer 16 of FIG. 1, respectively. Unlike the conductive layer 126A, the conductive layer 126C is configured for the PFET device 100C, for example, by using one or more p-type work function metal layers. The device 100C further includes S / D features 110C configured for the PFET device 100C, for example, by using p-doped silicon germanium, such as p-doped epitaxially grown silicon germanium. Referring to FIGS. 5A and 5B, cross-sectional views of the PFET core device 100D are shown. Many aspects of device 100D are the same as or similar to device 100C. For example, device 100D also includes substrate 102, isolation structure 103, gate spacers 108, S / D features 110C, and dielectric layers 112, 114, and 116. Unlike device 100C, device 100D includes nanowire channel 104D. In the present embodiment, nanowire channel 104D comprises nanowires of the second semiconductor material (made of layers 106), while layers 105 are removed from the channel region of device 100D. It is noted that in the S / D regions of device 100D, layers 105 and 106 are still alternately stacked. Another difference between the devices 100C and 100D is that the device 100D includes a gate stack 107D configured for the core device 100D. Gate stack 107D includes interfacial layer 120, high-k dielectric layer 122 (which may include one or more layers of high-k dielectrics), and conductive layer 126C. In an embodiment, the interface layer 120, the high-k dielectric layer 122, and the conductive layer 126C may use the same materials as the interface layer 12, the high-k dielectric stack 14B, and the conductive layer 16 of FIG. 1, respectively. Gate stack 107D includes a thinner high-k dielectric stack or fewer high-k dielectric layers between interfacial layer 120 and conductive layer 126C than gate stack 107C. For example, gate stack 107D engages nanowire channel 104D by enclosing the nanowires of nanowire channel 104D, as shown in FIG. 5B. One reason that channel 104C (see FIGS. 4A-B) includes a stacked fin instead of nanowires (such as channel 104D) in the present embodiment is that device 100C may include a relatively thicker dielectric stack (including interface layer 120 and high-k dielectric layers 122 and 124), which may then be too thick to fit into the space between adjacent nanowires.FIGS. 6A-B show a flow diagram of a method 200 for forming the devices 100A, 100B, 100C, and 100D in the same IC. FIGS. 7A-B show a flow diagram of a method 300 for providing an initial structure for the method 200. Methods 200 and 300 are merely examples and are not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional operations may be provided before, during, and after each of the methods 200 and 300, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the methods. Methods 200 and 300 are described below in connection with FIGS. 8A-35.At operation 202, the method 200 (FIG. 6A ) provides a structure (or device structure) including an NFET I / O device structure 100A, an NFET core device structure 100B, a PFET I / O device structure 100C, and a PFET core device structure 100D, as shown in FIG. 26. Referring to FIG. 26, for simplicity, the four device structures are shown in two rows and three columns. The upper row shows cross-sectional views of the NFET device structures 100A and 100B, and the lower row shows cross-sectional views of the PFET device structures 100C and 100D. The leftmost column shows the NFET core device structure 100B and the PFET core device structure 100D in an X-cut view. The middle column shows the NFET core device structure 100B and the PFET core device structure 100D in a Y-sectional view. The rightmost column shows the NFET I / O device structure 100A and the PFET I / O device structure 100C in a Y-sectional view. The X-sectional views of the device structures 100A and 100C are not shown in FIG. 26 (and in FIGS. 18-25 and 27-35 ), but those skilled in the art may derive these views from FIGS. 2A and 4A, for example.Still referring to FIG. 26, each of the device structures 100A, 100B, 100C, and 100D includes the substrate 102, the isolation structure 103, the gate spacers 108, and the dielectric layers 112, 114, and 116. Each of the four device structures further includes a gate trench 166 where the gate spacers 108 are the sidewalls and expose the channel region of the respective device structures. The I / O device structures 100A and 100C include stacked fin channels 104A and 104C, respectively, and each of the two stacked fin channels 104A and 104C includes the alternating stacked layers 105 and 106. The NFET core device structure 100B includes a nanowire channel 104B having nanowires 105. The PFET core device structure 100D includes a nanowire channel 104D having nanowires 106. In the present embodiment, features 105 include silicon, such as silicon in a crystalline structure, and may be doped with one or more n-type dopants, such as phosphorus or arsenic. Further, the features 106 include germanium, for example germanium in a crystalline structure, or silicon-germanium alloy, and may be doped with one or more p-dopants such as boron or indium. The outer surfaces of the stacked fin channels 104A and 104C and nanowire channels 104B and 104D are exposed in the respective gate trenches 166. The NFET device structures 100A and 100B include the n-S / D features 110A, while the PFET device structures 100C and 100D include the p-S / D features 110C.Forming the device structures shown in FIG. 26 from an initial substrate includes a variety of methods, one embodiment of which is shown in FIGS. 7A and 7B in conjunction with FIGS. 8A-25.Referring to FIG. 7A, at operation 302, the method 300 provides a structure including an NFET I / O device structure, an NFET core device structure, a PFET I / O device structure, and a PFET core device structure. Each of the device structures includes a stacked fin channel, a dummy gate engaging the stacked fin channel, gate spacers on the sidewalls of the dummy gate, and S / D features adjacent the gate spacers. The process 302 also includes a variety of methods, as shown in FIGS. 8A-16.Referring to FIGS. 8A (X section) and 8B (Y section), a device structure 100 is shown, which may be any of the NFET I / O device structure 100A, the NFET core device structure 100B, the PFET I / O device structure 100C, and the PFET core device structure 100D. The device structure 100 includes the substrate 102, stacked fins 104 (two are shown) over the substrate 102, and the isolation structure 103 that laterally isolates the fins 104. In the stacked fins 104, the layers 105 and 106 are alternately stacked. The stacked fins 104 may be formed by epitaxially growing the layers 105 and 106 over the entire surface of the substrate 102 and subsequently patterning to form the individual fins 104. The fins 104 may be patterned by any suitable method. For example, the fins 104 may be patterned using one or more photolithography techniques, such as dual-patterning or multi-patterning techniques. Generally, double patterning or multi-patterning techniques combine photolithography and self-aligned techniques so that patterns can be created having, for example, center spacings that are less than those otherwise obtained with a single, direct photolithography technique. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography method. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers or mandrels may then be used to pattern the fins 104 by etching the initial layers 105 and 106. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable methods.Referring to FIGS. 9A (X cut) and 9B (Y cut), the process 302 further forms a dummy interface layer 150, a dummy gate electrode 152, a first hard mask layer 154, and a second hard mask layer 156, which are sequentially stacked over the fins 104. The process 302 further forms the gate spacers 108 over the sidewalls of the layers 150, 152, 154, and 156. The dummy interface layer 150 may include a dielectric material such as a silicon oxide layer (e.g., SiO 2) or silicon oxynitride (e.g., SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The dummy gate electrode 152 may include polycrystalline silicon (poly-Si) and may be formed by suitable deposition methods such as low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD). The two hard mask layers 154 and 156 may include one or more layers of a dielectric material such as silicon oxide and / or silicon nitride, and may be formed by CVD or other suitable methods. The various layers 150, 152, 154, and 156 may be patterned by photolithography and etching techniques. The gate spacers 108 may include a dielectric, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectrics, or combinations thereof, and may include one or more layers of material. The gate spacers 108 may be formed by depositing a spacer material as a capping layer over the isolation structure 103, the fins 104, and the dummy gate stack 150 / 152 / 154 / 156. Then, the spacer material is etched by an anisotropic etch process to expose the isolation structure 103, the hard mask layer 156, and a top surface of the fins 104. Portions of the spacer material on the sidewalls of the dummy gate stack 150 / 152 / 154 / 156 become the gate spacers 108. Adjacent gate spacers 108 provide trenches 158 that expose the fins 104 in the S / D regions of the device.Referring to FIG. 10 (X section), the act 302 forms S / D features 110 in the S / D regions. For example, the process 302 may etch recesses into the fins 104 exposed in the trenches 158 and epitaxially grow semiconductor materials in the recesses. The semiconductor materials may be raised above the top surface of the fins 104, as shown in FIG. 10. The operation 302 may form the S / D features 110 for the NFET and PFET devices separately. For example, the act 302 may form the S / D features 110 with an n-doped silicon for the NFET devices (e.g., 110A of FIGS. 2A, 3A, and 26) and with a p-doped silicon germanium for the PFET devices (e.g., 110C of FIGS. 4A, 5A, and 26).Referring to FIG. 11 (X section), the process 302 forms the dielectric layers 112 and 114. The dielectric layer 112 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials; and may be formed by CVD, PVD (physical vapor deposition), ALD, or other suitable methods. The dielectric layer 114 may comprise tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectrics. The dielectric layer 114 may be formed by PECVD or FCVD (flowable CVD), or other suitable methods. Referring to FIG. 12 (X cut), the operation 302 performs an etch back process or a CMP (chemical mechanical polishing) process to remove the hard mask layer 156 and expose the hard mask layer 154. Referring to FIG. 13 (X cut), the operation 302 performs a rotary CMP process to remove the hard mask layer 154 and expose the dummy gate electrode 152. Referring to FIG. 14 (X section), the process 302 applies an etch back process to the dielectric layer 114 to recess under the top surface of the gate spacers 108. Referring to FIG. 15 (X cut), the process 302 deposits a dielectric layer 116, which may include a nitride such as silicon nitride, to protect the dielectric layer 114 during subsequent etching processes. Referring to FIG. 16 (X cut), the operation 302 performs a CMP process to planarize the upper surface of the device structure 100.At operation 304, the method 300 (FIG. 7A ) removes the dummy gate electrode 152, resulting in a gate trench 166 (see FIGS. 17A-B ). The operation 304 may include one or more etch processes that are selective to the material in the dummy gate electrode 152. The resulting structure 100 is shown in FIG. 17A (X cut) and FIG. 17B (Y cut), wherein the dummy interfacial layer 150 is exposed in the gate trench 166.At operation 306, the method 300 (FIG. 7A ) forms an etch mask 168 covering the NFET I / O device structure 100A, PFET I / O device structure 100C, and PFET core device structure 100D, as shown in FIG. 18. As described above, at this stage of fabrication, device structures 100A, 100B, 100C, and 100D may be prepared by operations 302 and 304 as shown in FIGS. 8A-17B, where device structure 100 may be any of device structures 100A, 100B, 100C, and 100D. The etch mask 168 may be a patterned photoresist formed by photoresist coating, exposure, post exposure bake, and development in one example. The NFET core device structure 100B is exposed by the etch mask 168.At operation 308, the method 300 (FIG. 7A ) removes the dummy interface layer 150 from the NFET core device structure 100B, for example, by wet etching, dry etching, reactive ion etching, or other suitable etching methods. For example, operation 308 may use one or more HF-based wet etchants for wet etching or an NH 3- H 2- mixture for dry etching. During this process, the etch mask 168 covers the NFET I / O device structure 100A, PFET I / O device structure 100C, and PFET core device structure 100D.At operation 310, the method 300 (FIG. 7A ) removes the etch mask 168 by ashing or stripping, for example. The resulting device structures are shown in FIG. 19. Referring to FIG. 19, the stacked fin 104B is exposed in the gate trench 166 in the NFET core device structure 100B, and the dummy interface layer 150 is exposed in the gate trenches 166 in the other device structures 100A, 100C, and 100D.At operation 312, the method 300 (FIG. 7A ) forms nanowires 150 in the NFET core device structure 100B, as shown in FIG. 20. In an embodiment, the fins 104B may include an interfacial control layer, such as a silicon cap, on the surfaces of the fins 104B. Continuing with this embodiment, operation 312 includes a step of removing the interfacial control layer, for example, by applying a wet etch with NH 4 OH or TMAH based etchants or by applying a dry etch with NH 3- H2gas mixture. In the present embodiment, layers 105 comprise silicon and layers 106 comprise silicon germanium. In furtherance of this embodiment, operation 312 includes a dry etching process to selectively remove the layers 106 from the channel region of the device structure 100B. For example, the dry etching method may use an HCl gas having a temperature of 500 to 700° C. or a mixed gas of CF 4, SF 6 and CHF 3. Because the dummy interface layer 150 covers the fins 104A, 104C, and 104D, the operation 312 forms the nanowires 105 only in the device structure 100B.At operation 314, the method 300 (FIG. 7A ) forms a passivation layer 170 covering the various device structures 100A, 100B, 100C, and 100D, as shown in FIG. 21. In an embodiment, the passivation layer 170 includes a nitride layer over an oxide layer. For example, the oxide layer may include silicon dioxide (SiO 2), aluminum oxide (Al 2 O3), aluminum silicon oxide (AlSiO), hafnium silicon oxide (HfSiO), and other types of oxides; and the nitride layer may include silicon nitride (Si 3 N 4), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide oxynitride (SiCON), and other types of nitride. Each layer in the passivation layer 170 may be formed by CVD, PVD, ALD, or other suitable deposition methods.At operation 316, the method 300 (FIG. 7B ) forms an etch mask 172 covering the NFET I / O device structure 100A, the NFET core device structure 100B, and the PFET I / O device structure 100C, as shown in FIG. 22. The PFET core device structure 100D is exposed by the etch mask 172. The etch mask 172 may be a patterned photoresist similar to the etch mask 168.At operation 318, the method 300 (FIG. 7B ) removes the passivation layer 170 from the PFET core device structure 100D, thereby exposing the dummy interface layer 150 therein. In an embodiment, the operation 318 may include one or more etching processes to remove the passivation layer 170. For example, operation 318 may use a wet etchant with H3PO4to remove the nitride layer in passivation layer 170, and then use a wet etchant with an HF-based solution (e.g., a mixture of HF and NH 4 F), NH 4 OH, or TMAH to remove the oxide layer in passivation layer 170. Further, operation 318 may apply a dry etch (e.g., using NH 3- H 2- gas mixture) instead of a wet etch to remove the oxide layer in the passivation layer 170.At operation 320, the method 300 (FIG. 7B ) removes the etch mask 172 from the various structures. In an embodiment, the process 320 may employ an ashing process or a stripping process to remove the etch mask 172. The resulting device structures after operations 318 and 320 are shown in FIG. 23.At operation 322, the method 300 (FIG. 7B ) removes the dummy interface layer 150 from the PFET core device structure 100D, for example, by wet etching, dry etching, reactive ion etching, or other suitable etching methods, similar to operation 308. During this process, the passivation layer 170 covers the NFET I / O device structure 100A, NFET core device structure 100B, and PFET I / O device structure 100C.In operation 324, the method 300 (FIG. 7B ) forms nanowires in the PFET core device structure 100D. In an embodiment, the fins 104D may include an interfacial control layer, such as a silicon cap, on the surfaces of the fins 104D. Continuing with this embodiment, operation 324 includes a step of removing the interfacial control layer, for example, as described with reference to operation 312. In the present embodiment, layers 105 comprise silicon and layers 106 comprise silicon germanium. In furtherance of this embodiment, operation 324 may include a dry etch process to selectively remove the layers 105 from the channel region of the device structure 100D. For example, the dry etching process may introduce a mixed gas of NH 3 and H 2. Alternatively, the act 324 may include a wet etching process to selectively remove the layers 105 from the channel region of the device structure 100D. For example, the wet etching process may use one or more NH 4 OH or TMAH based wet etchants. The resulting device structures after operations 322 and 324 are shown in FIG. 24.At operation 326, the method 300 (FIG. 7B ) removes the passivation layer 170 from the various structures, for example, using methods described with reference to operation 318. The resulting device structures are shown in FIG. 25.At operation 328, the method 300 (FIG. 7B ) removes the dummy interface layer 150 from the NFET I / O device structure 100A and the PFET I / O device structure 100C, similar to operation 308. Operation 328 employs a selective etch process in which the etchant / etchants selectively remove the dummy interface layer 150 while the features 104A, 104C, 105, and 106 remain substantially intact. The resulting device structures are shown in FIG. 26.At operation 204, the method 200 (FIG. 6A ) forms an interfacial control layer 174 in the gate trenches 166. Referring to FIG. 27, in the present embodiment, the interfacial control layer 174 is formed over the stacked fin channels 104A and 104C and the nanowires 104B and 104D. The interfacial control layer 174 may also be deposited directly over the isolation structure 103, the gate spacers 108, and top surfaces of the various structures 100A, 100B, 100C, and 100D. In an embodiment, the interfacial control layer 174 may include silicon and may be formed by CVD epitaxy. In another embodiment, the interfacial control layer 174 may have Si-S (silicon-sulfur) bonds and SiGe-S (silicon-germanium-sulfur) bonds and may be formed by treating the various surfaces with a sulfur-containing chemical. In yet another embodiment, the interfacial control layer 174 may have Si-N (silicon-nitrogen) bonds and SiGe-N (silicon-germanium-nitrogen) bonds and may be formed by treating the various surfaces with a nitrogen-containing chemical, such as NH 3- gas. In various embodiments, the interfacial control layer 174 may be formed to have a thickness of less than 1 nm. The interfacial control layer 174 helps to improve the flatness of the various surfaces for subsequent deposition of the interfacial layer 120. In some embodiments of method 200, operation 204 is optional and may be omitted.At operation 206, the method 200 (FIG. 6A ) deposits the interface layer 120 over the interface control layer 174 in the gate trenches 166 (FIG. 28 ). At operation 208, the method 200 (FIG. 6A ) deposits the high-k dielectric stack 121 (comprising one or more high-k dielectric layers) over the interfacial layer 120 (FIG. 28 ). Referring to FIG. 28, in device structures 100A and 100C, interfacial layer 120 and high-k dielectric stack 121 are deposited over the top and sidewall surfaces of stacked fins 104A and 104C, over the top surface of isolation structure 103, and on sidewalls of gate spacer 108. In device structures 100B and 100D, interfacial layer 120 and high-k dielectric stack 121 are deposited around the surfaces of nanowires 104B and 104D, over the top surface of isolation structure 103, and on sidewalls of gate spacer 108. The interface layer 120 and the high-k dielectric stack 121 are deposited as substantially conformal layers in the present embodiment.The interfacial layer 120 may include silicon dioxide (SiO 2), aluminum oxide (Al 2 O 3), aluminum silicon oxide (AlSiO), silicon oxynitride (SiON), or other suitable materials, and may be deposited using chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. Specifically, in the present embodiment, the interface layer 120 has a thickness of 0.8 to 1.2 nm (8 to 12 Å).The high-k dielectric stack 121 includes one or more layers of high-k dielectrics. In the embodiment shown, the high-k dielectric stack 121 includes two layers 122 and 124 of different high-k dielectrics. Each of the two layers 122 and 124 may include a high-k dielectric material, for example, hafnium silicon oxide (HfSiO), hafnium oxide (HfO 2), aluminum oxide (Al 2, O 3), zirconium oxide (ZrO 2), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), yttrium oxide (Y 2 O 3) and strontium titanate (SrTiO 3). In a particular embodiment, layer 122 comprises hafnium oxide (HfO 2) from 1 to 2 nm (10 to 20 Å) and layer 124 comprises aluminum oxide (Al 2 O 3) from 0.5 to 2 nm (5 to 20 Å). In another embodiment (not shown), high-k dielectric stack 121 includes three layers of different high-k dielectrics, for example, a layer of Al 2 O 3 over a layer of HfO 2 over a layer of HfSiO. In yet another embodiment, high-k dielectric stack 121 includes only a single layer of high-k dielectric, such as a 3 to 4 nm (30 to 40 Å) HfO 2- layer. The high-k dielectric stack 121 may be deposited using CVD, ALD, and / or other suitable methods.At operation 210, the method 200 (FIG. 6A ) forms a hard mask 176 covering the device structures 100A, 100B, 100C, and 100D, as shown in FIG. 29. In an embodiment, the hard mask 176 may comprise a metal nitride such as titanium nitride (TiN) and may be deposited using CVD, PVD, ALD, or other suitable methods.At operation 212, the method 200 (FIG. 6A ) forms an etch mask 178 covering the NFET I / O device structure 100A and the PFET I / O device structure 100C, leaving the NFET core device structure 100B and the PFET core device structure 100D exposed by the etch mask 178. Referring to FIG. 30, in the present embodiment, the etch mask 178 may be a patterned photoresist formed by photoresist coating, exposure, post-exposure bake, and development in one example. In the present embodiment, the hard mask 176 prevents the photoresist 178 from directly contacting the high-k dielectric stack 121, as such direct contacting could introduce defects into the high-k dielectric stack 121.At operation 214, the method 200 (FIG. 6A ) removes the hard mask 176 from the NFET core device structure 100B and the PFET core device structure 100D. The act 214 may remove the hard mask 176 using, for example, an HF-based acidic solution, an H 2 O 2- based solution, a sulfur peroxide mixture (SPM), or other oxidants. The resulting device structures are shown in FIG. 31 where the high-k dielectric stack 121 is exposed in the device structures 100B and 100D.At operation 216, the method 200 (FIG. 6B ) removes the etch mask 178 from the NFET I / O device structure 100A and the PFET I / O device structure 100C. The act 216 may use ashing or stripping to remove the etch mask 178 in one example. The resulting device structures are shown in FIG. 32 where high-k dielectric stack 121 is exposed in device structures 100B and 100D and hard mask 176 covers device structures 100A and 100C.At operation 218, the method 200 (FIG. 6B ) partially removes the high-k dielectric stack 121 in the NFET core device structure 100B and the PFET core device structure 100D while the hard mask 176 protects the device structures 100A and 100C. Referring to FIG. 33, high-k dielectric stack 121 has been partially removed from device structures 100B and 100D (in this example, layer 124 has been removed). In an embodiment, one or more top layers in high-k dielectric stack 121 are removed by operation 218. Continuing with this embodiment, operation 218 applies one or more etching processes to selectively remove the one or more uppermost layers while maintaining other layers intact. In an example, high-k dielectric stack 121 includes a layer of Al 2 O 3 over a layer of HfO 2. Operation 218 may employ a wet etchant with DHF (diluted hydrogen fluoride) or a mixture of HF and NH 4 F to selectively remove the layer of Al 2 O 3 where the layer of HfO 2 has good resistance to these etchants. In another embodiment, the top layer in the high-k dielectric stack 121 is only partially removed by the operation 218. In an example not shown, the high-k dielectric stack 121 is a single layer of HfO2. Operation 218 may employ a wet etch process, a dry etch process, a reactive ion etch process, or an atomic layer etch process to partially recess the single layer of HfO 2 such as by 0.5 to 2 nm (5 to 20 Å). Operation 218 may control the etch depth by a timer or using other suitable methods.At operation 220, the method 200 (FIG. 6B ) removes the hard mask 176 from the NFET I / O device structure 100A and the PFET I / O device structure 100C. The resulting device structures are shown in FIG. 34, where high-k dielectric stack 121 is exposed in I / O device structures 100A and 100C and a partial high-k dielectric stack 121 (layer 122 in this example) is exposed in core device structures 100B and 100D. In the present embodiment, operation 220 applies etchants that selectively remove hard mask 176 while maintaining layer 124 (in I / O device structures 100A and 100C) and layer 122 (in core device structures 100B and 100D) substantially intact. In an example, the hard mask 176 includes titanium nitride and the operation 220 may apply a DHF-based or H 2 O 2- based etchant to selectively remove the hard mask 176.At operation 222, the method 200 (FIG. 6B ) deposits one or more conductive layers in the gate trenches 166. Referring to FIG. 35, the one or more conductive layers 126A and 126C are filled into the gate trenches 166 (FIG. 34 ) and directly over the high-k dielectric layers 124 and 122. For the NFET device structures 100A and 100B, the conductive layers 126A may include one or more n-type work function metals and a metal fill layer. For the PFET device structures 100C and 100D, the conductive layers 126C may include one or more p-type work function metals and a metal fill layer. The metal fill layer in the NFET and PFET device structures may use the same material / s. The operation 222 may include multiple deposition and etching processes to deposit the conductive layers 126A and 126C for the respective NFET and PFET device structures. The n-type work function layer comprises a metal having a sufficiently low effective work function selected from, without limitation, the group of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The p-type work function layer comprises a metal having a sufficiently high effective work function selected from, without limitation, the group of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The work function metal layers may include a plurality of layers and may be deposited by CVD, PVD, and / or other suitable methods. The metal fill layer may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials; and may be formed by CVD, PVD, plating, and / or other suitable methods. Operation 222 may perform a CMP process to remove excess materials from device structures 100A, 100B, 100C, and 100D to planarize a top surface of the respective device.The method 200 (FIG. 6B ) may perform additional operations to form a finished device. For example, the method 200 may form contacts and vias that electrically connect the S / D features 110A / C and the conductive layers 126A / C, and may form metal interconnects that connect the various transistors to form a completed IC.Without limitation, one or more embodiments of the present disclosure provide many advantages to a semiconductor device and its formation. For example, embodiments of the present disclosure form metal gate stacks without performing a high temperature post oxidation anneal (POA) process. This advantageously improves the S / D transition control. Further, metal gate stacks according to the present embodiments include a very thin silicon dioxide interface layer (e.g., from 0.8 to 1.2 nm (8-12 Å)) that supports continuous scaling down of the I / O transistors. Furthermore, embodiments of the present disclosure form the same initial high-k dielectric layers in the gate stacks of the I / O transistors and the core transistors and selectively remove some of the high-k dielectric layers from the core transistors to achieve different characteristics (such as TDDB and V BD) in the I / O and core transistors. This simplifies the IC manufacturing processes.

Claims

A semiconductor device, comprising: a substrate (102); an I / O device (100A) over the substrate; and a core device (100B) over the substrate, wherein the I / O device and the core device are either both NFETs or are both PFETs, wherein the I / O device comprises a gate trench (166), a stacked fin in the gate trench, and a first gate structure (10A; 107A; 107C), wherein the stacked fin comprises first and second semiconductor materials that are different and that are alternately stacked, wherein the first gate structure comprises: an interfacial layer (12; 120) over surfaces of the stacked fin; a first high-k dielectric stack (14A; 121) over the interfacial layer; and a conductive layer (16; 126) over and in physical contact with the first high-k dielectric stack, wherein the core device comprises a gate trench, nanowires in the gate trench, and a second gate structure (10B; 107B; 107D), the second gate structure having: the interface layer (12; 120); a second high-k dielectric stack (14B; 122) over the interface layer; and the conductive layer (16; 126) over and in physical contact with the second high-k dielectric stack, and wherein the first high-k dielectric stack (14A; 121) comprises the second high-k dielectric stack (14B; 122) and a third dielectric layer (15; 124) above the second high-k dielectric stack, wherein the first high-k dielectric stack (14A; 121) comprises at least two different high-k dielectric layers (122; 124), and the first high-k dielectric stack (14A; 121) and the second high-k dielectric stack (14B; 122) have at least the same lowermost high-k dielectric layer (122).The semiconductor device of claim 1, wherein the interfacial layer (12; 120) comprises silicon dioxide (SiO 2) having a thickness in the range of 0.8 to 1.2 nm.The semiconductor device of claim 1 or 2, wherein the first high-k dielectric stack (14a; 121) is 0.5 to 2 nm thicker than the second high-k dielectric stack (14B; 122).The semiconductor device according to any of the preceding claims, wherein the third dielectric layer (15;124) has a dielectric constant higher than that of silicon dioxide (SiO 2) and lower than that of the second high-k dielectric stack (14B;122).The semiconductor device of any preceding claim, wherein the second high-k dielectric stack (14B; 122) has a dielectric constant in the range of 15 to 30.The semiconductor device of any preceding claim, wherein: the interfacial layer (12; 120) comprises silicon dioxide (SiO 2) having a thickness in the range of 0.8 to 1.2 nm; the second high-k dielectric stack (14B; 122) comprises hafnium oxide (HfO 2) having a thickness in the range of 1 to 2 nm; and the third dielectric layer (15; 124) comprises aluminum oxide (Al 2 O 3) having a thickness in the range of 0.5 to 2 nm.The semiconductor device of any preceding claim, wherein the I / O device (100A) includes a first channel (104A) below the first gate structure (10A; 107A; 107C), the first channel including the first and second semiconductor materials (105, 106) that are alternately stacked.The semiconductor device of any preceding claim, wherein the nanowires comprise the first semiconductor material.The semiconductor device of any preceding claim, wherein the first semiconductor material comprises silicon, germanium or a silicon-germanium alloy.The semiconductor device of claim 1, wherein the interfacial layer (12; 120) comprises silicon dioxide (SiO 2), aluminum oxide (Al 2 O3), aluminum silicon oxide (AlSiO), or silicon oxynitride (SiON).The semiconductor device of claim 1, wherein high-k dielectric layers (14B; 122) of the high-k dielectric stacks comprise hafnium silicon oxide (HfSiO), hafnium oxide (HfO 2), aluminum oxide (Al 2 O3), zirconium oxide (ZrO 2), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), yttrium oxide (Y 2 O 3), strontium titanate (SrTiO 3) or a combination thereof.A semiconductor device according to any preceding claim, comprising: an NFET I / O device (100A), an NFET core device (100B), a PFET I / O device (100C), and a PFET core device (100D), wherein the NFET I / O device (100A) and the PFET I / O device (100C) are constructed according to the I / O device according to any preceding claim, and the NFET core device (100B) and the PFET core device (100D) are constructed according to the core device according to any preceding claim.A method (200) comprising: providing an NFET I / O device structure (100A), an NFET core device structure (100B), a PFET I / O device structure (100C), and a PFET core device structure (100D), wherein each of the NFET I / O device structure (100A) and the PFET I / O device structure (100C) comprises a gate trench (166) and a stacked fin (104) exposed in the gate trench (166), wherein the stacked fin (104) comprises first and second semiconductor materials that are alternately stacked, wherein each of the NFET core device structure (100B) and the PFET core device structure (100D) comprises a gate trench (166) and nanowires exposed in the gate trench (166); depositing an interfacial layer over surfaces of the stacked fin (104) and the nanowires exposed by the respective gate trenches (166); depositing one or more high-k dielectric layers over the interfacial layer in each of the gate trenches (166); forming a hard mask (176) covering the one or more high-k dielectric layers in the NFET I / O device structure (100A) and the PFET I / O device structure (100C) while exposing the one or more high-k dielectric layers in the NFET core device structure (100B) and the PFET core device structure (100D); partially removing the one or more high-k dielectric layers in the NFET core device structure (100B) and the PFET core device structure (100D) while the hard mask (176) covers the one or more high-k dielectric layers in the NFET I / O device structure (100A) and the PFET I / O device structure (100C), leaving a portion of the one or more high-k dielectric layers in the NFET core device structure (100B) and the PFET core device structure (100D); Removing the hard mask (176) from the NFET I / O device structure (100B) and the PFET I / O device structure (100C); and depositing one or more conductive layers over the one or more high-k dielectric layers in the NFET I / O device structure (100A) and the PFET I / O device structure (100C), and over the portion of the one or more high-k dielectric layers in the NFET core device structure (100B) and the PFET core device structure (100D).The method of claim 13, wherein the one or more high-k dielectric layers comprise a first high-k dielectric layer and a second high-k dielectric layer over the first high-k dielectric layer.The method of claim 14, wherein partially removing the one or more high-k dielectric layers completely removes the second high-k dielectric layer.The method of any of claims 13 to 15, further comprising: forming an interfacial control layer over the surfaces of the stacked fin (104) and the nanowires exposed by the respective gate trenches (166), wherein the interfacial layer is deposited over the interfacial control layer.

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