METHOD FOR FORMING SHAPED EPITACTIC SOURCE / DRAIN LAYERS OF A SEMICONDUCTOR COMPONENT

Abstract

Method for manufacturing a semiconductor component, comprising: Forming an insulating layer (24) over a fin structure (26), wherein a first section (28) of the fin structure (26) is exposed by the insulating layer (24) and a second section of the fin structure (26) is embedded in the insulating layer (24); Formation of a dielectric layer (32) over side walls of the first section (26) of the fin structure (26); Removing the first section (28) of the fin structure (26) and part of the second section of the fin structure (26) in a source / drain area, thereby forming a trench (42), and Forming an epitaxial source / drain structure in the trench (42) using a first process or a second process, wherein the first process comprises an improved epitaxial growth process which has an improved growth rate for a preferred crystallographic facet, and the second process involves using a modified etching process to reduce the width of the epitaxial source / drain structure; wherein the semiconductor component comprises an NMOS and / or a PMOS component; wherein, in the case of an NMOS component, the first process is carried out using a CVD process at a high temperature within a range of about 650 to 700 °C and a pressure within a range of about 27 to 47 kPa and / or the modified etching process comprises a CVD etching process carried out using a mixture of GeH4 and HCl with a mixing ratio of GeH4 to HCl within a range of about 0.5 to 1.2 and at a high temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa or using a mixture of SiH4 and HCl with a mixing ratio of SiH4 to HCl within a range of about 0.2 to 0.25 and at a high temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa; and / or wherein, in the case of a PMOS component, the first process is carried out using a CVD process at a high temperature within a range of 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa and / or the modified etching process comprises a CVD etching process using HCl with a flow rate within a range of approximately 50 to 120 sccm, a temperature within a range of 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa.

Description

TECHNICAL AREA

[0001] This disclosure relates to the fabrication of integrated semiconductor circuits and, in particular, a method for forming shaped epitaxial source / layers for improved component performance. Methods for fabricating semiconductor components are known, for example, from US 2017 / 0 098 698 A1, DE 10 2017 111 540 A1, US 2017 / 0 098 648 A1, US 2016 / 0 315 172 A1, US 2016 / 0 042 963 A1, and US 2015 / 0 099 336 A1. Further methods and devices are known from DE 10 2017 103 419 A1 and US 9 455 331 B1. BACKGROUND

[0002] While the semiconductor industry has evolved into nanometer-scale technology process nodes in the pursuit of higher device density, higher performance, and lower costs, challenges related to both manufacturing and design have led to the development of three-dimensional designs, such as Fin field-effect transistors (FETs). In a FinFET, a gate electrode is located adjacent to two side faces of a channel region with a dielectric gate layer inserted between them.

[0003] In advanced technology nodes, the epi-source or drain structure poses challenges for fin spacing scaling. Source and / or drain layer resistance and specific contact resistance can play a significant role as the device area scales. While a large epitaxial source / drain volume is beneficial for device performance, it can negatively impact yield at higher device densities, such as in static random-access memory (SRAM) chips. Solutions are needed that provide large epitaxial source / drain shapes for SRAM chip components that are compatible with complementary metal-oxide-semiconductor (CMOS) flow without negatively impacting yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present revelation is best understood by reading the following detailed description with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are used solely for illustrative purposes. The dimensions of the various elements may, in fact, be arbitrarily enlarged or reduced for the clarity of the discussion. Fig. Figure 1 is an exemplary process flow diagram illustrating a method for manufacturing a semiconductor component according to one or more embodiments of the present disclosure. Fig. Figure 2A shows a three-dimensional view of a FinFET. Fig. 2B represents a stage in a process for manufacturing a semiconductor component according to one or more embodiments of the present disclosure. Fig. Figure 3 represents a stage in a process for manufacturing a semiconductor component according to one or more embodiments of the present disclosure. Fig. Figure 4 represents a stage in a process for manufacturing a semiconductor component according to one or more embodiments of the present disclosure. Fig. Figure 5 is a diagram illustrating an example of an epitaxial source / drain (SD) layer of a semiconductor device. Fig. Figure 6 is a diagram illustrating an improved epitaxial SD layer of a semiconductor device using a first process according to one or more embodiments of the present disclosure. Fig. Figure 7 is a diagram illustrating an improved epitaxial SD layer of a semiconductor device using a second process according to one or more embodiments of the present disclosure. Fig. Figure 8 is a diagram illustrating various improved epitaxial SD structures of a semiconductor device according to one or more embodiments of the present disclosure. Fig. Figure 9 is a diagram illustrating forms of epitaxial SD structures of a semiconductor device that can be prevented if the manufacturing techniques of the present disclosure are used. Fig. Figure 10 is a diagram illustrating the shapes of epitaxial SD structures of a semiconductor device manufactured using fabrication techniques of the present disclosure. DETAILED DESCRIPTION

[0005] It must be understood that the following disclosure discloses many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and devices are described below to simplify the present disclosure. These are, of course, only examples. For instance, the dimensions of features are not limited to the disclosed range or values ​​but may depend on process conditions and / or desired properties of the component.The formation of a first feature over or on top of a second feature, as described below, can also include embodiments in which the first and second features are in direct contact, and can also include embodiments in which additional features can be inserted between the first and second features, so that the first and second features may not be in direct contact. Various features may be drawn arbitrarily at different scales for the sake of simplicity and clarity.

[0006] Furthermore, spatial reference terms, such as "below," "under," "lower," "above," "above," and the like, may be used here to facilitate description and to describe the relationship of one feature or characteristic to one or more other features or characteristics, as illustrated in the figures. The spatial reference terms may be intended to include different orientations of the component during use or operation, in addition to the orientation shown in the figures. The component may be oriented differently (rotated by 90° or in other orientations), and the spatial reference descriptors used here are interpreted accordingly. Additionally, the term "made of" may mean either "comprise" or "consist of."

[0007] Fig. Figure 1 is an exemplary process flow diagram for the manufacture of a semiconductor component according to one or more embodiments of the present disclosure. Flow diagram 10 illustrates only a relevant part of the overall manufacturing process. It is clear that additional operations before, during, and after the operations described by Figure 10 are required. Fig. 1. The following can be shown, and some of the operations described below can be substituted or omitted for additional embodiments of the method. The sequence of operations / processes can be interchangeable.

[0008] Fig. Figure 2A shows a three-dimensional view of a FinFET with reference to which the cross-sectional views 2B, 3 and 4 are described.

[0009] In S11 of Fig. 1 a structure 55, as shown in an X-section view 20, is constructed along the line CC' of the Fig. 2A, as in Fig. Figure 2B shows a structure formed by the first structure 25, which features a fin structure 26 of a semiconductor device, for example, a fin field-effect transistor (FinFET), which can be an NMOS or a PMOS device. In some embodiments, the NMOS and PMOS devices can be parts of a static random-access memory (SRAM) device, an oscillator such as a ring oscillator, or other circuits of an integrated circuit that can be manufactured with high component density.

[0010] The fin structure 26 can be formed on a substrate 22. The first structure 25 further comprises a first insulating layer 24 that covers the substrate 22 and a portion of the height of the fin structure 26 such that a first section 28 of the fin structure 26 is exposed. In some embodiments, the substrate 22 can be a p-type silicon substrate with an impurity concentration in the range of approximately 1 × 10⁻⁶ 15 cm -3 up to about 3×1015 cm -3 In other embodiments, the base substrate can be an n-type silicon substrate with an impurity concentration in the range of approximately 1 × 10⁻⁶. 15 cm -3 up to about 3×10 15 cm -3 be. The crystal orientation of the silicon substrate is (100) in some embodiments.

[0011] Alternatively, the substrate can comprise another elemental semiconductor, such as germanium, a compound semiconductor including group IV-IV compound semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe), and group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. In one or more embodiments, the substrate is a silicon layer from a silicon-on-insulator (SOI) substrate. Amorphous substrates, such as amorphous silicon or amorphous silicon carbide (SiC), or insulating materials, such as silicon oxide, can also be used as the base substrate.

[0012] The substrate can have various regions that have been suitably doped with impurities (for example, p-type or n-type conductivity). In some embodiments, the fin structure 26 consists of the same material as the substrate 22. For example, in some embodiments, the fin structure 26 can consist of p-type or n-type silicon. In some embodiments, the first insulating layer 24 can be a shallow trench insulation (STI) whose formation method is known.

[0013] In some embodiments, after the formation of the first insulating layer 24, a dummy gate structure is formed over sections of the fin structure 26 extending in the X-direction. The dummy gate structure is not visible in the X-sectional views 20 and 30 because these X-sectional views are located at different X-positions from the position of the dummy gate structure. The dummy gate structure is formed over a channel layer, for example, a portion of a fin structure 26. In some embodiments, the dummy gate structure can correspond to short-channel FETs having a gate length Lg1, or to a long-channel FET having a gate length Lg2, where Lg1 < Lg2 < ~30 nm. In some embodiments, the dummy gate structure comprises a dummy gate electrode layer made of polysilicon and a dielectric dummy gate layer.Sidewall spacers, comprising one or more layers of insulating material, are also formed on the sidewalls of the dummy gate electrode layer. These sidewall spacers have one or more layers of insulating material, such as silicon nitride based on material containing SiN, SiON, SiCN, and SiOCN. The film thickness of the sidewall spacers at their base ranges from approximately 3 nm to approximately 15 nm in some embodiments, and from approximately 4 nm to approximately 8 nm in other embodiments.

[0014] The dummy gate structure further comprises a mask insulating layer used to structure a polysilicon layer within the dummy gate electrode layers. The thickness of the mask insulating layer can range from approximately 10 nm to approximately 30 nm in some embodiments, and from approximately 15 nm to approximately 20 nm in other embodiments.

[0015] In S12 of Fig. 1 a second dielectric layer, as shown in an X-section view 30, is formed along the line CC' of the Fig. 2A, as in Fig. 3 shown. The second dielectric layer 32 is formed over side walls of the first section 28 (in Fig. (2B shown) of the fin structure 26. In some embodiments, the second dielectric layer 32 can be silicon nitride (Si3N4), silicon oxide (SiO2) or silicon oxynitride (SiO2). x N yThe second dielectric layer 32 can be formed in some embodiments using a plasma-enhanced chemical vapor deposition (PECVD) process or a physical vapor deposition (PVD) process, and can be structured and etched using known etching processes such as wet etching, plasma etching or other etching processes.

[0016] In S13 of Fig. 1 a trench 42, as shown in an X-section view 40, is dug along the line CC' of the Fig. 2A, as in Fig. The trench 42 is formed by removing a second section of the fin structure 26. The second section of the fin structure 26 includes the first section 28, and in some embodiments, the trench 42 may extend further into the first fin structure 26. In some embodiments, the removal of the second section of the fin structure 26 may be carried out by a suitable etching process, for example, a dry etching process such as plasma etching. However, other etching processes may be used in other embodiments. The trench 42 is an opening for forming the epitaxial source / drain (SD) structures. The trench 42 is therefore formed in positions on the fin structure 26 (along the X-direction) that correspond to the epitaxial SD structures.

[0017] In S14 of the Fig. 1. The epitaxial SD structure is formed, as shown in an X-section view 60, which is in Fig. Figure 6 shows the following. In the X-section view 60, only a part of the fin structure 26, the epitaxial SD structure, including an upper section 62, which is located in the trench 42 of the Fig. 4 is formed, and the second dielectric layer 32 is shown, and the substrate 22 is skipped. Furthermore, to better understand the improvements realized by the technology in question, the X-section view 50, which is shown in Fig. Figure 5 shows an example of an epitaxial SD structure. This epitaxial SD structure has a diamond-shaped top surface 52 and is formed using an epitaxial growth process. While the large volume of the diamond-shaped top surface 52 is advantageous for providing a low-resistance epitaxial SD structure, it can be problematic and cause unacceptable damage, especially in the case of high-density integrated circuits such as SRAMs and oscillators. The large lateral growth with an (110) orientation, compared to growth with orientations (100) and (111), is the source of the problem with the diamond-shaped top surface 52 of the epitaxial formation.

[0018] In the epitaxial SD structure of the technology in question, as in the X-section view 60, which is shown in Fig. Figure 6 shows the upper section 62 of the diamond-shaped upper surface 52 of the epitaxial SD structure of the Fig. 5 differs in that lateral growth (for example, in the (110) orientation) is suppressed in favor of growth in the (100) orientation. In other words, the epitaxial deposition for the epitaxial SD structure of the technology in question has a higher growth rate for a preferred crystallographic facet, for example, the (100) orientation. The epitaxial deposition is performed with improved (100):(111) and (100):(110) growth rates (for example, within a range of approximately 3 to 5). The growth ratio (100):(111) or (100):(110) represents a ratio of the growth rate of the epitaxial layer in the <100> -direction in relation to the into the <111> - or <110> -Direction.

[0019] The technology presented here can achieve the higher growth rate for the preferred crystallographic facet (for example, (100)) by employing either a first or a second process to form the epitaxial SD structures with the desired shape of the upper section 62. In some embodiments, the upper section 62 with the desired shape has flat side surfaces 64 and 66. The surfaces of the flat side surfaces 64 and 66 may be the same or different in some embodiments. The first process can be a high-temperature epitaxial growth process that guarantees the improved growth rate for the preferred crystallographic facet (for example, (100)), as described in more detail herein. The second process is a modified etching process that, after epitaxial growth under nominal conditions (for example, as in [reference]), Fig. 5 illustrated) in trench 42 of the Fig. 4, as further described below.

[0020] In S15 of the Fig. 1 can be a gate structure above the fin structure 26 of the Fig. 3. This is a further stage in the fabrication of a semiconductor device (for example, an NMOS or PMOS). The gate structure is formed using a process that employs the dummy gate structure discussed above. The process includes a first etching stop layer (ESL) and a first interlayer insulating layer (ILD) formed over the dummy gate structure and the epitaxial SD structure. The first ESL has one or more layers of insulating material, such as silicon nitride-based material, including SiN, SiON, SiCN, and SiOCN. The thickness of the first ESL ranges from approximately 3 nm to approximately 10 nm in some embodiments. The first ILD has one or more layers of insulating material, such as silicon oxide-based material, including silicon dioxide (SiO2) and SiON.

[0021] Following a planarization process on the first ILD layer and the ESL, sections of the dummy gate structure are removed, leaving the gate sidewall spacers in the gate space. A dielectric gate layer is then formed. This dielectric gate layer comprises one or more layers of dielectric material, such as a high-k dielectric material. The high-k dielectric material may include metal oxides. Examples of metal oxides used for high-k dielectric materials include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. In some embodiments, an interface layer, for example, composed of silicon oxide, may be formed over the fin structure (channel region) before the dielectric gate layer is formed.Furthermore, a work function adjustment (WFA) layer is formed in the gate space, and a full-area layer of a suitable conductive material is formed over the gate spaces and the first ILD layer. Finally, the gate electrode layer is formed over the full-area layer. In some embodiments, the gate electrode layer is polysilicon. The structuring of the polysilicon layer is achieved by using a hard mask, which in some embodiments includes a silicon nitride layer and an oxide layer. In other embodiments, the gate electrode layer has a single layer or a multilayer structure. Furthermore, the gate electrode layer can be doped polysilicon with uniform or non-uniform doping.In some alternative embodiments, the gate electrode layer comprises a metal such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, and other conductive materials with a working function compatible with the substrate material, or combinations thereof. The electrode layer for the gate electrode layer can be formed using a suitable process such as atomic layer deposition (ALD), CVD, PVD, plating, or combinations thereof. The width of the gate electrode layer (in the X direction) ranges from approximately 30 nm to approximately 60 nm in some embodiments.

[0022] Returning to Fig. 6. As explained above, the formation of the epitaxial SD structure with a reduced lateral dimension can be continued using a high-temperature deposition technique or a modified etching process. One of the objectives of the high-temperature deposition process is to promote the growth of crystallographic facet (100) and possibly to inhibit the growth of crystallographic facets (110) and (111). The high-temperature deposition process may differ for NMOS and PMOS devices.

[0023] In some embodiments, for NMOS devices, the epitaxial SD layer (for example, as in 60 of the Fig. 6) An epitaxial formation of a semiconductor material, formed using a high-temperature, high-pressure deposition process, such as a chemical vapor deposition (CVD) process, although other deposition methods may be used in other embodiments. The CVD process may be carried out at a high temperature, within a range of about 650 to 700 °C, and at a high pressure, within a range of about 27 to 47 kPa (200 to 350 Torr).

[0024] In other embodiments, when PMOS components are to be formed, the epitaxial SD structure (for example, as in 60 of the Fig. 6) An epitaxial formation of a semiconductor material formed using a high-temperature deposition process, such as a chemical vapor deposition (CVD) process or other deposition methods in other embodiments. The CVD process can be carried out at a high temperature, within a range of approximately 600 to 650 °C, and at a pressure within a range of approximately 0.7 to 7 kPa (5 to 50 Torr).

[0025] In one or more embodiments, exemplary semiconductor materials that can be used for the epitaxial SD structures include Si, SiP, SiC, SiCP, SiGe, Ge, or materials of Group III-V, or any other suitable semiconductor material. In some embodiments, the epitaxial SD layers can be deposited, for example, using ALD, PVD, molecular beam epitaxy (MBE), or other suitable epitaxial deposition techniques. In some embodiments, an optional annealing process, for example, at a temperature within the range of approximately 250 to 350 °C, can be performed to improve the metal-to-source / drain contact resistance.

[0026] The modified etching process can be used after epitaxial deposition under nominal conditions (for example, to form an epitaxial SD structure, as in Fig. 5 shown) in trench 42 of the Fig. 4. For example, the nominal conditions for PMOS device formation may use a mixture of dichlorosilane (SiH₂Cl₂) plus germanium tetrahydride (GeH₄) as a process gas, and at a process temperature within a range of about 600 to 620 °C and a pressure within a range of about 0.7 to 1 kPa (5 to 10 Torr). In some embodiments, the nominal conditions for NMOS device formation may use a mixture of dichlorosilane (SiH₂Cl₂) with phosphine (PH₃) as a dopant, and at a process temperature within a range of 650 to 670 °C and a pressure within a range of 27 to 33 kPa (200 to 250 Torr).

[0027] In the modified etching process, as in Fig. As shown in Figure 7, lateral sections 72 and 73 of the diamond-shaped top surface 56 are removed to form a top section 76 with flat side surfaces 74 and 76. This can improve component performance because the laterally narrower diamond-shaped top surface 56 significantly reduces the chance of unwanted contacts and thus suppresses leakage between two adjacent epitaxial SD structures. In some embodiments, the modified etching process can be a CVD etching process, although any other etching process can be used in other embodiments.

[0028] In some embodiments, for NMOS component formation, the modified etching process can be an anisotropic etching process performed using a mixture of germanium tetrahydride (GeH4) and hydrochloric acid (HCl) with a GeH4 to HCl ratio within a range of approximately 0.5 to 1.2. The CVD etching process can be carried out at a high temperature within a range of approximately 650 to 750 °C and a pressure within a range of approximately 0.7 to 13 kPa (5 to 100 Torr). In other embodiments, different etching processes using varying process conditions can be employed. In the CVD etching process, a film deposition process and an etching process occur simultaneously, and by adjusting the process conditions, it is possible to control the configurations (dimensions, shape, etc.) of the formed structure.

[0029] In other embodiments, for NMOS device formation, the etching process can be carried out using a mixture of silicon tetrahydride (silane, SiH4) and hydrochloric acid (HCl) with a SiH4 to HCl ratio within a range of approximately 0.2 to 0.25. This CVD etching process can be performed at a high temperature within a range of approximately 650 to 750 °C and a pressure within a range of approximately 0.7 to 13 kPa (5 to 100 Torr). Other etching processes using different process conditions can be employed in other embodiments.

[0030] In some embodiments, when forming a PMOS component, the modified etching process can be a CVD etching process using HCl at a flow rate within a range of approximately 50 to 120 sccm. The CVD etching process can be performed at a high temperature within a range of approximately 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa (5 to 50 Torr). In other embodiments, other etching processes using different process conditions can be employed.

[0031] Fig. Figure 8 is a diagram illustrating various improved epitaxial SD structures 80 (82, 84, 86 and 88) of a semiconductor device according to one or more embodiments of the present disclosure. The improved epitaxial SD structures 82, 84, 86 and 88 can be produced using one of the high-temperature deposition processes or the modified etching processes described above with reference to the Fig. 6 and Fig. 7 are described. As described above, one of the tasks of the high-temperature deposition process is to promote the growth of the crystallographic (100) facets and possibly to prevent the growth of the crystallographic (110) and (111) facets. The modified etching process of the present disclosure produces the epitaxial SD structures with a laterally smaller top surface section, for example, by using a CVD etching process after forming the epitaxial SD structure under nominal conditions. The resulting epitaxial SD structures of both processes (for example, high-temperature deposition and modified etching) are similar to the epitaxial SD structures 82, 84, 86, and 88, which have flat side surfaces with different dimensions such as “a” and “b”, as described in Fig. Figure 8 shows the dimensions of the epitaxial SD structures. Dimension “a” represents the height of a flat side of the epitaxial SD structures, and dimension “b” represents the height of the upper triangular shape of the epitaxial SD structures. In some embodiments, the epitaxial SD structures (for example, 82, 84, 86, and 88) can have different dimensions “a”, “b”, and “w”, where “w” is the width of the epitaxial SD structure along a direction in which the gate extends. For example, the values ​​of “a” in some embodiments can be within a range of about 5 to 60 nm, the values ​​of “b” can be within a range of about 5 to 10 nm, and the values ​​of “w” can be within a range of about 5 to 30 nm.The ratio of the height “d” of the epitaxial SD structure to the height “c” of the second dielectric layer 32, also known as the fin-side wall (FSW), can, in some embodiments, be within a range of approximately 5.6 to 6.2. The FSW 32 can have different heights for different sides of each epitaxial SD structure (for example, 86) in some embodiments. In other embodiments, the FSW does not exist (for example, it is removed, as in 88). In some embodiments, the value of the d / w ratio can be within a range of approximately 6 to 10, and the value of the a / w ratio can be within a range of 4 to 7.

[0032] Fig. Figure 9 is a diagram illustrating various shapes 90 of epitaxial SD structures of a semiconductor device fabricated using the fabrication techniques of the present disclosure. Shapes 92, 94, and 96 show irregularities in the device structures due to large lateral extension of the upper portions of the epitaxial SD structures 91, 93, 95, 97, and / or 99. As can be seen from the figure, shape 92 shows a short circuit between two adjacent n-type structures. Shape 94 exhibits an irregular n-type structure, and shape 96 shows a short circuit between two adjacent n- and p-type structures. These and similar irregularities, which can result in leakage and potentially malfunctioning devices, can be prevented by forming the epitaxial SD structures using one of the high-temperature processes or the modified etching processes of the technology described above.

[0033] In some embodiments of the present disclosure, the above-mentioned etching process is carried out after the improved epitaxial growth process to obtain a preferred form of the epitaxial SD layer.

[0034] Fig. Figure 10 is a diagram depicting shapes of 100 undamaged epitaxial SD structures of a semiconductor device fabricated using the fabrication techniques of the present disclosure. Shapes 102, 104, 106, and 108 depict n-type and p-type device structures that show no signs of damage due to excessive lateral extension of the upper portions of the epitaxial SD structures 101, 103, 105, and 107. As can be seen from the figure, shapes 102 and 108 show n-type structures with restricted lateral growth as a result of using one of the high-temperature processes or the modified etching processes of the present disclosure. The two adjacent p-type structures are formed with normal lateral growth. The restricted lateral growth of the n-type structure appears to be slightly different for the two n-type device structures.Some difference in lateral growth can be expected if the side wall spacers (for example, 32 of the . Fig. 3) for the two structures being quite similar. It must be understood that an asymmetry in the sidewall spacers can result in the prevention of unilateral epitaxial growth. It is clear that not all advantages have necessarily been discussed here; no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.

[0035] The process concepts described above can be integrated into the present MOSFET manufacturing process and implemented in a number of different technology nodes.

[0036] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Method for manufacturing a semiconductor device, comprising: Forming an insulating layer (24) over a fin structure (26), wherein a first section (28) of the fin structure (26) is exposed by the insulating layer (24) and a second section of the fin structure (26) is embedded in the insulating layer (24); Formation of a dielectric layer (32) over side walls of the first section (26) of the fin structure (26); Removing the first section (28) of the fin structure (26) and part of the second section of the fin structure (26) in a source / drain area, thereby forming a trench (42), and Forming an epitaxial source / drain structure in the trench (42) using a first process or a second process, wherein the first process comprises an improved epitaxial growth process which has an improved growth rate for a preferred crystallographic facet, and the second process involves using a modified etching process to reduce the width of the epitaxial source / drain structure; wherein the semiconductor component comprises an NMOS and / or a PMOS component; wherein, in the case of an NMOS component, the first process is carried out using a CVD process at a high temperature within a range of about 650 to 700 °C and a pressure within a range of about 27 to 47 kPa and / or the modified etching process comprises a CVD etching process carried out using a mixture of GeH4 and HCl with a mixing ratio of GeH4 to HCl within a range of about 0.5 to 1.2 and at a high temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa or using a mixture of SiH4 and HCl with a mixing ratio of SiH4 to HCl within a range of about 0.2 to 0.25 and at a high temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa; and / or wherein, in the case of a PMOS component, the first process is carried out using a CVD process at a high temperature within a range of 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa and / or the modified etching process comprises a CVD etching process using HCl with a flow rate within a range of approximately 50 to 120 sccm, a temperature within a range of 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa. [2] Method according to claim 1, wherein the preferred crystallographic facet comprises a (100) facet and wherein the improved growth rate comprises a ratio of a growth rate of an epitaxial layer in the (100) direction with respect to the (111) or (110) direction within a range of about 3 to 5. [3] Method according to any of the preceding claims, wherein the insulating layer (24) comprises an STI material and wherein the dielectric layer (32) is Si3N4, SiO2 or SiO x N y comprising and wherein the dielectric layer (32) is asymmetric over two side walls of the first section (28) of the fin structure (26) and results in an asymmetry of the epitaxial source / drain structure formed by the enhanced epitaxial growth process. [4] Method for manufacturing a semiconductor device, comprising: Forming a first structure (25) extending in a first direction, wherein the first structure (25) has a fin (26) made of a first material and has a first section (28) that is exposed and a second section that is embedded; Forming a dielectric (32) layer over side walls of the first section (28) of the fin (26); Removing the first material from the first section (28) and part of the second section of the fin (26) in a source / drain area, thereby forming a trench (42); Forming an epitaxial source / drain structure in and above the trench (42), and Performing a modified etching process to partially remove sections of an upper part of the epitaxial structure that have grown in a second direction perpendicular to the first direction, thereby creating flat sides on the upper part of the epitaxial structure. wherein the semiconductor device comprises an NMOS device and the modified etching process comprises a CVD etching process using a mixture of GeH4 and HCl with a mixing ratio of GeH4 to HCl within a range of approximately 0.5 to 1.2 or a mixture of SiH4 and HCl with a mixing ratio of SiH4 to HCl within a range of approximately 0.2 to 0.25, or wherein the semiconductor device comprises a PMOS device and the modified etching process comprises a CVD etching process using HCl with a flow rate within a range of approximately 50 to 120 sccm. [5] Method according to claim 4, wherein the first structure (25) has an insulating layer (24) deposited on the second section of the fin (26), and wherein the first material comprises a substrate material. [6] Method according to claim 4 or 5, wherein, in the case that the semiconductor component comprises an NMOS component, the CVD etching process is carried out at a temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa. [7] Method according to claim 4, wherein in the case that the semiconductor component comprises a PMOS component, the CVD etching process is carried out at a temperature within a range of about 600 to 650 °C and a pressure within a range of about 0.7 to 7 kPa. [8] Semiconductor component, comprising: a fin field-effect transistor component that features the following: a fin structure (26) projecting from a substrate layer in a first direction and extending in a second direction perpendicular to the first direction; an epitaxial source / drain structure deposited on fin structure (26), and a gate stack comprising a gate electrode layer and a dielectric gate layer covering a section of the fin structure (26) and extending in the second direction, wherein the epitaxial source / drain structure has a diamond-shaped top surface and flat side surfaces (64, 66, 74, 76) parallel to the first direction, wherein a ratio of the height of one of the flat side surfaces (64, 66, 74, 76) of the epitaxial source / drain structure to the width of the epitaxial source / drain structure is in a range of about 4 to 7, and wherein a height of an upper triangular shape of the epitaxial source / drain structure is between 5 nm and 10 nm.

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