Structuring method for a semiconductor component and resulting structures

Abstract

A process which features the following: Defining a first mandrel (124) and a second mandrel (124) over a hard mask layer (108); Deposition of a spacer layer (126) over and along the side walls of the first mandrel (124) and the second mandrel (124); Forming a sacrificial material (138) above the spacer layer (126) between the first spike (124) and the second spike (124), wherein the sacrificial material (138) comprises an inorganic oxide; Removing first horizontal sections of the spacer layer (126) to expose the first mandrel (124) and the second mandrel (124), with remaining sections of the spacer layer (126) providing spacers (127) on side walls of the first mandrel (124) and the second mandrel (124); Removal of the first spike (124) and the second spike (124); and Structuring the hard mask layer (108) using the spacers (127) and the sacrificial material (138) as an etching mask, wherein the formation of the sacrificial material (138) has the following features: Forming a structured mask (134, 128) over the spacer layer (126), wherein the structured mask (134, 128) has an opening that exposes a section of the spacer layer (126) between the first mandrel (124) and the second mandrel (124); Separation of the sacrificial material (138) in the opening; and Removing the structured mask (134, 128), wherein the removal of the structured mask (134, 128) is carried out after the deposition of the sacrificial material (138).

Description

STATE OF THE ART

[0001] With the increasing miniaturization of semiconductor devices, various processing techniques (e.g., photolithography) are adapted to allow the fabrication of devices with increasingly smaller dimensions. For example, with increasing gate density, the fabrication processes of various features within the devices (e.g., overlapping interconnect features) are adapted to be compatible with the miniaturization of device features as a whole. However, as semiconductor processes have increasingly smaller process windows, the fabrication of these devices has reached and even exceeded the theoretical limits of photolithography equipment. As semiconductor devices become ever smaller, the desired spacing between elements (i.e., the distance) of a device is smaller than the spacing that can be achieved using traditional optical masks and photolithography equipment.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2014 / 0024209A1, US 2010 / 0009470A1, US 2015 / 0040077A1, US 2014 / 0087563A1, US 6348414B1 and US 2017 / 0092496A1.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity of discussion. Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A and Fig. Figure 17B illustrates cross-sectional views of various intermediate stages in the manufacture of a semiconductor device in accordance with some embodiments. Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A and Fig. Figure 20B illustrates cross-sectional views of various intermediate stages in the manufacture of a semiconductor device in accordance with some other embodiments. Fig. 21A, Fig. 21B, Fig. 22A, Fig. 22B, Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A, Fig. 27B, Fig. 28A, Fig. 28B, Fig. 29A, Fig. 29B and Fig. Figure 30 illustrates cross-sectional views of various intermediate stages in the manufacture of a semiconductor device in accordance with some other embodiments. DETAILED DESCRIPTION

[0005] Several embodiments are described with respect to a specific structuring process, namely a SADP (Self-Aligned Double Patterning) process, in which mandrels are structured, spacers are formed along the sidewalls of the mandrels, and the mandrels are removed, leaving the spacers behind to define a pattern at half the distance between the mandrels. However, various embodiments can also be directed towards other structuring processes, such as SAQP (Self-Aligned Quadruple Patterning) and the like.

[0006] A semiconductor device and a method are provided in accordance with some embodiments. In particular, a self-aligning double structuring (SADP) process is performed for structuring conduits in a semiconductor device. The structured conduits have a spacing that is at least half of a minimum spacing achievable using photolithographic processes. The structured conduits are defined between adjacent sidewalls of spacers, and a structured sacrificial material (occasionally referred to as a reversal material) is formed in the structured conduits.The sacrificial material can comprise an inorganic material formed by structuring openings in a mask (where the openings expose selected areas of the structured conduits) and depositing the inorganic material in the openings using a suitable layer deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like. Once the sacrificial material has been formed, the spacers and the sacrificial material are used to structure an underlying mask layer, which in turn is used to structure a target layer. The underlying target layer can be a layer used for a variety of purposes.For example, the target layer can be a low-dielectric-number layer in which openings are structured using the mask layer. Subsequently, conductive material can be filled into the openings of the low-dielectric-number layer to define interconnects. The interconnects can have a finer spacing than would be achievable using photolithographic processes alone. Compared to organic sacrificial materials formed using a spin-deposition process, the deposition processes of inorganic materials in this embodiment result in improved sacrificial material definition with fewer defects (e.g., less bubble formation). Thus, finely spaced semiconductor structures with improved yield can be fabricated.

[0007] Fig. Figures 1 to 17B illustrate cross-sectional views of intermediate stages in the formation of features in a target layer 102 on a semiconductor device 100 in accordance with some exemplary embodiments. The target layer 102 is a layer in which several patterns are to be formed in accordance with embodiments of the present disclosure. In some embodiments, the semiconductor device 100 is processed as part of a larger wafer. In such embodiments, after various features of the semiconductor device 100 have been formed (e.g., active components, interconnect structures, and the like), a singulation process can be applied to scribe conductor regions of the wafer in order to separate individual semiconductor chips from the wafer (also referred to as singulation).

[0008] In some embodiments, the target layer 102 is an inter-metal dielectric (IMD) layer. In such embodiments, the target layer 102 comprises a material with a low dielectric constant, for example, a dielectric constant (k-value) of less than 3.8, less than about 3.0, or less than about 2.5. In alternative embodiments, the target layer 102 is an IMD layer comprising a material with a high dielectric constant, having a k-value greater than 3.8. Openings can be structured in the target layer 102 using the processes of the embodiment, and conductive traces and / or vias can be formed in the openings as described below.

[0009] In some embodiments, the target layer 102 is a semiconductor substrate. The semiconductor substrate can be formed from a semiconductor material such as silicon, silicon germanium, or the like. In some embodiments, the semiconductor substrate is a crystalline semiconductor substrate, such as a crystalline silicon substrate, a crystalline silicon carbon substrate, a crystalline silicon germanium substrate, a III-V compound semiconductor substrate, or the like. The semiconductor substrate can be structured by a process of the embodiment, and subsequent process steps can be used to form shallow trench isolation (STI) regions in the substrate. Semiconductor ribs can protrude between the formed STI regions.Source / drain regions can be formed in the semiconductor fins, and gate dielectric and electrode layers can be formed via channel regions of the fins, thereby forming semiconductor devices such as fin field effect transistors (finFETs).

[0010] In some embodiments, the target layer 102 is a conductive layer, such as a metal layer or a polysilicon layer, which is extensively deposited. Structuring processes of the embodiment can be applied to the target layer 102 to structure semiconductor gates and / or dummy gates of finFETs. By using processes of the embodiment to structure a conductive target layer 102, the gap between adjacent gates can be reduced and the gate density can be increased.

[0011] In Fig. 1 is a layer stack, including the target layer 102, formed in the semiconductor device 100. In some embodiments, the target layer 102 may be formed on top of a semiconductor substrate 104. The semiconductor substrate 104 may be formed from a semiconductor material, such as silicon, doped or undoped, or may be an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 104 may also include other semiconductor materials, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Components (not illustrated), such asTransistors, diodes, capacitors, resistors, etc., can be formed in and / or on an active surface of the semiconductor substrate 104. In other embodiments, where the target layer 102 is a semiconductor substrate used to form finFETs, the semiconductor substrate 104 can be omitted.

[0012] Although Fig. Figure 1 illustrates the target layer 102 as being in physical contact with the semiconductor substrate 104. Any number of interlayers can be arranged between the target layer 102 and the semiconductor substrate 104. Such interlayers can include an interlayer dielectric (ILD) layer comprising a dielectric with a low dielectric constant and having contact terminals formed therein, other interlayer media (IMD) layers with conductive traces and / or vias formed therein, one or more interlayers (e.g., etch stop layers, adhesion layers, etc.), combinations thereof, and the like. For example, an optional etch stop layer (not illustrated) can be arranged directly beneath the target layer 102. The etch stop layer can serve as a stop for an etching process subsequently performed on the target layer 102.The material and process used to form the etch stop layer can depend on the material of the target layer 102. In some embodiments, the etch stop layer can be made of silicon nitride, SiON, SiCON, SiC, SiOC, or SiC. x N y , SiO x , other dielectrics, combinations thereof or the like, and it can be formed by plasma-enhanced chemical vapor deposition (PECVD - Plasma Enhanced Chemical Vapor Deposition), low-pressure CVD (LPCVD - Low Pressure CVD), plasma vapor deposition (PVD - Plasma Vapor Deposition) or the like.

[0013] The layer stack further includes an anti-reflective coating (ARC) 106, which is formed over the target layer 102. The ARC 106 assists in the exposure and focusing of overlying photoresist layers (discussed below) during the structuring of the photoresist layers. In some embodiments, the ARC 106 may be formed from SiON₄, silicon carbide, materials doped with oxygen (O) and nitrogen (N), or the like. In some embodiments, the ARC 106 is essentially nitrogen-free and may be formed from an oxide. In such embodiments, the ARC 106 may also be referred to as a nitrogen-free ARC (NFARC). The ARC 106 may be formed by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma deposition (HDP), or the like.

[0014] The layer stack further includes a hard mask layer 108 formed over the ARC 106 and the target layer 102. The hard mask layer 108 can be formed from a material comprising a metal (e.g., titanium nitride, titanium, tantalum nitride, tantalum, a metal-doped carbide (e.g., tungsten carbide), or the like) and / or a metalloid (e.g., silicon nitride, boron nitride, silicon carbide, or the like), and it can be formed by PVD, radio frequency PVD (RFPVD), atomic layer deposition (ALD), or the like. In subsequent processing steps, a pattern is formed on the hard mask layer 108 using a structuring process of the embodiment. The hard mask layer 108 is then used as an etching mask for etching the target layer 102, whereby the pattern of the hard mask layer 108 is transferred to the target layer 102.

[0015] The layer stack further includes a dielectric layer 110 formed above the hard mask layer 108. The dielectric layer 110 can be formed from a silicon oxide, such as boron phosphosilicate tetraethyl orthosilicate (BPTEOS) or undoped tetraethyl orthosilicate (TEOS) oxide, and it can be formed by CVD, ALD, spin coating, or the like. In some embodiments, the dielectric layer 110 serves as an etch stop layer for the structuring of subsequently formed mandrels and / or spacers (e.g., the mandrels 124, see Figure 1). Fig. 4, and the spacers 127, see Fig. 13A). In some embodiments, the dielectric layer 110 also serves as an anti-reflective coating.

[0016] The layer stack further includes a mandrel layer 112, which is formed above the first dielectric hard mask layer 108. The first mandrel layer 112 can be made of a semiconductor, such as amorphous silicon, polysilicon, silicon nitride, silicon oxide, or another material that exhibits high etch selectivity with respect to the underlying layer, e.g., the dielectric layer 110.

[0017] A three-layer photoresist 120 is formed on the layer stack above the mandrel layer 112. The three-layer photoresist 120 comprises a bottom layer 114, a middle layer 116 above the bottom layer 114, and a top layer 118 above the middle layer 116. The bottom layer 114 and the top layer 118 can be composed of photoresists (e.g., light-sensitive materials), which include organic materials. In some embodiments, the bottom layer 114 can also be a bottom anti-reflective coating (BARC). The middle layer 116 can comprise an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The middle layer 116 exhibits high etch selectivity with respect to the upper layer 118 and the lower layer 114.The various layers of the three-layer photoresist 120 can be sequentially deposited, for example, using spin deposition processes. Although a three-layer photoresist 120 is discussed here, in other embodiments the photoresist 120 can also be a single-layer or a double-layer photoresist (e.g., comprising only the lower layer 114 and the upper layer 118 without the middle layer 116). The type of photoresist used (e.g., single-layer, double-layer, or three-layer) can depend on the photolithography process used to structure the mandrel layer 112. For example, a single-layer or double-layer photoresist 120 can be used in modern extreme ultraviolet (EUV) lithography processes.

[0018] In some embodiments, the upper layer 118 is structured using a photolithographic process. Subsequently, the upper layer 118 is used as an etching mask for structuring the middle layer 116 (see Fig. 2) The middle layer 116 is then used as an etching mask for structuring the lower layer 114, and the lower layer 114 is then used to structure the mandrel layer 112 (see Fig. 3 and Fig. 4) It has been observed that by using a three-layer photoresist (e.g., the three-layer photoresist 120) to etch a target layer (e.g., the mandrel layer 112), improved definition can be achieved for finely spaced patterns in the target layer (e.g., the mandrel layer 112).

[0019] The top layer 118 is patterned using any suitable photolithography process to form the openings 122 therein. As an example of patterning the openings 122 in the top layer 118, a photomask (not shown) can be placed over the top layer 118. The top layer 118 can then be exposed to a radiation beam, including an ultraviolet (UV) or excimer laser, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, or the like, while the photomask masks areas of the top layer 118. Exposure of the top photoresist layer can be achieved using an immersion lithography system to increase the resolution and reduce the minimum achievable distance.A hardening or curing operation can be performed to harden the top layer 118, and a developer can be used to remove either the exposed or non-exposed portions of the top layer 118, depending on whether a positive or negative stop varnish is used. The openings 122 may have stripe shapes in a top view (not illustrated). The spacing P1 of the openings 122 may be the minimum spacing achievable using photolithographic processes alone. For example, the spacing P1 of the openings 122 is about 80 nm in some embodiments. Other spacings P1 of the openings 122 are also being considered.

[0020] After structuring the upper layer 118, the pattern of the upper layer 118 is transferred to the middle layer 116 in an etching process. The etching process is anisotropic, so that the openings 122 in the upper layer 118 also extend through the middle layer 116 and have approximately the same size in the middle layer 116 as in the upper layer 118. The resulting structure is in Fig. 2 illustrated.

[0021] Optionally, a trimming process (not illustrated) can be performed to increase the size of the openings 122 in the middle layer 116. In one embodiment, the trimming process is an anisotropic plasma etching process using process gases, including O2, CO2, N2 / H2, H2, or the like, or a combination thereof, or any other gases suitable for trimming the middle layer 116. The trimming can increase the width W1 of the openings 122 and decrease the width W2 of the sections of the middle layer 116 between the openings 122. The trimming process can be performed to achieve a desired width W1 to width W2 ratio, so that subsequently defined conduits are uniformly spaced. In other embodiments, the middle layer 116 is initially structured to have a desired width W1 to width W2 ratio, and the trimming process can be omitted.

[0022] In Fig. 3. An etching process is carried out to transfer the pattern of the middle layer 116 to the lower layer 114, causing the openings 122 to extend through the lower layer 114 as well. The etching process of the lower layer 114 is anisotropic, so the openings 122 in the middle layer 116 also extend through the lower layer 114 and are approximately the same size in the middle layer 116 as in the lower layer 114. The upper layer 118 can be consumed as part of the etching of the lower layer 114 (see Fig. 1 and Fig. 2).

[0023] In Fig. 4 will be the pattern of the lower layer 114 (see Fig. 3) transferred to the thorn layer 112 using an etching process. The etching process of the thorn layer 112 is anisotropic, so that the openings 122 in the lower layer 114 also extend through the thorn layer 112 and have approximately the same size in the thorn layer 112 as in the lower layer 114. Thus, the thorns 124 are defined from remaining sections of the thorn layer 112 (e.g., sections of the thorn layer 112 between the openings 122). The thorns 124 have a spacing P1 (see also Fig. 1) In some embodiments, the distance P1 is a minimum distance achievable using photolithographic processes. During the etching of the mandrel layer 112, the middle layer 116 is consumed and the lower layer 114 may be at least partially consumed. In embodiments in which the lower layer 114 is not completely consumed during the etching of the mandrel layer 112, an ashing process can be carried out to remove any remaining residue of the lower layer 114.

[0024] In Fig. 5. A spacer layer 126 is formed over and along the side walls of the mandrels 124. The spacer layer 126 can also extend along the upper surfaces of the dielectric layer 110 in the openings 122. The material of the spacer layer 126 is selected to exhibit high etch selectivity with respect to the dielectric layer 110 and the mandrels 124. For example, the spacer layer 126 can comprise AlO, AlN, AlON, TaN, TiN, TiO, Si, SiO, SiN, metals, metal alloys, and the like, and it can be deposited using any suitable process, such as ALD, CVD, or the like. In some embodiments, the deposition process of the spacer layer 126 is uniform, so that the thickness of the spacer layer 126 on the side walls of the mandrels 124 is essentially equal (e.g. within manufacturing tolerances) to the thickness of the spacer layer 126 on the upper surface of the mandrels 124 and the bottom surfaces of the openings 122.In various embodiments, areas of the openings 122 between side walls of the spacer layer 126 define conduction patterns. The conduction patterns can correspond to desired positions of structured features (e.g., the conductive lines 142 / 144) that are subsequently formed in the target layer 102 (see, e.g., Figure 1). Fig. 17A and Fig. 17B).

[0025] In Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A and Fig. 13B is structured sacrificial material (e.g., sacrificial material 138, see Fig. 11A and Fig. 11B) over selected sections of the spacer layer 126. In particular, the structured sacrificial material is deposited in selected areas of the conduit pattern (areas of the openings 122 between sidewalls of the spacer layer 126, see Fig. 5) The structured sacrificial material can be used to further define a desired pattern for etching the target layer 102. For example, the structured sacrificial material can be deposited to define areas where no structured features (e.g., conductive lines) are formed (e.g., cut) in the target layer 102 (see, e.g., Fig. 17A and Fig. 17B). In Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A and Fig. Figures ending with the designation "A" in 13B consistently illustrate the same cross-sectional view as Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5, while figures ending with the designation “B” consistently show a cross-sectional view along line BB of a corresponding Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A and Fig. 13A illustrates. For example, illustrates Fig. 6B a cross-sectional view along line BB of Fig. 6A; Fig. Figure 7B illustrates a cross-sectional view along line BB of Fig. 7A; and so on.

[0026] Firstly, referring to Fig. 6A and Fig. 6B, a three-layer photoresist 134 is formed over the spacer layer 126. The three-layer photoresist 134 can be deposited between the spikes 124, such as between the sidewalls of the spacer layer 126 in the conductor patterns. The three-layer photoresist 134 comprises a bottom layer 128, a middle layer 130 over the bottom layer 128, and an top layer 132 over the middle layer 130. The bottom layer 128 and the top layer 132 can be formed from photoresists (e.g., light-sensitive materials), which include organic materials. In some embodiments, the bottom layer 128 can also be a BARC layer. The middle layer 130 can comprise an inorganic material, which may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide) or the like.The middle layer 130 exhibits high etch selectivity with respect to the upper layer 132 and the lower layer 128. The various layers of the three-layer photoresist 134 can be sequentially deposited in a comprehensive manner, for example using a spin-depositing process.

[0027] In some embodiments, the upper layer 132 is structured using a photolithographic process and is subsequently used as an etching mask for structuring the middle layer 130 (see Fig. 7A and Fig. 7B). The middle layer 130 is then used as an etching mask for structuring the lower layer 128 (see Fig. 7A and Fig. 7B). The top layer 132 is patterned using any suitable photolithography process to form the openings 136 therein. As an example of patterning the openings 136 in the top layer 132, a photomask (not shown) can be placed over the top layer 132. The top layer 132 can then be exposed to a radiation beam, including an ultraviolet (UV) or excimer laser, such as a 248 nm beam from a KrF excimer laser, a 193 nm beam from an ArF excimer laser, or a 157 nm beam from an F2 excimer laser, or the like, while the photomask masks areas of the top layer 132. The exposure of the top photoresist layer can be performed using an immersion lithography system to increase the resolution and reduce the minimum achievable distance.A curing or hardening operation can be performed to harden the top layer 132, and a developer can be used to remove either the exposed or non-exposed portions of the top layer 132, depending on whether a positive or negative stop resist is used. The pattern of openings 136 can correspond to a desired pattern of a subsequently formed sacrificial material. For example, the three-layer photoresist 134 can be used to define a shape of the subsequently formed sacrificial material (e.g., the sacrificial material 138, see ). Fig. 9A and Fig. 9B).

[0028] After structuring the upper layer 132, the pattern of the upper layer 132 is transferred to the middle layer 130 in an etching process. The etching process is anisotropic, so that the openings 136 in the upper layer 132 also extend through the middle layer 130 and have approximately the same size in the middle layer 130 as in the upper layer 132. The resulting structure is in Fig. 7A and Fig. 7B illustrates this.

[0029] In Fig. 7A and Fig. 7B, after the structuring of the middle layer 130, an etching process is carried out to transfer the pattern of the middle layer 130 to the lower layer 128, whereby the openings 136 then also extend through the lower layer 128. As part of the etching of the lower layer 128, the upper layer 132 (see Fig. 6A and Fig. 6B) are consumed.

[0030] In Fig. 8A and Fig. 8B is a sacrificial material 138 (occasionally also referred to as a reversal material) deposited above the lower layer 128 and into the openings 136. In some embodiments, the sacrificial material 138 is also deposited above the middle layer 130. In other embodiments (not illustrated), the middle layer 130 is removed before the sacrificial material 138 is deposited. The removal of the middle layer 130 may involve a suitable dry etching process or a combination of dry and wet etching processes. In such embodiments, the sacrificial material 138 may be formed directly on (e.g., in direct contact with) an uppermost surface of the lower layer 128.

[0031] In various embodiments, the sacrificial material 138 comprises an inorganic material. For example, the sacrificial material 138 can be an inorganic oxide, such as titanium oxide, tantalum oxide, silicon oxide, and the like. In some embodiments, the inorganic material is a low-temperature oxide (LTO). As used herein, the term "LTO" refers to an oxide deposited using a relatively low process temperature (e.g., 200°C or less). It has been observed that in such embodiments, the low-temperature deposition process does not cause significant damage to the lower layer 128. The sacrificial material 138 can be selected to exhibit sufficient etch selectivity with respect to the spacer layer 126 under the same etching process.For example, in some embodiments, the ratio of the etch rate of the sacrificial material 138 to the etch rate of the spacer layer 126 with respect to an identical etching process is at least 0.7. It has been observed that if the ratio of the etch rate of the sacrificial material 138 to the etch rate of the spacer layer 126 with respect to an identical etching process is within the above range, increased reliability in the structuring process can be achieved.

[0032] The sacrificial material 138 can be formed using a semiconductor deposition process, such as CVD, PVD, ALD, or the like. The semiconductor deposition process can be a uniform process that occurs on the sidewalls and a bottom surface of the openings 136. With continued deposition, sections of the sacrificial material 138 can fuse on opposite sidewalls of the openings 136, thereby filling the openings 136. Due to the semiconductor deposition process, the upper surface of the sacrificial material 138 may not be flat. For example, the recesses 138a in the upper surface of the sacrificial material 138 may be located in and / or above the openings 136.

[0033] Compared to spin-deposition processes, semiconductor layer deposition processes allow the sacrificial material 138 to be filled into the openings 136 with improved gap filling and fewer defects (e.g., less bubble formation in the sacrificial material 138). In embodiments where the middle layer 130 is removed before the deposition of the sacrificial material 138, the reduction in defects can be particularly pronounced. Without being bound to a specific theory, this further reduction in defects may result from the fact that the lower layer 128 provides a better surface area (e.g., with fewer nodes) for the deposition of the sacrificial material 138 compared to the middle layer 130.

[0034] Next, in Fig. 9A and Fig. 9B a planarization process (e.g., chemical mechanical polishing (CMP), dry etching, combinations thereof, or the like) for removing excess portions of the sacrificial material 138 outside the openings 136. In embodiments in which the sacrificial material 138 is formed above the middle layer 130, the planarization process may also remove the middle layer 130. After the planarization process, the lower layer 128 is exposed, and the upper surfaces of the sacrificial material 138 and the lower layer 128 may be coplanar. In some embodiments, the planarization process may also remove the recesses 138a (see Fig. 8A and Fig. 8B), which were formed in the sacrificial material 138, remove.

[0035] In Fig. 10A and Fig. In 10B, the lower layer 128 is removed using an ashing process. After the lower layer 128 has been removed, columns of sacrificial material 138 remain. The remaining sacrificial material 138 masks selected areas of the spacer layer 126. In some embodiments, the sacrificial material 138 can extend from a first sidewall section of the spacer layer 126 on a first mandrel 124 to a second sidewall section of the spacer layer 126 on a second mandrel 124.

[0036] In Fig. 11A and Fig. In 11B, the sacrificial material 138 is trimmed to obtain a desired profile. In some embodiments, trimming the sacrificial material 138 recesses the sacrificial material 138 below a top surface of the spacer layer 126, such as below a top surface of the mandrels 124. Trimming the sacrificial material 138 may expose sections of the spacer layer 126 above the mandrels 124 (see Fig. 11A). In some embodiments, trimming the sacrificial material 138 further reduces a width of the sacrificial material 138 at least in cross-section BB (see Fig. 11B).

[0037] Trimming the sacrificial material 138 can involve a dry etching process or a combination of dry and wet etching processes. Dry etching processes of the embodiment for trimming the sacrificial material 138 can include the use of fluorocarbon-based etchants (e.g., CF4). Other process gases, such as oxygen (O2), nitrogen (N2), argon (Ar), combinations thereof, or the like, can be used in combination with the fluorocarbon-based etchants. Wet etching processes of the embodiment for trimming the sacrificial material 138 can include the use of dilute hydrofluoric acid as an etchant. A desired shape of the sacrificial material 138 can be achieved, for example, by controlling the duration of the etching-trimming process.

[0038] Subsequently, an etching process is carried out to remove exposed horizontal sections of the spacer layer 126 to expose the mandrels 124. The vertical sections of the spacer layer 126 remain after etching and are referred to below as the spacers 127. Furthermore, masked sections of the spacer layer 126 (e.g., areas masked by the sacrificial material 138) may also remain after etching. In some embodiments, the etching of the spacer layer 126 is a dry etching process using a suitable etchant, such as CH4, Cl2, combinations thereof, and the like. Other process gases, e.g., nitrogen (N2), may be used in combination with the etchant during the dry etching process.The dry etching process can be anisotropic and etch away exposed, lateral sections of the spacer layer 126 without significantly removing vertical sections of the spacer layer 126 (the spacers 127) or the sacrificial material 138. The resulting structure is shown in . Fig. 12A and Fig. 12B illustrates.

[0039] In Fig. 13A and Fig. In section 13B, the mandrels 124 are removed using an etching process. Because the mandrels 124, the spacer layer 126, and the sacrificial material 138 exhibit etch selectivity with respect to the same etching process, the mandrels 124 can be removed without removing the spacers 127 or the sacrificial material 138. Etching the mandrels 124 exposes the underlying dielectric layer 110, which can serve as an etch stop layer.

[0040] Although Fig. 13A and Fig. While Figure 13B illustrates that all mandrels 124 are removed, various embodiments also consider the selective removal of the mandrels 124. For example, in a specific area (e.g., depending on the device layout) of a wafer on which the target layer 102 is formed, the mandrels 124 may not be formed and / or removed. To achieve the selective removal of the mandrels 124, a photoresist (not explicitly illustrated) can be deposited over the mandrels 124, the spacers 127, and the sacrificial material 138. The photoresist can be similar to photoresist 120, see Figure 13B. Fig. 1-3, and openings in the photoresist can expose areas where the prongs 124 are removed, while other areas of the prongs 124 are masked against removal. Subsequently, the photoresist can be removed using an ashing step.

[0041] After some or all of the mandrels 124 have been removed, the spacers 127 can have a distance P2. In embodiments where an SADP process, as described above, is used, the distance P2 is half of a minimum distance achievable by photolithographic processes. The combination of the spacers 127 and the sacrificial material 138 defines a pattern for the hard mask layer 108. Fig. Figure 14 illustrates a top view of a pattern defined by the spacers 127 and the sacrificial material 138. Fig. 13A illustrates a cross-sectional view along line AA of Fig. 14, while Fig. 13B a ​​cross-sectional view along line BB from Fig. Figure 14 illustrates this. In some embodiments, the pattern defined by the spacers 127 and the sacrificial material 138 is a negative of subsequently formed conductive lines. For example, the space around the pattern defined by the spacers 127 and the sacrificial material 138 corresponds to a pattern of subsequently formed conductive lines. As illustrated by Fig. As illustrated in Figure 14, the sacrificial material 138 extends over a space between adjacent spacers 127, and the sacrificial material 138 defines areas in which the negative pattern is cut. For example, the sacrificial material 138 can define areas between subsequently formed conductive lines.

[0042] Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A and Fig. Figure 17B illustrates cross-sectional views of the structuring and deposition of features in the target layer 102 based on the pattern defined by the spacers 127 and the sacrificial material 138. In the embodiments of Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A and Fig. 17B is the target layer 102, a dielectric layer, and structured conductive features are formed in the dielectric layer. Figures ending with "A" refer to a cross-sectional view along line AA of Fig. 14, while figures ending with the designation “B” refer to a cross-sectional view along line BB of Fig. 14 refer to.

[0043] Firstly, referring to Fig. 15A and Fig. 15B, the dielectric layer 110 (see Fig. 13A and Fig. 13B) and the hard mask layer 108 is sequentially etched using the spacers 127 and the sacrificial material 138 as an etching mask. Any remaining mandrels 124 (not illustrated) can also be used as an etching mask to structure the hard mask layer 108. Thus, the hard mask 108 can exhibit the same pattern as the spacers 127 and the sacrificial material 138 in a top view (see, e.g., Figure 13B). Fig. 14) In some embodiments, the etching of the hard mask layer 108 comprises anisotropic dry etching and / or wet etching. After the hard mask layer 108 has been structured, wet cleaning can be performed to remove any remaining portions of the spacers 127, the sacrificial material 138, and the dielectric layer 110.

[0044] The hard mask layer 108 is then applied in Fig. 16A and Fig. 16B is used as an etching mask for structuring the openings 140 in the target layer 102. Etching of the target layer 102 can comprise an anisotropic dry etching process and / or a wet etching process, which etches sequentially through the ARC 106 to the target layer 102. Remaining sections of the target layer 102 can exhibit the same pattern as the spacers 127 and the sacrificial material 138 of Fig. exhibit 14. After the openings 140 have been structured, wet cleaning can be carried out to remove any remaining sections of the hard mask layer 108 and the ARC 106.

[0045] After the openings 140 in the target layer 102 have been structured, features can be formed in the openings. In one embodiment, the target layer 102 is a dielectric layer with a low dielectric constant, and the structured target layer 102 provides an integrated matrix (IMD) for an interconnect structure. Conductive features, such as copper conductors, copper vias, and / or cobalt terminations, can be formed in the IMD layer, as shown by Fig. 17A and Fig. Figure 17B illustrates the formation of the conductive features, which may involve the deposition of one or more linings 142 along side walls and a bottom surface of the openings 140 (see Figure 17B). Fig. 16A and Fig. 16B). The linings 142 can comprise TiO, TiN, TaO, TaN or the like and can provide diffusion barrier, adhesion and / or seeding layers for the conductive feature. The linings can be deposited using any suitable process, such as PVD, CVD, ALD and the like.

[0046] After the linings 142 have been deposited, remaining sections of the opening can be filled with a conductive material 144, such as copper, using, for example, PVD, plating, or the like. The conductive material 144 can initially be deposited in such a way that it overfills the openings 140 (see Fig. 16A and Fig. 16B), and a planarization process is performed to remove excess sections of the conductive material 144 above the target layer 102. This allows conductive features to be formed in the target layer 102. In embodiments where the conductive features in the target layer 102 are conductive lines, the sacrificial material 138 is defined (see Fig. 14) Areas where the conductive lines are cut. By using the embodiments discussed herein, conductive lines with a spacing of 40 nm or less, or even 30 nm or less, can be reliably formed with fewer manufacturing defects and an increased yield.

[0047] Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A and Fig. Figure 20B illustrates cross-sectional views of the structuring of the target layer 102 based on the pattern defined by the spacers 127 and the sacrificial material 138, according to other embodiments. In the embodiments of Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A and Fig. 20B is the target layer 102, a semiconductor layer or a conductive layer, and the target layer is structured to define features (e.g., ribs and / or gates). Figures ending with "A" refer to a cross-sectional view along line AA of Fig. 14, while figures ending with the designation “B” refer to a cross-sectional view along line BB of Fig. 14 refer to.

[0048] Fig. 18A and Fig. Figure 18B illustrates the component after the hard mask layer 108 has been structured according to the structuring steps of the embodiment. The various processing steps before Fig. 18A are the same as above in terms of Fig. Items 1 to 15B were discussed and are omitted here for brevity.

[0049] What next? Fig. 18A and Fig. As illustrated in Figure 18B, an additional hard mask layer 180 can be deposited after the hard mask layer 108 has been structured. The hard mask layer 180 can be deposited in openings extending through the hard mask layer 108, so that the hard mask layer 180 surrounds the hard mask layer 108. The hard mask layer 180 comprises a metal (e.g., titanium nitride, titanium oxide, titanium, tantalum nitride, tantalum oxide, tantalum, a metal-doped carbide (e.g., tungsten carbide), or the like) and / or a metalloid (e.g., silicon nitride, silicon oxide, boron nitride, silicon carbide, or the like), and it can be formed by PVD, radiofrequency PVD (RFPVD), atomic layer deposition (ALD), or the like. However, the material of the hard mask layer 180 and the hard mask layer 108 differs in such a way that the material of the hard mask layer 180 exhibits etch selectivity compared to the material of the hard mask layer 108 with respect to the same etching process.After the hard mask layer 180 has been deposited, a planarization process (e.g. a CMP or dry etching process) can be carried out to expose the hard mask layer 108.

[0050] In Fig. 19A and Fig. In step 19B, the hard mask layer 108 is removed using a suitable dry and / or wet process. Because the materials of the hard mask layer 108 and the hard mask layer 180 differ and exhibit etch selectivity, the hard mask layer 108 can be removed without significantly removing the hard mask layer 180. Thus, a hard mask layer 180 with a negative (e.g., reversed) pattern to the hard mask layer 108 is provided.

[0051] The hard mask layer is then applied in 180 in Fig. 20A and Fig. 20B is used as an etching mask for structuring the target layer 102. Etching the target layer 102 can involve an anisotropic dry etching process and / or a wet etching process, which etches sequentially through the ARC 106 to the target layer 102. Remaining sections of the target layer 102 can form a negative pattern to the spacers 127 and the sacrificial material 138. Fig. 14. After the target layer 102 has been structured, wet cleaning can be performed to remove any remaining sections of the hard mask layer 180 and the ARC 106. This allows rib and / or gate structures to be defined in the target layer 102 if the target layer 102 is a semiconductor layer or a conductive layer.

[0052] Fig. 21A, Fig. 21B, Fig. 22A, Fig. 22B, Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A, Fig. 27B, Fig. 28A, Fig. 28B, Fig. 29A, Fig. 29B and Fig. Figure 30 illustrates cross-sectional views of various intermediate stages in the fabrication of a semiconductor device 200 according to some embodiments. The semiconductor device 200 may be similar to the semiconductor device 100, where identical reference numerals denote identical devices formed using the same processes. Fig. 21A, Fig. 21B, Fig. 22A, Fig. 22B, Fig. 23A, Fig. 23B, Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A, Fig. 27B, Fig. 28A, Fig. 28B, Fig. 29A and Fig. Figures ending with "A" in Figure 29B consistently illustrate the same cross-sectional view, while figures ending with "B" consistently illustrate a cross-sectional view along the line of the BB of a corresponding Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A and Fig. 29A illustrates. For example, illustrates Fig. 21B a cross-sectional view along line BB from Fig. 21A; Fig. Figure 22B illustrates a cross-sectional view along line BB of Fig. 22A; and so on.

[0053] In Fig. 21A and Fig. 21B is a sacrificial material 138 (occasionally also referred to as a reversal material) deposited above the lower layer 128 and into the openings 136. The process steps for forming features of the semiconductor device 200 before Fig. 21A and Fig. 21B can be essentially the same as the ones above in terms of Fig. The processes described in Sections 1 to 7B are described below, and therefore a further description of these processes is omitted for the sake of brevity. In some embodiments, the sacrificial material 138 is also deposited over the middle layer 130. In other embodiments (not illustrated), the middle layer 130 is removed before the sacrificial material 138 is deposited. The removal of the middle layer 130 may involve a suitable dry etching process or a combination of dry and wet etching processes. In such embodiments, the sacrificial material 138 may be formed directly on (e.g., in direct contact with) a top surface of the lower layer 128.

[0054] In various embodiments, the sacrificial material 138 comprises an inorganic material, such as titanium oxide, tantalum oxide, silicon oxide, and the like. In some embodiments, the inorganic material is a low-temperature oxide (LTO) deposited using a relatively low process temperature (e.g., 200°C or less). In such embodiments, the low-temperature deposition process does not cause significant damage to the lower layer 128. The sacrificial material 138 can be selected to exhibit sufficient etch selectivity with respect to the spacer layer 126 for the same etching process. For example, in some embodiments, the ratio of the etch rate of the sacrificial material 138 to the etch rate of the spacer layer 126 for the same etching process is at least 0.7.

[0055] The sacrificial material 138 can be formed using a semiconductor deposition process, such as CVD, PVD, ALD, or the like. The semiconductor deposition process can be a uniform process that takes place on the sidewalls and a bottom surface of the openings 136. With continued deposition, sections of the sacrificial material 138 can fuse on opposite sidewalls of the openings 136, thereby filling the openings 136. Due to the semiconductor deposition process, an upper surface of the sacrificial material 138 may not be flat. For example, the recesses 138b in the upper surface of the sacrificial material 138 may be located in and / or above the openings 136. In comparison to the recesses 138a in the semiconductor device 100 (see Fig. 8A and Fig. 8B), the recesses 138b can be larger. For example, the recesses 138b can extend below an upper surface of the middle layer 130 (if present) and / or below an upper surface of the lower layer 128.

[0056] Larger recesses 138b can be formed by controlling parameters of the deposition process for the sacrificial material 138. For example, the size of the recesses 138b can be controlled by selecting an appropriate thickness for the sacrificial material 138 relative to the width W3 of the openings 136. In general, the ratio of the thickness T1 of the sacrificial material 138 to the width W3 of an opening 136 is at least 0.5 to allow sufficient gap filling of the sacrificial material 138 in the opening 136. Furthermore, by increasing this ratio of thickness T1 to width W3, the recesses 138b (or the recesses 138a of Fig. 8A and Fig. 8B) become smaller (e.g., flatter and extending less deeply into the openings 136). In contrast, by reducing this ratio of thickness T1 to width W3, the recesses 138b (or the recesses 138A of Fig. 8A and Fig. 8B) become larger (e.g., deeper and extending further into the openings 136). As such, the size of the recesses in the sacrificial material 138 can be controlled by controlling the ratio of thickness T1 to width W3.

[0057] Next, in Fig. 22A and Fig. 22B A planarization process (e.g., a CMP, dry etching, or the like) is performed to remove excess portions of the sacrificial material 138 outside the openings 136. In embodiments where the sacrificial material 138 is formed above the middle layer 130, the planarization process may also remove the middle layer 130. After the planarization process, the lower layer 128 is exposed, and the upper surfaces of the sacrificial material 138 and the lower layer 128 may be coplanar. Because the recesses 138b are relatively large, the planarization process may not remove the recesses 138b in the sacrificial material 138. As shown in Fig. 21A and Fig. As illustrated in Figure 21B, the exceptions 138b can remain even after the planarization process.

[0058] In Fig. 23A and Fig. In 23B, the lower layer 128 is removed using an ashing process. After the lower layer 128 has been removed, columns of sacrificial material 138 remain. The remaining sacrificial material 138 masks selected areas of the spacer layer 126. In some embodiments, the sacrificial material 138 can extend from a first sidewall section of the spacer layer 126 on a first mandrel 124 to a second sidewall section of the spacer layer 126 on a second mandrel 124.

[0059] In Fig. 24A and Fig. 24B, the sacrificial material 138 is trimmed to achieve a desired profile. In some embodiments, trimming the sacrificial material 138 recesses the sacrificial material 138 below a top surface of the spacer layer 126, such as below a top surface of the mandrels 124. Trimming the sacrificial material 138 may expose sections of the spacer layer 126 above the mandrels 124 (see Fig. 24A). In some embodiments, trimming the sacrificial material 138 further reduces a width of the sacrificial material 138 at least in cross-section BB (see Fig. 24B). The trimming process can propagate the shape of the recesses 138b in the trimmed structure. For example, the recesses 138b in the sacrificial material 138 remain even after trimming. In some embodiments, the trimming process can even enlarge the recesses 138b in the trimmed sacrificial material 138. The trimming of the sacrificial material 138 can involve a dry etching process or a combination of dry and wet etching processes, as described above in relation to Fig. 11A and Fig. 11B described.

[0060] Subsequently, an etching process is performed to remove exposed horizontal sections of the spacer layer 126 in order to expose the mandrels 124. The vertical sections of the spacer layer 126 remain after etching to provide the spacers 127. Furthermore, masked sections of the spacer layer 126 (e.g., areas masked by the sacrificial material 138) may also remain after etching. However, due to the presence of the recesses 138b in the sacrificial material 138, sections of the spacer layer 126 that lie beneath the recesses 138b may not be sufficiently masked during the spacer etching process. Consequently, sections of the spacer layer 126 beneath the recesses 138b may be etched during the spacer etching process. In some embodiments, the etching of the spacer layer 126 includes a dry etching process, as described above. Fig. 12A and Fig. 12B described. The resulting structure is in Fig. 25A and Fig. 25B illustrates this.

[0061] In Fig. 26A and Fig. In 26B, the mandrels 124 are removed using an etching process. Because the mandrels 124, the spacer layer 126, and the sacrificial material 138 exhibit etch selectivity with respect to the same etching process, the mandrels 124 can be removed without removing the spacers 127 or the sacrificial material 138. Etching the mandrels 124 exposes the underlying dielectric layer 110, which can serve as an etch stop layer. After the mandrels 124 have been removed, the spacers 127 have a distance P2. In embodiments where an SADP process, as described above, is used, the distance P2 is half of a minimum distance achievable by photolithographic processes. The combination of the spacers 127 and the sacrificial material 138 defines a pattern for the hard mask layer 108.

[0062] Although Fig. 26A and Fig. Figure 26B illustrates the removal of all the mandrels 124. However, various embodiments also consider the selective removal of the mandrels 124. For example, in a specific area (e.g., depending on the device layout) of a wafer on which the target layer 102 is formed, the mandrels 124 may not be formed and / or may be removed. To achieve the selective removal of the mandrels 124, a photoresist (not explicitly illustrated) can be deposited over the mandrels 124, the spacers 127, and the sacrificial material 138. The photoresist can be similar to photoresist 120, see Figure 26B. Fig. 1-3, and the openings in the photoresist can expose areas where the prongs 124 are removed, while other areas of the prongs 124 are masked against removal. Subsequently, the photoresist can be removed using an ashing step.

[0063] Firstly, referring to Fig. 27A and Fig. 27B, the dielectric layer 110 (see Fig. 13A and Fig. 13B) and the hard mask layer 108 are sequentially etched using the spacers 127 and the sacrificial material 138 as an etching mask. As described above, the sacrificial material 138 is formed with the recesses 138b, which are carried forward by various structuring steps. The recesses 138b provide areas where the sacrificial material 138 does not form a strong mask. Because of this, areas of the hard mask layer 108 beneath the recesses 138b may be at least partially exposed, and such areas beneath the recesses 138b can be structured. Thus, the hard mask 108 can have openings 108a corresponding to the recesses 138b. The openings 108a may have smaller dimensions than would otherwise be achievable by photolithography techniques. In some embodiments, the etching of the hard mask layer 108 includes anisotropic dry etching and / or wet etching.After the hard mask layer 108 has been structured, wet cleaning can be carried out to remove any remaining sections of the spacers 127, the sacrificial material 138 and the dielectric layer 110.

[0064] In some embodiments, such as through Fig. 28A and Fig. As illustrated in Figure 28B, the hard mask layer 108 is used as an etching mask for structuring the openings 140 in the target layer 102. The openings 108a in the hard mask layer 108 can permit the structuring of the openings 140a in the target layer 102. The dimensions of the openings 140a (e.g., the width) can be smaller than those of the openings 140 in the target layer 102. Etching the target layer 102 can involve an anisotropic dry etching process and / or a wet etching process, which etches sequentially through the ARC 106 to the target layer 102. Remaining sections of the target layer 102 can exhibit the same pattern as the spacers 127 and the sacrificial material 138. After openings 140 and 140a have been structured, wet cleaning can be carried out to remove any remaining sections of the hard mask layer 108 and the ARC 106.

[0065] After the openings 140 in the target layer 102 have been structured, features can be formed in the openings. In one embodiment, the target layer 102 is a dielectric layer with a low dielectric constant, and the structured target layer 102 provides an integrated conductive layer (IMD) for an interconnect structure. The conductive features 150, such as copper conductors, copper vias, and / or cobalt terminations, can be formed in the IMD layer, as shown by Fig. 29A and Fig. Figure 29B illustrates the formation of the conductive features 150, which may be similar to the formation of the linings 142 / conductive material 144, as described above in relation to Fig. 17A and Fig. 17B described.

[0066] In other embodiments, in which the target layer 102 is a conductive layer or a semiconductor layer, an inverted pattern of the hard mask layer 108 can be structured in the target layer 102 using a similar process to that described above with respect to Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A and Fig. 20B described. For example, an additional hard mask can be deposited around the hard mask layer 108; the hard mask layer 108 is then removed, and the additional hard mask is used to pattern the target layer 102. The resulting patterned target layer 102 has a negative pattern compared to the pattern of the hard mask 108.

[0067] In various embodiments, by intentionally enclosing the recesses 138b in the sacrificial material and transferring the pattern of the recesses 138b to the underlying features, small features (e.g., the conductive features 150a) can be defined and formed within the target layer 102. For example, the following illustrates Fig. 30 a top view of the target layer 102 and the conductive features 150. As shown by Fig. As illustrated in Figure 30, the conductive features 150 are formed in the target layer 102, and the conductive features 150a can be defined with a small dimension and be more closely spaced to neighboring features than other features in the target layer 102.

[0068] Several of the embodiments described above employ a structuring process that utilizes a semiconductor layer deposition process to more reliably create a structured sacrificial material with fewer defects. This allows for the formation of finely structured features in a target layer with fewer defects and increased yield.

[0069] In accordance with one embodiment, a method includes defining a first mandrel and a second mandrel over a hard mask layer. The method also includes depositing a spacer layer over and along the sidewalls of the first mandrel and the second mandrel, and forming a sacrificial material over the spacer layer between the first mandrel and the second mandrel. The sacrificial material comprises an inorganic oxide. The method further includes removing initial horizontal sections of the spacer layer to expose the first mandrel and the second mandrel. Remaining sections of the spacer layer provide spacers on the sidewalls of the first mandrel and the second mandrel. The method further includes removing the first mandrel and the second mandrel and structuring the hard mask layer using the spacers and the sacrificial material as an etching mask.

[0070] In accordance with one embodiment, a method includes structuring a first opening in a mandrel layer. The mandrel layer is arranged over a target layer. The method also includes depositing a spacer layer over a bottom surface and along sidewalls of the first opening. The method also includes forming a structured mask over the spacer layer. The structured mask includes a second opening that exposes a portion of the spacer layer on the bottom surface of the first opening. The method also includes depositing sacrificial material in the second opening using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. The method also includes removing the structured mask.The process also includes structuring the spacer layer to provide spacers on the sidewalls of the thorn layer. The process also includes removing the thorn layer. The process also includes transferring a pattern of spacers and sacrificial material to the target layer.

[0071] In accordance with one embodiment, a method includes structuring multiple mandrels over a hard mask layer. The hard mask layer is arranged over a target layer. The method also includes depositing a spacer layer over and along the sidewalls of the multiple mandrels. The method also includes forming a structured mask over the spacer layer. The structured mask includes an opening that exposes a portion of the spacer layer between adjacent multiple mandrels. The method also includes depositing a sacrificial material over the structured mask in the opening. The sacrificial material includes a recess on an upper surface of the sacrificial material. The method also includes removing the structured mask and structuring the spacer layer to expose the multiple mandrels.Sidewall sections of the spacer layer remain after structuring the spacer layer along the sidewalls of the multiple mandrels to expose them. The process also involves removing the multiple mandrels and structuring the hard mask layer using the sidewall sections of the spacer layer and the sacrificial material as an etching mask.

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