SEMICONDUCTOR COMPONENT WITH A MEMS DIE

Abstract

A method of manufacturing a semiconductor device, the method comprising: Encapsulating a microelectromechanical system (MEMS) die (102) and via elements (104) with an encapsulation material (110); Removing a portion of the encapsulation material (110) to expose the MEMS die (102) and the via elements (104); Forming a lid assembly over the MEMS die (102), the rewiring layer (106) for electrically coupling the MEMS die (102) to the via elements (104); and Attaching a cover (114), an integrated circuit die (116) and a metallization layer (112) such that the metallization layer (112) electrically couples the integrated circuit die (116) to the via elements (104), wherein the cover (114) defines a cavity between the cover (114) and the MEMS die (102).

Description

background

[0001] Semiconductor devices with a MEMS (microelectromechanical system) die may contain a cavity designed to protect a vibrating surface or membrane of the MEMS. Smaller packages for semiconductor devices with a MEMS are desirable for mobile devices and other applications.

[0002] For these and other reasons, there is a need for the present invention.

[0003] The document US 2012 / 0 153 771 A1 relates to a microelectromechanical transducer and a corresponding assembly method.

[0004] The document DE 10 2011 001 304 A1 relates to an electrical component and an associated manufacturing method.

[0005] The document DE 10 2011 086 764 A1 relates to a MEMS chip package and an associated manufacturing method. Summary

[0006] Various aspects relate to a method of manufacturing a semiconductor device, the method comprising: encapsulating a microelectromechanical system (MEMS) die and via elements with an encapsulation material; removing a portion of the encapsulation material to expose the MEMS die and the via elements; forming a redistribution layer for electrically coupling the MEMS die to the via elements; and applying a lid assembly over the MEMS die, comprising a lid, an integrated circuit die, and a metallization layer such that the metallization layer electrically couples the integrated circuit die to the via elements, the lid defining a cavity between the lid and the MEMS die.

[0007] Various aspects relate to a semiconductor device comprising: a microelectromechanical system (MEMS) die; a lid over the MEMS die defining a cavity between the lid and the MEMS die; a passive component attached to an inner surface of the lid; an integrated circuit die attached to an inner surface of the lid, the integrated circuit die electrically coupled to the MEMS die; an encapsulation material laterally surrounding the MEMS die; a redistribution layer on the encapsulation material and the MEMS die; a via element extending through the encapsulation material, the integrated circuit die electrically coupled to the MEMS die through the via element and the redistribution layer; and a metallization layer on the inner surface of the lid, the metallization layer electrically coupling the integrated circuit die to the MEMS die, wherein the MEMS die includes a microphone. Short description of the drawings Fig. 1A illustrates a cross-sectional view of an example semiconductor device including a microelectromechanical system (MEMS) die. Fig. 1B illustrates a cross-sectional view of another example of a semiconductor device including a MEMS die. Fig. 2A-2G illustrate an example of a method for manufacturing the semiconductor devices of Fig. 1A and Fig. 1B. Fig. 3 illustrates a cross-sectional view of another example of a semiconductor device including a MEMS die. Fig. 4 illustrates a cross-sectional view of another example of a semiconductor device including a MEMS die. Fig. 5 illustrates a cross-sectional view of another example of a semiconductor device including a MEMS die. Fig. 6 illustrates a cross-sectional view of another example of a semiconductor device including a MEMS die. Detailed description

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples of how the disclosure may be practiced. In this regard, directional terminology such as "top," "bottom," "front," "back," "forward," "rear," etc., is used with reference to the orientation of the described figure(s). Because components of examples may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure.The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0009] It is understood that the features of the various examples described herein may be combined with one another unless specifically stated otherwise.

[0010] As used herein, the term “electrically coupled” is not intended to imply that the elements may be directly coupled to each other, and intervening elements may be provided between the “electrically coupled” elements.

[0011] Semiconductor devices having a MEMS die may include an ASIC die, where the MEMS die and ASIC die are mounted side by side on a printed circuit board (PCB). The MEMS die may be electrically coupled to the ASIC die via wire bonds. A metal lid may be mounted over the MEMS die and ASIC die. The metal lid may include an opening for receiving sound if the MEMS die includes a microphone. To achieve higher integration in the package and thus a more compact package, examples of the semiconductor devices described herein include disposing an integrated circuit die (e.g., an ASIC die) in or on a lid that encapsulates a MEMS die. In this way, the lateral dimensions of the packages are greatly reduced.

[0012] Fig. 1A illustrates a cross-sectional view of an example semiconductor device 100a. Semiconductor device 100a includes a MEMS die 102, via elements 104, a redistribution layer 106, an encapsulation material 110, a metallization layer 112, a lid 114, an integrated circuit die 116, contact elements 118, and passive components 120. MEMS die 102 includes a diaphragm 103 facing away from lid 114. In one example, MEMS die 102 includes a microphone, and diaphragm 103 is used to capture an acoustic signal. Integrated circuit die 116 may be an ASIC die for processing the signal captured by MEMS die 102.

[0013] The encapsulation material 110 laterally surrounds the MEMS die 102 and the via elements 104. The encapsulation material 110 may include a molding compound, a polymer, or other suitable dielectric material. The redistribution layer 106 is formed on the bottom surface of the encapsulation material 110, the MEMS die 102, and the via elements 104. The redistribution layer 106 electrically couples the MEMS die 102 to via elements 104. The redistribution layer 106 includes a dielectric material 108 and a conductive material 109 that provides signal traces and contact elements for electrically coupling the semiconductor device 100a to a printed circuit board, such as a PCB.

[0014] Via elements 104 extend through the encapsulation material 110 to electrically couple the redistribution layer 106 to the metallization layer 112. In one example, via elements 104 may be prefabricated (e.g., via via bars or embedded z-lines (EZLs)) and encapsulated with the MEMS die 102 in the encapsulation material 110. In another example, via elements 104 may be formed after encapsulating the MEMS die 102, such as by drilling a via through the encapsulation material 110 and filling the via with a conductive material. In still other examples, the via elements 104 may include other suitable electrically conductive elements for electrically coupling the redistribution layer 106 to the metallization layer 112.

[0015] The lid 114 defines a cavity 115 above the MEMS die 102 and the encapsulation material 110. The cavity 115 may provide a back volume for the MEMS die 102. The lid 114 may include a non-conductive material such as a molding compound, a polymer, or other suitable dielectric material. In one example, the lid 114 includes the same material as the encapsulation material 110. In other examples, the lid 114 includes a different material than the encapsulation material 110. The lid 114 may be thinned after being attached over the MEMS die 102 by grinding or another suitable process to reduce the vertical dimensions of the semiconductor device 100a.

[0016] The metallization layer 112 is applied to the inner surface and lower surface of the lid 114. Portions of the metallization layer 112 applied to the lower surface of the lid 114 are electrically coupled to via elements 104 using solder or another suitable electrically conductive material. The metallization layer 112 may be applied to the inner surface and lower surface of the lid 114 using a deposition process (e.g., physical vapor deposition), a plating process (e.g., electroless plating), a printing process, or another suitable process. The metallization layer 112 may be patterned after being applied to the inner surface and lower surface of the lid 114 using a lithography and etching process or another suitable process.

[0017] The integrated circuit die 116 (e.g., an ASIC die) is attached to the inside of the lid 114. The integrated circuit die 116 may include a flip-chip package, an eWLB (embedded wafer-level ball grid array) package, or another suitable package. The integrated circuit die 116 is electrically coupled to the metallization layer 112 via contact elements 118 (e.g., solder balls). Passive components 120, such as SMD (surface mount device) components, LSCs (land-side capacitors), and / or integrated passive components (IPDs), are electrically coupled to the metallization layer 112 via solder or another suitable electrically conductive material. The metallization layer 112 electrically couples the integrated circuit die 116 and the passive components 120 to each other and to via elements 104 such that the integrated circuit die 116 is electrically coupled to the MEMS die 102.The metallization layer 112 may also provide electromagnetic shielding for the MEMS die 102 and / or the integrated circuit die 116.

[0018] The semiconductor device 100a provides several advantages over previous devices. The semiconductor device 100a includes reduced lateral dimensions due to the integration of the integrated circuit die 116 and the passive components 120 on the lid 114. The semiconductor device 100a also includes reduced vertical dimensions because the lid 114 can be thinned after being attached over the MEMS die 102.

[0019] Fig. 1B illustrates a cross-sectional view of another example of a semiconductor device 100b. The semiconductor device 100b is similar to that previously described and described with reference to Fig. 1A, except that the semiconductor device 100b includes a redistribution layer 106 facing the lid 114. In this example, the metallization layer 112 is electrically coupled to via elements 104 through the redistribution layer 106. The via elements 104 may electrically couple the semiconductor device 100b to a printed circuit board, such as a PCB. In this example, the membrane 103 of the MEMS die 102 faces the lid 114, which may provide better mechanical protection for the membrane 103 compared to the semiconductor device 100a, where the membrane 103 faces away from the lid 114.

[0020] The Fig. 2A-2G illustrate an example of a method for manufacturing semiconductor devices 100a and 100b of Fig. 1A or 1B. Fig. 2A illustrates a cross-sectional view of an example of a semiconductor device after a first stage of the fabrication process. A carrier 132 with a carrier tape 134 applied to the top surface of the carrier is provided. A MEMS die 102 with a cap 130 is placed on the carrier tape 134. The MEMS die 102 contains excess semiconductor material 101 to protect the membrane 103 during the initial stages of the fabrication process. The cap 130 protects the MEMS die 102 and a cavity 131 between the cap 130 and the excess semiconductor material 101 during the initial stages of the fabrication process. Via elements 104 are placed on the MEMS die 102 on the carrier tape 134.

[0021] Fig. 2B illustrates a cross-sectional view of an example of a semiconductor device after a second stage of the fabrication process. The MEMS die 102, the cap 130, and the via elements 104 are encapsulated with an encapsulation material 110 (e.g., a molding material, a polymer). The MEMS die 102, the cap 130, and the via elements 104 may be encapsulated using an injection molding process, a dispensing process, a printing process, or another suitable process. After encapsulation, the carrier 132 and the carrier tape 134 are removed from the bottom surfaces of the MEMS die 102, the via elements 104, and the encapsulation material 110.

[0022] Fig. 2C illustrates a cross-sectional view of an example of the semiconductor device after a third stage of the fabrication process. A portion of the top surface of the encapsulation material 110 and a portion of the top surface of the cap 130 are removed using a grinding process or other suitable process to expose a top surface of the via elements 104.

[0023] Fig. 2D illustrates a cross-sectional view of an example of the semiconductor device after a fourth stage of the fabrication process. A redistribution layer 106 is formed on the bottom surfaces of the MEMS die 102, the via elements 104, and the encapsulation material 110. Deposition, lithography, and etching processes may be used to form the redistribution layer 106. The redistribution layer 106 includes a dielectric material 108 and a conductive material 109 that provides signal traces and contacts for electrically coupling the MEMS die 102 to via elements 104 and for electrically coupling the semiconductor device to a circuit board. The exposed portions of the conductive material 109 may be plated with a precious metal (e.g., gold).

[0024] Fig. 2E illustrates a cross-sectional view of another example of a semiconductor device after a fifth stage of the fabrication process. A portion of the top surface of the encapsulation material 110, a portion of the top surface of each via element 104, and the remaining portion of the cap 130 are removed using a grinding process or other suitable process to expose the MEMS die 102 with excess semiconductor material 101 above the membrane 103.

[0025] Fig. Figure 2F illustrates a cross-sectional view of an example of a semiconductor device after a sixth stage of the fabrication process. Excess semiconductor material 101 is removed using an etching process to expose the top surface of the membrane 103.

[0026] Fig. 2G illustrates a cross-sectional view of an example of a lid assembly for the semiconductor device. The lid assembly includes a metallization layer 112, a lid 114, an integrated circuit die 116, contact elements 118, and passive components 120. The lid 114 may include a non-conductive material (e.g., a molding material, a polymer) and defines a cavity 115. The lid 114 may be manufactured using an injection process, a milling process, a 3D printing process, or another suitable process. The metallization layer 112 includes signal traces to electrically interconnect the integrated circuit die 116, the passive components 120, and the MEMS die 102 ( Fig. 2F). The metallization layer 112 is formed on the inner surface and the bottom surface of the lid 114 using deposition, lithography or etching processes, a printing process, a plating process (e.g., electroless plating), or other suitable processes.

[0027] The integrated circuit die 116 is then electrically coupled to the metallization layer 112 via contact elements 118. The integrated circuit die 116 may include a flip-chip package, an eWLB package, or other suitable package. Passive components 120 may be electrically coupled to the metallization layer 112 via solder or other suitable electrically conductive material. The passive components 120 may include SMD components, LSCs, and / or IPSs. In this example, the passive components 120 are electrically coupled to the surface of the metallization layer 112 facing away from the lid 114. However, in other examples, the passive components 120 may be embedded within the lid 114 and electrically coupled to the surface of the metallization layer 112 facing the lid 114.

[0028] In one example, the lid assembly is then placed over the MEMS die 102 of Fig. 2F, with the redistribution layer 106 facing away from the lid assembly. The metallization layer 112 is electrically coupled to via elements 104 via solder or other suitable electrically conductive material to achieve the above-described and with reference to Fig. 1A. In another example, the lid assembly is placed over the MEMS die 102 of Fig. 2F, with the redistribution layer 106 facing the lid assembly. The metallization layer 112 is electrically coupled to the redistribution layer 106 via solder or another suitable electrically conductive material to achieve the above-described and with reference to Fig. 1B. In both examples, after attaching the lid assembly over the MEMS die 102, the lid 114 may be thinned by grinding or another suitable process to reduce the vertical dimensions of the semiconductor device.

[0029] Fig. 3 illustrates a cross-sectional view of another example of a semiconductor device 140. The semiconductor device 140 is similar to that previously described and described with reference to Fig. 1B, except that the semiconductor device 140 includes a conductive layer 142. The conductive layer 142 is electrically coupled to via elements 104 and may include signal traces and / or contacts to electrically couple the semiconductor device 140 to a circuit board. The conductive layer 142 may include a noble metal or other suitable conductive material. The conductive layer 142 may be formed using a deposition process (e.g., physical vapor deposition), a plating process (e.g., electroless plating), a printing process, or another suitable process.

[0030] Fig. 4 illustrates a cross-sectional view of another example of a semiconductor device 150. The semiconductor device 150 includes a MEMS die 102, via elements 104, a redistribution layer 106, encapsulation material 110, a metallization layer 152, a lid 154, contact elements 156, and an integrated circuit die 158. In this example, the lid 154 is planar, and the integrated circuit die 158 is embedded within the bottom surface of the lid 154. The metallization layer 152 is attached to the bottom surface of the lid 154 and the integrated circuit die 158 and electrically couples the integrated circuit die 158 to contact elements 156. The contact elements 156 are electrically coupled to the metallization layer 152 via solder or another suitable electrically conductive material.In one example, the metallization layer 152, the lid 154, and the integrated circuit die 158 are part of an eWLB package that provides the lid assembly for the semiconductor device 150.

[0031] The contact elements 156 electrically couple the metallization layer 152 to via elements 104 and define the height of the cavity 155 above the MEMS die 102. The contact elements 156 may be similar to or different from the via elements 104. The contact elements 156 may be prefabricated (e.g., via bars or EZLs) or other suitable contact elements. Each contact element 156 is stacked on a via element 104 and electrically coupled to the via element 104 using solder or other suitable electrically conductive material. In other examples, more than one contact element 156 may be stacked on each via element 104 to define the height of the cavity 155 above the MEMS die 102 and / or the height of the semiconductor device 150.

[0032] Fig. 5 illustrates a cross-sectional view of another example of a semiconductor device 160. The semiconductor device 160 includes a MEMS die 102, via elements 104, a redistribution layer 106, encapsulation material 110, a metallization layer 152, a lid 154, an integrated circuit die 158, a contact element 161, and via elements 168. The contact element 161 may be annular and includes a first metallization layer 162, a second metallization layer 164, and a spacer 166.

[0033] Via elements 168 extend through the encapsulation material 110 between via elements 104 and the sidewalls of the semiconductor device 160. In one example, via elements 168 may be prefabricated (e.g., via bars or EZLs) and encapsulated in encapsulation material 110 with the MEMS die 102 and the via elements 104. In another example, the via elements 168 may be formed after the MEMS die 102 is encapsulated, such as by drilling a via through the encapsulation material 110 and filling the via with a conductive material. In still other examples, the via elements 168 may include other suitable electrically conductive elements.

[0034] The spacer 166 may include an encapsulation material (e.g., a molding material, a polymer) or other suitable dielectric material on which the metallization layers 162 and 164 are formed. The spacer 166 defines the height of the cavity 155 above the MEMS die 102 and / or the height of the semiconductor device 160. The spacer 166 may be manufactured using an injection molding process, a milling process, a 3D printing process, or another suitable process. Fig. In the example illustrated in Figure 5, the spacer 166 has a trapezoidal cross-sectional shape. However, in other examples, the spacer 166 may have another suitable cross-sectional shape, such as a rectangular shape.

[0035] The first metallization layer 162 of the contact element 161 extends over a portion of the upper surface of the spacer 166, an inner side surface of the spacer 166, and a portion of the lower surface of the spacer 166. The second metallization layer 164 of the contact element 161 extends over a portion of the upper surface of the spacer 166, an outer side surface of the spacer 166, and a portion of the lower surface of the spacer 166. The first metallization layer 162 is electrically coupled to the metallization layer 152 and the via elements 104 via solder or another suitable electrically conductive material. The second metallization layer 164 is electrically coupled to the via elements 168 via solder or another suitable electrically conductive material. The second metallization layer 164 and the via elements 168 hermetically seal the semiconductor device 160.In one example, metallization layers 162 and 164 have the same thickness. In other examples, metallization layers 162 and 164 have different thicknesses. Metallization layers 162 and 164 may be formed using a deposition process (e.g., physical vapor deposition), a plating process (e.g., electroless plating), a printing process, or another suitable process.

[0036] Fig. 6 illustrates a cross-sectional view of another example of a semiconductor device 170. The semiconductor device 170 includes a MEMS die 102, via elements 104, a redistribution layer 106, encapsulation material 110, a metallization layer 172, a lid 174, an integrated circuit die 178, and / or an integrated circuit die 180. In this example, the lid 174 defines a cavity 175 between the lid 174 and the MEMS die 102. In one example, an integrated circuit die 178 is embedded within the inside of the lid 174. In another example, instead of the integrated circuit die 178 or in addition to the integrated circuit die 178, an integrated circuit die 180 is attached to the inside of the lid 174 via contact elements 182.

[0037] The metallization layer 172 is attached to the inner surface and the bottom surface of the lid 174 and couples the integrated circuit die 178 and / or the integrated circuit die 180 to via elements 104. As in Fig. 6, the semiconductor device 170 may include two rows of via elements 104 on at least one side of the MEMS die 102. In other examples, more than two rows of via elements 104 may be located on at least one side of the MEMS die 102. By having two rows of via elements 104 on at least one side of the MEMS die 102, a higher number of connections to semiconductor devices 170 may be made or a higher pitch may be provided between via elements 104.

[0038] Each semiconductor device 100a, 100b, 140, 150, 160 and 170 previously described and with reference to the Fig.1A, 1B, and 3-6 may also include a coating on the outer top and outer side surfaces to hermetically seal the semiconductor devices. In one example, the coating may include a parylene coating deposited at low temperature (e.g., 150°C) from a vapor phase to a suitable thickness (e.g., 1 µm or more).

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Encapsulating a microelectromechanical system (MEMS) die (102) and via elements (104) with an encapsulation material (110); Removing a portion of the encapsulation material (110) to expose the MEMS die (102) and the via elements (104); Forming a lid assembly over the MEMS die (102), the rewiring layer (106) for electrically coupling the MEMS die (102) to the via elements (104); and Attaching a cover (114), an integrated circuit die (116) and a metallization layer (112) such that the metallization layer (112) electrically couples the integrated circuit die (116) to the via elements (104), wherein the cover (114) defines a cavity between the cover (114) and the MEMS die (102). [2] The method of claim 1, further comprising: Placing the MEMS die (102) and the via elements (104) on a carrier (132) prior to encapsulation; and Removing the carrier (132) after encapsulation. [3] The method of claim 1 or 2, wherein attaching the lid assembly comprises attaching the lid assembly such that the redistribution layer (106) faces the lid assembly. [4] The method of claim 1 or 2, wherein attaching the lid assembly comprises attaching the lid assembly such that the redistribution layer (106) faces away from the lid assembly. [5] Method according to one of claims 1 to 4, further comprising: Thinning the cover (114) after attaching the cover assembly. [6] Semiconductor device comprising: a microelectromechanical system (MEMS) die (102); a lid (114) over the MEMS die (102) defining a cavity between the lid (114) and the MEMS die (102); a passive component (120) mounted on the inside of the cover (114); an integrated circuit die (116) attached to an inner surface of the lid (114), the integrated circuit die (116) being electrically coupled to the MEMS die (102); an encapsulation material (110) laterally surrounding the MEMS die (102); a rewiring layer (106) on the encapsulation material (110) and the MEMS die (102); a via element (104) extending through the encapsulation material (110), wherein the integrated circuit die (116) is electrically coupled to the MEMS die (102) through the via element (104) and the redistribution layer (106); and a metallization layer (112) on the inside of the lid (114), wherein the metallization layer (112) electrically couples the integrated circuit die (116) to the MEMS die (102), wherein the MEMS die (102) comprises a microphone.

Images